Metod for decreasing k-value of sioc layer deposited by cvd method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to the manufacture of integrated circuits. More specifically, the present invention relates to a process of depositing a dielectric layer on a substrate and a structure formed by the dielectric layer.

【0002】

[Conventional technology]

One of the major steps in the manufacture of modern semiconductor devices is the step of forming a metal or dielectric film on a substrate by a chemical reaction of a gas. This deposition process is called chemical vapor deposition, CVD. In a normal thermal CVD process, a reactive gas is supplied to the surface of a substrate, on which a heat-induced chemical reaction occurs to form the desired film.

【0003】

The geometry of semiconductor devices has dramatically reduced their size since this type of device was first introduced decades ago. Since then, integrated circuits have generally followed the two-year / half-size rule (often called Moore's Law). This rule means that the number of devices that fit on a chip doubles every two years. Today's manufacturing plants routinely produce devices with feature sizes of 0.35 μm and even 0.18 μm, and tomorrow's plants will soon produce devices with smaller geometry.

【0004】

To further reduce the size of devices on integrated circuits, use conductive materials with low resistivity and insulators with low k (dielectric constant <4.0) to reduce capacitive coupling between adjacent metal wires. It has become necessary. One such low k material is spin-on glass, such as non-doped silicon glass (USG) or fluorine-doped silicon glass (FSG). These may be deposited as a gap-filled layer in the semiconductor manufacturing process.

【0005】

[Problems to be Solved by the Invention]

Typically, the liner / barrier layer is deposited between the subsequently deposited conductive material and the low k material so that by-products, such as moisture, do not diffuse into the conductive material. For example, the moisture that may be generated during the formation of the low potassium insulator easily diffuses to the surface of the conductive metal, increasing the resistivity of the surface of the conductive metal. A barrier / liner layer formed from conventional silicon oxide or silicon nitride material can block the diffusion of by-products. Similarly, a capping layer may be deposited on the low-k dielectric gap membrane to prevent the diffusion of contaminants, such as moisture. However, the barrier / liner layer and the capping layer typically have a dielectric constant significantly greater than 4.0, with higher dielectric constants resulting in a coupled insulator that does not significantly reduce the dielectric constant.

【0006】

Therefore, there is a need for a dielectric layer with a low dielectric constant and an adjacent liner / barrier layer that gives a low dielectric constant as a whole.

【0007】

[Means for solving problems]

The present invention generally provides a method of depositing a silicon oxycarbide (silicon oxide) layer having a low dielectric constant and depositing a silicon carbon-containing layer on the silicon oxycarbide layer. In one embodiment, the present invention comprises depositing a dielectric layer having silicon, oxygen and carbon with a carbon content of at least 1% atomic weight and a dielectric constant less than about 3 on the substrate. Provided is a substrate processing method comprising a step of depositing a silicon carbon-containing layer on a dielectric layer. The silicon carbon-containing layer may be an amorphous silicon carbide layer that can be doped with oxygen, nitrogen, or both.

【0008】

Another aspect of the invention is to deposit a dielectric layer on a substrate by reacting an organic silane compound with an oxidizing gas, where the dielectric layer has a carbon content of at least 1% in atomic weight and a dielectric constant less than about 3. Provided is a substrate processing method comprising depositing a silicon carbide layer or a doped silicon carbide layer on a dielectric layer under plasma conditions sufficient to reduce the dielectric constant of the dielectric layer.

【0009】

In another embodiment of the present invention, an organic silicon compound containing three or more alkyl groups is reacted with ozone to have a carbon content of about 5% to about 50% in atomic weight and a dielectric constant less than about 3. A silicon carbide layer or doped silicon by the step of depositing the dielectric layer on the substrate and the reaction of the alkylsilane compound under plasma conditions sufficient to reduce the dielectric constant of the dielectric layer to a value less than about 2.4. A substrate processing method is provided that includes a step of depositing a carbide layer on a dielectric layer.

【0010】

Another aspect of the present invention provides a substrate comprising a dielectric layer having silicon, oxygen and carbon and a carbon content of at least 1% (atomic weight), and a silicon carbon-containing layer covering the dielectric layer.

【0011】

A more specific description of the invention, which has been briefly summarized so far, is exemplified in the accompanying drawings so that the above-mentioned features, advantages, and modes of the invention can be understood in detail. It may be obtained by referring to the embodiment of.

【0012】

However, it should be noted that the accompanying drawings only show typical embodiments of the present invention and therefore should not be considered to limit their scope. This is because the present invention allows other embodiments that are just as effective.

【0013】

For a better understanding of the present invention, the following detailed description should be referred to.

【0014】

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described with reference to a method and apparatus for depositing a silicon oxycarbide layer having a low dielectric constant and depositing a silicon carbon-containing layer on the silicon oxycarbide layer. Surprisingly and unexpectedly, plasma deposition of a silicon carbon-containing layer on top of the silicon oxycarbide layer reduces the dielectric constant of the underlying silicon oxycarbide material, which is probably silicon oxy. It is believed to be done by removing some of the carbon without shrinking or deforming the carbide layer.

【0015】

The silicon oxycarbide layer is deposited by reacting an organic silane compound to form a silicon-carbon bond and a dielectric layer with a dielectric constant less than about 3. The silicon oxycarbide layer can be deposited as a gap-filling dielectric layer between the planar layer or the conductive material before depositing the silicon carbon-containing layer. The silicon carbon-containing layer is preferably a silicon carbide cap layer that can be doped with oxygen, nitrogen, or both.

【0016】

The silicon oxycarbide layer has carbon in the silicon-carbon bond, which contributes to the reduction of permittivity and barrier properties. The residual carbon content of the deposited film is about 1% to about 5% in atomic weight, preferably about 5% to about 50% in atomic weight. The deposited membrane may contain CH or CF bonds in all parts of the membrane to impart hydrophobic properties to the silicon oxycarbide layer. It is considered that the dielectric constant is reduced to about 3 or less by including the carbon-silicon bond in the silicon oxycarbide layer.

【0017】

The silicon oxycarbide layer is made of an organic silicon compound having carbon as an organic functional group, and this carbon is not easily desorbed by oxidation under treatment conditions. Suitable organic functional groups are alkyl groups, alkenyl groups, cyclohexenyl groups, allyl groups and functional derivatives. Organic silicon compounds include, for example:

【0018】

Methylsilane CH₃-SiH₃, Dimethylsilane (CH₃)₂-SiH₂, Trimethylsilane (CH₃)₃-SiH, Tetramethylsilane (CH₃)₄-Si, Dimethylsilanediol (CH)₃)₂-Si (OH)₂, Ethylsilane CH₃-CH₂-SiH₃, Phenylsilane C₆H₅-SiH₃, Diphenylsilane (C₆H₅)₂-SiH₂, Diphenylsilanediol (C₆H₅)₂-Si- (OH)₃, Methylphenylsilane C₆H₅-SiH₂-CH₃, Disilanomethane SiH₃-CH₂-SiH₃, Bis (Methyl Syranno) Methane CH₃-SiH₂-CH₂-SiH₂-CH₃, 1,2-Jishiranoetan SiH₃-CH₂-CH₂-SiH₃, 1,2-Bis (Methylsilano) Ethane CH₃-SiH₂-CH₂-CH₂--- SiH₂-CH₃, 2,2-Disilano Propane SiH₃-C (CH)₃)₂-SiH₃, 1,3,5-Tricilano-2,4,6-Trimethylene -(-SiH₂CH₂-)₃-(Cyclic), Dimethyldimethoxysilane (CH)₃)₂-Si- (OCH₃)₂, Diethyldietoxysilane (CH)₃CH₂)₂-Si- (OCH₃)₂, Dimethyldietoxysilane (CH)₃)₂-Si- (OCH₂CH₃)₂, Diethyldimethoxysilane (CH)₃CH₂)₂-Si- (OCH₃)₂, 1,3-Dimethyldisiloxane CH₃-SiH₂-O-SiH₂-CH₃, 1,1,3,3-tetramethyldisiloxane (CH₃)₂SiH-O-SiH- (CH₃)₂, Hexamethyldisiloxane (CH₃)₃-Si-O-Si- (CH₃)₃, 1,3-bis (silanomethylene) disiloxane (SiH₃-CH₂-SiH₂-)₂-O, Bis (1-methyldisyloxanyl) methane (CH₃-SiH₂-O-SiH₂-)₂-CH₂, 2,2-bis (1-methyldisyloxanyl) propane (CH₃-SiH₂-O-SiH₂-)₂-C (CH)₃ )₂, 2,4,6,8-Tetramethylcyclotetrasiloxane -(-SiHCH₃-O-)₄-(Cyclic), Octamethylcyclotetrasiloxane -(-Si (CH)₃)₂-O-)₄-(Cyclic), 2,4,6,8,10-Pentamethylcyclopentasiloxane -(-SiHCH₃-O-)₅-(Cyclic), 1,3,5,7-Tetrasilano-2,6-dioxy-4,8-dimethylene -(-SiH₂-CH₂-SiH₂-O-)₂-(cycl I c), 2,4,6-Tricilane tetrahydropyran -SiH₂-CH₂-SiH₂-CH₂-SiH₂-O -(Cyclic), 2,5-disirane tetrahydrofuran -SiH₂-CH₂-CH₂-SiH₂-O- (cyclic ), And these fluorinated derivatives.

【0019】

In a preferred embodiment of the present invention, the silicon oxycarbide layer is deposited by reacting an organic silicon compound containing three or more alkyl groups with an oxidizing gas containing ozone. If the organic silicon compound contains oxygen, the silicon oxycarbide layer may be deposited without an oxidant. Preferred organic silicon compounds include:

【0020】

Trimethylsilane (CH₃)₃-SiH, Tetramethylsilane (CH₃)₄-Si, 1,1,3,3-tetramethyldisiloxane (CH₃)₂-SiH-O-SiH- (CH₃)₂, Hexamethyldisiloxane (CH₃)₃-Si-O-Si- (CH₃)₃, 2,2-bis (1-methyldisyloxanyl) propane CH₃-SiH₂-O-SiH₂-)₂-C (CH)₃ )₂, 2,4,6,8-Tetramethylcyclotetrasiloxane -(-SiHCH₃-O-)₄-(Cyclic), Octamethylcyclotetrasiloxane -(-Si (CH)₃)₂-O-)₄-(Cyclic), 2,4,6,8,10-Pentamethylcyclopentasiloxane -(-SiHCH₃-O-)₅-(Cyclic), And these fluorinated derivatives.

【0021】

The most preferred organic silicon compound is trimethylsilane. Trimethylsilane is the preferred alkylsilane for forming amorphous silicon carbide layers, as will be described in detail later.

【0022】

The organic silicon compound is preferably oxygen (O).₂), Ozone (O₃), Nitrous oxide (N)₂O), carbon monoxide (CO), carbon dioxide (CO)₂), Water (H₂O), or by reacting with a combination thereof, is oxidized during the deposition of the silicon oxycarbide layer. When ozone is used as the oxidizing gas, the ozone generator typically converts about 15% by weight of oxygen in the source gas to ozone, the rest typically oxygen. However, the concentration of ozone may increase or decrease depending on the amount of ozone desired and the type of ozone generator used. Oxygen may be provided by decomposing an organic silicon compound having oxygen.

【0023】

The organic silane compound is oxidized during deposition such that the carbon content of the deposited membrane is from about 1% to about 50%, preferably about 5% to about 50% in atomic weight. During the deposition of the silicon oxycarbide layer, the substrate is maintained at a temperature of about -20 ° C to about 500 ° C, preferably at a temperature of about 170 ° C to about 180 ° C.

【0024】

Following the deposition, the deposited dielectric material has a temperature of about 100 ° C to about 400 ° C to reduce the water content and increase the solidity and hardness of the dielectric material, if desired. Then, it may be annealed for about 1 minute to about 60 minutes, preferably about 30 minutes. Annealing is preferably performed after the deposition of the next layer that prevents shrinkage or deformation of the dielectric layer. Inert gases such as argon and helium may be added to the annealing atmosphere.

【0025】

In the case of plasma deposition of silicon oxycarbide layer, the organic silicon material is about 0.03 W / cm.²~ About 3.2W / cm²It is deposited using the power density of. These power densities are RF power levels from about 10W to about 1000W for a 200mm substrate. The silicone oxycarbide layer can be deposited continuously or interrupted to improve porosity, eg, changing chambers and giving cooling time. RF power can be provided at high frequencies, such as 13MHz to 14MHz. RF power can be provided in continuous or short duration cycles. In the latter case, the power is on at a specified level for cycles smaller than about 200 Hz, with a total on-cycle between about 10% and about 30% of the total duty cycle.

【0026】

In one embodiment of plasma deposition, oxygen or oxygen-containing compounds are dissociated to increase reactivity and achieve the desired oxidation of the deposited membrane. RF power is coupled to the deposition chamber, facilitating the dissociation of the compound. In addition, the compound may be dissociated in the microwave chamber before entering the deposition chamber.

【0027】

Sedimentation preferably occurs in a single deposition chamber, but the silicon oxycarbide layer is sequentially in two or more deposition chambers so that the membrane can be cooled during deposition, for example. Can be deposited.

【0028】

The silicon carbon-containing layer deposited on the silicon oxycarbide layer can include a silicon carbide material, an oxygen-doped silicon carbide material, a nitrogen-doped silicon carbide material, or a combination thereof. The silicon carbon-containing layer is preferably an amorphous hydrogenated silicon carbide. The amorphous silicon carbide layer is produced by the reaction of an alkylsilane compound or a carbon-containing material and a silicon-containing material in a plasma of an inert gas. In addition, an oxygen or nitrogen source, such as ammonia, may be present during the reaction to form a doped silicon carbide layer.

【0029】

Suitable alkylsilane compounds for depositing silicon carbide layers include:

【0030】

Methylsilane (CH₃SiH₃), Dimethylsilane ((CH)₃)₂SiH₂), Trimethylsilane ((CH)₃)₃SiH), Diethyl silane ((CH)₂H₅)₂SiH₂), Propylsilane (C₃H₇SiH₃), Vinyl Methyl Silane (CH)₂= CH) CH₃SiH₂), 1,1,2,2-tetramethyldisilane (HSi (CH)₃)₂-Si (CH)₃)₂H), Hexamethyldisilane ((CH)₃)₃Si-Si (CH)₃)₃), 1,1,2,2,3,3-hexamethyltrisilane (H (CH)₃)₂Si-Si (CH)₃)₂-Si H (CH₃)₂), 1,1,2,3,3-pentamethyltrisilane (H (CH)₃)₂Si-SiH (CH)₃)-Si H (CH₃)₂), Dimethyldisylanoethane (CH)₃-SiH₂-(CH₂)₂-SiH₂--- CH₃), Dimethyldisylanopropane (CH)₃-SiH- (CH₂)₃-SiH-CH₃), Tetramethyldisylanoethane ((CH)₂-SiH- (CH₂)₂-SiH- (CH)₂), Tetramethyldisylanopropane ((CH₃)₂-Si- (CH₂)₃-Si- ( CH₃)₂), And these fluorinated carbon derivatives.

【0031】

The alkylsilane compound is a relatively inert gas, preferably a noble gas, such as helium or argon, or nitrogen (N).₂) Is reacted in the plasma containing. The deposited silicon carbide film has a permittivity of about 6 or less, preferably about 3 or less. The deposition of the silicon carbide layer reduces the permittivity of the silicon oxycarbide layer to a value lower than about 2.4.

【0032】

The preferred silicon carbide layer is deposited in one embodiment by feeding trimethylsilane to the plasma processing chamber at a flow rate of about 10 to about 1000 sccm (standard cubic centimeter per minute). An inert gas, such as helium, argon, or a combination thereof, is also supplied to the chamber at a flow rate of about 50 sccm to about 5000 sccm. Chamber pressure is maintained from about 100 millitorls to about 15 tolls. During the deposition process, the temperature of the substrate surface is maintained between about 100 ° C and about 450 ° C. Alternatively, a doped silicon carbide layer can be deposited by introducing an oxygen and / or nitrogen source, or other dopant, into the processing chamber at a flow rate of about 50 sccm to about 10,000 sccm.

【0033】

The organic silicon compound and the inert gas (and the optional dopant) are introduced into the processing chamber through a gas dispersion rate about 200 mm to about 600 mm away from the substrate on which the silicon carbide layer is deposited. Power from a single 13.56MHz RF power supply is supplied to chamber 10 and is approximately 0.3 watts / cm.²~ About 3.2 watts / cm²Plasma is formed at a power density of about 100 watts to about 1000 watts for a 200 mm substrate. Preferably about 0.9 watts / cm²~ About 2.3 watts / cm²Power density, or a power level of about 300 watts to about 700 watts for a 200 mm substrate, is supplied to the processing chamber to generate plasma. Further, the ratio of the silicon source to the dopant in the gas mixture should be in the range of about 1: 1 to about 1: 100. The above process parameters are approximately 100 Å / for the silicon carbide layer when performed on a 200 mm (millimeter) substrate placed in a deposition chamber available from Applied Materials, Inc., Santa Clara, CA, USA. Gives a deposition rate of min to about 3000 Å / min.

【0034】

The process of depositing a silicon carbide layer with a low dielectric constant is a co-pending U.S. patent application filed October 1, 1998, U.S. Patent Application No. 09 / 165,248, and March 16, 1999. It is explained in more detail in No. 09 / 270,039 and Co-pending U.S. Patent Application No. 09 / 627,667 filed on July 28, 2000. These descriptions are incorporated herein by reference to the extent consistent with the present invention. The embodiments described herein for depositing a silicon carbide layer are provided to illustrate the present invention. The specific embodiments shown shall not be used to limit the scope of the invention. In addition, the present invention anticipates other processes and materials used to deposit silicon carbide layers.

【0035】

The deposition process of the present invention can be carried out in a substrate processing system as described in more detail later.

【0036】

Example of CVD reaction chamber FIG. 1 is a vertical cross-sectional view of a parallel process chemical vapor deposition chamber 10 having a high vacuum region 15. The processing chamber 10 includes a gas dispersion manifold 11. The gas dispersion manifold disperses the processing gas onto the substrate (not shown) through the openings in it. The board rests on a board support speed or susceptor 12 that is raised or lowered by the lift motor 14. For example, a liquid injection system (not shown) typically used for liquid injection of TEOS may also be provided to inject a liquid organic silicon compound.

【0037】

The processing chamber 10 heats the processing gas and the substrate by, for example, a resistance heating coil (not shown) or an external lamp (not shown). Referring to FIG. 1, the susceptor 12 is placed on a support mandrel 13, and the susceptor 12 (and the substrate supported on the upper surface of the susceptor 12) is placed in the lower loading / offloading position and above the manifold 11 close to it. It is designed to move to and from the processing position of.

【0038】

When the susceptor 12 and the substrate are in the processing position 14, they are surrounded by the insulator 17 and the processing gas is discharged to the manifold 24. During the process, the gas inlet to the manifold 11 is evenly distributed in the radial direction over the surface of the substrate. The vacuum pump 32 having a throttling valve controls the rate of gas discharge from the chamber.

【0039】

The deposited gas and the carrier gas are introduced into the mixing system 19 via the gas line 18 before reaching the manifold 11. In the mixing system 19, the gases are mixed and then sent to the manifold 11. In general, the processing gas supply line 18 for each of the processing gases is further (i) a safety deadline valve (not shown) that can be used to automatically or manually shut off the flow of the processing gas into the chamber. ), And (ii) include a mass flow controller (also not shown) that measures the flow of gas through the gas supply line. When toxic gases are used during the process, several safety deadline valves are located on each gas supply line in the usual configuration.

【0040】

The deposition process performed in the processing chamber 10 can be a thermal process or a plasma process. In a plasma process, the RF energy applied from the RF power supply 25 to the dispersion manifold 11 (the susceptor 12 is grounded) typically creates a controlled plasma adjacent to the substrate. Alternatively, RF power can be delivered to the susceptor 12, or RF power can be delivered to different components at different frequencies. The RF power source 25 can supply single or mixed frequency RF power to enhance the decomposition of the reactants introduced into the high vacuum region 15. A mixed frequency RF power supply typically supplies power to the distributed manifold 11 at a high frequency of 13.56 MHz (RF1) and power to the susceptor 12 at a low frequency of 360 KHz (RF2). The silicon oxycarbide layer of the present invention is most preferably produced using low level constant frequency RF power or pulse level high frequency RF power.

【0041】

When additional dissociation of the oxidative gas is desired, the optional microwave chamber 28 can be used to input about 0 watts to about 6000 watts of microwave power into the oxidative gas before entering the deposition chamber. Applying microwave power separately will prevent excessive dissociation of the organic silicon compound prior to reaction with the oxidizing gas. When microwave power is applied to the oxidative gas, a gas dispersion rate with separate passages for the organic silicon compound and the oxidative gas is preferred.

【0042】

Typically, the chamber lining, dispersion manifold 11, susceptor 12, and any or all of the various other reaction chamber hardware are made from materials such as aluminum or anodized aluminum. An example of such a CVD reaction chamber is Wang et al., U.S. Pat. No. 5, 5,113, entitled "The Use of Thermal CVD / PECVD Reaction Chambers and Thermochemical Vapor Deposition of Silicon Dioxide and Insitu Multistep Flattening Process" (A). Thermal CVD / PECVD Reactor and Use for Thermal Chemical Vapor Deposition of Silicon Dioxide and In-situ Multi-step Planarized Process).

【0043】

The lift motor 14 raises and lowers the susceptor 12 between the processing position and the lower substrate loading position. The motor, the gas mixing system 19, and the RF power supply 25 are controlled by the system controller 34 via the control line 36. The reaction chamber includes analog assemblies such as mass flow controllers (MFCs) and standard or pulse RF generators. These are controlled by the system controller 34. The system controller 34 executes the system control software stored in the memory 38. The memory 38 is a hard disk drive in a preferred embodiment. Motors and optical sensors are used to move and determine the position of the movable mechanical assembly, eg, the throttling valve of the vacuum pump 32, and the motor that positions the susceptor 12.

【0044】

The system controller 34 controls all of the activity of the CVD reaction chamber. Preferred embodiments of controller 34 include hard disk drives, floppy® disk drives, and card racks. Card racks include single board computers (SBCs), analog and digital input / output boards, interface boards, and stepper motor controller boards. The system controller complies with the Versa Modular Europeans (VME) standard, which specifies the dimensions and types of boards, card cages, and connectors. In addition, the VME standard specifies a bus structure with a 16-bit data bus and a 24-bit address bus.

【0045】

The system controller 34 operates under the control of a computer program stored in the hard disk drive 38. Computer programs dictate timing, gas mixing, RF power levels, susceptor locations, and other parameters for a particular process.

【0046】

With reference to FIG. 2, the process can be executed, for example, using the computer program product 210 running on the system controller 34. Computer program code is written in a normal computer-readable programming language, such as 68000 assembly language, C, C ++, or Pascal. Appropriate program code is entered into a single file or multiple files using a regular text editor and stored or organized in a computer-enabled medium, such as a computer's memory system. If the code text entered is a high-level language, the code is compiled and the resulting compiled code is linked with the object code of the precompiled window library routine. To execute the compiled and linked object code, the user of the system calls the object code and causes the computer system to load the code into memory. The CPU reads the code from memory, executes it, and executes the task specified in the program.

【0047】

FIG. 2 shows a block diagram of the hierarchical control structure of the computer program 210. In response to a menu or screen displayed on the CRT monitor, the user enters the process set number and processing chamber number into the process selector subroutine 220 using the light pen interface. A process set is a predetermined set of process parameters required to execute a specified process, identified by a default set number. The process selector subroutine 220 (i) selects the desired processing chamber on a cluster tool, eg, the Centura platform (available from Applied Mattel Als), and (ii) manipulates the processing chamber to operate the desired process. Select the desired set of process parameters required to perform. Process parameters for performing a particular process include processing conditions such as processing gas composition and flow rate, temperature, pressure, plasma conditions such as RF bias power level and magnetic field power level, cooling gas pressure, and chamber wall. It is related to the temperature of the gas and is provided to the user in the form of a recipe. The parameters specified by the recipe are entered using the light pen / CRT monitor interface.

【0048】

The signal for monitoring the process is provided by the analog input and digital input boards of the system controller, and the signal for controlling the process is output to the analog output and digital output board of the system controller 34.

【0049】

The process sequencer subroutine 230 contains program code that accepts a set of processing chambers and processing parameters specified from the process selector subroutine 220 and controls the operation of various processing chambers. A large number of users can enter the processing set number and the processing chamber number, or one user can enter a large number of processing chamber numbers. Therefore, the sequencer subroutine 230 operates to schedule the selected processes in a desired order. Preferably, the sequencer subroutine 230 (i) monitors the operation of the processing chamber to determine if the chamber is in use, (ii) what process is performed in the chamber in use. Includes computer-readable program code to perform the steps of determining what is being done, (iii) performing the desired process based on the availability of the processing chamber and the type of process to be performed. The usual method of monitoring the processing chamber, for example polling, can be used. When scheduling which process should be executed, sequencer subroutine 230, for the selected process, is the current condition contrasted with the desired process condition of the processing chamber being used, or each of them. It can be designed to take into account the "age" of the request entered by a particular user, or other relevant factors that the system programmer wants to include in determining scheduling priorities.

【0050】

Once the sequencer subroutine 230 determines the combination of processing chamber and processing set to be executed next, the sequencer subgroup 230 executes the processing set by passing specific processing set parameters to the chamber manager subroutine 240. Wake up. Chamber manager subroutine 240 controls a number of processing tasks within processing chamber 10 according to the processing set determined by sequencer subroutine 230. For example, the chamber manager subroutine 240 contains program code that controls the CVD process operation within the processing chamber 10. Further, the chamber manager subroutine 240 controls the execution of various chamber component subroutines. The chamber component subroutine controls the operation of the chamber component required to execute the selected processing set. Examples of chamber component subroutines are the susceptor control subroutine 250, the processing gas control subroutine 260, the pressure control subroutine 270, the heater control subroutine 280, and the plasma control subroutine 290. Those with ordinary skill in the art can easily understand that other chamber control subroutines can be included, depending on what process execution is desired within the processing chamber 10. There will be.

【0051】

In operation, the chamber manager subroutine 240 selectively schedules or calls process component subroutines according to the particular set of processes being executed. The chamber manager subroutine 240 schedules process component subroutines in the same way that the sequencer subroutine 230 schedules which processing chamber 10 and processing set to execute next. Typically, the chamber manager subroutine 240 is a step of monitoring various chamber components, a step of determining which component needs to operate for a set of processes to be performed, based on process parameters. Includes a step that causes the execution of a chamber component subroutine in response to a monitoring and decision step.

【0052】

From now on, the operation of a specific chamber component subroutine will be described with reference to FIG. The susceptor control positioning subroutine 250 is used to load the substrate into the susceptor 12 and optionally raise the substrate to the desired height in the processing chamber 10 to control the distance between the substrate and the gas dispersion manifold 11. Contains the chamber component control program code to be used. When the substrate is loaded into the processing chamber 10, the susceptor 12 descends to receive the substrate, after which the susceptor 12 rises to the desired height in the chamber and from the gas dispersion manifold 11 during the CVD process. Maintain the substrate at the first distance or spacing of. In operation, the susceptor control subroutine 250 controls the movement of the susceptor 12 in response to the processing set parameters transferred from the chamber manager subroutine 240.

【0053】

The processing gas control subroutine 260 has a program code for controlling the composition and flow rate of the processing gas. The processing gas control subroutine 260 controls the open / closed position of the safety deadline valve and ramps up / down the mass flow controller to obtain the desired gas flow rate. The processing gas control subroutine 260, like all chamber component subroutines, is called by the chamber manager subroutine 240 to receive processing parameters related to the desired gas flow rate from the chamber manager subroutine. Typically, the processing gas control subroutine 260 opens the gas supply line, iteratively (i) reads the required mass flow controller, and (ii) receives the readings from the chamber manager subroutine 240 as the desired flow rate. (Iii) Operate to adjust the flow rate of the gas supply line as needed. Further, the processing gas control subroutine 260 includes a step of monitoring whether the gas flow rate is a dangerous speed and a step of activating the safety deadline valve when a dangerous condition is detected.

【0054】

In some processes, an inert gas, such as helium or argon, is flushed into the processing chamber 10 to stabilize the pressure in the chamber before the reactive processing gas is introduced into the chamber. For these processes, the processing gas control subroutine 260 is programmed to include a step of flowing an inert gas into the chamber 10 for the amount of time required to stabilize the pressure in the chamber. Then the steps described above will be performed. Further, when the processing gas is vaporized from a liquid precursor such as 1,3,5-tricilano-2,4,6 trimethylene (1,3,5-trisilanacyclohexane), the processing gas control subroutine 260 is a bubble assembly. It will be written to include the step of whipping the feed gas, eg helium, in the liquid precursor within. In this type of process, the processing gas control subroutine 260 adjusts the flow of supply gas, the pressure in the bubbler, and the bubbler temperature to obtain the desired processing gas flow rate. As described above, the desired processing gas flow rate is transferred to the processing gas control subroutine 260 as a processing parameter. In addition, the processing gas control subroutine 260 access the stored table containing the values required for a given processing gas flow rate to provide the required supply gas flow rate, bubbler pressure, and bubbler temperature for the desired processing gas flow rate. Includes steps to obtain. Once the required values are obtained, the supply gas flow rate, bubbler pressure, and bubbler temperature are monitored, compared to the required values, and adjusted accordingly.

【0055】

The pressure control subroutine 270 contains program code that controls the pressure in the processing chamber 10 by adjusting the open size of the throttling valve in the discharge pump 32. The open size of the throttling valve is set to control the chamber pressure to the desired level in relation to the total processing gas flow, the size of the processing chamber, and the pumping set pressure for the discharge pump 32. When the pressure control subroutine 270 is called, the desired or target pressure level is received as a parameter from the chamber manager subroutine 240. The pressure control subroutine 270 measures the pressure in the processing chamber 10 by reading one or more conventional pressure manometers connected to the chamber, compares the measured value with the target pressure, and stores the corresponding to the target pressure. It operates to obtain a PID (proportional, integral, differential) value from the pressure table and adjust the throttling valve according to the PID value obtained from the pressure table. Alternatively, the pressure control subroutine 270 may be written to open or close the throttling valve to a particular opening size to adjust the processing chamber 10 to the desired pressure.

【0056】

The heater control subroutine 280 contains program code that controls the temperature of the heating module or the radiant heat used to heat the susceptor 12. The heater control subroutine 280 is also called by the chamber manager subroutine 240 to receive a target or set temperature parameter. The heater control subroutine 280 measures the temperature by measuring the voltage output of the thermocouple placed in the susceptor 12, compares the measured temperature with the set temperature, and increases the current applied to the heating module. Or reduce it to achieve the set value temperature. The temperature is obtained from the measured voltage by looking up the corresponding temperature in the stored conversion table or by calculating the temperature using a fourth-order polynomial. The heater control subroutine 280 gradually controls the ramp-up / down of the current applied to the heating module. Gradual ramp up / down increases the life and reliability of the heating module. In addition, a built-in failsafe mode can be included to detect process safety compliance. This mode can shut off the operation of the heating module if the processing chamber 10 is not set up properly.

【0057】

The plasma control subroutine 290 includes program code that sets the power level of the RF bias voltage applied to the processing electrodes in the processing chamber 10 and optionally the level of the magnetic field generated in the reaction chamber. Like the chamber component subroutine described above, the plasma control subroutine 290 is called by the chamber manager subroutine 240.

【0058】

The above description of the CVD system is primarily for illustrative purposes and other CVD equipment such as electrode cyclotron resonance (ECR) plasma CVD equipment, inductively coupled RF high density plasma CVD equipment and the like may be used. Further, the above-mentioned system can be modified, for example, the design of the susceptor, the design of the heater, the position of the RF power connection, and the like. For example, the substrate could be supported and heated by a resistance heated susceptor. The pretreatment and the method of forming the pretreated layer of the present invention are not limited to a specific apparatus or a specific plasma excitation method.

【0059】

Silicon oxycarbide layer deposition and silicon carbide material The damascene structure including the silicon oxycarbide layer and the silicon carbide layer or the doped silicon carbide layer deposited on the silicon carbide layer is shown in FIG. The conductive portion 310 is deposited in the substrate 300. The silicon oxycarbide is deposited as a dielectric layer 314 on the dielectric liner or barrier layer 312 of the silicon carbide as described herein. Alternatively, the liner or barrier layer may include other dielectric liners and barrier materials such as silicon nitride. Silicon carbide is deposited on the dielectric layer 314 as a cap layer 316 as described herein. The cap layer 316 may serve as an etching stop or liner layer during further substrate processing. The cap layer 316, the dielectric layer 314, and the dielectric liner or barrier layer 312 are pattern etched to define a line opening that exposes the connection 317, eg, the underlying conductive portion 310. The conductive liner / barrier layer 318 is deposited inside the connection 317 and the conductive material 320 is deposited on the layer 318 to fill the connection 317. Typically, after deposition, the substrate is flattened as shown.

【0060】

Preferred damascene structures manufactured according to the present invention include a silicon oxycarbide layer and a silicon carbide layer, as shown in FIG. 3, and methods of making this structure are depicted as sequential schematics in FIGS. 4A-4C. 4A-4C are cross-sectional views of the substrate on which the steps of the present invention have been performed.

【0061】

As shown in FIG. 4A, the dielectric layer 314 of the silicon oxycarbide material formed from one or more organic silicon compounds by the deposition process described herein depends on the size of the structure produced. It is deposited on the liner or barrier layer 312 to a thickness of about 5,000 Å to about 10,000 Å. The dielectric layer 314 may be deposited in a plasma deposition process, but is preferably deposited in a plasma-free deposition process by reacting trimethylsilane with oxygen containing about 15% by weight ozone.

【0062】

The liner or barrier layer 312 may be a silicon carbide layer created from PECVD of the alkylsilane compound using plasma of an inert gas. The silicon carbide layer may be doped with oxygen or nitrogen. Alternatively, the liner / barrier layer 312 may constitute a conductive portion 310 preformed within the substrate 300, such as a conductive material, such as copper, which minimizes oxidation and / or diffusion, such as. Silicon nitride (silicon nitride) may be included.

【0063】

The cap layer 316 containing the silicon carbide layer or the doped silicon carbide layer described herein is then reacted with trimethylsilane using about 10 to about 1000 watts of RF power on a 200 mm substrate. It is deposited on the dielectric layer 314 to a thickness of about 200 to about 1000 Å. The silicon carbide material may be doped with oxygen or nitrogen.

【0064】

The cap layer 316, the dielectric layer 314, and the liner or barrier layer 312 are then pattern etched to define the connection 317 and expose the conductive portion 310 within the substrate 300, as shown in FIG. 4B. Preferably, the cap layer 316, the dielectric layer 314, and the liner or barrier layer 312 are pattern etched by conventional photolithography and etching processes for silicon carbide films. The photoresist or other material used to pattern the cap layer 316 is removed by an oxygen strip or other suitable process.

【0065】

Following etching of the deposited material and removal of the photoresist material, the exposed portion of the cap layer 316, the dielectric layer 314, and the liner or barrier layer 312 is treated by a reactive preclean process to expose the connection 317. Contaminants, microparticles, residues, and oxides formed on the portion and on the surface of the substrate may be removed. The reactive preclean process puts the substrate into a plasma containing hydrogen or an inert gas such as argon, 0.03 watts / cm.²~ About 3.2 watts / cm²It has a process of exposing to a power level of about 10 watts to 1000 for a power density or 200 millimeter substrate. The processing chamber is maintained at a pressure of about 20 tolls or less and a substrate temperature of about 450 ° C. or less during the reactive cleaning process.

【0066】

Referring to FIG. 4C, the cap layer 316, the dielectric layer 314, and the liner or barrier layer 312 are etched to define the connection 317, and after the photoresist is removed, the connection 317 is filled with the conductive material 320. The structure is formed of a conductive material such as aluminum, copper, tungsten, or a combination thereof, and a conductive barrier layer that prevents diffusion. Nowadays, due to the low resistivity of copper (3.1 Ω cm for aluminum vs. 1.7 Ω cm for copper), copper tends to be used to form smaller features.

【0067】

Preferably, the conductive barrier layer 318 is first consistently deposited in the connection 317 so that copper does not migrate to the surrounding silicon and / or dielectric material. The barrier layer contains titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof, among other conventional barrier layer materials. The copper 320 is then deposited by chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form a conductive structure. Once the structure is filled with copper or other conductive material, the surface is flattened by chemical mechanical polishing to create the final damascene structure shown in FIG.

【0068】

A dual damascene structure containing two silicon oxycarbide layers and two silicon carbide cap layers deposited above or a doped silicon carbide cap layer is shown in FIG. The conductive portion 502 is deposited in the substrate 500. The first silicon oxycarbide layer is deposited as the first dielectric layer 510 on a liner or barrier layer 512, eg, the silicon carbide layer described herein. The first silicon carbide cap layer 514 is deposited on top of the first dielectric layer 510 as described herein. The silicon carbide cap layer 514 is pattern etched to reduce the permittivity of the silicon oxycarbide layer and to define vertical connections, eg contact / via openings. In dual damascene construction applications, a second dielectric layer 518 containing a second silicon oxycarbide layer is deposited on top of the patterned silicon carbide cap layer 514. The second silicon carbide cap layer 519 is deposited on top of the second dielectric layer 518 and is pattern etched to define horizontal connections, eg lines. The etching process defines the horizontal connection to the lower first silicon carbide layer 314, which acts as an etching stop, and also defines the vertical connection, and the conductivity in the substrate 500 before filling the connection with the conductive material 526. Performed to expose sex portion 502.

【0069】

Preferred methods for creating the dual damascene structure shown in FIG. 5 are shown sequentially in FIGS. 6A-6E. 6A-6E are cross-sectional views of a substrate on which the steps of the present invention are performed.

【0070】

As shown in FIG. 6A, the first dielectric layer 510 of the silicon oxycarbide material according to the organic silicon compounds and deposition process described herein is a liner or barrier layer, depending on the size of the structure produced. It is deposited on 512 to a thickness of about 5,000 Å to about 10,000 Å. The first dielectric layer 510 may be deposited in a plasma deposition process, but is preferably deposited in a plasma-free deposition process by reacting trimethylsilane with oxygen containing about 15% by weight ozone. The liner layer 512 may be a silicon carbide layer doped with oxygen or nitrogen. Alternatively, the liner / barrier layer 512 may include a conductive material, such as another material that minimizes the oxidation and / or diffusion of copper, such as silicon nitride. Copper may constitute a conductive portion 502 preformed within the substrate 500.

【0071】

As shown in FIG. 6B, the first cap layer 514 containing the silicon carbide layer or the doped silicon carbide layer described herein is then placed on a 200 mm substrate on the first dielectric layer. By reaction of trimethylsilane using RF power of about 10 to about 1000 watts, it is deposited to a thickness of about 200 to about 1000 Å. The first cap layer 514 is then patterned to define the contact / via opening 516 and expose the first dielectric layer 510 in the area where the contact / via is formed, as shown in FIG. 6C. Etched. Preferably, the first cap layer 514 is pattern etched by conventional photolithography and etching processes for silicon carbide films.

【0072】

After the first cap layer 514 has been etched to pattern the contact / via 516 and the photoresist has been removed, the second dielectric layer 518 is about the first dielectric layer 510, as shown in FIG. 6D. As described, it is deposited on the first cap layer 514 to a thickness of about 5000 Å to about 10,000 Å.

【0073】

Next, the second cap layer 519, including the silicon carbide layer or the doped silicon carbide layer described herein, of the second dielectric layer 518, as described for the first cap layer 514. It is deposited above to a thickness of about 200-about 1000 Å. The silicon carbide material may be doped with oxygen or nitrogen. The second cap layer 519 is then patterned to define the line 520 as described for the first cap layer 514, as shown in FIG. 6E. The lines 520 and contact / via 516 are then reactive ion etched to define the metallization structure (ie, the opening to the line or contact / via) and expose the conductive portion, as shown in FIG. 6F. Alternatively, it is etched by another surface anisotropic etching technique. The photoresist or other material used to pattern and etch the second cap layer 519 is removed by an oxygen strip or other suitable process.

【0074】

Following etching of the deposited material and removal of the photoresist material, a second cap layer 519, a second dielectric layer 518, a first cap layer 514, a first dielectric layer 510, and a liner or barrier layer 512. The exposed portion of the contact / via opening 516, line opening 520, and conductive portion 502 are treated by a reactive preclean process to remove contaminants, particulates, residues, and oxides formed on the exposed portion of the conductive portion 502. May be done. The reactive preclean process preferably goes to a plasma containing hydrogen and / or an inert gas, such as argon, at about 0.03 watts / cm.²~ About 3.2 watts / cm²Includes exposing the substrate at a power density of about 10 watts to about 1000 for a 200 millimeter substrate. The processing chamber is maintained at a pressure of about 20 tolls or less and a substrate temperature of about 450 ° C or less during the reactive clean process.

【0075】

The conductive material, such as aluminum, copper, tungsten, or a combination thereof, is then used to form the metallization structure. Currently, due to the low resistivity of copper (1.7Ωcm vs. 5.1Ωcm for aluminum), copper tends to be used to form smaller features. Preferably, as shown in FIG. 6G, the conductive barrier layer 524 is first deposited consistently in the metallization pattern so that copper does not migrate into the surrounding silicon and / or dielectric material. The barrier layer contains titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof, among other conventional barrier layer materials. Copper 526 is then deposited by chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof to form a conductive structure. Once the structure is filled with copper or other metal, the surface is flattened by chemical and mechanical polishing, as shown in FIG.

【0076】

As shown in FIG. 7, the silicon oxycarbide layer and silicon and carbon-containing materials described herein are used in the gap filling process using the CVD chamber previously described with reference to FIG. Can be done. Referring to FIG. 7, at 700, the substrate is placed in the processing chamber 10, and at 705, a silicon carbide dryer layer is deposited by a CVD or plasma CVD process from the reaction of the alkylsilane compound described above, such as trimethylsilane. To. The deposition step 705 can include capacitively coupled plasma in the processing chamber 10, or inductively coupled and capacitively coupled plasma.

【0077】

The silicon oxycarbide gap filled layer is then deposited on the liner layer at 710 by reacting an organic silicon compound, such as trimethylsilane, with a combination of oxidants, such as oxygen and ozone. The gap-filled layer may then be annealed in an inert atmosphere for the time required to remove moisture and solidify the deposited material. Next, at 715, a plasma CVD process deposits a silicon carbide cap layer onto the gap-filled layer from the reaction of the aforementioned alkylsilane compound, eg trimethylsilane, in a plasma containing a relatively inert gas. Will be done. Then, at 720, the substrate is removed from the processing chamber 10.

【0078】

With reference to one embodiment in FIGS. 8A-8E, the three-layer gap filling process involves the reaction of an alkylsilane compound, such as trimethylsilane, to form an amorphous hydrogenated silicon carbide layer as described herein. By producing, the PECVD lining layer 800 is provided. The lining layer 800 acts as an isolation layer between the subsequent organic silicon gap filling layer 802, the underlying substrate surface 804, and the metal wires 806, 808, 810 formed on the substrate surface. The gap filling layer 802 is covered with a capping layer 812 of an amorphous hydrogenated silicon carbide layer. This process is executed and controlled using a computer program stored in memory 38 of computer controller 34 for the CVD processing chamber 10.

【0079】

Referring to FIG. 8A, in one embodiment, the PECVD lining layer 800 is an organic silane compound such as trimethylsilane (CH).₃)₃It is deposited in the processing chamber 10 by introducing SiH and producing a plasma of an inert gas such as helium or argon. One exemplary treatment regime is to introduce trimethylsilane into the treatment chamber at a flow rate of about 30 sccm to 500 sccm and helium, argon, or a combination thereof into the treatment chamber at a rate of about 100 sccm to about 2000 sccm. Introduced, maintain chamber pressure at about 3 to about 10 tolls, maintain substrate surface temperature at about 200 ° C to about 400 ° C, supply about 300 to 700 watts to the chamber for processing. Includes the generation of gas plasma. The distance between the gas dispersion speed 11 and the substrate is about 300 mm to about 600 mm.

【0080】

With reference to FIG. 8B, the gap-filled layer 802 is deposited using the alkylsilane compounds described herein. The preferred treatment gas for the gap-filled layer 802 is trimethylsilane (CH).₃)₃SiH and Ozone O₃Is. In one embodiment, the deposition process introduces trimethylsilane at a flow rate of about 50 sccm to about 500 sccm, preferably about 175 sccm, and a mixture of oxygen and ozone from about 2000 sccm to about 6000 sccm, during the deposition of the gap-filled layer 802. Preferably introduced at a flow rate of about 5000 sccm, where ozone is about 15% by weight of the mixture and trimethylsilane (CH).₃)₃SiH and O₃The chamber pressure is maintained at about 50 to about 500 tolls, preferably about 100 tolls. Prior to depositing the cap layer 812 shown in FIG. 8D, the gap filling layer 802 may be partially cured or annealed to remove solvents such as water, as shown in FIG. 8C. Curing is carried out in the processing chamber 10 by the presence of a relatively inert gas atmosphere, such as noble gas or nitrogen, pumping at a pressure of 10 tolls and a temperature of about 400 ° C. for about 30 minutes. It is said.

【0081】

Referring to FIG. 8D, after the PECVD gap-filled layer 802 is deposited, the amorphous hydrogenated silicon carbide capping layer 812 is deposited on top of the layer 802 by the plasma process described herein. .. With reference to FIG. 8E, after deposition of the capping layer (if any), the gap filling layer 802 is preferably annealed at a temperature of about 100 ° C to about 450 ° C in a solvent or other chamber. Moisture and other solvents are removed. Of course, the treatment conditions will be changed according to the desired properties of the deposited membrane.

【0082】

The description so far has been directed to preferred embodiments of the invention, and other further embodiments of the invention may be devised without departing from the basic scope of the invention.

[Simple explanation of drawings]

[Figure 1]

FIG. 6 is a cross-sectional view of an exemplary CVD reaction chamber configured to be used according to the embodiments described herein.

[Figure 2]

FIG. 5 is a flow chart of a process control computer program product used with the exemplary CVD reaction chamber of FIG.

[Fig. 3]

FIG. 5 is a cross-sectional view showing a damascene structure including a silicon oxycarbide layer and a silicon carbide cap layer described herein.

[Fig. 4A]

FIG. 5 is a cross-sectional view showing one embodiment of a damascene deposition sequence.

[Fig. 4B]

FIG. 5 is a cross-sectional view showing one embodiment of a damascene deposition sequence.

[Fig. 4C]

FIG. 5 is a cross-sectional view showing one embodiment of a damascene deposition sequence.

[Fig. 5]

FIG. 5 is a cross-sectional view showing a dual damascene structure including two silicon oxycarbide layers and two silicon carbide cap layers described herein.

[Fig. 6A]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 6B]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 6C]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 6D]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 6E]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 6F]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 6G]

FIG. 5 is a cross-sectional view showing one embodiment of a dual damascene deposition sequence.

[Fig. 7]

FIG. 5 is a flow chart showing steps taken when depositing a silicon oxycarbide layer and a silicon carbide cap layer in a gap filling process according to another embodiment described herein.

[Fig. 8A]

It is a schematic diagram of the layer deposited on the substrate by the process of FIG.

[Fig. 8B]

It is a schematic diagram of the layer deposited on the substrate by the process of FIG.

[Fig. 8C]

It is a schematic diagram of the layer deposited on the substrate by the process of FIG.

[Fig. 8D]

It is a schematic diagram of the layer deposited on the substrate by the process of FIG.

[Fig. 8E]

It is a schematic diagram of the layer deposited on the substrate by the process of FIG.

[Explanation of symbols]

10 ... Chemical Vapor Deposition Chamber, 11 ... Gas Dispersion Manifold, 12 ... Suceptor, 14 ... Lift Motor 14.