Interconnection circuit and its data transmission method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention generally relates to long interconnects between components of integrated circuits, and particularly to interconnect circuits having a function of interrupting data transmission by long interconnects depending on a congestion state. ..

【0002】

[Conventional technology]

Recent advances in large-scale integrated (LSI) circuit design and manufacturing technology have been remarkable, and interconnect wires commonly used to connect elements of LSI circuits are becoming smaller and smaller. Current interconnect wires are as thin as about 0.2 microns (μm). These micro-level wires can have wiring resistances of up to 300 ohms / mm, which can interfere with high-speed transmission of data signals.

【0003】

The large wiring resistance becomes a problem especially in large-scale LSIs produced in recent years. This is because a large-scale LSI has a large chip area, and the ratio of the portion of the connection portion on the chip that requires a long interconnection wire is increased accordingly. The required interconnect wire length can exceed 10 mm.

【0004】

For example, the wiring resistance, wiring capacitance, the output resistance of the drive circuit for activating the wire, and the input capacitance of the circuit located at the output end of the interconnect (ie, the "downstream" end) are the symbols R1, C1, Rs, respectively. When, and C are assigned, the input / output delay time (that is, latency) of this interconnect wire is expressed by the following equation. Rs * (C1 + C) + R1 * (C1 / 2 + C) [0005]

10 mm long interconnect wire used in next generation LSIs (eg 0.lμm generation CMOS devices) with typical performance (eg R1 = 3,000 ohms, C1 = 2,000fF, Rs = 370 ohms, And for products with C = 28fF), the latency of this 10mm wire is about 3.8ns.

【0006】

The operating frequency of LSIs with this 0.1 μm generation CMOS configuration usually exceeds 1 GHz. Therefore, it can be said that the latency of 3.8 ns is a very large value with respect to the operating frequency.

【0007】

The most common way to reduce the interconnection latency on the chip due to wiring resistance is to insert repeaters (inverter or buffer amplifier type) on the interconnect wires at intervals. However, even when a repeater is inserted, the interconnection latency increases as the LSI process scales, and this latency always causes a decrease in the performance of advanced LSIs.

【0008】

The problem with interconnect latency is significant when the downstream termination of a long interconnect cannot receive data at the same rate as the input endpoint of the interconnect (ie, the "upstream termination") sends the data. It gets worse. In today's widespread systems, for example, if the downstream termination of a long interconnect refuses to receive a data signal sent over an interconnect wire due to congestion, the rejection notice is on the upstream side of the long interconnect. Sent to the end. At this point, data entry at the upstream end of the interconnect is temporarily interrupted, but data passing on the line of the interconnect may be lost. If reception is not possible at the downstream end, it is necessary to either discard the data in the interconnect or temporarily store the data until the downstream end can resume data reception. This data storage function is typically performed by one or more large data buffers at or near the downstream end of the long interconnect.

【0009】

Also, if a signal that refuses to receive data is delayed in reaching the upstream end of the long interconnection (eg, due to latency associated with the interconnection), it is sent from the upstream end to the long interconnection during the latency period. Some data signals are wasted. That is, these data signals are not received at the downstream end even though they are sent from the upstream end. In order to prevent such data signal loss that occurs in this situation, it is necessary to increase the capacity of the data buffer provided at the downstream end of the long interconnection. Providing large data buffers for long interconnects is not only expensive but also inefficient.

【0010】

Further, in the conventional application method, since there is no valid data signal on the long interconnection when the downstream end resumes data reception, until the first data signal reaches the downstream end after the data reception is restarted. Can cause a significant delay (this delay is maximal and equals the latency of the full length of the long interconnect). Such delays can significantly reduce the data transmission rate and the overall throughput of the interconnect.

【0011】

[Problems to be Solved by the Invention]

As mentioned above, the conventional simple method of adding inverters and buffer amplifiers at intervals on the interconnection has a latency during the period until the transmitted data signal is actually received at the downstream end. It has the effect of reducing and increasing data throughput, but is insufficient to address the problems caused by data congestion in interconnects.

【0012】

An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to reduce the latency of long interconnection and at the same time reduce the data loss during congestion in order to create a next-generation high-performance large-scale LSI. To provide a data transmission method.

【0013】

[Means for solving problems]

In order to achieve the above object, the interconnection circuit of the present invention includes a data line for transmitting the data signal and a congestion line for transmitting the congestion signal in the interconnection circuit for transmitting the data signal. It is characterized in that either interruption processing or reestablishment processing of transmission of the data signal in the selected portion of the data line is selected and executed according to the congestion signal.

【0014】

In the interconnect circuit of the present invention of claim 2, the data line transmits the data signal, the congestion line transmits the congestion signal, the direction of transmission of the data signal, and the direction of transmission of the congestion signal. It is characterized in that and are in opposite directions.

【0015】

The interconnect circuit of the present invention according to claim 3 is characterized in that the data line temporarily stores the data signal while the transmission of the data signal is selectively interrupted.

【0016】

The interconnection circuit of the present invention according to claim 4 includes a first terminal for inputting the data signal to the data line and a second terminal for receiving the data signal from the data line, and the congestion signal is the first terminal. It is characterized by showing the status of two terminals.

【0017】

In the interconnect circuit of the present invention of claim 5, the congested line has a speed at which the congested signal indicating that the second terminal cannot receive data is slower than the congested signal indicating that the second terminal can receive data. It is characterized by transmitting by.

【0018】

The interconnect circuit of the present invention of claim 6 comprises one or more additional data lines transmitting additional data signals, said additional data line being in a selected portion of the additional data line. It is characterized in that either the interruption process or the re-establishment process of the transmission of the additional data signal is selected and executed according to the congestion signal.

【0019】

The interconnect circuit of the present invention according to claim 7 is characterized in that the data line and the one or more additional data lines are arranged in parallel.

【0020】

In the interconnect circuit of the present invention of claim 8, the data line selects and executes either the interruption processing or the reestablishment processing of the transmission of the data signal according to the congestion signal, and executes the data signal. It is characterized by including a plurality of data drive circuits for temporarily storing the data signal when the transmission of the above is interrupted.

【0021】

The interconnect circuit of the present invention according to claim 9 is characterized in that the plurality of data drive circuits include at least one of an arithmetic operation function and a logic operation function.

【0022】

The interconnect circuit of the present invention according to claim 10, wherein the data line interrupts the transmission of the data signal in response to the first congestion signal and reestablishes the transmission of the data signal in response to the second congestion signal. It is characterized by comprising one data drive circuit and a second data drive circuit that interrupts the transmission of the data signal in response to the third congestion signal and reestablishes the transmission of the data signal in response to the fourth congestion signal. ..

【0023】

In the interconnection circuit of the present invention according to claim 11, the data line interrupts the transmission of the data signal in response to the first congestion signal and reestablishes the transmission of the data signal in response to the second congestion signal. A plurality of first data drive circuits and a plurality of second data drive circuits that interrupt the transmission of the data signal in response to the third congestion signal and reestablish the transmission of the data signal in response to the fourth congestion signal. It is characterized in that each of the plurality of first data drive circuits and each of the plurality of second data drive circuits are arranged and arranged alternately.

【0024】

In the interconnect circuit of the present invention of claim 12, the congestion line supplies the first congestion signal to the first data drive circuit and supplies the third congestion signal to the second data drive circuit. It is a feature.

【0025】

In the interconnect circuit of the present invention of claim 13, the congestion line supplies the second congestion signal to the first data drive circuit and supplies the fourth congestion signal to the second data drive circuit. It is a feature.

【0026】

The interconnect circuit of the present invention according to claim 14 is characterized in that the first congestion signal is equal to the fourth congestion signal and the second congestion signal is equal to the third congestion signal.

【0027】

The interconnection circuit of the present invention according to claim 15 is an interconnection circuit that transmits a data signal, and is a data line that transmits a data signal from a first terminal to a second terminal, and each of the plurality of data drive circuits. The data line is provided with a congestion line for supplying the congestion signal, and the data line is a plurality of data drives that select and execute either an interruption process or a reestablishment process of transmission of the data signal according to the congestion signal. It is characterized by having a circuit.

【0028】

The interconnect circuit of the present invention according to claim 16 is a plurality of secondary drive circuits in which the congested line transmits the congested signal in the congested line in a direction opposite to the transmission direction of the data signal. It is characterized by having.

【0029】

The interconnect circuit of the present invention according to claim 17 is characterized in that the congestion line sequentially supplies the congestion signal to each of the plurality of data drive circuits from the second terminal to the first terminal. To do.

【0030】

In the interconnect circuit of the present invention according to claim 18, the congestion signal indicates the situation of the second terminal, and the plurality of data drive circuits indicate that the second terminal does not receive data. It is characterized in that the transmission of the data signal is interrupted in response to the congestion signal and the transmission of the data signal is reestablished in response to the second congestion signal indicating that the second terminal is receiving data.

【0031】

The interconnect circuit of the present invention according to claim 19 is characterized in that the first congestion signal is transmitted on the congestion line at a speed slower than that of the second congestion signal.

【0032】

The interconnect circuit of the present invention according to claim 20 is characterized in that the number of the secondary drive circuits is different from the number of the data drive circuits.

【0033】

The interconnect circuit of the present invention according to claim 21 transmits an additional data signal from the first terminal to the second terminal, and either interrupts or reestablishes the transmission of the additional data signal. It is characterized by including a plurality of additional data lines that are selected and executed according to the congestion signal.

【0034】

The interconnect circuit of the present invention according to claim 22 is characterized in that the data line and the plurality of additional data lines are arranged in parallel.

【0035】

The interconnect circuit of the present invention according to claim 23 is characterized in that the data drive circuit temporarily stores the data signal while the transmission of the data signal is interrupted.

【0036】

The interconnect circuit of the present invention according to claim 24 is characterized in that the data drive circuit includes at least one of an arithmetic operation function and a logic operation function.

【0037】

In the interconnect circuit of the present invention according to claim 25, the congestion line supplies the first congestion signal and the second congestion signal, and the data line receives the data signal in response to the first congestion signal. It is characterized in that the transmission is interrupted and the transmission of the data signal is reestablished in response to the second congestion signal.

【0038】

The data transmission method of the present invention according to claim 26 is a data transmission method of an interconnection circuit that transmits a data signal by interconnection, and the interconnection circuit transmits the data signal via a plurality of data drive circuits. A data line for transmitting from the first terminal to the second terminal and a congestion line for transmitting a congestion signal to each of the plurality of data drive circuits are provided, and the data signal in the plurality of data drive circuits is provided. One of the transmission interruption process and the reestablishment process is selected and executed according to the congestion signal.

【0039】

The data transmission method of the present invention according to claim 27 is characterized in that the congestion line includes a plurality of secondary drive circuits that transmit the congestion signal in a direction opposite to the transmission direction of the data signal. To do.

【0040】

The data transmission method of the present invention according to claim 28 is that the data line temporarily stores the data signal while the plurality of secondary drive circuits are interrupting the transmission of the data signal. It is a feature.

【0041】

In the data transmission method of the present invention according to claim 29, the second terminal alternates with the step of transmitting a first congestion signal indicating that the second terminal has not received data and the first congestion signal. A second congestion signal indicating that the data is being received is transmitted, and the first congestion signal is transmitted at a speed slower than that of the second congestion signal.

【0042】

In the data transmission method of the present invention according to claim 30, the interconnection circuit includes a plurality of additional data lines for transmitting additional data signals from the first terminal to the second terminal, and the data line comprises a plurality of additional data lines. It is characterized by comprising a step of selecting and executing either one of the interruption processing and the reestablishment processing of the transmission of the additional data signal according to the congestion signal.

【0043】

The data transmission method of the present invention according to claim 31 is characterized in that the data line and the plurality of additional data lines are arranged in parallel.

【0044】

The data transmission method of the present invention according to claim 32 is characterized in that the plurality of data drive circuits include at least one of an arithmetic operation function and a logic operation function.

【0045】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

【0046】

First, the principle of the present invention will be described in detail.

【0047】

The present invention addresses the above and other disadvantages of conventional methods by providing long interconnects with data and congestion circuits. The data circuit may include an associated data drive circuit for each of the short data wires. It is also possible to cascade the congestion circuit to the data circuit and transmit a congestion signal indicating the status of the downstream end of the interconnection to each data drive circuit. According to the present invention, the effect on the latency of long interconnects caused by wiring resistance is significantly reduced, resulting in increased data throughput in data transmission. Furthermore, by transmitting the status of the downstream termination of the interconnection to the data drive circuit, each data drive circuit functions as a buffer for temporarily storing the data signal, and unnecessary data loss due to the temporary stop of data transmission. Can be prevented.

【0048】

As mentioned above, in order to reduce the effect of wiring resistance on the latency of the entire long interconnect, the long interconnect wire is split into multiple short wires and the drive circuit (including repeater or buffer amplifier) is wired. Can be inserted on a short line of. In other words, the long interconnect wires can be divided into short data wires of a predetermined number n, and a separate data drive circuit can be adopted as a means of activating each data wire. According to one embodiment of the invention utilizing this configuration, n of these units (one unit consists of a data wire and a related data drive circuit for activating it) are mutually exclusive. Combine to form a data circuit (ie, a data line) over the entire length of the interconnect. Data lines can be cascaded to the relevant congestion circuits (ie, congestion lines) in this overall configuration. The data signal can be sequentially transmitted on the data wire constituting the data line according to the signal received from the congested line.

【0049】

Due to this interconnection circuit configuration, data transmission in long interconnection is not only high speed but also very reliable. For example, in the case of the 10mm wire used in the above example, if you divide it into 20 short data wires and insert 20 data drive circuits between the data wires, the resulting data line latency will be It can be expressed by the following formula. 20 * [Rs * (C1 / 20 + C) + R1 / 20 * (C1 / 2/20 + C)] [0050]

If the same values as above are used for all variables, the latency value for the same 10mm interconnect will be reduced to about 1.2ns.

【0051】

Further, using a plurality of data drive circuits as described above means that a plurality of data signals exist at the same time in the long interconnection. Assuming that the data is input to the upstream end of the long interconnect in a cycle of 100 PS and the latency of the long interconnect is about 1.2 ns, which is the same as above, theoretically, the total length of the interconnect is 12 data. The signal will always be present. However, this requires that the cycle of data input to the data wire is longer than the delay time of the data drive circuit. Assuming that 20 data drive circuits in the above example are inserted on the overall length of the interconnection, the delay time between each data drive circuit can be expressed by the following equation. Rs * (C1 / 20 + C) + R1 / 20 * (C1 / 2/20 + C) In the case of the above example, the value calculated by this equation is about 59 ps.

【0052】

Since a plurality of data signals can exist over the entire length of the interconnection, the throughput of the data transmitted on the data line is improved. Since the throughput value is proportional to the reciprocal of the delay time between the data drive circuits, in the above example, the throughput value reaches the theoretical maximum value of 16 Gbps. This value is in contrast to the example of undivided long interconnects. The throughput value achieved with undivided long interconnects is only 0.26 Gbps.

【0053】

According to the interconnection circuit of the present invention that employs a congested line in relation to each data line, it is possible to store the data signal existing in the entire length of the interconnection at the time when the downstream end rejects the data reception. .. Therefore, in the interconnect circuit of the present invention, it is substantially unnecessary to prepare a large-capacity data buffer at or near the downstream end of the interconnect in order to temporarily store these data signals. Even if it is desirable to use a data buffer, a very small data buffer is sufficient in the present invention.

【0054】

Further, in the interconnection circuit of the present invention, unnecessary loss of the data signal transmitted from the upstream end to the long interconnect during the latency period after the downstream end transmits the data reception refusal signal is prevented. In other words, in the present invention, even in the case where the delay time generated until the signal rejecting data reception reaches the upstream end is long, in the present invention, the signal is upstream after the downstream end sends the reject signal. It is not necessary to provide a large-capacity buffer at the downstream end of the long interconnect to temporarily store the data signal sent before it is received by the side end.

【0055】

The features of the interconnect circuit of the present invention are generally summarized as follows.

【0056】

In one embodiment of the invention, the interconnect circuit uses a data line composed of a plurality of short data wires to transmit a data signal from terminal 1 to terminal 2 downstream, said short data. Each of the wires has an associated data drive circuit, which has the function of temporarily interrupting and then reestablishing data transmission on the associated data wire. The data drive circuit can be sequentially replaced between the first type drive circuit (first data drive circuit) and the second type drive circuit (second data drive circuit), and can operate in response to a signal from a congested line. A congested line consisting of a plurality of short congested wires transmits a congested signal from the third terminal to the fourth terminal in the direction opposite to the data signal transmission (that is, in the upstream direction), and each of the short congested wires is related. It has a secondary drive circuit. The congestion signal can indicate the status of these second terminals.

【0057】

According to the present embodiment, the interconnect circuit selectively activates and deactivates the output terminal of the data drive circuit, thereby causing the data transmission in each data drive circuit to be terminated from the downstream end to the upstream end of the interconnection. Suspend and reestablish in order towards. Both the congestion signal that interrupts data transmission and the congestion signal that reestablishes data transmission can propagate at the same rate on the congestion line until they reach all secondary drives sequentially upstream.

【0058】

According to another embodiment of the present invention having the same overall configuration as described above, again, the interconnect circuit transmits a data signal from the downstream first terminal to the second terminal depending on the situation of the second terminal. .. However, in the present embodiment, the congestion signal that interrupts the data transmission propagates on the congestion line in order from the secondary drive circuit closest to the downstream end toward all other secondary drive circuits at a relatively low speed. can do. Regarding the speed at which the congestion signal that interrupts this data transmission propagates upstream on the congestion line, two or more consecutive data signals in the data line are input to the same data drive circuit, and the data of the data drive circuit is input. As long as the condition that transmission activity should not be temporarily interrupted is satisfied, it can be reduced to the maximum.

【0059】

Each data drive circuit can function as a data buffer while the data signal is not being transmitted. Further, each data drive circuit may be provided with a congestion input terminal for receiving a signal from a congestion line indicating the status of the second terminal. Appropriate congestion signals are sequentially transmitted upstream from the end of the second terminal side of the interconnection to the data drive circuit in the data line. As an example, the signals input to the congestion input terminal of the data drive circuit in the data line are counted from the data drive circuit closest to the second terminal of the interconnection, A (1), A (2), A (3). ), ..., A (n). The output signal of the secondary drive circuit in the congested line counts from the secondary drive circuit data closest to the third terminal (that is, the downstream end of the interconnection), B (1), B (2), B ( 3), ..., B (n). In this case, A (l) = B (1), A (2) = B (2), A (3) = B (3), ..., A (n) = B (n).

【0060】

The speed at which the data drive circuit starts from the data drive circuit closest to the end on the 2nd terminal side and interrupts the activity of the individual data wires upstream toward the 1st terminal, and the data drive circuit causes the individual data wires. Can be reactivated at equal rates.

【0061】

In the interconnect circuit configured according to the embodiment of the present invention, if the number of secondary drive circuits in the congested line is k * m and the number is different from the number of data drive circuits n in the data line, the following It is expressed by the formula of. A (1) = A (2) = ... = A (k) = B (1), A (k + 1) = A (k + 2) = ... = A (2 * k) = B (2), ... A (k * m-k + 1) = A (k * m-k + 2) = ... = A (k * m) = B (n) [0062]

The time required to transmit the data signal from the 1st terminal to the 2nd terminal is Td, the time required to transmit the congestion signal from the 3rd terminal to the 4th terminal is Tb, and the number of data drive circuits is n, 2. Assuming that the number of next drive circuits is m and the minimum time required to input one data signal to the first terminal of the data line is Ts, the value of Tb / m does not exceed the difference (Ts-Td / n). Can be maximized within range. This limitation prevents two or more consecutive data signals from being input to the data drive circuit that is deactivated according to the signal received from the congested line.

【0063】

Further, the present invention is also effective for interconnections including a plurality of parallel 1-bit data lines, each of which is generally configured by the method described above. In such an embodiment, each individual data line is composed of individual data wires, and individual data drive circuits are connected to the individual data wires in an alternating manner. This alternating connection is made between the first type of drive circuit and the second type of drive circuit, as described above.

【0064】

When a plurality of data lines are created in parallel along the entire length of the interconnection in this way, each data drive circuit can be numbered in ascending order of distance from the first terminal, for example. By assigning a common signal sent from the congested line to determine whether to activate the individual data wire of each data drive circuit with the same number counting from the 1st terminal side, the first The entire bit length of the data message transmitted from the 1st terminal to the 2nd terminal can be longer than 1 bit.

【0065】

Further, in the above-described embodiment, as a feature of the interconnection circuit based on the present invention, it can be mentioned that various drive circuits have a function of arithmetic operation or logical operation.

【0066】

Next, referring to the drawings, FIG. 1 is a schematic diagram of an interconnect circuit according to a first embodiment of the present invention. According to the present invention, an interconnect circuit is provided for transmitting a data signal from the first terminal to the second terminal via a long interconnect. In FIG. 1, data transmission is performed from left to right. The data circuit, that is, the data line 20, may be provided with a predetermined number n of data wires 1. The data flow in each data wire 1 can be selectively interrupted and reestablished by the associated data drive circuit 2a or 2b. As described below, the data drive circuit 2a and the data drive circuit 2b can have different overall configurations, and can be arranged alternately. Each of the data drive circuits 2a and 2b can be provided with a function of temporarily suspending or reestablishing data transmission in each individual data wire 1. In the present embodiment, as shown in FIG. 1, n units including the data wire 1 and the data drive circuit 2a or 2b can be cascaded to the congestion line 30.

【0067】

As detailed below, the congestion signal for interrupting data transmission and the congestion signal for reestablishing data transmission are congested wires 3 of a predetermined number (which may not be equal to n) of the congested line 30. It is transmitted from the third terminal to the fourth terminal via. These congestion signals indicating the data reception status of the second terminal are propagated through the congestion wire 3 by the related secondary drive circuit 4. In the cascade connection configuration illustrated in FIG. 1, the data drive circuits 2a and 2b receive signals through the congestion input terminal 5 and are interconnected from the second terminal end (ie, the "downstream" end) to the first terminal. Data signals can be interrupted or reestablished in sequence up to the side termination (ie, the "upstream" termination).

【0068】

In other words, if the second terminal of the interconnection refuses to receive data, a congestion signal for temporarily interrupting data transmission can be transmitted from the third terminal to the fourth terminal. The direction in which the congestion signal is transmitted is from right to left in FIG. 1 (the direction opposite to the data transmission).

【0069】

That is, the data signal is propagated downstream from the end of the 1st terminal side of the interconnection to the end of the 2nd terminal side, and the congestion signal is propagated in the direction of the end of the 2nd terminal side of the interconnection to the end of the 1st terminal side. Can be considered. When the congestion signal for interrupting data transmission reaches the fourth terminal at the upstream end of the interconnection, multiple data signals can be stored in the data line. At the same time, the upstream end of the interconnect (ie, the first terminal) is notified that the downstream end of the interconnect (ie, the second terminal) has refused to receive data.

【0070】

According to this embodiment, a plurality of data signals existing on the entire length of the interconnection circuit at the time when the second terminal refuses to receive data are not discarded, resulting in waste. Therefore, each of the data drive circuits 2a and 2b of FIG. 1 can be provided with a function of operating as a data buffer and temporarily storing a data signal (that is, while data transmission is interrupted).

【0071】

As a result, it is not necessary to provide a separate large-capacity data buffer for temporarily storing these data signals at or near the second terminal.

【0072】

Even in cases where the delay time that occurs before the signal that refuses to receive data reaches the upstream end of the interconnection becomes long, the data signal is safely stored in the data drive circuits 2a and 2b during this latency period. , The first terminal does not cause waste by transmitting a data signal to the data line 20 during the delay time. Therefore, it is not necessary to provide a large-capacity data buffer at or near the second terminal.

【0073】

As described above, the congestion signal indicating the status of the second terminal can be sequentially transmitted from the downstream end of the interconnection to the data drive circuits 2a and 2b in the direction of the first terminal. In the present embodiment, the transmission speed of the congestion signal for temporarily interrupting the data transmission can be the same as the transmission speed of the congestion signal for reestablishing the data transmission. In this case, when the second terminal resumes data reception, there is a correlation between the time required for the data signal to reach the second terminal immediately after the restart of data reception and the latency of the entire long interconnection. do not. Further, the speed at which the data signal is transmitted to the second terminal can be equal to the speed at which the data signal is transmitted from the first terminal. This is because the data signal is temporarily stored in the data drive circuits 2a and 2b installed on the entire length of the interconnection, so that this data transfer rate is achieved at the same time as the data reception at the second terminal is restarted. ..

【0074】

In another embodiment of the invention, the rate at which the congestion signal for interrupting data transmission propagates upstream can be slower than the rate at which the congestion signal for reestablishing data transmission propagates upstream. Even after deceleration, the speed of the congestion signal for interrupting data transmission is the same data drive circuit 2a in which two consecutive data signals input to the data line 20 are temporarily stopped in data transmission activity. Or it is enough to prevent simultaneous input to 2b. In the present embodiment, the number of data signals that can be temporarily stored in the data line 20 can be increased while the second terminal refuses to receive data.

【0075】

Examine Figure 1 in more detail. A (1) to A (n) indicate the potential difference at the convergence input terminal 5 of each individual data drive circuit 2a and 2b. B (1) to B (n) indicate the potential difference at the output terminal 11 of each individual secondary drive circuit 4. C (l) to C (n) indicate the potential difference at the output of each data drive circuit 2a and 2b. Numbers are assigned in order from the downstream end of the interconnect to the upstream end.

【0076】

FIG. 2 is a schematic diagram of an embodiment of the data drive circuit 2a intended for use in the embodiment illustrated in FIG. FIG. 3 is a schematic diagram of an embodiment of the data drive circuit 2b intended for use in the embodiment illustrated in FIG. FIG. 4 is a schematic view of an embodiment of the secondary drive circuit 4 intended for use in the present invention.

【0077】

In the operation of the interconnection circuit, a data signal is input at the first terminal, transmitted via a data line 20 composed of a plurality of data wires 1 driven by individual data drive circuits 2a or 2b, and second. It can be output to the terminal. The data drive circuit 2a or 2b closest to the first terminal receives the data input via the data wire 1 connected to the input terminal 8 and activates the data wire 1 connected to the output terminal 9. To become. The data wire 1 connected to the output terminal 9 is connected to the input terminal 8 of the next data drive circuit 2a or 2b, and so on. In this way, the data signal is sequentially transmitted to the data drive circuits 2a and 2b between the first and second terminals. As described below, the activation of each data wire 1 can be selectively interrupted and reestablished by the data drive circuits 2a and 2b according to the signal received at the congestion input terminal 5.

【0078】

FIG. 2 shows an embodiment of the data drive circuit 2a (first data drive circuit). When the potential difference level at the congestion input terminal 5 is high (second congestion signal), the data wire 1 connected to the output terminal 9 is activated. On the contrary, when the potential difference level at the congestion input terminal 5 is low (first congestion signal), the data transmission is temporarily interrupted. The data transmission function and the data buffer function of the data drive circuit 2a are realized by the configuration of the plurality of nMOS transistors 6 and the plurality of pMOS transistors 7 shown in the figure. FIG. 3 shows in detail an embodiment of a data drive circuit 2b (second data drive circuit) in which the configurations of the transistor 6 and the transistor 7 are slightly different. In the present embodiment, when the potential difference level at the congestion input terminal 5 is low (fourth congestion signal), the data wire 1 connected to the output terminal 9 is activated. On the contrary, when this level is high (third congestion signal), data transmission is temporarily interrupted.

【0079】

When the embodiment shown in FIG. 4 is implemented as the secondary drive circuit 4 of FIG. 1, when the potential difference level of the third terminal is low, the potential difference of the output terminals 11 of each secondary drive circuit 4, that is, B (l), The levels of B (2), ..., B (n-2), B (n-1), B (n) are repeated alternately high, low, high, low ... Similarly, when the potential difference level of the third terminal is high, the potential differences B (l), B (2), ..., B (n-2), B (n-1), B (n) in FIG. 1 The levels are low, high, low, high ... This alternating potential difference is generated by transistors 6 and 7 aligned in each secondary drive circuit 4.

【0080】

As briefly mentioned above, in the embodiment illustrated as an example in FIG. 1, alternating connection type data drive circuits 2a and 2b are adopted. That is, one embodiment of the data drive circuit 2a shown in FIG. 2 and the other embodiment of the data drive circuit 2b shown in FIG. 3 are alternately used in order from the data drive circuit 2a closest to the second terminal. .. As shown in the figure, when such a configuration is cascaded to the congestion line 30 that employs the secondary drive circuit 4, if the potential difference level of the third terminal is low, the data signal will be transmitted from the first terminal in the data line 20. If the data signal is transmitted in the direction of the second terminal and the potential difference level of the third terminal is high, the data signal is not transmitted in the data line 20.

【0081】

As an example, consider the case where the potential difference level of the third terminal changes from low to high. In this case, the change in this signal propagates in the form of a congestion signal indicating that the second terminal has previously refused to receive data. The congestion signal propagates upstream from the third terminal to the fourth terminal in each of the continuous secondary drive circuits 4. That is, the potential difference at the output terminal 11 of each secondary drive circuit 4 is in the order of B (1), B (2), ..., B (n-2), B (n-1), B (n). to be influenced. As the congestion signal moves upstream, the activity of the data wire 1 is temporarily interrupted by the data drive circuits 2a and 2b in order from the data drive circuit 2a closest to the end of the second terminal side of the data line 20. ..

【0082】

FIG. 5 shows the output terminals 9 (ie, C) of the data drive circuits 2a and 2b immediately after the potential difference level of the third terminal changes from low to high (that is, immediately after the generation of the congestion signal indicating the refusal of data reception). It is a figure which shows the data signal which exists in (n), C (n-1), C (n-2), ..., C (1)). Figure 6 shows C (n), C (n-1), and C (n-2) when the congestion signal indicating that the second terminal refused to receive data propagated to half the distance of the interconnect circuit. ), ..., It is a figure which shows the data signal existing in C (1). Figure 7 shows C (n), C (n-1), C (n-2), and. .., It is a figure which shows the data signal existing in C (1).

【0083】

At the time shown in FIG. 5, at the moment when the second terminal refuses to receive the data, the five data signals A to E are in the process of being transmitted in the long interconnection circuit of the present invention. FIG. 5 illustrates a case where the latency of the long interconnection is 5 times that of the data signal cycle transmitted from the first terminal.

【0084】

In FIG. 6, since the data drive circuits interrupt the data transmission in order from the downstream end of the interconnection, the number of data drive circuits that output the data signal gradually decreases. In addition, since a certain amount of time has passed since the congestion signal propagated from the third terminal, new data signals F and G are input to the data line.

【0085】

In FIG. 7, all the data drive circuits in the data line interrupt the data transmission, and the data signal is not propagating. In addition, since it took more time for the congestion signal to propagate to the fourth terminal, new data signals H and I in addition to the data signals A to G are input to the data line from the end of the interconnection on the first terminal side. .. However, at this point, the 1st terminal has been notified of the refusal of data reception by the 2nd terminal, so it will be longer until the congestion signal indicating the resumption of data reception by the 2nd terminal reaches the 4th terminal. No data signal is input to the data line.

【0086】

Next, consider the case where the second terminal is ready to receive the data signal and the potential difference level of the third terminal changes from high to low. In this case, the congestion signal indicating the restart of data reception at the second terminal is displayed on the secondary drive circuit by the congestion line as B (1), B (2), ..., B (n-2), B ( It is transmitted in the order of n-1) and B (n). As the congestion signal indicating the resumption of data reception moves upstream, the data drive circuit reestablishes data transmission in order from the data drive circuit closest to the end on the second terminal side of the interconnect circuit. As described above, the input of the new data signal to the data line is stopped until the first terminal receives the notification of the data reception status of the second terminal, while the congestion signal propagates toward the upstream end of the interconnection. As a result, the data signals existing on the data line are exhausted.

【0087】

Figure 8 shows C (n), C (n-1), C (n-2), ..., C ( It is a figure which shows the data signal existing in 1). Figure 9 shows C (n), C (n-1), C (n-2), ..., C (1) when the congestion signal indicating the resumption of data reception propagates the entire length of the interconnection. It is a figure which shows the data signal which exists in.

【0088】

In FIG. 8, since the data drive circuits reestablish data transmission in order from the end of the interconnection on the second terminal side, the number of data drive circuits that output data signals is increasing. Also, since a certain amount of time has passed since the congestion signal indicating the resumption of data reception propagated upstream from the 3rd terminal (that is, after the potential difference level of the 3rd terminal changed from high to low). The data signals A and B have already been output to the second terminal. These data signals no longer exist in the data line.

【0089】

As shown in FIG. 7, since the congestion signal initially transmitted from the 3rd terminal indicating the refusal of data reception reached the 4th terminal, the number of data lines in the data line is compressed in a form larger than that in FIG. It becomes possible to store between the 1st terminal and the 2nd terminal.

【0090】

As shown in FIGS. 8 and 9, when a congestion signal indicating the resumption of data reception propagates upstream from the third terminal to the fourth terminal of the congestion line through the secondary drive circuit, one signal. Propagate through each individual congestion input terminal to the data drive circuit. This propagation sequentially reestablishes the data transmission in the data wire, and as a result, the above data signal compressed in the data line is gradually decompressed and output to the second terminal.

【0091】

In other words, when the second terminal refuses to receive data (that is, when the potential difference level of the third terminal changes from low to high), the multiple data signals existing in the interconnect circuit are the interconnect circuit. It is automatically stored in a compressed form inside and is not destroyed unnecessarily. These data signals are temporarily stored in the data drive circuit until the second terminal can receive the data. Further, it is not necessary to prepare a large-capacity data buffer near the second terminal for temporarily storing these data signals while the second terminal rejects the data.

【0092】

Further, as described above, even in the case where the propagation time generated until the congestion signal reaches the upstream end of the interconnection becomes long, the data signals transmitted from the first terminal during the latency period of the congestion signal are mutual. It is safely stored in the connected data line and is not unnecessarily transmitted over the data line. Nor is it necessary to have a large data buffer at the downstream end of the interconnect circuit to store these additional data signals.

【0093】

Similarly, as described above, both the congestion signal indicating the refusal of data reception by the second terminal and the congestion signal indicating the resumption of data reception by the second terminal are terminals 3 to 4 on the congestion line. It can be transmitted at the same speed in the upstream direction toward. In this case, when the second terminal resumes data reception, there is no correlation between the time required for the data signal to reach the second terminal immediately after the restart of data reception and the latency of the entire interconnection. .. Further, the speed at which the data signal is transmitted to the second terminal can be equal to the speed at which the data signal is transmitted from the first terminal. This is because the data signal is temporarily stored in the data drive circuit installed over the entire length of the interconnection, so that this data transfer rate is achieved at the same time as the restart of data reception at the second terminal.

【0094】

In another embodiment of the present invention, the transmission speed of the congestion signal indicating the refusal of data reception can be slower than the transmission speed of the congestion signal indicating the resumption of data reception by the second terminal. The congestion signal that interrupts data transmission propagates upstream at a sufficient speed even if it slows down, so the data transmission activity of two consecutive data signals input to the data line is temporarily stopped. It is not input to the same data drive circuit at the same time. In this embodiment, as shown in FIG. 7, the number of data signals that can be temporarily stored in the interconnected data line can be increased while the second terminal refuses to receive data.

【0095】

Next, returning to the example taken above, consider an interconnect wire with a length of 10 mm. This long interconnect wire has typical values for 0.1 μm generation CMOS devices (ie, wire resistance R1 = 3,000 ohms, wire capacitance C1 = 2,000 fF, drive circuit output resistor Rs = 370 ohms, which activates the wires. And it is assumed that it has a capacity C = 28fF) at the end of the output. The latency of this 10mm wire is about 3.8ns. If this wire is split into 20 short data wires and the 20 data drive circuits described above are inserted into a 10 mm wire, the latency of the interconnect circuit will be 1.2 ns.

【0096】

The data input speed of the data signal entering the long interconnection can be, for example, 5 Gbps. This is also a typical value for a 0.1 μm generation CMOS device. For a single long interconnect wire using the above parameters, the delay time that occurs before the second terminal receives the first data signal after resuming data reception is 1.2 ns. On the other hand, according to the present invention, the delay time that occurs until the second terminal receives the first data signal after resuming data reception does not exceed the data cycle of the data signal, so that the maximum is 200 ps. Therefore, in the interconnection circuit according to the present invention, 6 to 7 pieces of data are stored within the time required for the second terminal to receive the first data signal after resuming data reception in the conventional long interconnection wire. It will be understood that the signal is transmitted to the second terminal.

【0097】

In order to maximize the number of data signals compressed and stored in the interconnect circuit while the data transmission is temporarily interrupted, the congestion signal for interrupting the data transmission is the secondary of the congestion line. It is necessary to reduce the speed transmitted on the drive circuit. Even if it slows down, the speed of the signal to interrupt the data transmission is sufficient, so two or more consecutive data signals input to the data line are the same with the data transmission activity temporarily stopped. It is not input to the data drive circuit at the same time. This state is ensured by:

【0098】

The time required to transmit the data signal from the 1st terminal to the 2nd terminal is Td, the time required to transmit the congestion signal from the 3rd terminal to the 4th terminal is Tb, and the number of data drive circuits in the data line is n. , If the number of secondary drive circuits in the congested line is m and the minimum time required to input the data signal to the first terminal of the interconnect circuit is Ts, the value of Tb / m is the difference (Ts-Td / n). ) Can be maximized within the range that does not exceed.

【0099】

As a method of maximally increasing the value of Tb as described above, an additional embodiment of the secondary drive circuit 4 can be implemented in the configuration as shown in FIG. FIG. 10 relates to this and is a schematic diagram of another embodiment of the secondary drive circuit 4 intended for use according to the present invention. In the embodiment shown in FIG. 10, the CMOS inverter circuit between the input terminal 10 and the output terminal 11 is larger in size and more complicated than the embodiment shown in FIG. When this configuration is adopted, the latency of the congestion line 30 of FIG. 1 using the embodiment of the secondary drive circuit 4 shown in FIG. 10 is increased by that amount.

【0100】

According to the above description of several embodiments of the present invention, the length of the data signal transmitted over the data line can be one bit. However, in still another embodiment of the present invention, a plurality of data lines having a configuration similar to that of the data line 20 shown in FIG. 1 can be arranged in parallel. As an example of such an interconnection circuit, FIG. 11 shows a plurality of parallel data lines 20.₁~20₃An embodiment in which the above is adopted is shown. In this figure, data line 20 gives priority to clarity.₁~20₃Although the number of data lines is limited to three, it will be understood that it is desirable to have a larger number of data lines.

【0101】

As shown in FIG. 11, the congestion input terminal 5 can be shared. 20₁~20₃By cascading a plurality of data lines such as, etc. in parallel, a multi-bit signal can be transmitted by the same method as described above. That is, individual data line 20₁~20₃Each of them transmits one bit of a multi-bit data signal. For example, when k parallel data lines are incorporated in an interconnection circuit, a k-bit signal can be transmitted from the first terminal to the second terminal.

【0102】

In still other embodiments, the data drive circuit and the secondary drive circuit, which have been described and illustrated as mere amplifier circuits, can be changed to circuits having arithmetic or logical operation functions.

【0103】

Those skilled in the art will appreciate that the interconnect circuits described herein can always achieve maximum data throughput from the moment data reception is resumed at the second terminal of the interconnect. Will. Similarly, this data throughput is not hampered by the latency of long interconnects.

【0104】

Further, the data drive circuit inserted in the data line over the entire length of the interconnect circuit can function as a data buffer for temporarily storing the data signal. This is in contrast to traditional drive circuits, which only serve to reduce the latency of long wires and increase maximum data throughput.

【0105】

Further, when the second terminal of the long interconnect circuit refuses to receive data, it is not necessary to discard the data signal existing in the data line of the interconnect circuit of the present invention, and the congestion signal moves on the congestion circuit. There is no need to discard the data signal input to the data line during the process.

【0106】

As described above, the interconnect circuits of the present invention can provide maximum data throughput while minimizing data loss and inefficiency. The preferred embodiments disclosed herein are merely illustrated and illustrated as examples and do not impose any restrictions.

【0107】

Although the present invention has been described above with reference to preferred embodiments and examples, the present invention is not necessarily limited to the above embodiments and examples, and is variously modified within the scope of the technical idea. Can be carried out.

【0108】

The interconnect circuit of the present invention can not only transmit a digital signal as a data signal but also an analog signal. When transmitting an analog signal as a data signal, the following applications can be considered. For example, a high-speed analog signal can be temporarily confined in an interconnect circuit, and the time width of the confined analog signal can be widened to output from the interconnect circuit. In this case, the interconnect circuit will function as an analog memory or as a converter from a high speed analog signal to a low speed analog signal (or vice versa).

【0109】

[Effect of the invention]

As described above, the interconnect circuit of the present invention and its data communication method can provide maximum data throughput while minimizing data loss and inefficiency.

【0110】

According to the present invention, it is possible to increase the throughput of data in data transmission by significantly reducing the influence on the latency of long interconnection caused by wiring resistance. Furthermore, by transmitting the status of the downstream termination of the interconnection to the data drive circuit, each data drive circuit functions as a buffer for temporarily storing the data signal, and unnecessary data due to a temporary stop of data transmission. Loss can be prevented.

【0111】

Also, according to the present invention, the data flow in each data wire of the data line can be selectively interrupted and reestablished by the associated data drive circuit.

【0112】

In addition, the data signal is transmitted from the first terminal at the speed at which the data signal is transmitted to the second terminal by temporarily storing the data in the data drive circuit installed on the entire length of the interconnection. Can be equal to the speed of the case.

[Simple explanation of drawings]

[Figure 1]

It is the schematic of one Embodiment of the interconnection circuit of the 1st Embodiment of this invention.

[Figure 2]

It is the schematic of one Embodiment of the data drive circuit of the 1st Embodiment of this invention.

[Fig. 3]

It is the schematic of the other embodiment of the data drive circuit of the 1st Embodiment of this invention.

[Fig. 4]

It is the schematic of one Embodiment of the secondary drive circuit of the 1st Embodiment of this invention.

[Fig. 5]

It is a figure which shows the data signal which exists in the interconnection circuit of this invention immediately after the 2nd terminal refuses the reception of data.

[Fig. 6]

It is a figure which shows the data signal existing in the interconnect circuit of this invention at the time when the congestion signal which shows that the 2nd terminal refused to receive data propagated to half the distance of the interconnect circuit.

[Fig. 7]

It is a figure which shows the data signal which exists in the interconnect circuit of this invention at the time when the congestion signal which shows that the 2nd terminal refused to receive data propagated to the whole interconnect circuit.

[Fig. 8]

It is a figure which shows the data signal existing in the interconnect circuit of this invention at the time when the congestion signal which shows that the 2nd terminal resumed the reception of data propagated to half the distance of the interconnect circuit.

[Fig. 9]

It is a figure which shows the data signal which exists in the interconnect circuit of this invention at the time when the congestion signal which shows that the 2nd terminal has resumed the reception of data propagated to the whole interconnect circuit.

[Fig. 10]

It is the schematic of the secondary drive circuit of another embodiment of this invention.

[Fig. 11]

It is the schematic of the interconnection circuit which adopted the structure in which a plurality of data lines of the other embodiment of this invention are arranged in parallel.

[Explanation of symbols]

1 data wire 2a data drive circuit 2b data drive circuit 3 Congestion wire 4 Secondary drive circuit 5 Congestion input terminal 6 transistor 7 transistor 8 Input terminal 9 Output terminal 10 Input terminal 11 Output terminal 20, 20₁~20₃ Data line 30 Congested line