Asymmetric data path medium access controller

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

Cross-reference to related applications This application is the priority of inventor Michael Tate, US Provisional Patent Application No. 60 / 234,396, entitled "Asymmetric Data Path Medium Access Controller" filed September 21, 2000, the contents of which are incorporated herein by reference. It claims the right.

【0002】

[Technical field to which the invention belongs]

The present invention relates to methods and devices for maintaining throughput of data elements, and more specifically, methods and devices for maintaining throughput of data elements by using sampling methods that increase the number of bits in the output compared to the input. Regarding the device.

【0003】

[Conventional technology]

The Institute of Electrical and Electronics Engineers (IEEE) standard 802.3ae, named "10 Gigabit / s Ethernet Expert Committee," provides native connections to local area networks (LANs), metropolitan area networks (MANs), wide area networks (WANs), etc. Defines an industrial standard of Gigabit per second for interconnecting high-performance switches, routers, servers, etc. in the Internet. The two features described in this 802.3ae standard are the 32-bit data path and clock. In operation, this 32-bit data and clock is received by the physical layer device and sent to the medium access controller (MAC) via the medium independent interface (MII).

【0004】

The MAC resides on the data path between the physical layer controller (PHY) and the packet switching controller (PSC). According to industry standards, MACs need to support certain standardized features and functions. However, MAC designers are often flexible in deciding how to respond to standardized features and features.

【0005】

The data transmission rate of a data path is generally the product of the data path width and the data sampling rate. In addition, if the same total total throughput is maintained in the pipelined system, the clock frequency of the data transmission system is inversely proportional to the data path width. It is known to implement Ethernet MAC layer logic as a set of receive and transmit data paths of the same bit width in which operations are performed. Thus, receive and transmit data paths of the same magnitude in a MAC application will require the same clock frequency for each path.

【0006】

[Problems to be Solved by the Invention]

The desired clock frequency for the transmit data path is easily generated by an external commercially available oscillator. However, the receive clock for the receive data path is derived from the IEEE specification MII receive data clock. However, the clock frequency provided by the specified MII is not suitable for using only the rising edge sampling of 32-bit wide data, for example, to maintain a particular data rate, such as a 10 Gbps data transmission rate. .. In fact, the receive clock provided by MII, standardized by the IEEE standard, is about half the frequency required to generate the desired 32-bit data path at a transmitting 10 Gbps data rate.

【0007】

Disadvantages of traditional methods of maintaining data throughput at high data rates indicate that there is a need to maintain high data throughput for data elements that meet the standard features standardized by IEEE 802.3ae.

【0008】

[Means for solving problems]

An exemplary embodiment of the invention provides an asymmetric data path that achieves high data throughput, eg, 10 Gbps or higher. According to this exemplary embodiment, the desired clock frequency for the transmit data path can be generated by an external, commercially available oscillator. However, the receive clock is derived from a normalized clock with a frequency that would otherwise be too slow to accommodate the data throughput rate using conventional methods. Thus, an exemplary embodiment of the invention includes an asymmetric data path in which the width of the receive data path is greater than the width of the transmit data path in order to accept different clock rates for the receive and transmit data paths.

【0009】

Therefore, an exemplary way to maintain the throughput of a data path is to receive a clock, and multiple instances of data with a first width at the input, and two instances of data with a second width. In order to create the above, it is a step of processing each consecutive instance of a plurality of instances of data having the first width, the second data width is equivalent to the first data width, and the second data. Two or more of the multiple instances of data with width are used to create multiple instances of data with a third data width, the third data width is larger than the second data width, and the third Multiple instances of data with a data width of are used to create multiple instances of data with an output data width, and the output data width is equivalent to the third data width, and the output data width. Includes the step of sending multiple instances of data with.

【0010】

The present invention introduces, for example, a 10 Gigabit Ethernet MAC receiving functional element without introducing the unnecessary risks and complications associated with the use of multiple clock samplings or rising and falling edge sampling through the receiving functional element. Provides a way to maintain the throughput of data elements. In another embodiment of the invention, the method comprises receiving a first plurality of instances of data having a clock and a first bit width as inputs in a first element, a clock, and a first. The step of sending the first plurality of instances of data having a width of 1 to the second element, and the first width to create the second plurality of instances of data having a second width. It has a step of processing a first plurality of instances of data having a clock, and a step of transmitting a second plurality of instances of data having a second width to a third element, and a third width. To create a third plurality of instances of data, a step of processing the second plurality of instances of data having a second width, and a third plurality of instances of data having a third width. It includes a step of sending to the 4 elements and a step of processing the third plurality of instances of the data having the third width in order to create the fourth plurality of instances of the data having the fourth width.

【0011】

In another embodiment of the invention, the method comprises receiving a first piece of data having a first bit width bit, a management bit, and a clock bit, and a first bit width bit, and a clock bit. Is included in the received data path, and the first bit width bit is processed to generate processed data having a second bit width greater than the first bit width.

【0012】

In another embodiment of the invention, the switch is combined with one or more ports that receive a plurality of inbound packets and transmit the plurality of outbound packets and an input port to receive the plurality of inbound packets. To be coupled to a tier device, a physical layer device to receive multiple inbound packets from the physical layer device, and a media independent interface to receive the output of the media independent interface and increase the bit width. Includes a media access controller that processes the output of the media independent interface and a packet switching controller that is coupled to the media access controller to receive increased bit width data and transmit increased bit width data.

【0013】

In another embodiment of the invention, the media access controller follows the first rising edge of the clock, the first gate that samples the input data stream with the first bit width, the first falling edge of the clock. According to the second rising edge of the clock, the second gate to sample the input data stream, and an output data stream having a second bit width greater than the first bit width. Includes a third gate coupled to the first and second gates that combines the outputs of the first and second gates.

【0014】

In yet another embodiment of the invention, the media access controller receives input data in a first data path having a first bit width and in the first bit width and is greater than the first bit width. Includes a second data path that includes a receive function element that processes the input data to create output data with a second bit width.

【0015】

The above and other features, aspects, and advantages of the present invention will be better understood in light of the following description, claims, and accompanying drawings.

【0016】

BEST MODE FOR CARRYING OUT THE INVENTION

An exemplary embodiment of the invention uses a standardized clock with a frequency that would otherwise be too slow to accommodate data throughput rates using conventional methods, eg. It provides an asymmetric data path that achieves high data throughput of 10 Gbps. In order to understand the advantages of the present invention, it is useful to illustrate the present invention, for example in the flow of an exemplary network system of high speed Ethernet switches. Those skilled in the art will appreciate that the invention is not limited to one exemplary embodiment described. Instead, the invention can be utilized to provide higher throughput data rates in any symmetric or asymmetric data path.

【0017】

FIG. 1 is a simplified block diagram showing an exemplary operating environment of the present invention. According to one exemplary embodiment, one or more media independent interfaces (MII) 114 (a) and 114 (b), one or more PHY 108 (a) and 108 (b), and one or more. Switch 100, which includes multiple MACs 104 (a) and 104 (b), is a packet switching controller (PSC) 102 and, for example, an Ethernet telephone running on a personal computer (PC) or LAN 112 (a) and 112 (b). Provides two-way communication with the device.

【0018】

The media independent interfaces 114 (a) and 114 (b) provide bidirectional interfaces between PHY 108 (a) and 108 (b) and MAC 104 (a) and 104 (b), respectively. It is preferable that the PHY 108 (a) and 108 (b) receive the inbound packet and transmit the outbound packet to the LAN 112 (a) and 112 (b), respectively. The PHY preferably performs flow independent physical layer processing on inbound packets. According to one exemplary embodiment, the PHY can perform all physical layer interface (PHY) functions for full-duplex or half-duplex Ethernet.

【0019】

For example, in one exemplary embodiment described, the PHY may also decode received data packets and encode output data packets according to various standards such as 4B5b, MLT3, and Manchester decoding. it can. The PHY 108 (a) and 108 (b) can also perform clock and data recovery, stream cipher decryption, and digital adaptive equivalence as well.

【0020】

In the exemplary embodiment described, MAC 104 (a) and 104 (b) perform flow independent MAC layer processing on inbound packets. For example, MAC 104 (a) and 104 (b) can also process incoming Ethernet packets and send higher tier packets to PCS102. The PCS102 receives inbound packets, classifies the packets, creates application data for the inbound packets, modifies the inbound packets according to the application data, and sends the modified inbound packets to, for example, the switching backplane. preferable.

【0021】

In one exemplary embodiment, the packet switching controller 102 can likewise receive outbound packets from other packet switching controllers via the backplane. The PSC102 is then outbound for forwarding to local devices via MII114 (a) and 114 (b), PHY108 (a) and 108 (b), and LAN112 (a) and 112 (b), respectively. Packets can be sent to MAC 104 (a) and 104 (b). In one exemplary embodiment of the invention, MAC 104 (a) and 104 (b) encode packets in the transmit path into Ethernet packets for communication to external devices operating on a local area network. The MAC 104 (a) and 104 (b) can also perform additional management functions, such as link integrity monitoring, as well.

【0022】

In other embodiments, the packet switching controller 102 may also allow one or more outbound packets to undergo output processing before being forwarded to MAC 104 (a) and 104 (b). In addition, the packet switching controller 102 can execute any combination of non-programmable logic, programmable logic, or programmable and non-programmable logic.

【0023】

Referring to FIG. 2, the exemplary MAC 104 includes a transmit function element 300, a transmit control element 120 coupled between the transmit path management control element (MCE) 101 and the PSC 102, according to the present invention. In the exemplary embodiment described, the transmit control element 120 receives an outbound packet from the PSC 102. An exemplary transmit control element can conditionally transmit a special packet (flow control packet) that makes it impossible and possible to transmit a packet from the other MAC of the link as soon as requested by the system. In addition, preferably under the control of the receive control element, the transmit control element can likewise prohibit the flow of frames from the system to the transmit function element 300.

【0024】

In one exemplary embodiment of the invention, the transmit function element 300 is outbound according to one or more operational communication protocols, such as medium access control (MAC) bridging, and Internet Protocol (IP) routing. Can process packets. The transmit function element 300 can encapsulate the outbound data at the appropriate MAC address of an external device on the LAN prior to transmission via MII114.

【0025】

Further, the exemplary MAC can similarly include a receive function element 200 and a receive control element 130 coupled between the MCE 101 and the PSC 102. An exemplary receive function element 200 receives an inbound packet from the MCE101, preferably strips data from the frame and checks for transmission errors in the received frame. In one exemplary embodiment, the receive control element recognizes special packets (eg, flow control packets) that make it impossible and possible to send packets from the MAC to the PSC 102.

【0026】

FIG. 3 is a simplified block diagram showing the exemplary data path of FIG. 2 in great detail. An exemplary system can include system interface 150 and PHY 108. An exemplary MAC 104 can include a transmit control element 120, a receive control element 130, a transmit function element 300, a receive function element 200, and a management control element (MCE) 101.

【0027】

In operation, the PHY 108 propagates an input data packet to the MCE 101 via a 76-bit data path within the MII 114. In one embodiment, the input data packet preferably contains 32-bit data, 4-bit control information, and 2-bit management information. The MCE101 transmits the configuration information to the ISO layer below the MAC layer via the management information bit, and searches the status information from this layer. In the exemplary embodiment described, the MCE101 removes management information and transfers the remaining 32 data bits and 4 bits of control data to the receiving function element 200.

【0028】

In one exemplary embodiment, the receive functional element 200 provides receive functionality according to various communication protocols, such as, for example, IEEE 802.3ae receive functionality associated with the MAC layer. Similarly, the receive control element can also provide flow control functionality according to various communication protocols, such as IEEE 802.3x functionality. In one exemplary embodiment, the system interface 150 can include a 32-bit transmit data path width and a 64-bit receive data path width. In the exemplary embodiment described, the system interface preferably comprises a FIFO 140 that receives data from the receiving data path and transfers the data to the transmitting data path.

【0029】

FIG. 4 is a simplified block diagram showing additional details of the receive function element 200 shown in FIG. In one exemplary embodiment of the invention, the receiving functional element 200 preferably receives input data 316 with a width of 32 bits and a standardized clock signal 314. In one exemplary embodiment of the invention, the data 316 and the clock signal 314 are received from the MCE 101 via the media independent interface 114 (see Figure 3).

【0030】

According to one exemplary embodiment, the receive function element is for converting two 32-bit wide serial data streams into a single 64-bit wide parallel data stream with an output of 320 for the receive control element 130. , It is preferable to use dual data rate (DDR) sampling (shown in Figure 3). In this way, the receive data path at system interface 150 is 64-bit wide, while the transmit data path is 32-bit wide.

【0031】

In one embodiment, the receiving function element 200 couples this 32-bit wide input data 316 into two gate elements 302 and 304. In the exemplary embodiment described, one gate element preferably samples the input data 316 on the rising edge of the clock signal, and the other gate element is on the negative or falling edge of the clock signal. Sample the input data 316. (This is shown in the timing diagrams of FIGS. 5 and 6.) As a result, each of the gate elements 302 and 304 preferably transfers a 32-bit wide serial data stream to the master gate 306.

【0032】

The master gate 306 performs demultiplexing processing that converts a plurality of input streams of 32-bit wide series data 302 (a) and 304 (a) into 64-bit wide parallel data according to the rising edge of the clock. Is preferable. In the exemplary embodiments described, rising edge sampling is used to internally process and output 64-bit wide data.

【0033】

In operation, the demultiplexed parallel data 306 (a) can be input to the logical block 308, which checks the inter-packet gap (IPG) of the parallel data stream and performs preamble insertion and data alignment. In addition, in one exemplary embodiment, the logic block 308 preferably analyzes parallel data 306 (a) and creates statistical information.

【0034】

In one exemplary embodiment of the invention, the logical block 308 transfers the received FIFO handshake signal 314 to an external FIFO element 140 within the system interface (see Figure 3). In one exemplary embodiment, the logical block 308 receives the receive FIFO handshake signal 314 so that the FIFO handshake signal 314 functionally flows to the external FIFO via the receive control element 130 (see FIG. 3). Indirectly transfer. The reception control element 130 preferably monitors the handshake signal as it passes through. After the FIFO handshake signal is sent, the logical block 308 outputs 64-bit wide data 320 to the external FIFO. In addition, in the exemplary embodiment described, the cyclic redundancy check element 310 performs a cyclic redundancy check on the current output data and the comparator 312 sets the current redundancy check to the previous cyclic redundancy check data. Compare. The statistics produced by the logical block, and the result of the cyclic redundancy check comparison, can then be output 322 for use by other elements outside the MAC.

【0035】

In the exemplary embodiment described, the rest of the operation of the receive pipeline can likewise use the rising edge of the clock signal 314 on the internal 64-bit pipeline bus. This eliminates the demand for rising and falling edge processing solutions that are difficult to achieve due to the asymmetry found in most clock signals.

【0036】

FIG. 5 is a waveform diagram of an exemplary clock signal 314. From this, it can be seen that the clock signal 314 includes falling and rising edges. According to one exemplary embodiment, the first gate element, represented by G1, at each successive rising edge of the clock (402, 406, 410, etc.), is a contiguous array of instances of data having a first width. To sample. In addition, the second gate element, represented by G2, samples each successive instance of data having the first width at the continuous falling edges of the clock (404, 408, 412, etc.). Subsequently, the data having the second larger width is processed at the second rising edges 414 and 416 of the clock 314.

【0037】

FIG. 6 graphically illustrates the timing of an exemplary asymmetric data path. According to one exemplary embodiment of the invention, the input data 502 is represented by data bits D1, D2, D3 and the like, and in a preferred embodiment it comprises 32 data bits. The waveform / timing diagram of FIG. 6 shows a timing diagram of how 32-bit wide input data 502 is converted to 64-bit wide output data 512. According to an exemplary embodiment of the invention, the first gate element 302 samples input data 316 (502) on the "rising" edge of clock signal 314 (504). In addition, the second gate element 304 samples the input data 316 (502) on the "falling" edge of the clock signal 314 (504). In the exemplary embodiment described, the master gate 306 (510) uses the rising edge following the clock signal 504 to parallel two 32-bit wide data streams 502 and 504 with a 64-bit width. Convert to a data stream. In addition, this 64-bit wide output data with CRC added is also illustrated.

【0038】

FIG. 7 is a flow diagram illustrating an exemplary method for manipulating data according to the present invention. Similar elements in the flow diagram of FIG. 7 (eg, MCE101, mastergate element 306, logical block 308, and receive function element 200) represent similar elements in the previous drawings.

【0039】

According to one exemplary embodiment, the input data 601 includes 32 bits of data, 2 bits of management information, and 4 control bits. In the exemplary embodiment described, the MII interface transfers input data to a management control element (MCE). The MCE preferably strips the 2-bit management information from the input data 603 and transfers the input data 607, which includes 32 data bits and 4 control bits, to the receiving function element 200.

【0040】

Within the receive function element 200, the input data 607 is sampled according to the rising and falling edges of the clock signal 609 to create two data outputs 613, each of which is 32-bit wide data. The two 32-bit wide serial data streams can subsequently be parallelized according to the rising edge of clock 615 to create 64-bit wide parallel data 617. This parallel data can then be processed to create statistical information 619. For example, in one exemplary embodiment, the logical block can inspect packet-to-packet gap (IPG) intervals for preamble insertion, data alignment, and statistical information generation. The received FIFO handshake signal from the receive function element 200 is sent to the external FIFO 621 before the data is output to the system interface.

【0041】

According to one exemplary embodiment, the 64-bit wide data is output 645 and the current output data is subjected to a cyclic redundancy check (CRC) 635. According to one exemplary embodiment, the receiving functional element can check for errors in the current CRC by comparing the CRC data for the current output with the stored (old) CRC data. .. In operation, if an error is found 639, the CRC element recalculates the data 641 and another comparison 635 with the old CRC data before outputting the CRC data 637 to receive the statistics. To send the new CRC data 643 again. In this way, the data output 645 having a 64-bit wide data path becomes the output from the receiving function element 200.

【0042】

Those skilled in the art will appreciate that the invention can be practiced in other particular embodiments without departing from the spirit or fundamental nature of the invention. For example, the invention is not limited to an asymmetric data path in which the transmit clock is fast enough to maintain the desired data throughput. Instead, the invention can be utilized to increase data throughput in both transmit and receive data paths, or in transmit data paths alone. Therefore, this description is exemplary in all respects and is not limiting. The scope of the present invention is indicated by the scope of claims, and all modifications that fall within the equivalent meaning and scope of the present invention shall be included in the present invention.

[Simple explanation of drawings]

[Figure 1]

FIG. 3 is a simplified block diagram of a system with a medium access controller for providing bidirectional communication between a packet switch and one or more local area networks.

[Figure 2]

It is a simplified block diagram of the media access controller of FIG. 1 according to an exemplary embodiment of the present invention.

[Fig. 3]

FIG. 6 is a block diagram illustrating significant details of a system for providing bidirectional communication between a packet switch shown in FIG. 1 and one or more local area networks, according to an exemplary embodiment of the invention.

[Fig. 4]

FIG. 3 is a simplified block diagram of a receiving function element of the system of FIG. 3 according to an exemplary embodiment of the present invention.

[Fig. 5]

FIG. 5 is a waveform diagram of a clock signal schematically showing data sampling according to an exemplary embodiment of the present invention.

[Fig. 6]

It is a figure which shows schematicly the timing of the receiving function of FIG. 4 by one exemplary Embodiment of this invention.

[Fig. 7]

It is a flowchart which shows the method of processing data by one exemplary Embodiment of this invention.

[Explanation of symbols]

100 switches 101 Management control element 102 Packet switching controller 104 (a), (b) Media access controller 108 (a), (b) Physical layer 112 (a), (b) LAN 114 (a), (b) Media independent interface 120 Transmission control element 130 Receive control element 150 system interface 200 Receive function element 300 transmit function element 302, 304 Gate element 302 (a), 304 (a) serial data 306 Master Gate 306 (a), 617 Parallel data 310 Cyclic Redundancy Check Element 312 Comparator 314, 609 clock signal 316 Input data 320, 322, 645 output 402, 406, 410 Rising edge 404, 408, 412 Falling edge 414, 416 Second rising edge 502, 601, 603, 607 Input data 512, 613 output data 615 clock 621 External FIFO 635 Cyclic Redundancy Check 637 CRC data 641 data 643 New CRC data 645 data output D1, D2, D3 data bits G1, G2 gate element