Cp flip-flop

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to flip-flops, and in particular, in active mode (power on), low power and high-speed operation is possible in a smaller area than existing low-power flip-flops, and in sleep mode (power off). It relates to a CP flip-flop that performs a latch function with the minimum power consumption.

【0002】

[Conventional technology]

FIG. 1 is a circuit diagram of an existing Transmission Gate master-slave Flip Flop (hereinafter referred to as "TGFF"). Referring to FIG. 1, the TGFF is composed of a master stage on the left side of the dotted line and a slave stage on the right side of the dotted line.

【0003】

When the clock signal Clk is in the high (low) state, the master stage receives and latches the input data Data, and the slave stage latches and outputs the previous logical state. When the clock signal Clk is in the low (high) state, the master stage no longer receives the input data Data, and the slave stage transmits and outputs the logical state of the master stage. Here, Vdd is a high supply voltage, GND is a ground voltage, Clkb is a reverse clock, a signal in which the phase of the clock Clk is inverted, and Q is a positive output end.

【0004】

FIG. 2 is a circuit diagram of an existing Hybrid Latch Flip Flop (hereinafter referred to as "HLFF"). With reference to FIG. 2, the HLFF is composed of a dynamic front stage on the left side of the dotted line and a static back stage on the right side of the dotted line.

【0005】

When the clock signal Clk transitions from high level to low level, the input data Data is transmitted to the front stage within the delay time of the reverse clock signal Clkb that is inverted and delayed by the three inverters, and the front stage is charged or discharged or its. The previous state is maintained, and the back stage maintains the previous logical state as it is. When the clock signal Clk transitions from the low level to the high level, the front stage no longer receives the input data Data, and the back stage transmits the previous logical state to the back stage and outputs it.

【0006】

FIG. 3 is a circuit diagram of an existing Semi Dynamic Flip Flop (hereinafter referred to as "SDFF"). With reference to FIG. 3, the SDFF is composed of a precharge stage on the left side of the dotted line and an output buffer stage on the right side of the dotted line. When the input data Data is logically high, all the precharge stages are discharged and the output Q_b is in the logical high state, and when the input data Data is logically low, the precharge stage is charged to the logical high state and the output Q_b is in the logical high state. It becomes a logical low state.

【0007】

FIG. 4 is a circuit diagram of a flip-flop (Sense Amplifier Flip Flop; hereinafter referred to as "SAFF") used as an existing sense amplifier. Referring to FIG. 4, the SAFF is stored and output in a latch circuit composed of two NAND gates when the clock is high, and the voltage level of the input signal is stored in the input signal when the clock is low. Regardless of the output Q and Qb, the previous state is maintained.

【0008】

[Problems to be Solved by the Invention]

The existing flip-flops described above consume a large amount of power because the master stage or the dynamic front stage must be precharged. Currently, the system requires high speed and low power, and there is a disadvantage that the used area and power consumption are large in order to satisfy this by using the existing flip-flop.

【0009】

If MTCMOS (Multi Threshold Complementary Metal Oxide Silicon) technology is used, the flip-flop can be used not only in the active mode of a system provided with a circuit (power down circuit) that shuts off the power supply and does not operate, but also in the sleep mode. However, there is a disadvantage that the design of the control signal for storing the data is complicated, in addition to having to add a circuit for storing the latched data when the power supply is cut off.

【0010】

Here, the MTCMOS technology refers to a structure in which a MOS switch having a relatively high threshold voltage is connected in series between a power supply (Vdd, Vss or GND) and a logic circuit. The MTCMOS technology refers to a technology capable of reducing power consumption by supplying or interrupting the power supply to the logic circuit composed of MOS transistors having a relatively low threshold voltage by opening and closing the MOS switch.

【0011】

In the MTCMOS technology, in the active mode, the MOS switch is turned on to supply the power supply to the logic circuit, and in the sleep mode, the MOS switch is turned off to cut off the power supply from the logic circuit to cut off the power supply of the entire system. Power consumption can be minimized.

【0012】

In particular, this technique is very useful in reducing the power consumption of circuits used in systems that spend more time in sleep mode than in active mode. However, as described above, there is a disadvantage that the data stored in the latch circuit or the flip-flop is lost unless there is a special means to prepare for when the power supply is cut off.

【0013】

Therefore, an object of the present invention is to provide a CP flip-flop (Complementary Passtransistor based flip-flop) capable of a smaller area, lower power consumption, and higher speed operation than existing low-power flip-flops.

【0014】

Furthermore, it is an object of the present invention to provide a CP flip-flop that can latch the data and minimize the power consumption without adding a circuit for storing the latched data in sleep mode. To do.

【0015】

[Means for solving problems]

The first CP flip-flop of the present invention includes a clock delay unit that inverts and delays a clock signal, a switch unit that switches input data in response to the clock signal and the output signal of the clock delay unit, and a switch unit of the switch unit. A latch portion for storing at least one or more output signals is provided.

【0016】

According to the preferred first embodiment, the clock delay section comprises an odd number of series-connected inverters that inverting and delay the clock signal. The switch unit includes a first switch that switches input data in response to the clock signal, and a second switch that switches the output signal of the first switch in response to the output signal of the clock delay unit. .. In the latch circuit, a first inverter in which the second switch of the switch unit is connected to an input terminal, an output terminal of the first inverter is connected to an input terminal, and an input terminal of the first inverter is connected to an output terminal. It is equipped with a connected second inverter.

【0017】

According to the preferred second embodiment, the CP flip-flop further comprises a first inverter that inverts the input data. The clock delay unit includes an odd number of inverters connected in series for inverting and delaying the clock signal. The switch unit includes a first switch that switches the input data in response to the clock signal, a second switch that switches the output signal of the first switch in response to the output signal of the clock delay unit, and the above. It includes a third switch that switches the output signal of the first inverter in response to a clock signal, and a fourth switch that switches the output signal of the third switch in response to the output signal of the clock delay unit. In the latch portion, the second inverter of the switch portion is connected to the input terminal, the fourth switch is connected to the output terminal, and the fourth switch of the switch portion is connected to the input terminal. , A third inverter in which the second switch is connected to the output terminal is provided.

【0018】

According to the preferred third embodiment, the clock delay unit reverse-delays the clock signal in response to the clock signal and the enable signal. The switch unit includes a first switch that switches input data in response to the clock signal and a second switch that switches the output signal of the first switch in response to the output signal of the clock delay unit. The latch portion includes a logic circuit and a latch circuit. The logic circuit includes a NAND gate that responds to a set signal and a reset signal. The latch circuit includes a first inverter and a second inverter for storing data, and four NMOS transistors that respond to a set signal and a reset signal.

【0019】

According to the preferred fourth embodiment, the CP flip-flop further comprises a first inverter that inverts the input data. The clock delay unit reverse-delays the clock signal in response to the clock signal and the enable signal. The switch unit includes a first switch that switches the input data in response to the clock signal, a second switch that switches the output signal of the first switch in response to the output signal of the clock delay unit, and the clock signal. A third switch that switches the output signal of the first inverter in response to the above, and a fourth switch that switches the output signal of the third switch in response to the output signal of the clock delay unit are provided. The latch portion includes a logic circuit and a latch circuit. The logic circuit includes a NAND gate that responds to a set signal and a reset signal. The latch circuit includes a second inverter for storing data, a third inverter, and four NMOS transistors that respond to a set signal and a reset signal.

【0020】

The second CP flip-flop of the present invention includes a first virtual power supply unit, a second virtual power supply unit, a clock delay unit, a switch unit, and a latch unit.

【0021】

The first virtual supply power supply unit receives the first supply power supply having the highest voltage among the supplied power supplies and provides the first virtual supply power supply. The second virtual power supply unit receives the second supply power supply having the lowest voltage among the supplied power supplies and provides the second virtual power supply power supply. The clock delay unit receives the clock signal and inverts / delays the clock signal to output, or further receives at least one control signal and inverts / delays the clock signal in response to the received control signal. Output with a delay. The switch unit switches input data in response to the clock signal and the output signal of the clock delay unit. The latch portion stores at least one output signal of the switch portion.

【0022】

The clock delay section and the switch section are all composed of LT MOS transistors, and the latch section is composed of a plurality of LT (Low Threshold) MOS transistors or a plurality of LT MOS transistors and at least one HT (High Threshold) MOS transistor. The LT MOS transistor is located between the first power supply and the second power supply, between the first power supply and the second virtual power supply, and between the first virtual power supply and the second virtual power supply. And operate in one of four cases between the first virtual power supply and the second virtual power supply, and the HT MOS transistor operates between the first power supply and the second power supply. LT MOS transistors have a relatively lower threshold voltage than HT MOS transistors. For example, the threshold voltage of the LT MOS transistor is between 0.1 volt and 0.4 volt for the LT NMOS transistor Vtn and between -0.1 volt and -0.4 volt for the LT MOSFET transistor Vtp, and the threshold voltage of the HT MOS transistor. Threshold voltage is HT It is usually between 0.4 and 0.7 volts for an NMOS transistor Vtn and between -0.4 and -0.7 volts for an HT MOSFET transistor Vtp.

【0023】

Desirably, in the LT MOS transistor, the threshold voltage Vtn of the LT NMOS transistor is 0.33 ± 0.04 volt, and the threshold voltage Vtp of the LT NMOS transistor is -0.4 ± 0.04 volt. In the HT MOS transistor, the threshold voltage Vtn of the HT NMOS transistor is 0.6 ± 0.06 volt, and the threshold voltage Vtp of the HT MOSFET transistor is -0.65 ± 0.06 volt.

【0024】

According to the preferred first embodiment, the clock delay section comprises a plurality of odd numbered inverters connected in series with each other, each of which is composed of an LT MOS transistor. The switch unit includes a first switch that switches the input data in response to the clock signal, and a second switch that switches the output signal of the first switch in response to the output signal of the clock delay unit. The first switch and the second switch are each composed of at least one LT MOS transistor. In the latch portion, the output terminal of the first inverter to which the output signal of the second switch is applied is connected to the input terminal, the output terminal of the first inverter is connected to the input terminal, and the output terminal is connected to the input terminal of the first inverter. It is equipped with the second inverter. The first inverter and the second inverter are each composed of HT MOS transistors. One end of the latch portion is connected to the first supply power supply, the other end is connected to the input terminal of the first inverter, and the gate may further include a first LT photoresist transistor connected to the output terminal of the first inverter. ..

【0025】

In the preferred first mode and the second to sixth modes described below, the LT MOS transistor operates between the first virtual power supply and the second virtual power supply, and the HT MOS transistor is the HT MOS transistor. It is desirable to operate between the first power supply and the second power supply.

【0026】

According to the preferred second embodiment, the clock delay unit responds to a third inverter that reverses the clock signal, a fourth inverter that reverses the third inverter, and an output signal and an anti-floating signal of the fourth inverter. It is provided with a NOR gate that outputs a reverse clock signal obtained by inverting and delaying the clock signal. The third inverter and the fourth inverter include an LT MOS transistor, and the NOR gate includes an LT MOS transistor and an HT MOS transistor. The switch portion and the latch portion are the same as in the case of the first embodiment. The anti-floating signal serves to eliminate leakage current by turning off the NMOS transistors 1122 and 1124 of FIGS. 14 to 17 when the power supply is turned off.

【0027】

According to the preferred third embodiment, the CP flip-flop further comprises a third inverter that reverses the input data. The plurality of inverters are composed of LT MOS transistors. The clock delay unit includes a plurality of odd-numbered inverters, each of which is composed of an LT MOS transistor. The switch unit includes a first switch that switches the input data in response to the clock signal, a second switch that switches the output signal of the first switch in response to the output signal of the clock delay unit, and the clock signal. A third switch for switching the output signal of the third inverter in which the input data signal is reversed in response to the above, and a fourth switch for switching the output signal of the third switch are provided. Each of these 1st to 4th switches has at least one LT It is composed of MOS transistors. In the latch portion, the output signal of the second switch is applied to the input terminal, and the output signal of the fourth switch is applied to the first inverter whose output terminal is connected to the output terminal of the fourth switch and the input terminal. A second inverter whose output terminal is connected to the output terminal of the second switch is provided. The first inverter and the second inverter are each composed of HT MOS transistors. One end of the latch portion is connected to the first supply power supply, the other end is connected to the output terminal of the second switch, and the gate is connected to the output terminal of the fourth switch. One end is connected to the first supply power supply, the other end is connected to the output terminal of the fourth switch, and the gate can further include a second LT multiplexer transistor connected to the output terminal of the second switch.

【0028】

According to the preferred fourth embodiment, the clock delay unit responds to a fourth inverter that reverses the clock signal, a fifth inverter that reverses the fourth inverter, and an output signal and an anti-floating signal of the fifth inverter. It is provided with a NOR gate that outputs a reverse clock signal obtained by inverting and delaying the clock signal. The fourth inverter and the fifth inverter are composed of LT MOS transistors, and the NOR gate is composed of LT MOS transistors and HT MOS transistors. The switch portion and the latch portion are the same as in the third embodiment.

【0029】

According to the preferred fifth embodiment, the CP flip-flop further comprises a data hold section. One end of this data hold unit is connected to the output terminal of the second switch, the first HT NMOS transistor to which the data hold signal is applied to the gate, and one end is connected to the output terminal of the fourth switch, and the gate is connected to the gate. The second HT NMOS transistor to which the data hold signal is applied, the fourth inverter in which the input terminal is connected to the other end of the first HT NMOS transistor and the output terminal is connected to the other end of the second HT NMOS transistor, and the input terminal A fifth inverter is provided which is connected to the other end of the second HT NMOS transistor and whose output terminal is connected to the other end of the first HT NMOS transistor. The 4th inverter and the 5th inverter are HT It is composed of MOS transistors. In the latch portion, the input terminal is connected to the output terminal of the second switch, the output terminal is connected to the output terminal of the fourth switch, and the input terminal is connected to the output terminal of the fourth switch. A second inverter whose output terminal is connected to the output terminal of the second switch is provided. The first inverter and the second inverter are each composed of LT MOS transistors. One end of the latch portion is connected to the first supply power supply, the other end is connected to the output terminal of the second switch, and the gate is connected to the output terminal of the fourth switch. One end is connected to the first supply power supply, the other end is connected to the output terminal of the fourth switch, and the gate can further include a second LT multiplexer transistor connected to the output terminal of the second switch. The third inverter and the switch unit that reverse the remaining data signals are the same as in the case of the third embodiment.

【0030】

According to the preferred sixth embodiment, the CP flip-flop further comprises a set / reset section. This set / reset unit has a first NAND gate that responds to a set signal and a reset signal, a first HT µtransistor whose one end is connected to the output terminal of the second switch and the reset signal is applied to the gate, and one end is the first. The second HT µtransistor is connected to the output terminal of the four switches, the other end is connected to the other end of the first HT µtransistor, and the set signal is applied to the gate, and one end is connected to the second supply power supply. The other end is commonly connected to the other ends of the first HT µtransistor and the second HT µtransistor, and the gate is provided with a third HT µtransistor to which the output signal of the first NAND gate is applied. The first NAND gate is LT It is equipped with a MOS transistor. The clock delay unit includes a fourth inverter that inverts the clock signal, a second NAND gate that responds to the output signal and enable signal of the fourth inverter, and a NOR that responds to the output signal of the second NAND gate and the floating prevention signal. Equipped with a gate. The remaining switch portion, latch portion, and third inverter are the same as in the case of the third embodiment.

【0031】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In each drawing, the same reference numerals indicate the same elements. In addition, the following embodiments are merely exemplary, and more diverse modifications and equivalent other embodiments are possible to those who have conventional knowledge in the art. Therefore, the true technical protection scope of the present invention is determined by the technical idea of the claims.

【0032】

FIG. 5 is a circuit diagram of a CP flip-flop according to the first embodiment of the present invention. Referring to FIG. 5, the CP flip-flop according to the first embodiment of the present invention includes a clock delay unit 210, a switch unit 220, a latch unit 230, and a buffer unit 240.

【0033】

The clock delay unit 210 includes a first inverter 211 that inverts the clock signal Clk, a second inverter 212 that inverts the output signal of the first inverter 211, and a third inverter 213 that inverts the output signal of the second inverter 212. To do. The switch unit 220 includes a first switch 221 that switches the input data Data in response to the clock signal Clk, and a second switch 222 that switches the output signal of the first switch 221 in response to the output signal of the clock delay unit 210. To do. In the latch portion 230, the output terminal is connected to the fourth inverter 231 connected to the second switch 222, the input terminal is connected to the output terminal of the fourth inverter 231, and the output terminal is connected to the input terminal of the fourth inverter 231. 5 Equipped with an inverter 232. The buffer unit 240 includes a sixth inverter 242.

【0034】

FIG. 6 is a circuit diagram of a CP flip-flop according to a second embodiment of the present invention. Referring to FIG. 6, the CP flip-flop according to the second embodiment of the present invention includes a clock delay unit 310, a switch unit 320, a latch unit 330, a buffer unit 340, and a first inverter 350.

【0035】

The first inverter 350 inverts the input data Data. The clock delay unit 310 includes a second inverter 311 that inverts the clock signal Clk, a third inverter 312 that inverts the output signal of the second inverter 311 and a fourth inverter 313 that inverts the output signal of the third inverter 312. To do. The switch unit 320 has a first switch 321 that switches the input data Data in response to the clock signal Clk, a second switch 322 that switches the output signal of the first switch 321 in response to the output signal of the clock delay unit 310, and a clock. It includes a third switch 323 that switches the output signal of the first inverter 350 in response to the signal Clk, and a fourth switch 324 that switches the output signal of the third switch 323 in response to the output signal of the clock delay unit 310. .. In the latch section 330, the input terminal is connected to the second switch 322 of the switch section 320, the output terminal is the fifth inverter 331 connected to the fourth switch 324 of the switch section 320, and the input terminal is the fourth switch of the switch section 320. It is provided with a sixth inverter 332 which is connected to 324 and whose output terminal is connected to the second switch 322 of the switch unit 320. The buffer unit 340 includes a seventh inverter 341 whose input terminal is connected to the second switch 322 of the switch unit 320, and an eighth inverter 342 whose input terminal is connected to the fourth switch 324 of the switch unit 320.

【0036】

The operation of the CP flip-flop according to the first embodiment and the second embodiment of the present invention will be described with reference to FIGS. 5 and 6. If the clock Clk is in the low state, the switches 221, 321 and 323 that receive the input signal Data in the switches 220 and 320 cannot receive the input signal Data because they are in the off state, but the switches 221, 321, and 323 can not receive the input signal Data, respectively. The connected switches 222, 322 and 324 are in the on state. When the clock Clk transitions to the high state, the switches 221, 321 and 323 are turned on so that the input signal Data can be received. On the other hand, the switches 222, 322 and 324 operated by the output signals of the clock delay units 210 and 310 that invert and delay the clock Clk signal are turned off after a certain delay time from the moment when the clock Clk transitions to the high state. Will be done.

【0037】

Therefore, if the clock Clk transitions from the low state in which the input signal Data cannot be received to the high state, all the switches of the switch units 220 and 320 are in the on state for the period in which the clock delay units 210 and 310 delay the clock Clk. As a result, the input signal Data passes through the flip-flop and determines the logical state of the latch units 230 and 330, and at the same time determines the output signals of the buffer units 240 and 340.

【0038】

The output signals of the clock delay units 210 and 310 turn off the switches 222, 322 and 324 when a certain delay time elapses after the clock Clk signal transitions to the high state, so that the input signal Data is already latched. It cannot affect 230, 330 or buffers 240, 340. At this time, the output signals of the buffer units 240 and 340 are determined by the logical values stored in the latch units 230 and 330.

【0039】

If the clock Clk transitions to the low state, the output signals of the buffer units 240 and 340 do not change because the input signal Data can no longer be received.

【0040】

FIG. 7 is a circuit diagram of a CP flip-flop according to a third embodiment of the present invention. Referring to FIG. 7, the CP flip-flop according to the third embodiment of the present invention includes a clock delay unit 410, a switch unit 420, a latch unit 430, and a buffer unit 440.

【0041】

The clock delay unit 410 includes a first inverter 411 that inverts the clock signal Clk, a first NAND gate 412 to which the output signal of the first inverter 411 is applied to one end and an enable signal EN is applied to the other end, and the first NAND gate. A second inverter 413 that inverts the output signal of the 412 is provided. The switch unit 420 includes a first switch 421 that switches the input data Data in response to the clock signal Clk, and a second switch 422 that switches the output signal of the first switch 421 in response to the output signal of the clock delay unit 410. Equipped.

【0042】

The latch portion 430 includes a logic circuit 430a and a latch circuit 430b. The logic circuit 430a includes a second NAND gate 437 that responds to the set signal S and the reset signal RS. The latch circuit 430b includes three NMOS transistors, that is, a first MOS transistor 433 to a third MOS transistor 435 and a third inverter 431 and a fourth inverter 432. The input terminal of the third inverter 431 is connected to the output terminal of the second switch 422 of the switch unit 420, the input terminal of the fourth inverter 432 is connected to the output terminal of the third inverter 431, and the output terminal of the switch unit 420. It is connected to the second switch 422. One end of the first MOS transistor 433 is connected to the output terminal of the second switch 422 of the switch unit 420, and the reset signal RS is applied to the gate. One end of the second MOS transistor 434 is connected to the other end of the first MOS transistor 433, the other end is connected to the output terminal of the third inverter 431, and a set signal S is applied to the gate. One end of the third MOS transistor 435 is commonly connected to the other end of the first MOS transistor 433 and one end of the second MOS transistor 434, the other end is connected to the supply power supply voltage Vss, and the output signal of the second NAND gate 437 is sent to the gate. It is applied. The buffer unit 440 includes a fifth inverter 441.

【0043】

FIG. 8 is a circuit diagram of a CP flip-flop according to a fourth embodiment of the present invention. Referring to FIG. 8, the CP flip-flop according to the fourth embodiment of the present invention includes a clock delay unit 510, a switch unit 520, a latch unit 530, a buffer unit 540, and a first inverter 550.

【0044】

The first inverter 550 inverts the input data Data. The clock delay section 510 includes a second inverter 511 that inverts the clock signal Clk, a first NAND gate 512 to which the output signal of the second inverter 511 is applied to one end and an enable signal EN to the other end, and the first NAND gate. A third inverter 513 that inverts the output signal of 512 is provided. The switch unit 520 has a first switch 521 that switches the input data Data in response to the clock signal Clk, a second switch 522 that switches the output signal of the first switch 521 in response to the output signal of the clock delay unit 510, and a clock. It includes a third switch 523 that switches the output signal of the first inverter 550 in response to the signal Clk, and a fourth switch 524 that switches the output signal of the third switch 523 in response to the output signal of the clock delay unit 510. ..

【0045】

The latch portion 530 includes a logic circuit 530a and a latch circuit 530b. The logic circuit 530a includes a second NAND gate 537 that responds to the set signal S and the reset signal RS. The latch circuit 530b includes three NMOS transistors, that is, a first MOS transistor 533 to a third transistor 535, a fourth inverter 531 and a fifth inverter 532. In the 4th inverter 531, the input terminal is connected to the output terminal of the 2nd switch 522 of the switch unit 520, the output terminal is connected to the output terminal of the 4th switch 524 of the switch unit 520, and the 5th inverter 532 has an input terminal. It is connected to the 4th switch 524 of the switch unit 520, and the output terminal is connected to the 2nd switch 522 of the switch unit 520. One end of the first MOS transistor 533 is connected to the output terminal of the second switch 522 of the switch unit 520, and the reset signal RS is applied to the gate. One end of the second MOS transistor 534 is connected to the other end of the first MOS transistor 533, the other end is connected to the output terminal of the fourth inverter 531, and a set signal S is applied to the gate. One end of the third MOS transistor 535 is commonly connected to the other end of the first MOS transistor 533 and one end of the second MOS transistor 534, the other end is connected to the supply power supply voltage Vss, and the output signal of the logic circuit 530a is applied to the gate. Will be done.

【0046】

The buffer unit 540 includes a sixth inverter 541 whose input terminal is connected to the output terminal of the fifth inverter 532 of the latch unit 530, and a seventh inverter whose input terminal is connected to the output terminal of the fourth inverter 531 of the latch unit 530. It is equipped with 542.

【0047】

The operation of the CP flip-flop according to the third embodiment and the fourth embodiment of the present invention will be described with reference to FIGS. 7 and 8. When the enable signals applied to the clock delay units 410 and 510 are logically high, the CP flip-flop functions as a normal flip-flop, and when the enable signal EN is logical low, the clock delay unit 410 Since the output signal of 510 is in the low state, the switches 422, 522 and 524 of the switch units 420 and 520 are turned off and the input signal Data cannot be received.

【0048】

When the set signal S and the reset signal RS are in the logical high state, the CP flip-flop according to the present invention operates as a normal flip-flop.

【0049】

When the set signal S is in the low state, the output signals of the logic circuits 430a and 530a of the latch portions 430 and 530 are in the logic high state, and the third transistors 435 and 535 of the latch circuits 430b and 530b are turned on. Since the set signal S is in the low state, the reset signal RS must be logically high when viewed logically, and the transistors 433 and 533 of the latch circuits 430b and 530b are turned on and the output signals of the inverters 441 and 541. Goes high.

【0050】

When the reset signal RS is in the low state, the output signals of the logic circuits 430a and 530a of the latch portions 430 and 530 are in the logic high state, and the transistors 435 and 535 of the latch circuits 430b and 530b are turned on. Since the reset signal RS is in the low state, the set signal S must be logically high when viewed logically, the second transistors 434 and 534 of the latch circuits 430b and 530b are turned on, and the transistors 433 and 533 are It is turned off and the output signals of the inverters 441 and 541 are in the low state.

【0051】

Here, the use of the NAND gate in the logic circuits 430a and 530a of the latch portions 430 and 530 is an example in consideration of the unstable logic state when the set signal S and the reset signal RS are in the high state at the same time.

【0052】

According to the four embodiments of the first to fourth embodiments according to the present invention, it can be seen that the number of gates is reduced as compared with the existing flip-flops. This means that when the present invention is embodied, the area used on the wafer is reduced. Also, since the signal is transmitted at a very short moment, it has the advantage of being able to respond to a considerably high frequency of the system clock. Unlike existing flip-flops, the front stage does not have to be precharged, so power consumption is relatively reduced. Further, the CP flip-flop according to the present invention has a small load on the clock signal, and the total amount of gate widths of the transistors used is also smaller than that of the existing circuit.

【0053】

The CP flip-flop according to the present invention and the existing flip-flop are simulated and compared under the same conditions. FIG. 9 is a circuit diagram showing a test bench for testing flip-flops. Referring to FIG. 9, it is assumed that the capacitive load of the input data Data and the clock signal Clk is 50 fF (fem to Farad), respectively, and the capacitive load of the flip-flop is 200 fF for both the output terminal Q and the reverse output terminal Q_b.

【0054】

A constant consideration when designing flip-flops is the trade-off between speed and power consumption. Therefore, all flip-flops must be designed to minimize PDP (Power Delay Product).

【0055】

To simplify the comparative test, the maximum gate width of the transistor is 20 μm, the minimum gate width is 0.7 μm, and the input data Data and clock clock have a width of 35 μm and a width of 15 μm of the MIMO transistor. A buffer inverter was used.

【0056】

The circuit simulation considered a 0.35 μm standard CMOS process, assuming a level 28 modified BSIM Model for the MOSFET model, a clock frequency of 500 MHz, and a 16 clock cycle for the input data data sequence.

【0057】

FIG. 10 is a graph comparing the power consumption occupied by the circuit in the simulation according to FIG. With reference to FIG. 10, it can be seen that the power consumption of the clock signal and the data signal does not differ greatly, but the power consumption consumed inside the circuit differs considerably. The input data used at this time is 10101010 ....

【0058】

FIG. 11 is a graph comparing PDPs in the simulation according to FIG. With reference to FIG. 11, it can be seen that PDP (Power Delay Product), that is, the product of power consumption and response delay, increases in the order of CPFF, TGFF, HLFF, SDFF and SAFF. The input data used at this time is 11001100 ....

【0059】

FIG. 12 is a circuit diagram of a CP flip-flop according to a fifth embodiment of the present invention. Referring to FIG. 12, the CP flip-flop includes a clock delay unit 910, a switch unit 920, a latch unit 930, and a buffer unit 940.

【0060】

The first virtual power supply VVdd responds to the reversed signal MSB of the Mode Selection signal MS and uses the switch M1 with a given on-resistance component to make the first virtual power supply Vdd. Is a power supply that transmits the above to the flip-flop circuit. The second virtual power supply VVss or VGND responds to the mode selection signal MS and transmits the second virtual power supply Vss to the flip-flop circuit using a switch M2 having a predetermined on-resistance component. It is a power supply. It is desirable that switch M1 is composed of HT NMOS transistors and switch M2 is composed of HT NMOS transistors.

【0061】

The clock delay unit 910 includes three inverters 911 to 913 and outputs a reverse clock signal Clkb obtained by inverting and delaying the clock signal Clk, and the three inverters 911 to 913 are composed of LT MOS transistors. The switch unit 920 includes a first switch 921 that switches the input data D in response to the clock signal Clk, and a second switch 922 that switches the output signal of the first switch 921 in response to the reverse clock signal Clkb. The first switch 921 and the second switch 922 are each composed of at least one LT MOS transistor. The latch portion 930 includes a first inverter 932 that reverses the output signal of the second switch 922, a second inverter 931 that reverses the output signal of the first inverter 932 and feeds it back to the input terminal of the first inverter 932, and one end thereof. It comprises a first LT multiplexer transistor 933 that is connected to the output terminal of the second switch 922, the other end is connected to the first supply power supply Vdd, and the gate is connected to the output terminal of the first inverter 932. The first inverter 932 and the second inverter 931 are HT. It is composed of MOS transistors. The buffer unit 940 includes an inverter composed of LT MOS transistors.

【0062】

The clock delay unit 910 and the switching unit 920 include an LT MOS transistor. The latch portion 930 includes a plurality of LT MOS transistors, or further includes at least one HT MOS transistor. The plurality of LT MOS transistors have a lower threshold voltage than the HT MOS transistor, and are between the first supply power supply voltage and the second supply power supply voltage, or the first virtual power supply voltage and the second supply power supply. It operates between a voltage or between the first virtual power supply voltage and the second virtual power supply voltage. The HT MOS transistor operates between the first supply power supply voltage and the second supply power supply voltage.

【0063】

Here, the threshold voltage is 0.33 ± 0.04 volt for the LT NMOS transistor, -0.4 ± 0.04 volt for the LT NMOS transistor, 0.6 ± 0.06 volt for the HT NMOS transistor, and -0.65 ± for the HT NMOS transistor. It should be 0.06 volt.

【0064】

FIG. 13 is a circuit diagram of a CP flip-flop according to a sixth embodiment of the present invention. Referring to FIG. 13, the CP flip-flop includes a clock delay unit 1010, a switch unit 920, a latch unit 930, and a buffer unit 940.

【0065】

The CP flip-flop according to the sixth embodiment is the same as the CP flip-flop according to the fifth embodiment, except for the clock delay portion 1010. That is, the clock delay unit 1010 is the data stored when the third inverter 1011 that reverses the clock signal Clk, the fourth inverter 1012 that reverses the output signal of the third inverter 1011, and the CP flip-flop are in the sleep mode. It is equipped with an anti-floating signal AF (Anti-Floating) provided to stabilize the state of the fourth inverter 1012 and a NOR gate 1013 that responds to the output signal of the fourth inverter 1012. The third inverter 1011 and the fourth inverter 1012 are composed of LT MOS transistors, and the NOR gate 1013 is composed of LT MOS transistors and HT MOS transistors.

【0066】

FIG. 14 is a circuit diagram of a CP flip-flop according to a seventh embodiment of the present invention. Referring to FIG. 14, the CP flip-flop includes a clock delay unit 1110, a switch unit 1120, a latch unit 1130, a buffer unit 1140, and a third inverter 1150.

【0067】

The clock delay unit 1110 includes three inverters 1111 to 1113 that reverse-delay the clock signal Clk, and these three inverters 1111 to 1113 are composed of LT MOS transistors. The switch unit 1120 includes a first switch 1121 to a fourth switch 1124. The first switch 1121 switches the input data D in response to the clock signal Clk, the second switch 1122 switches the output signal of the first switch 1121 in response to the reverse clock signal Clkb, and the third switch 1123 switches the clock signal. The output signal of the third inverter 1150 is switched in response to Clk, and the fourth switch 1124 switches the output signal of the third switch 1123 in response to the reverse clock signal Clkb. Each of the first switch 1121 to the fourth switch 1124 is composed of at least one LT MOS transistor.

【0068】

The latch portion 1130 is a first inverter 1132 that reverses the output signal of the second switch 1122, a second inverter 1131 that reverses the output signal of the first inverter 1132 and feeds it back to the input terminal of the first inverter 1132, and one end is the first. The output terminal of the 1st LT photoresist transistor 1133 and one end connected to the output terminal of the 2 switch 1122, the other end connected to the 1st power supply Vdd, and the gate connected to the output terminal of the 1st inverter 1132 It comprises a second LT photoresist transistor 1134 connected to, the other end connected to the first supply power supply Vdd, and the gate connected to the output terminal of the second inverter 1131. The first inverter 1132 and the second inverter 1131 are composed of HT MOS transistors.

【0069】

The buffer unit 1140 includes a fourth inverter 1141 in which the output terminal of the second switch 1122 is connected to the input terminal, and a fifth inverter 1142 in which the output terminal of the fourth switch 1124 is connected to the input terminal. The third inverter 1150 reverses the input data D and is composed of LT MOS transistors.

【0070】

FIG. 15 is a circuit diagram of a CP flip-flop according to an eighth embodiment of the present invention. Referring to FIG. 15, the CP flip-flop includes a clock delay section 1210, a switch section 1120, a latch section 1130, a buffer section 1140 and a third inverter 1150.

【0071】

The CP flip-flop according to the eighth embodiment is the same as the CP flip-flop according to the seventh embodiment, except for the clock delay portion 1210. That is, the clock delay unit 1210 uses the fourth inverter 1211 that reverses the clock signal Clk, the fifth inverter 1212 that reverses the output signal of the fourth inverter 1211, and the floating prevention signal AF and the output signal of the fifth inverter 1212. It comprises a responsive NOR gate 1213. The 4th inverter 1211 and the 5th inverter 1212 are composed of LT MOS transistors, and the NOR gate 1213 is composed of LT MOS transistors and HT MOS transistors.

【0072】

FIG. 16 is a circuit diagram of a CP flip-flop according to a ninth embodiment of the present invention. Referring to FIG. 16, the CP flip-flop includes a clock delay unit 1110, a switch unit 1120, a latch unit 1330, a buffer unit 1140, a third inverter 1150, and a data hold unit 1360.

【0073】

The CP flip-flop according to the ninth embodiment is the same as the CP flip-flop according to the seventh embodiment, except that the latch portion 1330 is different and the data hold portion 1360 is added.

【0074】

In the latch portion 1330, the output signal of the second switch 1122 is applied to the input terminal, the output terminal of the first inverter 1332 is connected to the output terminal of the fourth switch 1124, and the output signal of the fourth switch 1124 is applied to the input terminal. A second inverter 1331 whose output terminal is connected to the output terminal of the second switch 1122 is provided. The first inverter 1332 and the second inverter 1331 are composed of LT MOS transistors.

【0075】

One end of the data hold unit 1360 is connected to the output terminal of the second switch 1122, and one end is connected to the output terminal of the first HT NMOS transistor 1361 to which the data hold signal DH (Data Hold) is applied to the gate, and one end is connected to the output terminal of the fourth switch 1124. A fourth inverter in which the data hold signal DH is applied to the gate, the input terminal is connected to the other end of the first HT NMOS transistor 1361, and the output terminal is connected to the other end of the second HTN MOS transistor 1362. It includes 1363 and a fifth transistor 1364 whose input terminal is connected to the output terminal of the fourth transistor 1363 and whose output terminal is connected to the input terminal of the fourth transistor 1363. The 4th inverter 1363 and the 5th inverter 1364 are composed of HT MOS transistors.

【0076】

FIG. 17 is a circuit diagram of a CP flip-flop according to a tenth embodiment of the present invention. Referring to FIG. 17, the CP flip-flop includes a clock delay section 1410, a switch section 1120, a latch section 1130, a buffer section 1140, a third inverter 1150, and a set / reset section 1460.

【0077】

The CP flip-flop according to the tenth embodiment is the same as the CP flip-flop according to the seventh embodiment, except that the clock delay unit 1410 is different and the set / reset unit 1460 is added. The clock delay unit 1410 is a fourth inverter 1411 that reverses the clock signal Clk, a first NAND gate 1412 that responds to the output signal and enable signal En of the fourth inverter 1411, and an output signal and a floating prevention signal of the first NAND gate 1412. It is equipped with a NOR gate 1413 that responds to AF. The 4th inverter 1411 and the 1st NAND gate 1412 are composed of LT MOS transistors, and the NOR gate 1413 is composed of LT MOS transistors and HT MOS transistors.

【0078】

The set / reset unit 1460 has a second NAND gate 1461 that responds to the set signal S and the reset signal RS, and a first HT NMOS transistor 1462 whose one end is connected to the output terminal of the second switch 1122 and the reset signal RS is applied to the gate. One end is connected to the output terminal of the 4th switch 1124, the other end is connected to the other end of the 1st HT NMOS transistor 1462, and the set signal S is applied to the gate. It is coupled to the other end of 1462, the other end is connected to the second supply power supply Vss, and the gate is provided with a third HT NMOS transistor 1464 to which the output signal of the second NAND gate 1461 is applied. The second NAND gate 1461 is composed of LT MOS transistors.

【0079】

FIG. 18 is a detailed circuit diagram of the clock delay portion shown in FIGS. 13 and 15. Referring to FIG. 18, the LT polymerase transistor 151 and the LT NMOS transistor 152 constitute a fourth inverter that inverts the clock signal Clk, and the LT epitaxial transistor 153 and the LT NMOS transistor 154 invert the output signal of the fourth inverter. Configure the 5th inverter. One end of the NOR gate is connected to the first supply power supply Vdd, and one end is connected to the other end of the first HT facsimile transistor 155 to which the floating prevention signal AF is applied to the gate, and one end is connected to the other end of the first HT facsimile transistor 155, and the other end is reversed. The first LT photoresist transistor 156, which is connected to the clock signal Clkb and the output signal of the fifth inverter is applied to the gate, one end is connected to the reverse clock terminal Clkb, the other end is connected to the supply power supply GND, and the gate is connected to the first LT 5 The second LT NMOS transistor 157 to which the output signal of the inverter is applied, one end is connected to the reverse clock terminal Clkb, the other end is connected to the second supply power supply Vss or GND, and the anti-floating signal AF is applied to the gate. 2nd HT It comprises an NMOS transistor 158.

【0080】

The inverted clock signal Clkb is commonly generated from the other end of the first LT NMOS transistor 156, one end of the first LT NMOS transistor 157, and one end of the second HT NMOS transistor 158.

【0081】

Various embodiments of the present invention shown in FIGS. 12 to 17 are circuits proposed for use in MTCMOS LSIs.

【0082】

The CP flip-flop according to the present invention does not require an additional circuit for storing latched data in the sleep mode, and uses an LT MOS transistor as an element constituting the circuit of the clock delay part and the switch part, so that the circuit can be used. Minimizes power consumption not only when in active mode but also when in sleep mode.

【0083】

Referring to FIG. 12, the mode selection signal MS remains high when in active mode. At this time, it is desirable that the two transistors M1 and M2 used as switches have a large gate width / gate length ratio (Gate Width / Gate Length) in order to minimize the on-resistance. This successfully serves as a power supply to the first virtual power supply Vdd and the second virtual power supply VVss or VGND generated by the first power supply Vdd and the second power supply Vss or GND through the switches M1 and M2, respectively. This is to make it happen.

【0084】

Since the mode selection signal MS remains low in sleep mode, the first virtual power supply VVdd and the second virtual power supply VVss or VGND are the actual power supply lines, the first power supply Vdd and the second power supply Vss. Or it is disconnected from GND. However, since the latch portion 930 is connected to the first power supply Vdd and the second power supply Vss or GND, there is no problem in storing data even in the sleep mode.

【0085】

On the other hand, the switch transistors M1 and M2, which are turned off in response to the mode selection signal MS, have the advantage that the subthreshold leakage current flowing in the sleep mode in the CP flip-flop composed of the LT MOS transistors is suppressed to the maximum. This is because a MOS transistor having a large threshold voltage has a much smaller leakage current than a MOS transistor having a low threshold voltage. Also, by fixing the anti-floating signal AF to the high state in sleep mode, the switch of the CP flip-flop is kept off. By doing so, it is possible to more reliably prevent the leakage current that may occur when the switch is floated. Also when the power is turned off, the leakage current preventing turns off the NMOS transistors 1122 and 1124 in FIGS. 14 through 17 kill.

【0086】

FIG. 19 shows the relationship between the mode selection signal MS and the floating prevention signal AF. Referring to FIG. 19, after a certain period of time AW (Active Waiting) elapses after the mode selection signal MS transitions from the sleep mode to the active mode, the logical state of the floating prevention signal AF transitions from the high state to the low state. .. When the mode selection signal MS is switched from the sleep mode to the active mode, if the mode selection signal MS and the floating prevention signal AF transition at the same time, the switch is made before the second virtual power supply VGND is completely discharged by the mode selection signal MS. The data stored in the latch section may be lost due to the opening of. Therefore, as shown in FIG. 19, it is desirable that the floating prevention signal AF transitions to the low state with a slight time delay AW as compared with the mode selection signal MS.

【0087】

FIG. 20 shows the relationship between the mode selection signal MS and the data hold signal DH. Referring to FIG. 20, the data hold signal DH is used during a predetermined period of SW (Sleep Waiting) before the mode selection signal MS transitions from the active mode to the sleep mode, and the mode selection signal MS changes from the sleep mode to the active mode. It has a logical high value for a period of time AW after the transition. As shown in FIG. 20, the data hold signal DH is a signal for reading or writing data to the latch portion at the time of switching between the active mode and the sleep mode.

【0088】

The CP flip-flop according to the present invention uses a small number of transistors compared to the number of transistors used to realize the existing flip-flop, and the timing design between the control signals required to operate the flip-flop is easy. There is an advantage to make it. The CP flip-flop can also be used for MTCMOS LSI, and when compared with the master-slave flip-flop circuit used for existing MTCMOS LSI, no special circuit for storing data stored in sleep mode is added. It has the advantage that it does not require complicated timing design to operate the flip-flop. Therefore, it can be applied to low power DSPs (Digital Signal Processors) and microprocessor LSI flip-flops, including portable LSIs that require low power operation.

【0089】

[Effect of the invention]

As described above, the CP flip-flop according to the present invention does not need to be precharged, and data can be transmitted to the output at once, so that a narrow area, low power consumption, and high-speed operation can be realized. It also has the advantage of being able to operate in active and sleep modes without the need to add a separate circuit to store the latched data when applied to an MTCMOS LSI.

[Simple explanation of drawings]

[Figure 1]

It is a circuit diagram of an existing transmission gate MS-FF (Master-Slave Flip-Flop).

[Figure 2]

It is a circuit diagram of an existing hybrid latch flip-flop.

[Fig. 3]

It is a circuit diagram of an existing semi-dynamic flip-flop.

[Fig. 4]

It is a circuit diagram of a flip-flop used as an existing sense amplifier.

[Fig. 5]

It is a circuit diagram of the CP flip-flop which concerns on 1st Embodiment of this invention.

[Fig. 6]

It is a circuit diagram of the CP flip-flop which concerns on 2nd Embodiment of this invention.

[Fig. 7]

It is a circuit diagram of the CP flip-flop which concerns on 3rd Embodiment of this invention.

[Fig. 8]

It is a circuit diagram of the CP flip-flop which concerns on 4th Embodiment of this invention.

[Fig. 9]

It is a circuit diagram of a test bench for testing a flip-flop.

[Fig. 10]

It is the figure which compared the power consumption occupied by the circuit by the simulation which concerns on FIG.

[Fig. 11]

It is the figure which compared PDP by the simulation which concerns on FIG.

[Fig. 12]

It is a circuit diagram of the CP flip-flop which concerns on 5th Embodiment of this invention.

[Fig. 13]

It is a circuit diagram of the CP flip-flop which concerns on 6th Embodiment of this invention.

[Fig. 14]

It is a circuit diagram of the CP flip-flop which concerns on 7th Embodiment of this invention.

[Fig. 15]

It is a circuit diagram of the CP flip-flop which concerns on 8th Embodiment of this invention.

[Fig. 16]

It is a circuit diagram of the CP flip-flop which concerns on 9th Embodiment of this invention.

[Fig. 17]

It is a circuit diagram of the CP flip-flop which concerns on the tenth embodiment of this invention.

[Fig. 18]

It is a detailed circuit diagram of the clock delay part shown in FIG. 13 and FIG.

[Fig. 19]

It is a waveform diagram which shows the relationship between the mode selection signal MS and the floating prevention signal AF for storing latched data.

[Fig. 20]

It is a waveform diagram which shows the relationship between the mode selection signal MS and the data hold signal DH.

[Explanation of symbols]

210 Clock delay 220 Switch section 230 Latch part 240 Buffer part