Semiconductor device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a Double Diffused Metal Oxide Semiconductor (hereinafter, referred to as DMOS) transistor.

【0002】

[Conventional technology]

As an example of a semiconductor device for switching a large current, a semiconductor device including a DMOS transistor will be described. As shown in FIG. 30, the N-epitaxial layer 102 is formed on the p-silicon substrate 101. An N + embedded diffusion region 103 is formed between the p-silicon substrate 101 and the N-epitaxial layer 102. Further, a P + embedded diffusion region 104 is formed between the N + embedded diffusion region 103 and the N-epitaxial layer 102.

【0003】

An N diffusion region 107 is formed on the surface of the N-epitaxial layer 102. The P diffusion region 106 is formed so as to surround the N diffusion region 107 from the surroundings. Further, on the surface of the N-epitaxial layer 102, a P diffusion region 105 is formed which is in contact with the P diffusion region 106 and reaches the P + embedded diffusion region 104. A gate electrode 110 is formed on the surface of the P diffusion region 106 located between the N diffusion region 107 and the N-epitaxial layer 102 with an insulating film interposed therebetween.

【0004】

A source electrode 111 electrically connected to the N diffusion region 107 is formed. Further, a silicon oxide film 109 for separation is formed on the surface of the N-epitaxial layer 102. A drain electrode 112 is formed on the opposite side of the silicon oxide film 109 from the source electrode 111. The drain electrode 112 is electrically connected to the N diffusion region 108 formed in the N-epitaxial layer 102. The conventional semiconductor device is configured as described above.

【0005】

[Problems to be Solved by the Invention]

In a normal semiconductor device, the electric field tends to concentrate at the corner of the P diffusion region 106, but in the above-mentioned semiconductor device, the corner is due to the depletion layer (RESURF effect) extending from the P + embedded diffusion region 104 as shown in FIG. The electric field concentrated on the part is relaxed.

【0006】

As a result, in this semiconductor device, the depletion layer end extending from the interface between the N-epitaxial layer 102 and the P + embedded diffusion region 104 toward the N diffusion region 108 and the depletion layer extending toward the P + embedded diffusion region 104 side. It can be increased to a withstand voltage based on the width L of the depletion layer closest to the edge.

【0007】

However, conversely, in this semiconductor device, the withstand voltage is limited by the portion where the ends of both depletion layers are closest to each other. In order to further improve the withstand voltage, it is necessary to increase the distance between the ends of both depletion layers, and it is effective to take measures to increase the film thickness of the N-epitaxial layer 102.

【0008】

However, when the film thickness of the N-epitaxial layer 102 is made thicker, it is necessary to form the P diffusion region 105 or the like for separating the N-epitaxial layer 102 deeper accordingly. Further, when a vertical NPN transistor or the like is formed as a semiconductor element, a current flows in the vertical direction, but in this case, there is a problem that the resistance of the semiconductor device increases.

【0009】

The present invention has been made to solve the above problems, and a semiconductor device capable of easily improving the withstand voltage without increasing the film thickness of the N-epitaxial layer and without changing the manufacturing method. The purpose is to provide.

【0010】

[Means for solving problems]

The first aspect of the semiconductor device in one aspect of the present invention is a semiconductor substrate having a main surface, a first conductive type semiconductor layer, a first conductive type first embedded impurity region, and a second conductive type second embedded. It includes an impurity region, a second conductive type first impurity region, a first conductive type second impurity region, and a semiconductor element. The first conductive type semiconductor layer is formed on the main surface of the semiconductor substrate. The first conductive type first embedded impurity region is formed between the semiconductor layer and the semiconductor substrate. The second conductive type second embedded impurity region is formed between the first embedded impurity region and the semiconductor layer. The second conductive type first impurity region is formed on the surface of the semiconductor layer and is electrically connected to the second embedded impurity region. The first conductive type second impurity region is formed on or inside the surface of the semiconductor layer located in the region above the second embedded impurity region. The semiconductor element includes a first impurity region and a second impurity region, and is formed on the surface of the semiconductor layer to have a switching function. When the semiconductor element is off, the withstand voltage is ensured by the depletion layer extending from the interface between the second embedded impurity region and the semiconductor layer. In the second embedded impurity region, the first recessed portion or the second embedded impurity region in which the surface of the second embedded impurity region is recessed in a direction away from the second impurity region is located in a portion located substantially directly below the second impurity region. Includes the first gap that is interrupted.

【0011】

According to this semiconductor device, a first recessed portion in which the surface of the second embedded impurity region is recessed so as to be away from the second impurity region in a portion located substantially directly below the second impurity region, or a first recessed portion in which this region is interrupted. The formation of one gap increases the effective thickness of the semiconductor layer in this portion. As a result, in the off state, the depletion layer end extending toward the second embedded impurity region of the depletion layer extending from the interface between the semiconductor layer and the second embedded impurity region becomes another portion immediately below the second impurity region. It will be located deeper than the part. As a result, as compared with the conventional semiconductor device, the width of the depletion layer located directly under the second impurity region is extended, the withstand voltage in the portion directly under the second impurity region is increased, and the withstand voltage of the entire semiconductor device is improved. ..

【0012】

In order to provide a DMOS transistor as a semiconductor element, specifically, a first conductive type third impurity region formed so as to be surrounded by a first impurity region on the surface of the first impurity region, and a third impurity region thereof. It is desirable to include an electrode portion formed by interposing an insulating film on the surface of the first impurity region sandwiched between the semiconductor layer and the semiconductor layer.

【0013】

Further, when the IGBT is provided as the semiconductor element, it is desirable that the second conductive type fourth impurity region formed so as to be in contact with the second impurity region is further included.

【0014】

When a bipolar transistor is provided as the semiconductor element, it is desirable that the second conductive type fifth impurity region formed on the surface of the semiconductor layer is included.

【0015】

Further, it is desirable that the second embedded impurity region contains a plurality of first recessed portions.

【0016】

In this case, in the off state, many portions where the width of the depletion layer extends are formed, so that the withstand voltage of the semiconductor device having a wider second impurity region can be improved.

【0017】

Further, it is desirable that the second embedded impurity region contains a plurality of first gaps.

【0018】

In this case, the effective thickness of the semiconductor layer in this portion is further increased, and the width of the depletion layer extending from the interface between the semiconductor layer and the second embedded impurity region is further increased in the off state. As a result, the withstand voltage of the semiconductor device is further improved.

【0019】

Further, it is desirable that the second embedded impurity region includes a plurality of regions that are electrically floated by the plurality of first gaps.

【0020】

In this case, the potential of each floating second embedded impurity region also rises along the direction from the side of the first impurity region to the side of the second impurity region. As a result, the potential difference between the potential of the second embedded impurity region located immediately below the second impurity region and the potential of the second impurity region becomes smaller. As a result, the withstand voltage of the semiconductor device can be improved as the potential difference becomes smaller.

【0021】

Further, the first embedded impurity region is a second recessed portion or a first embedded region in which the surface of the first embedded impurity region is recessed in a direction away from the second impurity region in a portion located substantially directly below the first gap portion. It is desirable to include a second gap where is interrupted.

【0022】

In this case, the impurities constituting the first embedded impurity region are suppressed from diffusing into the semiconductor layer portion between the second embedded impurity regions located across the first gap, and the impurities in this portion are suppressed. The increase in concentration will be suppressed. As a result, even if the distance between the first gaps is widened, the increase in the pinch-off voltage can be suppressed to a small value, and the effective film thickness of the semiconductor layer located directly below the second impurity region can be made thicker. As a result, the withstand voltage of the semiconductor device can be further improved.

【0023】

Further, it is preferable that the bonding interface between the first embedded impurity region and the second embedded impurity region is uneven.

【0024】

In this case, the bonding interface between the first embedded impurity region and the second embedded impurity region becomes uneven, so that the depletion layer extending from the bonding interface becomes wider. As a result, the withstand voltage of the junction portion is improved, and the withstand voltage of the semiconductor device when the potential of the collector when, for example, a bipolar transistor is provided as the semiconductor element is negatively biased can be improved.

【0025】

The second aspect of the semiconductor device in one aspect of the present invention is a semiconductor substrate having a main surface, a first conductive type semiconductor layer, a first conductive type embedded impurity region, and a first conductive type first impurity region. And a second conductive type second impurity region and a semiconductor element. The first conductive type semiconductor layer is formed on the main surface of the semiconductor substrate. The first conductive type embedded impurity region is formed between the semiconductor substrate and the semiconductor layer. The first impurity region of the first conductive type is formed on the surface of the semiconductor layer and is electrically connected to the embedded impurity region. The second conductive type second impurity region is formed on the surface of the semiconductor layer located in the region above the embedded impurity region. The semiconductor element includes a first impurity region and a second impurity region, and is formed on the surface of the semiconductor layer to have a switching function. When the semiconductor element is off, the withstand voltage is ensured by the depletion layer extending from the interface between the second impurity region and the semiconductor layer. The embedded impurity region includes a recessed portion where the surface of the embedded impurity region is recessed in a direction away from the second impurity region in a portion located substantially directly below the second impurity region, or a gap portion where the embedded region is interrupted. ..

【0026】

According to this semiconductor device, in the off state, the depletion layer extends particularly from the interface between the second impurity region and the semiconductor layer. At this time, in the portion located substantially directly below the second impurity region, a recessed portion is formed so that the surface of the embedded impurity region is away from the second impurity region, or a gap portion in which this region is interrupted is formed. In this portion, the thickness of the effective semiconductor layer is increased, and the end of the depletion layer extending toward the embedded impurity region can reach a deeper position. As a result, the width of the depletion layer is widened and the withstand voltage of the semiconductor device is improved.

【0027】

When a DMOS transistor is provided as a semiconductor element, a first conductive type third impurity region formed so as to be surrounded by a second impurity region on the surface of the second impurity region, a third impurity region, and a semiconductor layer are used. It is desirable to include an electrode portion formed by interposing an insulating film on the surface of the sandwiched second impurity region.

【0028】

When a bipolar transistor is provided as a semiconductor element, it is desirable that the second conductive type fourth impurity region formed on the surface of the semiconductor layer is included.

【0029】

Further, it is desirable that the recessed portion or the gap portion is formed in the portion where the depletion layer extends.

【0030】

In this case, the extending depletion layer can be further extended, and when a bipolar transistor is provided as the semiconductor element, for example, the withstand voltage can be improved without lowering the current amplification factor.

【0031】

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 The semiconductor device including the DMOS transistor according to the first embodiment of the present invention will be described. As shown in FIG. 1, the N-epitaxial layer 2 is formed on the P-silicon substrate 1. An N + embedded diffusion region 3 is formed between the P-silicon substrate 1 and the N-epitaxial layer 2. Further, a P + embedded diffusion region 4 is formed between the N + embedded diffusion region 3 and the N-epitaxial layer 2.

【0032】

An N diffusion region 7 is formed on the surface of the N-epitaxial layer 2. The P diffusion region 6 is formed so as to surround the N diffusion region 7 from the surroundings. Further, on the surface of the N-epitaxial layer 2, a P diffusion region 5 is formed which is in contact with the P diffusion region 6 and reaches the P + embedded diffusion region 4. A gate electrode 10 is formed on the surface of the P diffusion region 6 located between the N diffusion region 7 and the N-epitaxial layer 2 with an insulating film interposed therebetween.

【0033】

A source electrode 11 electrically connected to the N diffusion region 7 is formed. Further, a silicon oxide film 9 for separation is formed on the surface of the N-epitaxial layer 2. A drain electrode 12 is formed on the opposite side of the silicon oxide film 9 from the source electrode 11. The drain electrode 12 is electrically connected to the N diffusion region 8 formed in the N-epitaxial layer 2.

【0034】

In this semiconductor device, the surface of the P + embedded diffusion region 4 located substantially directly below the N diffusion region 8 is recessed so as to be away from the N diffusion region 8, and in particular, the P + embedded diffusion region 4 is constricted in this portion. It is formed like this. The constriction 64 is formed, for example, along the direction in which the N diffusion region 8 extends.

【0035】

As shown in FIG. 2, the constriction 64 is subjected to ion implantation treatment using the photoresist pattern 61 covering at least the region immediately below the N diffusion region 8 as a mask, and then subjected to heat treatment. Is formed by.

【0036】

That is, the injected impurities are diffused into the N-epitaxial layer 2 region and the N + embedded diffusion region 3 located directly below the N diffusion region 8 by heat treatment, so that the P + embedded diffusion regions 4a and 4b are mutually located in this region. Connected, a constriction 64 is formed in this part.

【0037】

In the above-mentioned semiconductor device, a constriction 64 is formed in the portion of the P + embedded diffusion region 4 located directly below the N diffusion region 8, and the surface of the P + embedded diffusion region 4 is recessed so as to be away from the N diffusion region 8. Therefore, the effective thickness of the N-epitaxial layer 2 in this portion is increased as compared with the case where there is no such constriction.

【0038】

Therefore, in the off state, the depletion layer extends from the interface between the N-epitaxial layer 2 and the P + embedded diffusion region 4, but at the edge of the depletion layer extending toward the P + embedded diffusion region 4 at this time, As shown in FIG. 3, the portion directly below the N diffusion region 8 is located deeper than the other portions.

【0039】

As a result, as compared with the conventional semiconductor device, the width L1 of the depletion layer located directly under the N diffusion region 8 is extended, the withstand voltage at the portion directly under the drain electrode 12 is increased, and the withstand voltage of the entire semiconductor device is improved.

【0040】

In this embodiment, the case where the constriction 64 of the P + embedded diffusion region 4 is formed substantially directly below the N diffusion region 8 along the N diffusion region 8 has been described as an example. It may be formed intermittently in a dot shape. Further, the region to be the P + embedded diffusion region 4 may be initially formed in a dot shape, and the dot-shaped diffusion regions may be connected to each other by heat treatment to form the P + embedded diffusion region 4.

【0041】

Further, in the above-mentioned semiconductor device, as shown in FIG. 4, a current 63 may flow in the P + embedded diffusion region 4. As shown in FIG. 5, when the coil 62 (L load) is connected to the drain electrode of the DMOS transistor, the electromotive force of the coil 62 is generated at the moment when the DMOS on the high side changes from the on state to the off state. Causes the drain potential to be lower than the source potential.

【0042】

Therefore, the forward bias operation of the parasitic diode of the DMOS transistor causes a current to flow toward the coil as shown by the arrow. This current will flow through the P + embedded diffusion region 4.

【0043】

In such a case, as shown in FIG. 6, by forming the constriction 64 of the P + embedded diffusion region 4 along the direction in which the current 63 flows, the resistance when the current flows through the P + embedded diffusion region 4. Can be minimized.

【0044】

As described above, in this semiconductor device, the withstand voltage of the semiconductor device can be easily improved by simply changing the mask pattern for forming the P + embedded diffusion region 4 without increasing the thickness of the N-epitaxial layer 2. be able to.

【0045】

Embodiment 2 The semiconductor device including the DMOS transistor according to the second embodiment of the present invention will be described. As shown in FIG. 7, in this semiconductor device, a slit 65 is formed in the P + embedded diffusion region 4 located directly below the N diffusion region 8.

【0046】

Since the other configurations are the same as those of the semiconductor device shown in FIG. 1 described in the first embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0047】

Similar to the case of the first embodiment, the slit 65 in this semiconductor device is subjected to ion implantation treatment using a photoresist pattern covering a region immediately below the N diffusion region 8 as a mask, and then heat-treated. It is formed by passing through.

【0048】

At this time, due to the heat treatment, the injected impurities are diffused into the region of the N-epitaxial layer 2 located immediately below the N diffusion region 8 and the N + embedded diffusion region 3, but unlike the case of the first embodiment. Finally, in this part, the P + embedded diffusion regions 4a and 4b are not connected to each other.

【0049】

In particular, in the case of this semiconductor device, since the N + embedded diffusion region 3 and the drain electrode 12 are electrically connected, the N + embedded diffusion region 3 and the P + embedded diffusion regions 4a and 4b are in the withstand voltage holding state. A reverse bias is applied between. At this time, it is desirable that the pinch-off voltage in the slit 65 is lower than the withstand voltage between the N + embedded diffusion region 3 and the P + embedded diffusion regions 4a and 4b.

【0050】

As shown in FIG. 8, in the state before pinch-off, the depletion layer formed on the P + embedded diffusion region 4a side and the depletion layer formed on the P + embedded diffusion region 4b side are not connected. At this time, the drain voltage is equal to the potential of N + embedded diffusion region 3. Further, the potential of the N + embedded diffusion region 3 does not rise above the pinch-off voltage between the P + embedded diffusion regions 4a and 4b.

【0051】

When the pinch-off voltage is, for example, 20V, the potential of the N + embedded diffusion region 3 is 20V higher than the source potential. Then, as shown in FIG. 9, in the state after pinch-off, the depletion layer formed on the P + embedded diffusion region 4a side and the depletion layer formed on the P + embedded diffusion region 4b side are connected.

【0052】

As a result, as compared with the semiconductor device of the first embodiment, the effective thickness of the N-epitaxial layer 2 in the off state is increased (width of the depletion layer), and the withstand voltage in the portion immediately below the drain electrode 12 is further increased to achieve the semiconductor. The withstand voltage of the entire device is improved.

【0053】

Further, as in the case of the first embodiment, the withstand voltage of the semiconductor device can be improved only by changing the mask pattern for forming the P + embedded diffusion region.

【0054】

Embodiment 3 The semiconductor device including the DMOS transistor according to the third embodiment of the present invention will be described. As shown in FIG. 10, in this semiconductor device, a constriction 66 is formed in the N + embedded diffusion regions 3a and 3b located directly below the N diffusion region 8.

【0055】

Since the other configurations are the same as those of the semiconductor device shown in FIG. 7 described in the second embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0056】

The constriction 66 in the N + embedded diffusion region 3 uses a photoresist pattern covering the region immediately below the N diffusion region 8 as a mask, as in the case of forming the P + embedded diffusion region 4 in the first embodiment. It is formed by performing an ion implantation treatment and then performing a heat treatment.

【0057】

At this time, the injected impurities are diffused into the region of the N-epitaxial layer 2 located directly below the N diffusion region 8 and the P-silicon substrate 1 by heat treatment, and finally the N + embedded diffusion regions 3a and 3b are mutually formed. Connected, a constriction 66 is formed in this part.

【0058】

In the case of the semiconductor device described in the second embodiment, by widening the distance between the adjacent P + embedded diffusion regions 4a and 4b, the effective film thickness of the N-epitaxial layer 2 located directly below the N diffusion region 8 can be increased. Can be thickened.

【0059】

However, the impurities constituting the N + embedded diffusion region 3 are diffused in the portion of the N- epitaxial layer 2 between the P + embedded diffusion region 4a and the P + embedded diffusion region 4b, and the impurity concentration in this portion increases. Therefore, the extension of the depletion layer in this portion is suppressed, and the depletion layer may not be connected and pinch-off may not be possible. Therefore, in order to prevent this, the spacing between adjacent P + embedded diffusion regions 4a and 4b is limited.

【0060】

On the other hand, in this semiconductor device, the N + embedded diffusion region 3a and the N + embedded diffusion region 3b are connected in a region directly below the N diffusion region 8, and a constriction 66 is formed in this region. That is, the constriction 66 of the N + embedded diffusion region 3 is formed immediately below the portion sandwiched between the P + embedded diffusion region 4a and the P + embedded diffusion region 4b.

【0061】

Therefore, as shown in FIG. 11, the impurities constituting the N + embedded diffusion region 3 are suppressed from diffusing into the portion of the N-epitaxial layer 2 between the P + embedded diffusion region 4a and the P + embedded diffusion region 4b. , The increase in impurity concentration in this portion will be suppressed.

【0062】

As a result, as compared with the case of the semiconductor device in the second embodiment, the increase in the pinch-off voltage can be suppressed to be small even if the width (interval) of the slit between the P + embedded diffusion region 4a and the P + embedded diffusion region 4b is further widened. Therefore, the effective film thickness of the N-epitaxial layer 2 located directly below the N diffusion region 8 can be made thicker. As a result, the withstand voltage of the semiconductor device can be further improved.

【0063】

Embodiment 4 The semiconductor device including the DMOS transistor according to the fourth embodiment of the present invention will be described. As shown in FIG. 12, in this semiconductor device, a slit 67 is formed in the N + embedded diffusion region 3 located directly below the N diffusion region 8.

【0064】

Since the other configurations are the same as those of the semiconductor device shown in FIG. 10 described in the third embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0065】

The slit 67 in the N + embedded diffusion region 3 is subjected to ion implantation treatment using the photoresist pattern covering the region immediately below the N diffusion region 8 as a mask, as in the case of the second embodiment, and then the slit 67 is subjected to the ion implantation treatment. It is formed by undergoing the heat treatment of.

【0066】

At this time, the injected impurities are diffused into the region of the N-epitaxial layer 2 located directly under the N diffusion region 8 and the P- substrate 1 by the heat treatment, but finally, N + embedded diffusion is performed in this region. Regions 3a and 3b are not connected to each other.

【0067】

In this semiconductor device, when a reverse bias is applied between the N + embedded diffusion region 3 and the P- substrate 1, the depletion layer extending from the N + embedded diffusion regions 3a and 3b penetrates into the N-epitaxial layer 2 due to the JFET effect. It is desirable to be able to prevent this from happening. Further, it is desirable that the distance between the P + embedded diffusion region 4 and the P-board 1 is set so that the punch-through phenomenon does not occur between them.

【0068】

In the state before pinch-off, as shown in FIG. 13, the depletion layers formed on the side of P + embedded diffusion region 4a and the side of P + embedded diffusion region 4b are not connected to each other, but in the state after pinch-off, FIG. 14 As shown in, both depletion layers will be connected. Since the slit portion is formed in the N + embedded diffusion region 3, the depletion layer expands so as to include the portion of the N-epitaxial layer 2 located in the region sandwiched by the N + embedded diffusion regions 3a and 3b.

【0069】

As a result, the effective thickness of the N-epitaxial layer 2 in the off state can be increased as compared with the case of the semiconductor device according to the third embodiment. As a result, the withstand voltage in the portion directly below the drain electrode 12 is further increased, and the withstand voltage of the entire semiconductor device is improved.

【0070】

Embodiment 5 The semiconductor device including the DMOS transistor according to the fifth embodiment of the present invention will be described. As shown in FIG. 15, in the present semiconductor device, a plurality of constrictions 64 described in the first embodiment are formed in the P + embedded diffusion region 4.

【0071】

Since the other configurations are the same as those of the semiconductor device shown in FIG. 1 described in the first embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0072】

In the semiconductor device according to the first embodiment, it has been explained that a current may flow in the P + embedded diffusion region 4 during a predetermined operation. When a current flows through the P + embedded diffusion region 4, it is necessary to make the region area of the N diffusion region 8 relatively large in order to secure the current capacity.

【0073】

In such a case, as shown in FIG. 16, a plurality of constrictions are formed in the N + embedded diffusion region 3, so that many portions where the width of the depletion layer is extended are formed in the off state. As a result, even for a semiconductor device having a wider N diffusion region 8, the withstand voltage in the portion directly below the drain electrode 12 increases, and the withstand voltage of the entire semiconductor device can be improved .

【0074】

Embodiment 6 A semiconductor device including a DMOS transistor according to a sixth embodiment of the present invention will be described. As shown in FIG. 17, in this semiconductor device, a plurality of slits 67 are formed in the P + embedded diffusion regions 4a to 4f.

【0075】

Since the other configurations are the same as those of the semiconductor device shown in FIG. 15 described in the fifth embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0076】

In this semiconductor device, as in the case of the semiconductor device described in the second embodiment, the slit 67 is formed in the P + embedded diffusion region 4, which is more effective than the semiconductor device described in the fifth embodiment. The thickness of the typical N-epitaxial layer 2 can be further increased. As a result, the withstand voltage of the semiconductor device, which requires a relatively wide N + embedded diffusion region 3, can be further improved.

【0077】

Further, in this semiconductor device, as shown in FIG. 18, since each P + embedded diffusion region 4b to 4e is surrounded by an N-type semiconductor region, a depletion layer extending from the source (electrode 11) side is, for example, P + embedded. When the diffusion region 4b is reached, a depletion layer is formed so as to surround the P + embedded diffusion region 4b. Finally, when the depletion layer reaches the N diffusion region 8, all P + embedded diffusion regions 4b to 4e are surrounded by the depletion layer.

【0078】

In the depleted region of the N-epitaxial layer 2, the potential rises toward the N diffusion region 8 as shown by the arrow. At this time, if the P + embedded diffusion regions 4b to 4e are electrically floating, along the direction from the P diffusion region 5 (each P + embedded diffusion region 4a, 4f) side toward the N diffusion region 8 side. Therefore, the potential of the P + embedded diffusion region 4b to 4e also rises.

【0079】

As a result, the potential difference between the potentials of the P + embedded diffusion regions 4c and 4d located immediately below the N diffusion region 8 and the drain potential (potential of the N diffusion region 8) becomes smaller. As a result, the withstand voltage of the semiconductor device can be improved as the potential difference becomes smaller.

【0080】

Embodiment 7 As the semiconductor device according to the seventh embodiment of the present invention, a semiconductor device having a gate isolated bipolar transistor (Insulated Gate Bipolar Transistor, hereinafter referred to as IGBT) will be described. As shown in FIG. 19, an N diffusion region 7 is formed on the surface of the N-epitaxial layer 2. The P diffusion region 6 is formed so as to surround the N diffusion region 7 from the surroundings.

【0081】

Further, a P + region 15 is formed on the surface of the N-epitaxial layer 2. An N diffusion region 8 is formed directly below the P + region 15. The P + region 15 is the collector, the P diffusion region 6 is the emitter, and the N-epitaxial layer 2 is the base. The collector electrode 16 is connected to 15 in the P + region, and the emitter electrode 17 is connected to the P diffusion region 6.

【0082】

In this transistor, the base current is supplied through the channel region formed in the P diffusion region 6 by applying a predetermined voltage to the gate electrode 10. Such transistors are especially called IGBTs. Since the other configurations are the same as those of the semiconductor device shown in FIG. 1 described in the first embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0083】

In this semiconductor device, as shown in FIG. 20, a vertical PNP transistor is formed by the P + region 15, the N diffusion region 8, the N-epitaxial layer 2 and the P + embedded diffusion region 4 directly under the collector electrode 16. It will be in a state of being. The withstand voltage in the IGBT corresponds to the withstand voltage (BVceo) between the collector and the emitter when the base of this vertical transistor is floated. Then, the base width in this transistor becomes an effective N-epitaxial layer 2.

【0084】

In this IGBT, as shown in FIG. 20, a constriction 64 is formed in the portion of the P + embedded diffusion region 4 located directly below the N diffusion region 8, and as described in the first embodiment, this portion is formed. The effective thickness of the N-epitaxial layer 2 in the above is increased, and the width of the depletion layer in this portion is widened. As a result, the withstand voltage of the semiconductor device having the IGBT in the off state is improved.

【0085】

Embodiment 8 As the semiconductor device according to the eighth embodiment of the present invention, a semiconductor device having a PNP transistor will be described. As shown in FIG. 21, an N diffusion region 24 and a P diffusion region 25 are formed adjacent to each other on the surface of the N-epitaxial layer 2. Further, the P diffusion region 6 and the P diffusion region 5 are formed adjacent to each other on the surface of the N-epitaxial layer 2 separated from the N diffusion region 24 and the P diffusion region 25 with the silicon oxide film 9 interposed therebetween.

【0086】

A collector electrode 21 electrically connected to the P diffusion regions 5 and 6 is formed. An emitter electrode 22 electrically connected to the P diffusion region 25 is formed. A base electrode 23 electrically connected to the P diffusion region 24 is formed. Since the other configurations are the same as those of the semiconductor device shown in FIG. 1 described in the first embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0087】

In this semiconductor device, a PNP transistor based on the P diffusion region 5 and 6 and the P + diffusion region 4 as a collector, the P diffusion region 25 as an emitter, and the N-epitaxial layer 2 as a base is formed.

【0088】

The withstand voltage in the semiconductor device corresponds to the withstand voltage (BVceo) between the collector and the emitter when the base of this transistor is floated. This withstand voltage tends to decrease as the current amplification factor hFE of the transistor increases, and is inversely proportional to the current amplification factor hFE to the 1/3 to 1/4 power.

【0089】

Therefore, when it is desired to improve the withstand voltage of the semiconductor device, it is necessary to suppress the current amplification factor hFE of the transistor to some extent. In particular, when the N-epitaxial layer 2 is used as a base, the value of the current amplification factor hFE is often several hundreds or more because the impurity concentration of the base is considerably low.

【0090】

In this semiconductor device, as described in the first embodiment, the constriction 64 is formed in the portion of the P + embedded diffusion region 4, so that the effective thickness of the base N-epitaxial layer 2 is increased. Therefore, as shown in FIG. 22, the width of the depletion layer in this portion widens. As a result, the withstand voltage of the semiconductor device having the PNP transistor in the off state is improved.

【0091】

Embodiment 9 As the semiconductor device according to the ninth embodiment of the present invention, a semiconductor device having a PNP transistor will be described. As shown in FIG. 23, a plurality of constrictions 66 are formed in the N + embedded diffusion region 3. In addition, a plurality of constrictions 64 are also formed in the P + embedded diffusion region 4. Since the other configurations are the same as those of the semiconductor device shown in FIG. 21 described in the eighth embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0092】

As described above, the N + embedded diffusion region 3 having a plurality of constrictions 66 is formed by diffusing a plurality of impurity regions formed in advance at intervals by a subsequent heat treatment and connecting them to each other. The same applies to the P + embedded diffusion region 4 having a plurality of constrictions 64.

【0093】

Therefore, in the N + embedded diffusion region 3 and the P + embedded diffusion region 4 that are connected and integrated, it is equivalent to lowering the concentration of each impurity as compared with the case where each region is integrally formed from the beginning. .. As a result, the diffusion length of impurities that diffuse in the vertical direction from the N + embedded diffusion region 3 and the P + embedded diffusion region 4 also becomes shorter. That is, diffusion in the vertical direction is suppressed. Further, by forming a plurality of constrictions 64 and 66 in the N + embedded diffusion region 3 and the P + embedded diffusion region 4, respectively, the junction interface between the N + embedded diffusion region 3 and the P + embedded diffusion region 4 becomes uneven. As a result, the depletion layer extending from the interface 68 between the N + embedded diffusion region 3 and the P + embedded diffusion region 4 spreads further, and the withstand voltage of the pn junction between the N + embedded diffusion region 3 and the P + embedded diffusion region 4 increases.

【0094】

In a semiconductor device having this PNP transistor, the potential of the collector (N + embedded diffusion region 3) may be in a negative bias state and a withstand voltage may be required in that state depending on the intended use. When a bias is applied between the N + embedded diffusion region 3 and the P + embedded diffusion region 4, as shown in FIG. 24, the depletion layer extending from the interface between the P + embedded diffusion region 4 and the N-epitaxial layer 2 is formed. A depletion layer extending from the interface between the P + embedded diffusion region 4 and the N + embedded diffusion region 3 will be added.

【0095】

As described above, in this semiconductor device, it is equivalent to lowering the impurity concentration in the integrated N + embedded diffusion region 3 and P + embedded diffusion region 4. Moreover, by forming the constrictions 64 and 66, the interface 68 between the N + embedded diffusion region 3 and the P + embedded diffusion region 4 becomes uneven.

【0096】

Therefore, the depletion layer extending from the interface between the N + embedded diffusion region 3 and the P + embedded diffusion region 4 becomes wider. As a result, the withstand voltage of the pn junction between the N + embedded diffusion region 3 and the P + embedded diffusion region 4 is improved, and the withstand voltage of the semiconductor device when the collector potential is in a negative bias state can be improved.

【0097】

Embodiment 10 A semiconductor device including a vertical DMOS transistor according to a tenth embodiment of the present invention will be described. As shown in FIG. 25, the N-epitaxial layer 2 is formed on the P-silicon substrate 1. An N + embedded diffusion region 3 having a plurality of constrictions 69 is formed between the P-silicon substrate 1 and the N-epitaxial layer 2.

【0098】

N diffusion regions 34a, 34b, etc. are formed on the surface of the N-epitaxial layer 2. The P diffusion region 35a, etc. is formed so as to surround the N diffusion regions 34a, 34b, etc. from the surroundings. Further, on the surface of the N-epitaxial layer 2, an N + diffusion region 36 reaching the N + embedded diffusion region 3 is formed. A gate electrode 33 is formed on the surface of the P diffusion region 35a or the like located between the N diffusion regions 34a, 34b or the like and the N-epitaxial layer 2 with an insulating film interposed therebetween.

【0099】

Source electrodes 32 that are electrically connected to the N diffusion regions 34a, 34b, etc. are formed. A drain electrode 31 is formed on the surface of the N-epitaxial layer 2 on the opposite side of the source electrode 32 with the silicon oxide film 9 interposed therebetween. The drain electrode 31 is electrically connected to the N + diffusion region 36.

【0100】

In this semiconductor device, as shown in FIG. 26, by applying a voltage equal to or higher than a predetermined threshold voltage to the gate electrode 33, the current is N-epitaxial from the source electrode 32 through the N diffusion regions 34a, 34b, etc. It flows into the layer 2, reaches the N + embedded diffusion region 3 located below from there, and flows from the N + embedded diffusion region 3 to the drain electrode 31 via the N + diffusion region 36. In this way, in this semiconductor device, the current flows in the vertical direction.

【0101】

A plurality of constrictions 69 are formed in the N + embedded diffusion region 3. The constriction 69 is formed by a method similar to the method described in the first embodiment and the like.

【0102】

In the off state, as shown in FIG. 27, the depletion layer extends particularly from the interface between the P diffusion region 35 and the N-epitaxial layer 2. At this time, since a plurality of constrictions 69 are formed in the N + embedded diffusion region 3, the effective thickness of the N-epitaxial layer 2 is increased in this portion, and the depletion layer end extending toward the N + embedded diffusion region 3 is formed. You can reach deeper positions. As a result, the width of the depletion layer in this portion is widened, and the withstand voltage of the semiconductor device having the vertical DMOS transistor can be improved.

【0103】

Embodiment 11 The semiconductor device according to the eleventh embodiment of the present invention will be described. As shown in FIG. 28, P diffusion regions 45a and 45b are formed on the surface of the N-epitaxial layer 2 at intervals. Further, an N + diffusion region 44 in contact with the N + embedded diffusion region 3 is formed on the surface of the N-epitaxial layer 2.

【0104】

A collector electrode 42 electrically connected to the P diffusion region 45a is formed. An emitter electrode 43 electrically connected to the P diffusion region 45b is formed. A base electrode 41 electrically connected to the N + diffusion region 44 is formed. Since the other configurations are the same as those of the semiconductor device shown in FIG. 25 described in the tenth embodiment, the same members are designated by the same reference numerals and the description thereof will be omitted.

【0105】

In this semiconductor device, a horizontal PNP transistor based on the P diffusion region 45a is a collector, the P diffusion region 45b is an emitter, and the N-epitaxial layer 2 is formed.

【0106】

In the case of a horizontal PNP transistor, if the effective thickness of the N-epitaxial layer 2 located in the region directly below the P diffusion region 45b, which is the emitter, is relatively thin, the P diffusion region 45b to N-epitaxial The injection efficiency of the holes injected into layer 2 deteriorates. Therefore, there is a problem that the current amplification factor hFE in the transistor is lowered.

【0107】

Further, if the effective thickness of the portion of the N-epitaxial layer 2 located in the region directly below the P diffusion region 45a, which is the collector, is relatively thin, the extension of the depletion layer directly under the collector is limited. Therefore, there is a problem that the withstand voltage (BVceo) between the collector and the emitter is lowered.

【0108】

In the off state of this semiconductor device, as shown in FIG. 29, the depletion layer extends particularly from the interface between the P diffusion region 45a and the N-epitaxial layer 2. At this time, since a plurality of constrictions 69 are formed in the N + embedded diffusion region 3 where the depletion layer extends, the effective thickness of the N-epitaxial layer 2 increases in this portion, and the N + embedded diffusion region 3 increases. The end of the depletion layer extending to the side can reach deeper positions. As a result, the width of the depletion layer is widened, and the withstand voltage of the semiconductor device can be improved.

【0109】

Further, by increasing the thickness of the effective N-epitaxial layer 2, it is possible to suppress the deterioration of the injection efficiency of the holes injected into the N-epitaxial layer 2 from the P diffusion region 45b, and the current amplification factor of the transistor. It is possible to prevent the hFE from decreasing. In this way, in this semiconductor device, the above-mentioned problem of the transistor can be solved. In the tenth and eleventh embodiments, the case where the constriction is formed in the N + embedded diffusion region has been described, but the withstand voltage can be similarly improved even if the structure is provided with slits at appropriate intervals.

【0110】

The embodiments disclosed this time should be considered to be exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

【0111】

[Effect of the invention]

According to the first semiconductor device in one aspect of the present invention, the surface of the second embedded impurity region is recessed so as to be away from the second impurity region in the portion located substantially directly below the second impurity region. The formation of the recessed portion or the first gap portion in which this region is interrupted increases the effective thickness of the semiconductor layer in this portion. As a result, in the off state, the depletion layer end extending toward the second embedded impurity region of the depletion layer extending from the interface between the semiconductor layer and the second embedded impurity region is other than the portion directly below the second impurity region. It will be located deeper than the part. As a result, as compared with the conventional semiconductor device, the width of the depletion layer located directly under the second impurity region is extended, the withstand voltage in the portion directly under the second impurity region is increased, and the withstand voltage of the entire semiconductor device is improved. ..

【0112】

In order to provide a DMOS transistor as a semiconductor element, specifically, a first conductive type third impurity region formed so as to be surrounded by a first impurity region on the surface of the first impurity region, and a third impurity region thereof. It is desirable to include an electrode portion formed by interposing an insulating film on the surface of the first impurity region sandwiched between the semiconductor layer and the semiconductor layer.

【0113】

Further, when the IGBT is provided as the semiconductor element, it is desirable that the second conductive type fourth impurity region formed so as to be in contact with the second impurity region is further included.

【0114】

When a bipolar transistor is provided as the semiconductor element, it is desirable that the second conductive type fifth impurity region formed on the surface of the semiconductor layer is included.

【0115】

Further, it is desirable that the second embedded impurity region contains a plurality of first recessed portions. In this case, in the off state, many portions where the width of the depletion layer extends are formed, so that the second impurity region is wider. The withstand voltage of the semiconductor device having a region can be improved.

【0116】

Further, it is desirable that the second embedded impurity region contains a plurality of first gap portions, and in this case, the effective thickness of the semiconductor layer in this portion is further increased, and in the off state, the semiconductor layer and the second gap are present. The width of the depletion layer extending from the interface with the embedded impurity region is further increased. As a result, the withstand voltage of the semiconductor device is further improved.

【0117】

Further, it is desirable that the second embedded impurity region includes a plurality of regions that are electrically floated by the plurality of first gaps, and in this case, the first impurity region is viewed from the side. The potential of each floating second embedded impurity region will also increase along the direction toward the side of the two impurity regions. As a result, the potential difference between the potential of the second embedded impurity region located immediately below the second impurity region and the potential of the second impurity region becomes smaller. As a result, the withstand voltage of the semiconductor device can be improved as the potential difference becomes smaller.

【0118】

Further, the first embedded impurity region is a second recessed portion or a first embedded region in which the surface of the first embedded impurity region is recessed in a direction away from the second impurity region in a portion located substantially directly below the first gap portion. It is desirable to include a second gap portion where is interrupted. In this case, the impurities constituting the first embedded impurity region are semiconductors between the second embedded impurity regions located across the first gap portion. The diffusion to the layer portion is suppressed, and the increase in the impurity concentration in this portion is suppressed. As a result, even if the distance between the first gaps is widened, the increase in the pinch-off voltage can be suppressed to a small value, and the effective film thickness of the semiconductor layer located directly below the second impurity region can be made thicker. As a result, the withstand voltage of the semiconductor device can be further improved.

【0119】

Further, it is desirable that the bonding interface between the first embedded impurity region and the second embedded impurity region is uneven. In this case, the bonding interface between the first embedded impurity region and the second embedded impurity region is uneven. The shape causes the depleted layer extending from this bonding interface to expand more. As a result, the withstand voltage of the junction portion is improved, and the withstand voltage of the semiconductor device when the potential of the collector when, for example, a bipolar transistor is provided as the semiconductor element is negatively biased can be improved.

【0120】

According to the second aspect of the semiconductor device in one aspect of the present invention, in the off state, the depletion layer extends particularly from the interface between the second impurity region and the semiconductor layer. At this time, in the portion located substantially directly below the second impurity region, a recessed portion is formed so that the surface of the embedded impurity region is away from the second impurity region, or a gap portion in which this region is interrupted is formed. In this portion, the thickness of the effective semiconductor layer is increased, and the end of the depletion layer extending toward the embedded impurity region can reach a deeper position. As a result, the width of the depletion layer is widened and the withstand voltage of the semiconductor device is improved.

【0121】

When a DMOS transistor is provided as a semiconductor element, a first conductive type third impurity region formed so as to be surrounded by a second impurity region on the surface of the second impurity region, a third impurity region, and a semiconductor layer are used. It is desirable to include an electrode portion formed by interposing an insulating film on the surface of the sandwiched second impurity region.

【0122】

When a bipolar transistor is provided as a semiconductor element, it is desirable that the second conductive type fourth impurity region formed on the surface of the semiconductor layer is included.

【0123】

Further, it is desirable that the recessed portion or the gap portion is formed in the portion where the depletion layer extends. In this case, the extending depletion layer can be further extended, and for example, when a bipolar transistor is provided as the semiconductor element. The withstand voltage can be improved without lowering the current amplification factor.

[Simple explanation of drawings]

[Figure 1]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 1 of this invention.

[Figure 2]

It is one plan view for demonstrating the formation method of the P + embedded diffusion region in the same embodiment.

[Fig. 3]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 4]

FIG. 5 is a cross-sectional view showing how a current flows through the P + embedded diffusion region in the same embodiment.

[Fig. 5]

It is a figure which shows the equivalent circuit when the current flows in the P + embedded diffusion region in the same embodiment.

[Fig. 6]

In the same embodiment, it is another plan view for demonstrating the method of forming a P + embedded diffusion region.

[Fig. 7]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 2 of this invention.

[Fig. 8]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer before pinch-off.

[Fig. 9]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer after pinch-off.

[Fig. 10]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 3 of this invention.

[Fig. 11]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 12]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 4 of this invention.

[Fig. 13]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer before pinch-off.

[Fig. 14]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer after pinch-off.

[Fig. 15]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 5 of this invention.

[Fig. 16]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 17]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 6 of this invention.

[Fig. 18]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 19]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 7 of this invention.

[Fig. 20]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 21]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 8 of this invention.

[Fig. 22]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 23]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 9 of this invention.

[Fig. 24]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 25]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 10 of this invention.

[Fig. 26]

FIG. 5 is a cross-sectional view showing how a current flows in the ON state in the same embodiment.

[Fig. 27]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 28]

It is one cross-sectional view of the semiconductor device which concerns on Embodiment 11 of this invention.

[Fig. 29]

In the same embodiment, it is sectional drawing which shows the state of the depletion layer in the off state.

[Fig. 30]

It is one cross-sectional view of the conventional semiconductor device.

[Fig. 31]

It is sectional drawing which shows the state of the depletion layer in the off state of the conventional semiconductor device.

[Explanation of symbols]

1 P-silicon substrate, 2 N-epitode layer, 3, 3a, 3b N + embedded diffusion region, 4, 4a, 4b P + embedded diffusion region, 5, 6, 15, 25, 35, 45a, 45b P diffusion region, 7 , 8, 24, 34, 36, 44 N diffusion region, 9, 51 silicon oxide film, 10, 33 gate electrode, 11, 32 source electrode, 12, 31 drain electrode, 16, 21, 42 collector electrode, 17, 22 , 43 emitter electrodes, 23, 41 base electrodes, 61 patterns, 62 coils, 63 currents, 64, 66, 69 constrictions, 65, 67 slits, 68 interfaces.