JP2002158294A

Semiconductor memory device having metal contact structure and manufacturing method thereof

Abstract

[Task] Provided is a semiconductor memory device having a metal contact structure, which can secure a sufficient space for arranging the metal contact studs, has an improved manufacturing process, and has a high manufacturing yield.

Solution.The metal line 28 is connected to the active region 12, the gate electrode 14, and the bit line 16 through the second to fourth metal contacts 26b to 26d, respectively. The metal contact studs 27a and 27b are connected to the upper and lower parts 26b1 and 26b2 of the second metal contact 26b and to the upper and lower parts 26c1 and 26c2 of the third metal contact 26c, respectively. The metal contact studs 27a and 27b are formed in a layer different from the layer on which the bit line 16 is formed, and have a width wider than that of the bit line 16.

JP2002158294A, drawing sheet 1 — Sheet 1 of 3

Term

Term ended

Projected expiry passed 7 September 2021, 5 years ago.

18 claims: 3 independent, 15 dependent

1
【特許請求の範囲】【請求項1】隣接したビットライン間に形成されて上部部分と下部部分を有したメタルコンタクトと、前記上部部分と前記下部部分を連結して、前記ビットラインが形成される層とは異なる層に形成されたメタルコンタクトスタッドを含むことを特徴とする半導体メモリ装置。
2
【請求項2】前記メタルコンタクトスタッドはビットライン下層に形成されたことを特徴とする請求項1に記載の半導体メモリ装置。
3
【請求項3】前記メタルコンタクトスタッドは上部面積が下部面積より小さいことを特徴とする請求項1に記載の半導体メモリ装置。
4
【請求項4】セル領域と周辺領域を有した基板上に形成されたゲート電極と、前記基板上前記絶縁膜上に形成された第1絶縁膜と、前記メタルコンタクトスタッドを覆いながら前記第1絶縁膜上に形成された第2絶縁膜と、前記第2絶縁膜上に形成されて前記ビットラインコンタクトとコンタクトする第3導電物質を含んで、第1導電物質層でなった前記メタルコンタクトスタッドと前記メタルコンタクトの下部部分は前記第1絶縁膜を通過して形成されて、第2導電物質層でなった前記ビットラインは前記第1および第2絶縁膜を通過して形成されて、前記第3導電層はパターン化されてビットラインを形成することを特徴とする半導体メモリ装置。
5
【請求項5】 a)セル領域と周辺領域を有した基板上にゲート電極を形成する段階と、 b)前記基板上にゲート電極を覆うように第1絶縁膜を形成する段階と、 c)前記第1絶縁膜に第1メタルコンタクトホールおよびスタッドホールを形成する段階と、 d)前記第1絶縁膜に第1メタルコンタクトホールおよびスタッドホールに第1メタルコンタクトスタッドおよび第1メタルコンタクト部を形成する段階と、 e)前記第1絶縁膜と前記メタルコンタクトスタッド上に第2絶縁膜を形成する段階と、 f)前記第1および第2絶縁膜を通過するビットラインコンタクトホールを形成する段階と、 g)前記ビットラインコンタクトホールにビットラインコンタクトを形成する段階、および、 h)前記第2絶縁膜上にビットラインを形成する段階を含むことを特徴とする半導体メモリ装置の製造方法。
6
【請求項6】 i)前記基板のセル領域上にキャパシタを形成する段階と、 j)前記基板上に、ビットラインを覆う第3絶縁層を形成する段階と、 k)前記第2および第3絶縁層に、前記メタルコンタクトスタッドの一部を露出させる第2メタルコンタクトホールを形成する段階、および、 l)第2メタルコンタクトホールに第2メタルコンタクトを形成する段階をさらに含むことを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
7
【請求項7】前記スタッドホールを形成する段階は、前記第1絶縁層上に第1フォトレジストパターンを形成する段階、および、前記第1フォトレジストパターンをマスクで利用して前記第1絶縁層に前記スタッドホールをエッチングする段階をさらに含んで、前記第1フォトレジストは前記スタッドホールを形成した後に除去することを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
8
【請求項8】前記第1メタルコンタクトホールはアクティブ領域の一部と前記ゲート電極中少なくとも一つの一部を露出させるように異方性エッチングによって形成されることを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
9
【請求項9】 (d)段階は前記第1絶縁層上に第1導電物質層を蒸着する段階をさらに含んで、前記第1導電物質層は前記スタッドホールと前記第1メタルコンタクトホールを充填させることを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
10
【請求項10】 (e)段階はCMP技術を利用して前記第2絶縁層を平坦化させる段階をさらに含むことを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
11
【請求項11】 (f)段階は前記第2絶縁層上に第2フォトレジストパターンを形成する段階と、前記第2フォトレジストパターンのマスクを利用して前記ビットラインコンタクトホールを形成するために前記第1および第2絶縁層をエッチングする段階をさらに含んで、前記ビットラインが形成された後に、前記第2フォトレジストパターンを除去することを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
12
【請求項12】 (e)段階は前記第2絶縁層上に、前記ビットラインコンタクトホールを充填させながら、第2導電物質層を蒸着する段階と、前記第2絶縁層上の第2導電物質層の一部を除去する段階をさらに含むことを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
13
【請求項13】 (h)段階は前記第2絶縁層上に前記ビットラインコンタクトホールと接触する第3導電物質層を形成する段階と、前記第3導電物質層をパターン化して前記ビットラインを形成することを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
14
【請求項14】各々のメタルコンタクトスタッドの下部部分の領域は上部領域より小さいことを特徴とする請求項5に記載の半導体メモリ装置の製造方法。
15
【請求項15】 (k)段階は前記第3絶縁層上に第3フォトレジストパターンを形成する段階と、前記第3フォトレジストパターンのマスクを用いて前記第3絶縁層と第2絶縁層をエッチングして前記第2メタルコンタクトホールを形成する段階をさらに含んで、前記各々の第2メタルコンタクトホールは隣接したビットライン間を通過して前記メタルコンタクトスタッドの一部を露出させることを特徴とする請求項6に記載の半導体メモリ装置の製造方法。
16
【請求項16】 (l)段階は前記第3絶縁層上に、前記第2メタルコンタクトホールを充填させながら、第4導電物質層を形成する段階と、前記第3絶縁層上の第4導電物質層の一部を除去して前記第2メタルコンタクトを形成する段階をさらに含むことを特徴とする請求項6に記載の半導体メモリ装置の製造方法。
17
【請求項17】前記ビットラインコンタクト中少なくとも一つは前記基板のアクティブ領域と連結されることを特徴とする請求項12に記載の半導体メモリ装置の製造方法。
18
【請求項18】前記ビットラインコンタクト中少なくとも一つは前記ゲート電極中一つと連結されることを特徴とする請求項12に記載の半導体メモリ装置の製造方法。

Independent claims18

119 paragraphs in 1 section, as filed

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a metal contact structure and a method for manufacturing the same.

【0002】

[Conventional technology]

In semiconductor memory devices such as DRAM, metal contacts are mainly cells excluded as contacts for connecting various components such as active regions, gate electrodes, bit lines, and upper electrodes of capacitors to metal lines. It will exist in the area.

【0003】

Due to the small size of DRAM basic memory cells with single transistors and capacitors, such cells can be used to create very dense arrays. Since the main cost of semiconductor memory is generally the cost of silicon wafers, therefore, the more chips there are on a wafer, the lower the cost for the chips. Therefore, DRAM costs less per bit than memory with less dense arrays.

【0004】

FIG. 1 is a cross-sectional view showing a semiconductor memory device having a conventional metal contact structure. As shown in FIG. 1, the semiconductor memory device is composed of a cell area 100 and a peripheral area 200. In the cell region 100, a gate 14 is formed in the active region 12 of the silicon substrate 10. The silicon substrate 10 and the active region 12 are integrally formed, and the protruding portion of the substrate 10 is used in the active region 12, that is, the channel region. The bit line 16 and the capacitor C are formed on the upper part of the gate electrode. The capacitor C has an upper electrode 17 and a lower electrode 18. The first metal contact 26a is formed so as to contact the metal contact 28 with the upper electrode 17 of the capacitor C.

【0005】

Further, a bit line contact 24 is formed in the peripheral region 200 to connect the bit line 16 to the active region 12 and the gate electrode 14, respectively. The second and third metal contacts 26b and 26c are formed in contact holes arranged between adjacent bit lines 16, respectively. Further, the fourth metal contact 26d connects the metal line to the bit line 16. The first and second insulating layers 20 and 22 insulate the above-mentioned components, respectively, and are preferably an oxide film such as SiOx.

【0006】

The metal contact 26 is mainly formed after forming the upper electrode 17 of the capacitor C. At this time, the metal contact is required to be precisely aligned with the already formed active region 12, the gate electrode 14, the bit line 16, and the like. The alignment margin is relative between the region where the first metal contact 26a connects the metal line 28 to the upper electrode 17 of the capacitor C and the region where the fourth metal contact 26d connects the metal line 28 and the bit line 16. Due to its large size, precise alignment is not required. On the other hand, the second metal contact 26b and the third metal contact 26c require very precise alignment with the active region 12, the gate electrode 14, and the bit line 16. In particular, as the chip size becomes smaller, the second and third metal contacts 26b, 26c arranged in the peripheral region are very limited to the active region 12, the gate region 14, and the bit line 16. ) Alignment will be required. Therefore, the semiconductor manufacturing process, especially the photo-etching process, becomes very difficult.

【0007】

FIG. 2 is an enlarged view showing the D portion of FIG. The metal lines 28 arranged in the peripheral region are connected to the active region 12 and the gate 14 through the second and third metal contacts 26b and 26c, respectively. However, as described above, the second and third metal contacts 26b, 26c must be formed avoiding the adjacent bit lines 16. Therefore, as the chip size becomes smaller, the alignment margin decreases, and misalignment tends to cause a defect that the bit lines 16 adjacent to the metal contacts 26b and 26c are short-circuited.

【0008】

In order to overcome the above-mentioned problems, a technology using metal contact studs was introduced. 3 and 4 are exemplary cross-sectional views showing a conventional semiconductor memory device having a metal contact structure utilizing metal contact studs.

【0009】

As illustrated in FIG. 3, the metal contact studs 27a and 27b connect the upper and lower parts 26b1 and 26b2 of the second metal contact 26b and the upper and lower parts 26c1 and 26c2 of the third metal contact 26c, respectively. The metal contact studs 27a and 27b are formed at the same time as the bit line 16 after forming the lower portions 26b2 and 26c2 of the second and third metal contacts 26b and 26c, respectively. After forming the metal contact studs 27a and 27b, the upper parts 26b1 and 26c1 of the second and third metal contacts 26b and 26c pass through the metal contact studs 27a and 27b and the lower part of the second and third metal contacts 26b and 26c. It is connected to 26b2 and 26c2 respectively.

【0010】

However, as illustrated in FIG. 4, the smaller the chip size, the narrower the gap between adjacent bit lines 16. Therefore, it becomes difficult to secure a sufficient space for arranging the metal contact studs 27a and 27b, and as a result, the manufacturing process becomes difficult and the manufacturing yield decreases.

【0011】

[Problems to be Solved by the Invention]

An object of the present invention is to provide a semiconductor memory device having a metal contact structure, which can secure a sufficient space for arranging the metal contact studs, improve a manufacturing process, and have a high manufacturing yield. There is.

【0012】

[Means for solving problems]

In order to achieve the above-mentioned object of the present invention, the present invention includes a bit line and a metal contact stud, and the metal contact stud is a semiconductor memory device formed in a layer different from the layer on which the bit line is formed. provide.

【0013】

Desirably, the metal contact stud is formed in the lower layer of the bit line. Further, the lower portion of the metal contact stud is preferably smaller in area than the upper portion thereof.

【0014】

In the uniform state of the present invention, the semiconductor memory device is formed between adjacent bit lines, and the bit line is formed by connecting a metal contact having an upper portion and a lower portion and the upper portion and the lower portion. It contains metal contact studs formed in a layer different from the layer.

【0015】

In another aspect of the present invention, the present invention a) forms a gate electrode on a substrate having a cell region and a peripheral region, and b) forms a first insulating film on the substrate so as to cover the gate electrode. Steps, c) The step of forming the first metal contact hole and the stud hole in the first insulating film, d) The first metal contact hole and the first metal contact in the first insulating film and the stud hole. A step of forming a portion, e) a step of forming a second insulating film on the first insulating film and the metal contact stud, f) a step of forming a bit line contact hole passing through the first and second insulating films. , G) Provided is a method for manufacturing a semiconductor memory apparatus including a step of forming a bitline contact in the bitline contact hole and h) a step of forming a bitline on the second insulating film.

【0016】

Therefore, since the metal contact stud is formed in a layer different from the layer in which the bit line is formed, the alignment margin for forming the metal contact is increased. Therefore, for example, a short circuit due to misalignment between the metal contact and the bit line can be prevented, and a high yield can be achieved.

【0017】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in more detail through an embodiment of the present invention with reference to the accompanying drawings.

【0018】

FIG. 5 is an exemplary cross-sectional view showing a peripheral region of a semiconductor memory device having a metal contact structure according to a preferred embodiment of the present invention. As illustrated in FIG. 5, the metal lines 28 arranged in the peripheral region (200; see FIG. 1) pass through the second to fourth metal contacts 26b-26d to the active region 12, the gate electrode 14, and the bit line 16. Are connected to each other. The metal contact studs 27a and 27b are connected to the upper and lower parts 26b1 and 26b2 of the second metal contact 26b and to the upper and lower parts 26c1 and 26c2 of the third metal contact 26c, respectively. The metal contact studs 27a and 27b are formed in a layer different from the layer on which the bit line 16 is formed, and have a width wider than that of the bit line 16. Desirably, the metal contact studs 27a, 27b are formed below the bit line.

【0019】

Hereinafter, the manufacturing process of the semiconductor memory device having the metal contact structure according to the desired embodiment of the present invention will be described with reference to FIGS. 6 to 19. 6 to 19 are exemplary cross-sectional views showing a manufacturing process of a semiconductor memory apparatus having a metal contact structure according to a preferred embodiment of the present invention.

【0020】

First, referring to FIG. 6, after forming the gate 14 on the active region 12 of the silicon substrate (10; see FIG. 1), the first insulating film 30 is formed over the entire surface of the substrate while covering the gate electrode 14. Will be done. The surface of the first insulating film 30 is flattened by, for example, a CMP process.

【0021】

Referring to FIG. 7, the first photoresist pattern 32 is formed on the insulating film 30 by a photographic process.

【0022】

Then, referring to FIG. 8, the photoresist pattern 32 is used as an etching mask and the insulating film 30 is isotropically etched or wet-etched to prepare stud holes 34 and 36. The total area of the metal contact studs is determined by an isotropic etching process, and the area of the lower part of the metal contact studs 27a and 27b is formed smaller than the area of the upper part.

【0023】

Subsequently, referring to FIG. 9, the anisotropic etching process proceeds to form the first metal contact holes 26b2'and 26c2' on the active region 12 and the gate electrode 14, and the photoresist pattern 32 is removed.

【0024】

Referring to FIG. 10, the first conductive material layer 38 is formed on the first insulating film 30 while filling the stud holes 34 and 36 and the first metal contact holes 26b2'and 26c2'. The first conductive material layer 38 is preferably made of tungsten or polysilicon.

【0025】

Referring to FIG. 11, in the CMP step, a part of the first conductive material layer 38 on the first insulating film 30 is removed to remove the first and second metal contact studs 27a and 27b and the metal contacts 26b and 26c. Form 26b2 and 26c2 at the bottom of the.

【0026】

Subsequently, referring to FIG. 12, a second insulating film 40 is formed on the entire surface of the insulating film 30 to cover the first and second metal contact studs 27a and 27b. The second insulating film 40 is flattened in the CMP process.

【0027】

Then, referring to FIG. 13, a second photoresist pattern 42 is formed on the second insulating film 40 by a photographic process.

【0028】

Referring to FIG. 14, the second photoresist pattern 42 is used as an etching mask, and the first and second insulating films 30 and 40 are anisotropically etched to form a bitline contact hole 44, whereby the first and second insulating films 30 and 40 are anisotropically etched to form the first and second insulating films 30 and 40. 2 Remove the photoresist pattern 42.

【0029】

Referring to FIG. 15, a second conductive material layer is deposited on the second insulating film while filling the bit line contact hole 44. The second conductive material layer is preferably made of tungsten polysilicon.

【0030】

Referring to FIG. 16, in the CMP process, a part of the second conductive material layer 50 above the second insulating film 40 is removed to form the bit line contact 24. At least one of the bitline contacts 24 is coupled to the active region 12, and the remaining at least one is coupled to the gate electrode 14.

【0031】

Referring to FIG. 17, the third conductive material layer 46 is vapor-deposited on the flattened second insulating film 40 and is contacted with the bit line contact 24. The third conductive material layer 46 is preferably made of tungsten or polysilicon.

【0032】

Referring to FIG. 18, the third conductive material layer 46 is patterned in a photoetching step to form a bit line 16.

【0033】

Referring to FIG. 19, after forming the bit line 16 and then forming a capacitor in the cell region 100 (C; see FIG. 1), a third insulating film 48 is formed over the entire area of the substrate 10. The third insulating film 48 serves as an interlayer insulating film. After that, a third photoresist pattern (not shown) is formed on the third insulating film, and the interlayer insulating film 48 and the second insulating film 40 are anisotropic using the third photoresist pattern as an etching mask. The second and third metal contact holes 26b1 and 26c1 are formed by etching and passing through the adjacent bit lines 16 to expose the first and second metal contact studs 27a and 27b. A fourth conductive material layer (not shown) is formed on the third insulating film so as to fill the second and third metal contact holes 26b1 and 26c1. A part of the fourth conductive material layer on the third insulating film 48 is removed to form upper 26b1 and 26c1 of the second and third metal contacts 26b and 26c.

【0034】

Subsequently, the fifth conductive material layer is vapor-deposited and patterned using a photoetching process to form the metal line 28. The metal line 28 is preferably made of a conductive material such as tungsten or aluminum. In this way, the semiconductor memory device having the metal contact structure according to the desired embodiment of the present invention is completed.

【0035】

Although the above description has been made with reference to the preferred embodiment of the present invention, a skilled person skilled in the art will use the present invention within the scope of the idea and domain of the present invention described in the claims. It can be seen that it can be modified and changed in various ways.

【0036】

[Effect of the invention]

As described above, since the metal contact stud is formed in a layer different from the layer in which the bit line is formed, the alignment margin for forming the metal contact is increased. Therefore, for example, a short circuit due to misalignment between the metal contact and the bit line can be prevented, and a high yield can be achieved.

[Simple explanation of drawings]

[Figure 1]

It is sectional drawing which shows the semiconductor memory apparatus which had a conventional metal contact structure.

[Figure 2]

It is an enlarged view which shows the D part of FIG.

[Fig. 3]

It is sectional drawing which shows the peripheral area of the semiconductor memory apparatus which had the conventional modified metal contact structure.

[Fig. 4]

It is sectional drawing which shows the peripheral area of the semiconductor memory apparatus which had the conventional modified metal contact structure.

[Fig. 5]

It is sectional drawing which shows the peripheral area of the semiconductor memory apparatus which had the metal contact structure by the desirable embodiment of this invention.

[Fig. 6]