Semiconductor device and portable electronic apparatus

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device and a portable electronic device, and more specifically, to a semiconductor device having a dynamic threshold transistor and a substrate bias variable transistor, and a portable electronic device using the semiconductor device.

【0002】

[Conventional technology]

In order to reduce the power consumption in a CMOS (Complementary MOS) circuit using MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is most effective to reduce the power supply voltage. However, if the power supply voltage is simply lowered, the drive current of the MOSFET is lowered and the operating speed of the circuit is slowed down. It is known that this phenomenon becomes remarkable when the power supply voltage becomes 3 times or less the threshold value of the transistor. In order to prevent this phenomenon, the threshold value may be lowered, but this causes a problem that the leakage current when the MOSFET is off increases. Therefore, the lower limit of the threshold value is defined within the range where the above problem does not occur. Since the lower limit of the threshold value corresponds to the lower limit of the power supply voltage, it defines the limit of power consumption reduction.

【0003】

Conventionally, in order to alleviate the above problem, a dynamic threshold operation transistor (hereinafter referred to as DTMOS) using a bulk substrate has been proposed (Japanese Patent Laid-Open No. 10-22462, Novel Bulk Threshold Voltage MOSFET (B-DTMOS)). ) With Advanced Isolation (SITOS) and Gate to Shallow Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS, H. Kotaki et al., IEDM Tech. Dig., P459, 1996). The DTMOS has a feature that a high drive current can be obtained at a low power supply voltage because the effective threshold value is lowered when the DTMOS is turned on. The effective threshold of DTMOS drops when on because the gate electrode and well region are electrically short-circuited.

【0004】

The operating principle of the N-type DTMOS will be described below. The P-type DTMOS operates in the same manner by reversing the polarity. In the N-type MOSFET, when the potential of the gate electrode is at the low level (when off), the potential of the P-type well region is also at the low level, and the effective threshold value is the same as that of the normal MOSFET. Therefore, the off-current value (off-leak) is the same as in the case of a normal MOSFET.

【0005】

On the other hand, when the potential of the gate electrode is at a high level (when it is on), the potential of the P-shaped well region also becomes a high level, the effective threshold value decreases due to the substrate bias effect, and the drive current is the case of a normal MOSFET. Increases compared to. Therefore, a large drive current can be obtained while maintaining a low leakage current at a low power supply voltage.

【0006】

In DTMOS, the gate electrode and the well region are electrically short-circuited. Therefore, when the potential of the gate electrode changes, the potential of the well also changes. Therefore, the well regions of each DTMOS must be electrically separated from the well regions of adjacent MOSFETs. Therefore, the well region is composed of a shallow well region and a deep well region having different polarities from each other. Moreover, the shallow well regions of each DTMOS are electrically separated from each other by the element separation region.

【0007】

As a conventional method for suppressing off-leakage by low voltage drive and obtaining a high drive current, there is also a method of changing the well bias between stand-by and active (Japanese Patent Laid-Open No. 6-216346, JP-A-10-). 340998 Gazette).

【0008】

Hereinafter, a MOSFET that changes the well bias between standby and active will be referred to as a substrate bias variable transistor.

【0009】

The operating principle of the N-type substrate bias variable transistor will be described below. The P-type substrate bias variable transistor operates in the same manner by reversing the polarity. In the N-type substrate bias variable transistor, when the circuit is in the active state, 0V or a positive voltage is applied to the P-type well region from the bias generation circuit (based on the potential of the source). When a positive voltage is applied to the P-shaped well region, the effective threshold value decreases due to the substrate bias effect, and the drive current increases as compared with the case of a normal MOSFET. When the circuit is in the standby state, a negative voltage is applied to the P-shaped well region from the bias generation circuit. As a result, the effective threshold value is increased by the substrate bias effect, and the off-leakage is reduced as compared with a normal MOSFET or DTMOS.

【0010】

Normally, in a circuit using a substrate bias variable transistor, an active state or a standby state is selected for each circuit block. This is because the number of elements and the circuit area increase remarkably when a bias generation circuit is provided for each element. For the above reasons, the P-type well region of the N-type MOSFET is common in the circuit block (the same applies to the N-type well region of the P-type MOSFET). Therefore, in the active circuit block, 0V or a positive voltage is applied to the well region of all N-type MOSFETs, and off-leakage increases compared to ordinary MOSFETs or DTMOS (the same applies to P-type MOSFETs). is there).

【0011】

In a circuit using a substrate bias variable transistor, the well region of the MOSFET in the circuit block must be common. Therefore, the depth of the bottom surface of the element separation region is set to be deeper than the depth of the junction between the source region and drain region of the MOSFET and the shallow well region, and shallower than the depth of the lower end of the well region.

【0012】

A technique for combining the DTMOS and the substrate bias variable transistor and taking advantage of the respective advantages is disclosed (Japanese Patent Laid-Open No. 10-340998).

【0013】

A cross-sectional view of the element produced by this technique is shown in FIG. In FIG. 11, 311 is a semiconductor P-type substrate, 312 is an N-type deep well region, 313 is a P-type deep well region, 314 is an N-type shallow well region, 315 is a P-type shallow well region, and 316 is an element. Separation area, 317 is N-type MOSFET source area, 318 is N-type MOSFET drain area, 319 is P-type MOSFET source area, 320 is P-type MOSFET drain area, 321 is N-type shallow well area. N + diffusion layer for taking, 322 is P + diffusion layer for contacting the shallow well region of P type, 323 is gate insulating film, 324 is gate electrode, 325 is P type substrate bias variable transistor, 326 is N type Board bias variable transistor, 327 is N-type DTMOS, 328 is P-type DTMOS, 329 is well bias input to P-type board bias variable transistor, 330 is well bias input to N-type board bias variable transistor, Reference numeral 331 indicates a fixed bias input of a P-type deep well region. Although not shown, in the N-type DTMOS327, the gate electrode 324 and the P-type shallow well region 315 are electrically short-circuited, and in the P-type DTMOS328, the gate electrode 324 and the N-type shallow well region 314 are electrically short-circuited. Has been done.

【0014】

In DTMOS 327 and 328, the potentials of the shallow well regions 314 and 315 fluctuate according to the potential of the gate electrode 324. Under the shallow well regions 314 and 315, what are the shallow well regions 314 and 315 to prevent potential fluctuations in the shallow well regions 314 and 315 from affecting the shallow well regions 314 and 315 of other devices? It forms the opposite conductive type deep well regions 313 and 312. In addition, the element separation region 316 is formed at a depth sufficient to electrically separate the shallow well regions 314 and 315 of the elements adjacent to each other. As a result, the shallow well areas 314 and 315 are next to each other.It is electrically separated from the shallow well regions 314 and 315 of the contacting element. On the other hand, the shallow well region of the substrate bias variable transistor 326 in one circuit block must be common. Therefore, a P-type deep well region 313 is formed below the P-type shallow well region 315 of the N-type substrate bias variable transistor 326 in FIG. 11, and this P-type deep well region 313 is a P-type shallow well region 313. Together with the well area 315, it constitutes a common well area. Different potentials are applied to the P-type common well regions 313 and 315 during active and standby via the well bias input 330 to the N-type substrate bias variable transistor 326. An N-shaped deep well region 312 is formed deeper in the substrate so as not to affect other circuit blocks or elements of the DTMOS section. This electrically separates the P-shaped deep well region 313. In FIG. 11, an N-type deep well region 312 is formed below the shallow well region 314 of the P-type substrate bias variable transistor 325, and this N-type deep well region 312 is combined with the N-type shallow well region 314. Together they form a common well area 312,314. The N-type common well regions 312 and 314 are given different potentials during active and standby via the well bias input 329 to the P-type substrate bias variable transistor 325.

【0015】

FIGS. 12 and 13 show the procedure for forming the deep well regions 312,313 of this conventional semiconductor device. As shown in FIG. 12, using the photoresist 332 as a mask, impurity injection is performed to form a P-type deep well region 313, and then impurities are injected to form a deeper N-type deep well region 312. Do. Next, as shown in FIG. 13, impurities are injected to form an N-shaped deep well region 312'using the photoresist 332 as a mask. At this time, the depth of the N-type deep well region 312'is made similar to the depth of the P-type deep well region 313. In the above steps, the N-type deep well region 312 and 312'are integrated, and the P-type deep well region 312 is electrically separated.

【0016】

In this way, the substrate bias variable transistors 325,326 and DTMOS327,328 can be formed on the same substrate 311 to realize a circuit utilizing the advantages of each.

【0017】

[Problems to be Solved by the Invention]

As shown in FIG. 11, in a conventional semiconductor device (Japanese Patent Laid-Open No. 10-340998) in which DTMOS327,328 and substrate bias variable transistors 325,326 are combined, P-type deep well regions 313,313, ... Are electrically separated. However, the N-shaped deep well region 312 is common within one substrate 311. Therefore, it is possible to create multiple circuit blocks of N-type substrate bias variable transistors 326, 326 ... on the same board 311. However, it is not possible to create multiple circuit blocks of P-type substrate bias variable transistors 325 ... Can not. Therefore, the circuit block of the P-type substrate bias variable transistor 325 ... cannot be properly divided into an active circuit block and a standby circuit block. For example, even if only a part of the P-type substrate bias variable transistor 325,325 ... needs to be activated, the entire P-type substrate bias variable transistor 325,325 ... becomes active, and the leakage current. Will increase. Therefore, the power consumption will increase.

【0018】

Further, in the conventional semiconductor device, since the N-shaped deep well region 312 is integrated in the substrate 311, it has a PN junction having a large area comparable to the area of the entire substrate 311. That is, a very large capacitance is parasitic. Therefore, when active / standby switching is performed in the circuit block of the P-type substrate bias variable transistor 325,325 ..., the bias of the entire N-type deep well region 312 changes, and a large amount of electric charge is charged / discharged. become. Therefore, the power consumption will increase.

【0019】

In the active state (that is, when a potential lower than the power supply voltage is applied to the N-shaped deep well region 312), it may be easy to induce the latch-up phenomenon. In the NPNP structure consisting of a path through the N-type shallow well region 314 of the P-type DTMOS328, the P-type deep well region 313, the N-type deep well region 312, and the P-type shallow well region 315 of the N-type DTMOS324, P Consider the case where the N-type shallow well region 314 of the type DTMOS328 is biased below the ground potential (undershoot). Since the gate electrode 324 and the shallow well region 314 are electrically connected to the DTMOS328, a bias below the ground potential can be applied to the N-type shallow well region 314 of the P-type DTMOS328 through the gate electrode 324. At this time, since a forward voltage is applied to the junction between the N-type shallow well region 314 of the P-type DTMOS328 and the P-type deep well region 313, electrons are injected into the P-type deep well region 313. To. The electrons injected into the P-type deep well region 313 reach the N-type deep well region 312 and lower the potential of the N-type deep well region 312. When the potential of the N-type deep well region 312 drops, holes are injected from the P-type shallow well region 315 of the N-type DTMOS327 into the N-type deep well region 312. The holes injected into the N-type deep well region 312 reach the P-type deep well region 313 and raise the potential of the P-type deep well region 313. As the potential of the P-type deep well region 313 increases, the electron injection from the N-type shallow well region 314 of the P-type DTMOS328 into the P-type deep well region 313 increases more and more. The above process is repeated (positive feedback is applied), an abnormal current flows through the NPNP structure, and a latch-up phenomenon occurs. Here, if a voltage lower than the power supply voltage is applied to the N-type deep well region 312 from the beginning (that is, if the P-type substrate bias variable transistor 325 is in the active state), the latch-up phenomenon is more likely to occur. In addition, P-type board bias variable transformer Even if the Gista 325 is in a standby state (that is, if a potential higher than the power supply voltage is applied to the N-shaped deep well region 312), it may be easy to induce the latch-up phenomenon. In this case, a large reverse bias is applied to the junction between the P-type shallow well region 315 and the N-type deep well region 312 of the N-type DTMOS327, and the junction between the P-type deep well region 313 and the N-type deep well region 312. It takes. Therefore, punch-through occurs between the P-type shallow well region 315 and the P-type deep well region 313 of the N-type DTMOS327, which causes a latch-up phenomenon in the NPNP structure. In addition to the above, as the latch-up route, the drain region 318 of the N-type DTMOS327, the P-type shallow well region 315 of the N-type DTMOS327, the N-type deep well region 312, and the P-type deep well region 313 are used. An NPNP structure consisting of a route through which it passes can also be mentioned. As described above, when the bias of the N-shaped deep well region 312 changes significantly, it becomes difficult to control the latch-up phenomenon. Therefore, the reliability of the element is lowered. If the bias of 312 changes significantly, it becomes difficult to control the latch-up phenomenon. Therefore, the reliability of the element is lowered. If the bias of 312 changes significantly, it becomes difficult to control the latch-up phenomenon. Therefore, the reliability of the element is lowered.

【0020】

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having DTMOS and a substrate bias variable transistor, which has low power consumption and high reliability, and a portable electronic device using the same. There is.

【0021】

[Means for solving problems]

In order to achieve the above object, the semiconductor device of the present invention comprises a semiconductor substrate, the deepest well region of the first conductive type formed in the semiconductor substrate, and the deepest well of the first conductive type. The second deepest well region of the first conductive type formed on the region, the shallow well region of the second conductive type formed on the second deepest well region of the first conductive type, and the second conductive type. The first conductive type dynamic threshold transistor formed on the shallow well region of the mold and electrically connected to the gate electrode and the shallow well region of the second conductive type, and the first of the first conductive type. The second deepest well region of the second conductive type formed on the deep well region, the shallow well region of the second conductive type formed on the second deepest well region of the second conductive type, and the first 2 The substrate bias of the first conductive type electric field effect transistor formed on the shallow well region of the conductive type and the substrate bias of the first conductive type electric field effect transistor formed on the shallow well region of the second conductive type are changed. The input terminal for forming the second conductive type, the deepest well region of the second conductive type formed in the semiconductor substrate, and the second conductive type formed on the deepest well region of the second conductive type. A gate formed on the second deepest well region, the shallow well region of the first conductive type formed on the second deepest well region of the second conductive type, and the shallow well region of the first conductive type. A second conductive type dynamic threshold transistor in which an electrode and the shallow well region of the first conductive type are electrically connected, and a first conductive type formed on the deepest well region of the second conductive type. Formed on the second deepest well region of the mold, the shallow well region of the first conductive mold formed on the second deepest well region of the first conductive mold, and the shallow well region of the first conductive mold. A second conductive type electric field effect transistor, an input terminal formed on the shallow well region of the first conductive type for changing the substrate bias of the second conductive type electric field effect transistor, and the first conductive type. A well region deeper than the bonding depth between the second deepest well region of the mold and the shallow well region of the second conductive mold, and the deepest well region of the first conductive mold.A device separation region shallower than the depth of the junction with the second deepest well region of the second conductive type, and a junction between the second deepest well region of the second conductive type and the shallow well region of the first conductive type. It is characterized by having an element separation region that is deeper than the depth of the bond and shallower than the depth of the junction between the first deepest well region of the second conductive type and the second deepest well region of the first conductive type. It is said.

【0022】

In the present specification, the first conductive type means P type or N type. The second conductive type means N type when the first conductive type is P type, and P type when the first conductive type is N type.

【0023】

The semiconductor device of the present invention is a semiconductor device including a dynamic threshold transistor and a field effect transistor which is a substrate bias variable transistor. A plurality of well regions of each conductive type provided with a variable substrate bias transistor of the type are electrically independent of each other.

【0024】

Therefore, according to the invention, the second conductive type well region provided with the first conductive type field effect transistor can be easily separated from the other second conductive type well region. Further, the first conductive type well region provided with the second conductive type field effect transistor can be easily separated from the other first conductive type well region.

【0025】

Therefore, according to the above invention, an arbitrary number of circuit blocks of the substrate bias variable transistor can be formed, and the circuit blocks to be in the active state and the circuit blocks to be in the standby state can be appropriately separated. , The power consumption of the semiconductor device can be reduced.

【0026】

Further, according to the above invention, the PN junction area between the well region provided with the substrate bias variable transistor and the well region of the opposite conductive type can be reduced as compared with the conventional case, and the power consumption of the semiconductor device can be reduced. be able to.

【0027】

Furthermore, since the potential in the deep well region of the portion where the dynamic threshold transistor is provided can be fixed, the latch-up phenomenon can be easily suppressed.

【0028】

In one embodiment, on the second deepest well region of the second conductive type formed on the first deepest well region of the first conductive type and on the second deepest well region of the second conductive type. It is formed on the formed shallow well region of the second conductive type, the first conductive electric field effect transistor formed on the shallow well region of the second conductive type, and the shallow well region of the second conductive type. , A first conductive circuit block composed of an input terminal for changing the substrate bias of the first conductive electric field effect transistor, or formed on the deepest well region of the second conductive type. On the second deepest well region of the first conductive type, the shallow well region of the first conductive type formed on the second deepest well region of the first conductive type, and the shallow well region of the first conductive type. It consists of a second conductive type electric field effect transistor formed in the above, and an input terminal formed on the shallow well region of the first conductive type and for changing the substrate bias of the second conductive type electric field effect transistor. A plurality of at least one of the second conductive type circuit blocks is provided.

【0029】

According to the above embodiment, a plurality of circuit blocks made of first conductive type substrate bias variable transistors can be provided, and each circuit block can be put into a standby state or an active state as needed. Further, a plurality of circuit blocks composed of second conductive type substrate bias variable transistors can be provided, and each circuit can be put into a standby state or an active state as needed.

【0030】

In one embodiment, the first conductive type dynamic threshold transistor and the second conductive type dynamic threshold transistor, or the first conductive type field effect transistor and the second conductive type field effect transistor, or The first conductive type dynamic threshold transistor and the second conductive type field effect transistor, or the first conductive type field effect transistor and the second conductive type dynamic threshold transistor constitute a complementary circuit.

【0031】

According to the above embodiment, since the complementary circuit is configured, the power consumption can be further reduced.

【0032】

In one embodiment, there are at least two widths of the element separation region, the shallow well region on one side is the first conductive type, and the conductive type of the shallow well region on the other side is the second conductive type. And the width of the element separation region where the second deepest well region on one side is the second conductive type and the conductive type of the second deepest well region on the other side is the first conductive type. A, the conductive type of the shallow well region on both sides is the same, and the conductive type of the second deepest well region on both sides is different from each other. The width of the element separation region is B, and the conductive type of the shallow well region on both sides. When the width of the element separation region is the same and the conductive type of the second deepest well region on both sides is the same, where is C. A> C, B> C Is.

【0033】

According to the above embodiment, a device separation region having a wide width A and B and an element separation region having a narrow width C are provided, and the conductive type of the shallow well region is different on both sides of the element separation region, or the second deepest well region. When the conductive types of the above are different, since the element separation regions having wide widths A and B are provided, punch-through between well regions and threshold shift of the element due to diffusion of impurities can be suppressed. Moreover, when the conductive types of the well regions on both sides are the same, the width C of the element separation region is narrowed, so that the margin between the elements can be reduced.

【0034】

The semiconductor device of the present invention has a semiconductor substrate, a first conductive type deep well region formed in the semiconductor substrate, and a first conductive type shallow well formed on the first conductive type deep well region. A region, a deep well region of the first conductive type formed on the deep well region of the first conductive type, and a shallow well region of the second conductive type formed on the deep well region of the first conductive type. A first conductive type dynamic threshold transistor formed on the well region and the shallow well region of the second conductive type, and the gate electrode and the shallow well region of the second conductive type are electrically connected, and the above. The shallow well region of the second second conductive type formed on the deep well region of the second conductive type and the electric field effect of the first conductive type formed on the shallow well region of the second conductive type. The depth of the junction between the transistor, the deep well region of the first conductive type and the shallow well region of the second conductive type is deeper, and the deep well region of the first conductive type and the deep well region of the second conductive type are deep. It is provided with an element separation region having at least two widths shallower than the depth of bonding with the well region, the conductive types of the shallow well regions on both sides are the same, and the conductive types of the deep well regions on both sides are mutual. When the width of the different element separation regions is B, and the width of the element separation regions having the same conductive type of the shallow well regions on both sides and the same conductive type of the deep well regions on both sides is C, B> C Is. Further, the semiconductor device of the present invention has a semiconductor substrate, a first conductive type deep well region formed in the semiconductor substrate, and a first first conductive type formed on the first conductive type deep well region. The conductive shallow well region, the second conductive electric field effect transistor formed on the first conductive shallow well region, and the first conductive type deep well region formed on the first conductive type electric field effect transistor. A first, which is formed on the shallow well region of the first second conductive type and the shallow well region of the first second conductive type, and the gate electrode and the shallow well region of the second conductive type are electrically connected. 1 Conductive type dynamic threshold transistor, 2nd conductive type deep well region formed on the 1st conductive type deep well region, and 2nd conductive type deep well region formed on the 2nd conductive type deep well region. 2nd conductive type shallow well region, 1st conductive type electric field effect transistor formed on the 2nd conductive type shallow well region, and formed on the 2nd conductive type deep well region. The shallow well region of the second first conductive type and the shallow well region of the second first conductive type formed on the shallow well region of the second first conductive type, and the gate electrode and the shallow well region of the second conductive type are electrically connected with each other. The depth of the junction between the second conductive type dynamic threshold transistor connected to the conductor, the deep well region of the first conductive type and the shallow well region of the first conductive type, and the second The deep well region of the conductive type and the shallow well region of the second conductive type are deeper than the bonding depth, and the deep well region of the first conductive type and the deep well region of the second conductive type It has an element separation region having at least two widths shallower than the bonding depth of the above, the shallow well region on one side is the first conductive type, and the conductive type of the shallow well region on the other side is the second. The width of the element separation region is A on both sides, which is conductive and the deep well region on one side is the second conductive type, and the conductive type of the deep well region on the other side is the first conductive type. The conductive type of a shallow well region is the same, and the conductive type of the deep well region on both sides is different from each other. The width of the element separation region is B, the conductive type of the shallow well region on both sides is the same, and both sides. Deep conductor in

【0035】

According to the above embodiment, a device separation region having a wide width A and B and an element separation region having a narrow width C are provided, and the conductive type of the shallow well region is different on both sides of the element separation region, or the second deepest well region. When the conductive types of the above are different, since the element separation regions having wide widths A and B are provided, punch-through between well regions and threshold shift of the element due to diffusion of impurities can be suppressed. Moreover, when the conductive types of the well regions on both sides are the same, the width C of the element separation region is narrowed, so that the margin between the elements can be reduced.

【0036】

This makes it possible to suppress punch-through between well regions and threshold shift of the device due to diffusion of impurities in a semiconductor device having a well structure of at least two layers or more.

【0037】

In one embodiment, A = B.

【0038】

In this case, the number of types of widths of the element separation region is reduced, and manufacturing becomes easier.

【0039】

In one embodiment, 0.18 μm <A <0.7 μm.

【0040】

By doing so, it is possible to keep the margin between the well regions within an allowable range while surely suppressing the punch-through between the well regions and the threshold shift of the element due to the diffusion of impurities.

【0041】

In one embodiment, the element separation region is composed of STI (Shallow Trench Isolation).

【0042】

In the above embodiment, since the element separation region is made of STI, element separation regions having various widths can be easily formed, and thus a semiconductor device can be easily formed.

【0043】

The portable electronic device of the first embodiment includes the semiconductor device.

【0044】

Since the portable electronic device includes the semiconductor device having low power consumption, the battery life can be significantly extended.

【0045】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

【0046】

The semiconductor substrate that can be used in the present invention is not particularly limited, but a silicon substrate is preferable. Further, the semiconductor substrate may have a P-type or an N-type conductive type.

【0047】

FIG. 1 is a schematic view of a cross section of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a schematic view of a plane of the semiconductor device.

【0048】

As shown in FIG. 1, in this semiconductor device, the N-type very deep, that is, the deepest well region 12 and the P-type, which is the very deep, that is, the deepest well region 13 are formed in the P-type silicon substrate 11. It is formed.

【0049】

Within the N-type very deep well region 12, the N-type deep, that is, the second deepest well region 14 is formed. A shallow P-shaped well region 17 is formed in the deep N-shaped well region 14. An N-type source region 19 and an N-type drain region 20 are formed in the P-type shallow well region 17. Further, a gate electrode 26 is formed on the channel region between the N-type source region 19 and the N-type drain region 20 via the gate insulating film 25, and constitutes the N-type DTMOS 29, 29. .. Although not shown, in the DTMOS 29, the gate electrode 26 and the P-shaped shallow well region 17 are electrically connected. The element separation region 18 has a depth sufficient to electrically separate the P-shaped shallow well regions 17 and 17 of adjacent elements. Therefore, the P-shaped shallow well regions 17,17 of each DTMOS 29,29 are electrically separated from each other. The N-type very deep well region 12 is passed through the N-type deep well region 14, the N-type shallow well region 16 and the N-type impurity-rich region 23, and the N-type is very deep, that is, the first. It is connected to the bias input terminal 31 to the deep well region 12. Normally, a power supply voltage is applied to the bias input terminal 31 to the N-type very deep well region 12.

【0050】

Further, in the N-type very deep well region 12, the P-type deep, that is, the second deepest well region 15 is formed. A shallow P-shaped well region 17 is formed in the deep P-shaped well region 15. An N-type source region 19 and an N-type drain region 20 are formed in the P-type shallow well region 17. Further, a gate electrode 26 is formed on the channel region between the N-type source region 19 and the N-type drain region 20 via the gate insulating film 25, and N-type substrate bias variable transistors 27 and 27 are provided. It is configured. The P-shaped deep well region 15 and the P-shaped shallow well region 17 are integrated and are not separated in the element separation region 18. Therefore, the N-type substrate bias variable transistors 27,27 share the P-type well regions 15,17. The P-type deep well region 15 and the P-type shallow well region 17 are connected to the well bias input terminal 34 to the N-type substrate bias variable transistor 27 via the P-type impurity-rich region 24. There is. From a bias generation circuit (not shown) to the well bias input terminals 34 to the N-type substrate bias variable transistors 27 and 27, 0 V or a positive voltage is applied when active and a negative voltage is applied when standby.

【0051】

Within the very deep or first deepest well region 13 of the P type, the deep or second deepest well region 15 of the P type is formed. An N-type shallow well region 16 is formed in the P-type deep well region 15. A P-type source region 21 and a P-type drain region 22 are formed in the N-type shallow well region 16. Further, a gate electrode 26 is formed on the channel region between the P-type source region 21 and the P-type drain region 22 via the gate insulating film 25 to form a P-type DTMOS30. Although not shown, the DTMOS 30 has a gate electrode 26 and an N-shaped shallow well region 16 electrically connected to each other. The element separation region 18 has a depth sufficient to electrically separate the N-shaped shallow well regions 16 and 16 of adjacent elements. Therefore, the N-shaped shallow well regions 16 of each DTMOS30 are electrically separated from each other. The P-type very deep, that is, the deepest well region 13, is passed through the P-type deep, that is, the second deepest well region 15, the P-type shallow well region 17, and the P-type impurity-rich region 24. , P-shaped and connected to the bias input terminal 32 to the very deep well region 13. Normally, 0V is applied to the bias input terminal 32 to the P-shaped very deep well region 13.

【0052】

Further, in the P-type very deep well region 13, the N-type deep, that is, the second deepest well region 14 is formed. An N-type shallow well region 16 is formed in the N-type deep well region 14. A P-type source region 21 and a P-type drain region 22 are formed in the N-type shallow well region 16. Further, a gate electrode 26 is formed via a gate insulating film 25 on the channel region between the P-type source region 21 and the P-type drain region 22, and the P-type substrate bias variable transistor 28 is formed. Has been done. The N-type deep well region 14 and the N-type shallow well region 16 are integrated and are not separated in the element separation region 18. Therefore, the P-type substrate bias variable transistor 28 shares the N-type well regions 14 and 16. The N-type deep well region 14 and the N-type shallow well region 16 are connected to the well bias input terminal 33 to the P-type substrate bias variable transistor 28 via the N-type impurity-rich region 23. There is. From a bias generation circuit (not shown) to the well bias input terminal 33 to the P-type substrate bias variable transistor 28, a voltage lower than the power supply voltage or the power supply voltage is applied when active, and a voltage higher than the power supply voltage is applied when standby. (NMOS source potential is 0V, PCOS source potential is power supply voltage).

【0053】

Next, the semiconductor device of this embodiment will be described with reference to FIG. Note that in FIG. 2, individual wiring and a bias generation circuit for configuring the circuit are omitted. On the semiconductor substrate, there is a region 51 in which an N-type very deep well region is formed and a region 52 in which a P-type very deep well region is formed. In the region 51 in which the N-type very deep well region is formed, a block 53 made of an N-type substrate bias variable transistor and a block 54 made of an N-type DTMOS are formed. A block 55 made of a P-type substrate bias variable transistor and a block 56 made of a P-type DTMOS are formed in a region 52 in which a very deep P-type well region is formed.

【0054】

The block 53 made of an N-type substrate bias variable transistor may be connected to a block 53 made of another N-type substrate bias variable transistor by an upper wiring 57 connecting a common well region of the substrate bias transistor. The plurality of blocks 53, 53 composed of N-type substrate bias variable transistors connected to each other in this way function as one circuit block composed of N-type substrate bias variable transistors. A bias generating circuit (not shown) supplies the common well region of this circuit block with 0V or a positive voltage when active and a negative voltage when standby.

【0055】

The block 55 composed of the P-type substrate bias variable transistor may be connected to the block 55 composed of another P-type substrate bias variable transistor by the upper wiring 57 connecting the common well region of the substrate bias transistor. The blocks 55 and 55 composed of P-type substrate bias variable transistors connected to each other in this way function as one circuit block composed of P-type substrate bias variable transistors. A bias generating circuit (not shown) supplies a voltage lower than the power supply voltage or the power supply voltage to the common well region of this circuit block when active, and a voltage higher than the power supply voltage when standby.

【0056】

By using the well structure shown in FIG. 1 and further arranging it as shown in FIG. 2, it is possible to easily form a circuit block of a plurality of substrate bias variable transistors in a circuit in which a substrate bias variable transistor and DTMOS coexist. .. In addition, an N-type element and a P-type element can be connected by upper wiring to form a complementary (CMOS) circuit.

【0057】

Next, the procedure for manufacturing the semiconductor device will be described with reference to FIGS. 1 and 2.

【0058】

First, element separation regions 18,181,182,183 are formed on the semiconductor substrate 11. The element separation regions 18,181,182,183 can be formed by using, for example, the STI (Shallow Trench Isolation) method. By using the STI method, it is easy to form element separation regions of various widths at the same time. However, the method of forming the element separation regions 18,181,182,183 is not limited to the STI method, and the element separation regions 18,181,182,183 may have a function of electrically separating shallow well regions. For example, the substance embedded in the device separation regions 18,181,182,183 may be a conductive substance such as polysilicon or amorphous silicon in addition to the silicon oxide film and the silicon nitride film. However, when embedding a conductive substance such as polysilicon or amorphous silicon, it is necessary to secure the insulating property of the device separation region 18,181,182,183 by oxidizing the side wall of the device separation region 18,181,182,183 in advance.

【0059】

The depths of the element separation regions 18,181,182,183 are set so that the shallow well regions 16 and 17 of adjacent elements are electrically separated and the deep well regions 14 and 15 are not electrically separated. The depth of the element separation region 18,181,182,183 is preferably 0.2 to 2 μm, for example.

【0060】

The widths of the element separation regions 18,181,182,183 are set as follows. When the conductive types of the deep well regions 14 and 15 are different on both sides of the element separation region 181 as in the element separation region 181. For example, at the boundary between the N-type DTMOS29 and the N-type substrate bias variable transistor 27, the N-type DTMOS29 The deep well region 14 on the side is N-type, and the deep well region 15 on the N-type substrate bias variable transistor 27 side is P-type. In this case, punch-through between the P-type shallow well region 17 of the N-type DTMOS29 and the P-type deep well region 15 of the N-type substrate bias variable transistor 27 becomes a problem. Furthermore, impurities in the N-type deep well region 14 of the N-type DTMOS29 may diffuse, and the threshold value of the N-type substrate bias variable transistor 27 may change. Another example is the boundary between N-type DTMOS29 and P-type DTMOS30, which causes similar problems. In this case, on both sides of the element separation region 182 at the boundary, the conductive types of the shallow well regions 16 and 17 are opposite to each other, and the conductive types of the deep well regions 15 and 14 are also opposite to each other. In addition, the boundary between P-type DTMOS30 and P-type substrate bias variable transistor 28, the boundary between P-type DTMOS30 and N-type substrate bias variable transistor 27, the boundary between N-type DTMOS29 and P-type substrate bias variable transistor 28, and N-type. A similar problem occurs at the boundary between the substrate bias variable transistor 27 and the P-type substrate bias variable transistor 28. Therefore, the conductive types of the deep well regions 14 and 15 are opposite on both sides of the element separation region 181,183, and the conductive types of the shallow well regions 16 and 17 are opposite on both sides of the element separation region 182, and the deep well regions are opposite. If the conductive types of 14,15 are also the opposite, the width of the element separation regions 181,182,183 needs to be wide enough not to cause the above-mentioned punch-through and threshold change. For example, the impurity injection range in the deep well region is 0. Even if it is made very shallow, about 3 μm, the impurities spread in the lateral direction at the time of injection, and further diffuse in the lateral direction by the subsequent thermal diffusion. Even under the above injection conditions, when the width of the device separation region was less than 0.18 μm, the change in the threshold value could not be suppressed. Further, when the width of the element separation region is 0.7 μm or more, the margin required for element separation cannot be ignored. Therefore, in order to prevent the above-mentioned punch-through and threshold change, the width of the element separation regions 181,182,183 is preferably 0.18 μm to 0.7 μm. When the conductive type of the shallow well region 16 or 17 is the same and the conductive type of the deep well region 14 or 15 is the same on both sides of the element separation region 18 (the conductive type of the shallow well region 16 or 17 and the deep well region is the same. (It may be different), the smaller the width of the element separation region 18, the smaller the margin can be. Therefore, it is close to the limit dimension of processing. In this case, the width of the element separation region 18 can be, for example, 0.05 to 0.35 μm.

【0061】

That is, assuming that the width of the element separation region 182 is A, the width of the element separation regions 181,183 is B, and the width of the element separation region 18 is C, A = B> C. However, the widths of the element separation regions 181, 182, 183 do not have to be the same.

【0062】

Next, the procedure for forming the wells on the semiconductor substrate 11 will be described with reference to FIGS. 3 to 8.

【0063】

As shown in FIG. 3, an N-shaped extremely deep well region 12 is formed on the semiconductor substrate 11 with the photoresist 35 as a mask. As an impurity ion that gives N type³¹P⁺Can be mentioned. For example, as an impurity ion³¹P⁺When using, the injection energy is 500 to 3000 KeV, and the injection amount is 5 x 10.¹¹~1×10¹⁴cm^-2It can be formed under the conditions of.

【0064】

Next, as shown in FIG. 4, a P-shaped very deep well region 13 is formed using the photoresist 35 as a mask. As an impurity ion that gives P type¹¹B⁺Can be mentioned. For example, as an impurity ion¹¹B⁺When ions are used, the injection energy is 200 to 2000 KeV, and the injection amount is 5 x 10.¹¹~1×10¹⁴cm^-2It can be formed under the conditions of.

【0065】

Next, as shown in FIG. 5, an N-shaped deep well region 14 is formed using the photoresist 35 as a mask. As an impurity ion that gives N type³¹P⁺Can be mentioned. For example, as an impurity ion³¹P⁺When using, the injection energy is 240 ~ 1500KeV, and the injection amount is 5 × 10.¹¹~1×10¹⁴cm^-2It can be formed under the conditions of.

【0066】

Next, as shown in FIG. 6, a P-shaped deep well region 15 is formed using the photoresist 35 as a mask. As an impurity ion that gives P type¹¹B⁺Can be mentioned. For example, as an impurity ion¹¹B⁺When ions are used, the injection energy is 100 to 1000 KeV, and the injection amount is 5 x 10.¹¹~1×10¹⁴cm^-2It can be formed under the conditions of.

【0067】

Next, as shown in FIG. 7, an N-shaped shallow well region 16 is formed using the photoresist 35 as a mask. As an impurity ion that gives N type³¹P⁺Can be mentioned. For example, as an impurity ion³¹P⁺When using, the injection energy is 130 ~ 900KeV and the injection amount is 5 × 10.¹¹~1×10¹⁴cm^-2It can be formed under the conditions of.

【0068】

Next, as shown in FIG. 8, a P-shaped shallow well region 17 is formed using the photoresist 35 as a mask. As an impurity ion that gives P type¹¹B⁺Can be mentioned. For example, as an impurity ion¹¹B⁺When ions are used, the injection energy is 60 to 500 KeV and the injection amount is 5 x 10.¹¹~1×10¹⁴cm^-2It can be formed under the conditions of.

【0069】

The order of impurity injection for forming the well region is not limited to the above, and the order may be changed.

【0070】

The depth of the junction between the shallow well regions 16,17 and the deep well regions 14,15 and the depth of the junction between the deep well regions 14,15 and the very deep well regions 12,13 are the shallow well regions. It is determined by the conditions for injecting impurities into 16,17, the conditions for injecting impurities into deep well regions 14,15, the conditions for injecting impurities into very deep well regions 12,13, and the subsequent thermal steps. The depths of the element separation regions 18,181,182,183 are set so that the shallow well regions 16 and 17 of adjacent elements are electrically separated and the deep well regions 14 and 15 are not electrically separated.

【0071】

Further, in order to reduce the resistance of the shallow well regions 16 and 17, the same conductive high-concentration embedded region as the impurity ions of the shallow well regions 16 and 17 may be formed in the shallow well region. When the resistance of the shallow well regions 16 and 17 decreases, the input to the gate electrode 26 quickly propagates to the shallow well regions 16 and 17, and the substrate bias effect can be sufficiently obtained, and the operation speed of the DTMOS 29 and 30 is increased. Is realized. When the high-concentration embedded region is formed in the shallow P-shaped well region 17, for example, it is used as an impurity ion.¹¹B⁺, 100 ~ 400KeV as injection energy, 1 × 10 as injection amount¹²~1×10¹⁴cm^-2When formed under the conditions of, or in the shallow well region 16 of N type, as an impurity ion³¹P⁺, 240 ~ 750 KeV as injection energy, 1 × 10 as injection amount¹²~1×10¹⁴cm^-2Each can be formed under the conditions of.

【0072】

Furthermore, in order to prevent the impurity concentration from becoming too thin in the substrate surface region, the same conductive type impurity ions as the impurity ions in the shallow well regions 16 and 17 are injected into the shallow well regions 16 and 17 with a punch-through stopper. Is also good. Punch-through stopper injection is, for example, as an impurity ion when formed in the shallow P-shaped well region 17.¹¹B⁺, 10 ~ 60KeV as injection energy, 5 × 10 as injection amount¹¹~1×10¹³cm^-2When formed under the conditions of, or in the shallow well region 16 of N type, as an impurity ion³¹P⁺, 30 ~ 150KeV as injection energy, 5 × 10 as injection amount¹¹~1×10¹³cm^-2Each can be done under the conditions of.

【0073】

Next, the gate insulating film 25 and the gate electrode 26 shown in FIG. 1 are formed in this order.

【0074】

The material of the gate insulating film 25 is not particularly limited as long as it has insulating properties. Here, when a silicon substrate is used, a silicon oxide film, a silicon nitride film, or a laminate thereof can be used. Further, a highly dielectric film such as an aluminum oxide film, a titanium oxide film, and a tantalum oxide film, or a laminate thereof can also be used. The gate insulating film 25 preferably has a thickness of 1 to 10 nm when a silicon oxide film is used. The gate insulating film 25 can be formed by a method such as a CVD (chemical vapor deposition) method, a sputtering method, or a thermal oxidation method.

【0075】

Next, the material of the gate electrode 26 is not particularly limited as long as it has conductivity. Here, when a silicon substrate is used, a silicon film such as polysilicon or single crystal silicon can be mentioned. In addition to the above, metal films such as aluminum and copper can be mentioned. The gate electrode preferably has a thickness of 0.1 to 0.4 μm. The gate electrode can be formed by a method such as a CVD method or a vapor deposition method.

【0076】

Further, a sidewall spacer may be formed on the side wall of the gate electrode 26. The material of the sidewall spacer is not particularly limited as long as it is an insulating film, and examples thereof include silicon oxide and silicon nitride.

【0077】

Next, DTMOS29,30 forms a gate-board connection region (not shown). To form a gate-board connection region that electrically connects the gate electrode 26 and the shallow well regions 16, 17 in regions other than the source regions 19, 21, drain regions 20, 22 and channel regions, the gate electrodes 26 and A part of the gate oxide film is etched until the underlying substrate is exposed. In this exposed region, a region having a high impurity concentration (a region having a high P-type impurity in the case of an NMOS and a region having a high N-type impurity in the case of a PMOS) is formed. The gate electrode 26 and the shallow well regions 16 and 17 are electrically connected in the gate-board connection region by a later silicidization step.

【0078】

Next, on the surface layer of the shallow well regions 17 and 16, a source region (NMOS source region 19 and a MIMO source region 21) and a drain region (NMOS drain region 20) which are opposite to the shallow well regions 17 and 16 are conductive. And the MIMO drain region 22) is formed.

【0079】

The method of forming the source regions 19, 21 and the drain regions 20, 22 is self-aligned, for example, by injecting impurity ions of a conductive type opposite to the shallow well regions 17, 16 using the gate electrode 26 as a mask. be able to. The source regions 19, 21 and drain regions 20, 22 are, for example, as impurity ions.⁷⁵As⁺When ions are used, the injection energy is 3 to 100 KeV and the injection amount is 1 x 10.¹⁵~1×10¹⁶cm^-2Conditions, or as impurity ions¹¹B⁺When ions are used, the injection energy is 1 to 20 KeV and the injection amount is 1 x 10.¹⁵~1×10¹⁶cm^-2It can be formed under the conditions of. The surface layers of the shallow well regions 16 and 17 below the gate electrode 26 function as channel regions.

【0080】

Further, although the source regions 19 and 21 and the drain regions 20 and 22 are not shown, an LDD (Lightly Doped Drain) region may be provided on the gate electrode 26 side. The LDD region can be formed in a self-aligned manner by, for example, using the gate electrode 26 as a mask and injecting impurity ions of a conductive type opposite to the shallow well regions 16 and 17. In this case, in the source regions 19, 21 and the drain regions 20, 22, after forming the LDD region, a sidewall spacer (not shown) is formed on the side wall of the gate electrode 26, and ion implantation is performed using the gate electrode 26 and the sidewall spacer as a mask. By doing so, it can be formed in a self-consistent manner. The injection of impurities to form the LDD region is, for example, as impurity ions.⁷⁵As⁺When ions are used, the injection energy is 3 to 100 KeV and the injection amount is 5 x 10.¹³~1×10¹⁵cm^-2Conditions, or as impurity ions¹¹B⁺When ions are used, the injection energy is 1 to 20 KeV and the injection amount is 1 x 10.¹³~5×10¹⁴cm^-2It can be formed under the conditions of.

【0081】

As impurity ions for forming the source regions 19, 21, drain regions 20, 22 and LDD regions, the above.¹¹B⁺Ion and⁷⁵As⁺Besides Aeon,³¹P⁺ion,¹²²Sb⁺ion,¹¹⁵In⁺ion,⁴⁹BF₂⁺Ions and the like can also be used.

【0082】

Further, the surface layers of the source regions 19, 21, the drain regions 20, 22 and the gate electrodes 26 are silicidized in order to reduce the resistance thereof and improve the conductivity with the wiring connected to each. This silicidization electrically connects the gate electrode 26 and the shallow well regions 16 and 17 in the gate-board connection region. Examples of the silicide include tungsten silicide, titanium silicide and the like.

【0083】

Although not shown, the source region and the drain region may be of a stacked type (see JP-A-2000-82815). In this case, the areas of the source region and the drain region can be reduced, and high integration is possible.

【0084】

After this, the impurities are activated and annealed. Activation annealing is performed under conditions where the impurities are sufficiently activated and the impurities are not excessively diffused. For example, N-type impurities⁷⁵As⁺And P-type impurities¹¹B⁺If so⁷⁵As⁺After injecting, anneal at 800 ~ 1000 ° C for 10 ~ 100 minutes, then¹¹B⁺Can be annealed at 800-1000 ° C for 10-100 seconds after injection. In addition, in order to smooth the impurity profiles of the shallow well region, the deep well region and the very deep well region, it may be annealed separately before injecting the impurities in the source region and the drain region.

【0085】

After that, the semiconductor device can be formed by forming wiring or the like by a known method.

【0086】

In the above description, for convenience of explanation, only the substrate bias variable transistors 27,28 and the DTMOS29,30 are formed, but MOSFETs having a normal structure may be mixed. In this case, in an element that should be a normal MOSFET, the potential in the shallow well region may be fixed.

【0087】

In the semiconductor device, the shallow well regions 17 and 16 of the DTMOS 29,30 are electrically separated for each element by the opposite conductive type deep well regions 14 and 15 and the element separation region 18. Further, the common well region of the substrate bias variable transistor 27,28 is formed by the opposite conductive type deep well region 14,15, the opposite conductive type very deep well region 12,13, and the element separation region 18,181,183 for each circuit block. Is electrically separated. Furthermore, the potentials of the very deep well regions 12, 13 and the deep well regions 14, 15 of the DTMOS 29,30 are fixed.

【0088】

Therefore, according to the semiconductor device of the present embodiment, an arbitrary number of circuit blocks of the substrate bias variable transistors 27 and 28 can be formed. As a result, the circuit block to be in the active state and the circuit block to be in the standby state can be appropriately separated, and the power consumption of the semiconductor device can be reduced.

【0089】

Further, according to the semiconductor device of the present embodiment, the area of the PN junction between the common wells of the substrate bias variable transistors 27 and 28 and the PN junction region in contact with the common wells of the substrate bias variable transistors 27 and 28 is the circuit of the substrate bias variable transistors 27 and 28. It can be suppressed to about the area of the block. On the other hand, the conventional semiconductor device has a PN junction having a large area comparable to the area of the entire substrate. Therefore, in the semiconductor device of the present embodiment, the charge / discharge of the electric charge when the potential of the common wells of the substrate bias variable transistors 27 and 28 changes is reduced as compared with the conventional example. As a result, the power consumption of the semiconductor device can be reduced.

【0090】

Furthermore, according to the semiconductor device of the present embodiment, the potentials of the very deep well regions 12, 13 and the deep well regions 14, 15 of the DTMOS 29, 30 are fixed, so that the latch-up phenomenon can be easily controlled. become. This improves the reliability of the semiconductor device.

【0091】

A CMOS circuit can also be assembled using the semiconductor device of this embodiment. A CMOS circuit with low power consumption and high speed by appropriately combining the advantages of DTMOS29,30, which can obtain high drive current with low voltage drive, and substrate bias variable transistors 27,28, which can reduce off-leakage current very much. Can be realized. Further, if a plurality of circuit blocks of the substrate bias variable transistors 27 and 28 are formed and the circuit blocks other than the circuit blocks to be activated are set to the standby state, the power consumption of the CMOS circuit can be further reduced.

【0092】

FIG. 9 is a vertical sectional view showing a semiconductor device of another embodiment. The semiconductor device of FIG. 9 is different from the conventional semiconductor device shown in FIG. 11 only in that a narrow element separation region 316 and a wide element separation region 516,616,716,816 are mixed. Therefore, among the components of the semiconductor device of FIG. 9, the same components as those of the conventional semiconductor device shown in FIG. 11 are designated by the same reference numbers, and the description thereof will be omitted.

【0093】

On both sides of the narrow element separation region 316, there are shallow well regions 314,315 of the same conductive type, and 312,323 deep well regions of the same conductive type. On both sides of the wide element separation region 516, the conductive types of the shallow well regions 314 and 315 are opposite, and the conductive types of the deep well regions 313 are the same. Further, on both sides of the wide element separation region 616, the conductive type of the shallow well region 315 is the same, and the conductive type of the deep well regions 312 and 313 is opposite. Further, on both sides of the wide element separation region 716,816, the conductive type of the shallow well region 314,315 is opposite, and the conductive type of the deep well region 312,313 is also opposite. That is, assuming that the width of the element separation region 716 is A, the width of the element separation regions 516,616,816 is B, and the width of the element separation region 316 is C, A = B> C. However, the widths of the element separation regions 516,616,716,816 do not have to be the same.

【0094】

By providing the wide element separation regions 516,616,716,816 in this way, punch-through and changes in the threshold value can be prevented.

【0095】

Further, the semiconductor device of the present embodiment can be incorporated into a battery-powered portable electronic device. Examples of the portable electronic device include a mobile information terminal, a mobile phone, a game device, and the like. FIG. 10 shows an example of a mobile phone. The semiconductor device of the present invention is incorporated in the control circuit 111. The control circuit 111 may be composed of a logic circuit made of the semiconductor device of the present invention and an LSI (large-scale integrated circuit) in which a memory is mixedly mounted. 112 is a battery, 113 is an RF (radio frequency) circuit unit, 114 is a display unit, 115 is an antenna unit, 116 is a signal line, and 117 is a power supply line. By using the semiconductor device of the present invention in a portable electronic device, it is possible to significantly reduce the power consumption of the LSI unit while maintaining the function and operating speed of the portable electronic device. As a result, the battery life can be significantly extended.

【0096】

[Effect of the invention]

In the semiconductor device of the present invention, in a semiconductor device including a dynamic threshold transistor and a substrate bias variable transistor, a substrate bias variable transistor is provided for each of the conductive types by using a well region and an element separation region of three layers. It makes it possible to electrically separate a plurality of well regions from each other.

【0097】

Therefore, according to the present invention, an arbitrary number of circuit blocks of the substrate bias variable transistor can be formed for each conductive type, and the circuit blocks to be activated and the circuit blocks to be in the standby state are appropriately defined. It can be divided into two, and the power consumption of the semiconductor device can be reduced.

【0098】

Further, according to the present invention, the PN junction area between the well region provided with the substrate bias variable transistor and the well region of the opposite conductive type can be reduced, and the power consumption of the semiconductor device can be reduced.

【0099】

Furthermore, since the potential in the deep well region of the DTMOS portion can be fixed, the latch-up phenomenon can be easily suppressed.

【0100】

Further, in one embodiment, in a semiconductor device having three layers of well regions, the device separation region having at least two widths is provided, and the shallow well region on one side is the first conductive type and the other side. The conductive type of the shallow well region in is the second conductive type, and the second deepest well region on one side is the second conductive type, and the conductive type of the second deepest well region on the other side is the conductive type. Is the first conductive type, the width of the element separation region is A, the conductive types of the shallow well regions on both sides are the same, and the conductive types of the second deepest well regions on both sides are different from each other. The width of the element separation region is B, and the conductive type of the shallow well region on both sides is the same, and the conductive type of the second deepest well region on both sides is the same. Since C and B> C, even if the well region has a three-layer structure, the device separation region of wide A and B suppresses punch-through between well regions and the threshold shift of the device due to diffusion of impurities. It is possible to reduce the margin in the element separation region having a narrow width C.

【0101】

Further, the semiconductor device of the present invention is a semiconductor device having a well structure of at least two layers and has element separation regions having at least two widths, and a shallow well region on one side is the first conductive type. The conductive type of the shallow well region on the other side is the second conductive type, the deep well region on the one side is the second conductive type, and the conductive type of the deep well region on the other side is the first. The width of the element separation region, which is a conductive type, is A, the width of the shallow well regions on both sides is the same, and the conductive types of the deep well regions on both sides are different from each other. The width of the element separation region is B, both sides. When the width of the element separation region where the conductive type of the shallow well region in the above is the same and the conductive type of the deep well region on both sides is the same is C, A> C and B> C. Punch-through between well regions and threshold shift of the device due to diffusion of impurities can be suppressed in the wide A and B element separation regions, and the margin can be reduced in the narrow C element separation region.

【0102】

Further, since the portable electronic device of the present invention uses the semiconductor device, the power consumption of the LSI unit and the like can be significantly reduced, and the battery life can be significantly extended.

[Simple explanation of drawings]

[Figure 1]

It is a vertical sectional view of the semiconductor device of 1 Embodiment of this invention.

[Figure 2]

It is a top view of the semiconductor device of the said embodiment.

[Fig. 3]

It is a figure explaining the manufacturing method of the semiconductor device of the said Embodiment.

[Fig. 4]

It is a figure explaining the manufacturing method of the semiconductor device of the said Embodiment.

[Fig. 5]

It is a figure explaining the manufacturing method of the semiconductor device of the said Embodiment.

[Fig. 6]

It is a figure explaining the manufacturing method of the semiconductor device of the said Embodiment.

[Fig. 7]

It is a figure explaining the manufacturing method of the semiconductor device of the said Embodiment.

[Fig. 8]

It is a figure explaining the manufacturing method of the semiconductor device of the said Embodiment.

[Fig. 9]

It is a vertical sectional view of the semiconductor device of another embodiment of this invention.

[Fig. 10]

It is a figure of the portable electronic device of another embodiment of this invention.

[Fig. 11]

It is sectional drawing of the conventional semiconductor device.

[Fig. 12]

It is a figure explaining the manufacturing method of the conventional semiconductor device.

[Fig. 13]

It is a figure explaining the manufacturing method of the conventional semiconductor device.

[Explanation of symbols]

11 board 12,13 Very deep well area 14,15,312,313 Deep well area 16,17,314,315 Shallow well area 18,181,182,183,316,516,616,716,816 Element separation region 19,21 Source area 20,22 Drain area 25,323 Gate insulating film 26,324 Gate electrode 27,28,325,326 Board bias variable transistor 29,30,327,328 DTMOS 31,32,33,34,329,330,331 Bias input terminal