Diversity-receiving circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a diversity receiving circuit suitable for an OFDM modulation / demodulation method.

【0002】

[Conventional technology]

Generally, diversity type communication is adopted for the purpose of fading countermeasures and improvement of S / N in wireless communication. These are reception methods that perform high-quality communication by obtaining two or more signals with little correlation, selecting from them, or synthesizing them.

【0003】

In the frequency selective fading environment caused by this multipath propagation, the average amplitude and the amount of phase rotation differ for each subcarrier. Therefore, a method of diversifying synthesis for each subcarrier is known as a diversity method suitable for OFDM. In order to perform synthesis for each subcarrier, the OFDM signal synchronously processed in each branch is converted into a subcarrier signal by Fourier transform, and then diversity synthesis is performed. In addition, since it is necessary to align the reference phases of the subcarrier signals of each branch for diversity synthesis having a large improvement effect, equalization processing is performed before diversity synthesis.

【0004】

FIG. 13 shows a configuration example of a diversity receiving circuit suitable for the conventional OFDM modulation / demodulation method in which the signals of each branch after the equalization process are weighted and synthesized based on the reception level of each system and the amplitude information of each subcarrier. Here, an example of a diversity with two branches of the I system and the II system is shown.

【0005】

In this configuration example, the signals received by the antennas 41-1, 41-2 are input to the reception level detection circuits 42-1, 42-2 and the reception circuits 43-1, 43-2, respectively. The reception level detection circuits 42-1 and 42-2 detect the reception level of each input signal.

【0006】

On the other hand, the receiving circuits 43-1 and 43-2 perform necessary reception processing such as amplification and down-conversion of the input signal, respectively, and output the received signals (S1) and (S2). The received signals (S1) and (S2) output from these receiving circuits 43-1, 43-2 are input to the timing detection circuit 44-1, 44-2 and the timing synchronization circuit 45-1, 45-2, respectively. Will be done.

【0007】

The timing detection circuits 44-1, 44-2 detect the timing information required for the timing synchronization processing from the received signals (S1) and (S2), respectively, and the detected timing information is used in the timing synchronization circuits 45-1, 45-, respectively. Give to 2. The timing synchronization circuits 45-1 and 45-2 perform timing synchronization processing of the received signals (S1) and (S2) based on the given timing information, respectively.

【0008】

The timing synchronization signals (S3) and (S4) output from these timing synchronization circuits 45-1, 45-2 are the carrier frequency error detection circuit 46-1, 46-2 and the carrier frequency error correction circuit 47-1, respectively. , 47-2. The carrier frequency error detection circuits 46-1 and 46-2 detect the carrier frequency error amount from the timing synchronization signals (S3) and (S4), respectively, and the detected carrier frequency error amount is used as the carrier frequency error correction circuit 47-1. Give to, 47.2.

【0009】

The carrier frequency error correction circuits 47-1, 47-2 are signals (S3) and (S4) by the amount of phase rotation corresponding to the carrier frequency error amount given by the carrier frequency error detection circuits 46-1, 46-2, respectively. The carrier frequency error is corrected by rotating the phase in the reverse direction, and the carrier frequency error correction signals (S5) and (S6) are given to the Fourier conversion circuits 48-1 and 48-2, respectively. The Fourier transform circuits 48-1 and 48-2 are subcarrier signals obtained by Fourier transforming the carrier frequency error correction signals (S5) and (S6), respectively, in order to demultiplex the multiplexed OFDM signal. (S7) and (S8) are given to the channel characteristic detection circuit 49-1, 49-2 and the channel equalization circuit 50-1, 50-2, respectively.

【0010】

The channel characteristic detection circuits 49-1 and 49-2 detect the amplitude information and phase rotation amount of each subcarrier from the subcarrier signals (S7) and (S8), respectively, and the detection results are obtained by the channel equalization circuit 50, respectively. It is given to -1,50-2 and the signal synthesis circuit 51.

【0011】

The channel equalization circuits 50-1 and 50-2 are subcarrier signals (S7) and (S8) based on the amplitude information and phase rotation amount of each subcarrier given by the channel characteristic detection circuits 49-1 and 49-2, respectively. ) Is channel-equalized, and the channel-equalized channel equalization signals (S9) and (S10) are given to the signal synthesis circuit 51.

【0012】

The signal synthesis circuit 51 is diversified based on the reception level obtained by the reception level detection circuits 42-1 and 42-2 and the amplitude information of each subcarrier detected by the channel characteristic detection circuits 49-1 and 49-2. A weighting coefficient is calculated so as to increase the S / N of the subsequent signal, and the calculated weighting coefficient is multiplied by the signals (S9) and (S10) to perform weighting synthesis.

【0013】

[Problems to be Solved by the Invention]

When the above-mentioned conventional diversity method is applied to perform diversity synthesis for each subcarrier in a frequency-selective fading environment in which the average amplitude and phase rotation amount are different for each subcarrier, a large improvement in the code error rate can be obtained. ..

【0014】

However, in a low C / N environment, the detection accuracy of the carrier frequency error amount in the carrier frequency error detection circuit of each branch becomes low due to noise. Therefore, there is a problem that the improvement amount of the code error rate by the diversity synthesis becomes small.

【0015】

Therefore, the present invention improves the carrier frequency error detection accuracy of the carrier frequency error detection circuit and improves the code error rate by weighting and synthesizing the carrier frequency error detected from each branch based on the reception level of each branch. It is an object of the present invention to provide a diversity receiving circuit.

【0016】

[Means for solving problems]

In order to achieve the above object, the present invention has the above-mentioned reception paths in a diversity reception circuit having a plurality of reception paths and generating and outputting one signal by selecting or synthesizing one of the reception signals. Based on the magnitude of the reception level obtained in the above, the carrier frequency error amount obtained from the received signal is weighted, and the carrier frequency error estimation means for synthesizing the carrier frequency error amount is provided, and the carrier frequency error estimation is provided. Provided is a diversity receiving circuit in which a carrier frequency error amount estimated by means is used for carrier frequency error correction of each receiving path.

【0017】

Specifically, for improving fading and S / N, a plurality of receiving means for receiving each of a plurality of independent OFDM signals and a receiving level of the received signal obtained by each of the receiving means are detected. A plurality of reception level detecting means for detecting timing information required for timing synchronization processing from each of the received signals obtained by the receiving means, and the timing detecting means detected by the timing detecting means. A plurality of timing synchronization means that perform timing synchronization processing on the received signal obtained by each of the reception means using timing information, and a plurality of detection means for detecting a carrier frequency error amount from the output signal of each timing synchronization means. The carrier frequency error amount is obtained by weighting and synthesizing the carrier frequency error detecting means and each carrier frequency error amount detected by each carrier frequency error detecting means based on the reception level detected by each receiving level detecting means. A carrier frequency error estimating means for estimating the above, and a plurality of carrier frequency error correcting means for correcting the carrier frequency error of the output signal of each timing synchronization means based on the carrier frequency error amount estimated by the carrier frequency error estimating means. A plurality of Fourier transform means for Fourier transforming the output signals of the respective carrier frequency error correction means, and a plurality of detectors for detecting subcarrier amplitude information and phase information from the signals transformed by the Fourier transform means. A plurality of channels equalized by using the channel characteristic detecting means and the amplitude information and phase information of each of the subcarriers detected by the channel characteristic detecting means to equalize the output signals of the Fourier transform means. A signal for weighting and synthesizing the output signal of the means and each channel equalization means based on the reception level detected by each reception level detecting means and the amplitude information of each of the subcarriers detected by each channel detecting means. Provided is a diversity receiving circuit including a synthesis means.

【0018】

Further, a plurality of receiving means for receiving each of a plurality of systems of OFDM signals independent of each other for fading, a plurality of receiving level detecting means for detecting the reception level of the received signal obtained by each of the receiving means, and the above-mentioned The coarse carrier frequency error detecting means for detecting the carrier frequency error amount from the received signal obtained by each receiving means, and the carrier frequency error amount estimated by each rough carrier frequency error estimating means. A plurality of first carrier frequency error correction means for correcting the carrier frequency error for the received signal obtained by each receiving means and the output signals of the first carrier frequency error correction means are used for timing synchronization processing. A plurality of timing detection means for detecting necessary timing information and a plurality of timing synchronization processing for the output signal of each of the first carrier frequency error correction means using the timing information detected by each of the timing detection means. The timing synchronization means, a plurality of fine adjustment carrier frequency error detection means for detecting the carrier frequency error amount from the output signal of each timing synchronization means, the carrier frequency error amount detected by each coarse adjustment carrier frequency error detection means, and the carrier frequency error amount. A plurality of adding means for adding the amount of carrier frequency error detected by each fine-tuning carrier frequency error detecting means, and weighted synthesis of the output of each adding means based on the receiving level detected by each receiving level detecting means. By doing so, the carrier frequency error estimating means for estimating the carrier frequency error amount and the carrier frequency error detected by each of the coarse-tuned carrier frequency error detecting means from the carrier frequency error amount estimated by the carrier frequency error estimating means are obtained. A plurality of subtraction means for subtracting each, a plurality of second carrier frequency error correction means for correcting the carrier frequency error of the output signal of each timing synchronization means based on the output of each of the subtraction means, and the second carrier frequency error correction means. Multiple Fourier transform means that Fourier transform each output signal of the carrier frequency error correction means, and the previousA plurality of channel characteristic detection means for detecting the amplitude information and phase information of subcarriers from the signal Fourier transformed by each Fourier transform means, and the amplitude information and phase of each subcarrier detected by each of the channel characteristic detection means. A plurality of channel equalization means that perform equalization processing on the output signal of each Fourier transform means using information, and the reception in which the output signal of each channel equalization means is detected by each reception level detection means. Provided is a diversity receiving circuit including a signal synthesizing means for performing weighted synthesis based on the level and the amplitude information of each of the subcarriers detected by the channel detecting means.

【0019】

The diversity receiving circuit having the above configuration weights and synthesizes the carrier frequency error amount detected in each branch based on the reception level of each branch, and by this weighted synthesis, the detection error of the carrier frequency error amount is reduced. The carrier frequency error amount can be estimated with high accuracy, and by using this as the carrier frequency error correction amount common to each branch, the carrier frequency error correction of each branch can be performed with high accuracy, and the carrier frequency error correction can be performed. By improving the accuracy of, the code error rate characteristic of the diversity receiving circuit can be improved.

【0020】

Further, a coarse carrier frequency error detection circuit and a fine carrier frequency error detection circuit are provided in each branch, the detected carrier frequency errors are added to each branch, and the added carrier frequency error amount is used as the reception level of each branch. By weighting and synthesizing based on the basis, the detection error of the carrier frequency error amount becomes small, and the carrier frequency error amount can be estimated with high accuracy as compared with the case where the carrier frequency error amount is detected independently at each branch. In addition, a timing estimation circuit for synchronizing the timing of the received signal of each branch is provided, and the timing synchronization circuit is operated with the synthesized timing information based on the reception level and the timing signal of the timing detection circuit. There is no timing lag, which improves the accuracy of error detection of carrier frequency errors.

【0021】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 shows and describes a configuration example of a diversity receiving circuit according to the first embodiment of the present invention. Here, in the components shown in FIG. 1, the antenna 1-1, 1-2, the reception level detection circuit 2-1 and 2-2, the reception circuit 3-1 and 3-2, and the timing detection circuit 4-1 and 4 -2, Timing synchronization circuit 5-1,5-2, Carrier frequency error detection circuit 6-1,6-2, Carrier frequency error correction circuit 7-1,7-2, Fourier conversion circuit 8-1,8-2 , The channel characteristic detection circuit 9-1, 9-2, the channel equalization circuit 10-1, 10-2, and the signal synthesis circuit 11 have the same functions as the components of the same name shown in FIG. 13 described above. Therefore, detailed description here will be omitted.

【0022】

The diversity receiving circuit of this embodiment shows a configuration example of two branches of the I system and the II system. However, the present invention is not limited to "2" in each of the embodiments described below, and can be easily applied to a system having a large number of branches. This diversity receiving circuit has a configuration in which a carrier frequency error estimation circuit 12 is added to the conventional circuit configuration shown in FIG. 13, and the carrier frequency error estimation circuit 12 is used as a means for estimating a carrier frequency error with high accuracy. The carrier frequency error detected by the carrier frequency error detection circuits 6-1, 6-2 of each branch is based on the reception level of each branch detected by the reception level detection circuits 2-1, 2-2. Perform weighted composition.

【0023】

That is, the carrier frequency error correction circuits 7-1 and 7-2 have a conventional configuration in which the carrier frequency error is corrected based on the carrier frequency error detected by the carrier frequency error detection circuits 6-1, 6-2, respectively. Is different, and correction is performed with high accuracy based on the carrier frequency error estimated by the carrier frequency error estimation circuit 12.

【0024】

First, the signals received by the antennas 1-1 and 1-2 are input to the receiving circuits 3-1 and 3-2, amplified and subjected to predetermined reception processing, and the timing detection circuits 4-1 and 4- It is output to 2 and the timing synchronization circuits 5-1 and 5-2.

【0025】

From these timing synchronization circuits 5-1 and 5-2 to the carrier frequency error detection circuits 6-1, 6-2 and the carrier frequency error correction circuits 7-1 and 7-2, respectively, the timing synchronization signals (S3) and ( S4) is output. Then, the carrier frequency error detection circuits 6-1, 6-2 detect the carrier frequency error amounts (A1) and (A2) from the respective timing synchronization signals (S3) and (S4), and the carrier frequency error estimation circuit 12 is used. It is output.

【0026】

The carrier frequency error estimation circuit 12 is highly accurate by weighting and synthesizing the carrier frequency error amounts (A1) and (A2) based on the reception levels detected by the reception level detection circuits 2-1 and 2-2. The carrier frequency error amount (B) is estimated, and the estimated carrier frequency error amount (B) is output to the carrier frequency error correction circuits 7-1 and 7-2. The carrier frequency error correction circuits 7-1 and 7-2 perform carrier frequency error correction on the timing synchronization signals (S3) and (S4) based on the given carrier frequency error amount (B), respectively.

【0027】

As described above, in the conventional diversity receiving circuit, the carrier frequency error amount is independently detected and corrected at each branch, so that the detection accuracy of the carrier frequency error amount is lowered due to noise in a low C / N environment. The problem is that the amount of improvement in the code error rate characteristics by the method is also reduced.

【0028】

According to the diversity reception circuit of the present embodiment, the carrier frequency error amount detected in each branch is weighted and synthesized based on the reception level of each branch. Since the detection error of the carrier frequency error amount is reduced by this weighted synthesis, the carrier frequency error amount can be estimated with higher accuracy than when the carrier frequency error amount is detected independently at each branch.

【0029】

By setting the weighted and synthesized carrier frequency error amount as the carrier frequency error correction amount common to each branch, the carrier frequency error correction of each branch can be performed with high accuracy. Therefore, by improving the accuracy of the carrier frequency error correction, it is possible to improve the code error rate characteristic of the diversity receiving circuit.

【0030】

Next, FIG. 2 shows and describes a configuration example of the diversity receiving circuit according to the second embodiment of the present invention. Here, among the constituent parts shown in FIG. 2, the parts having the same functions as the constituent parts shown in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0031】

In this embodiment, as a means for estimating the carrier frequency error with high accuracy, it is detected from the coarse carrier frequency error detection circuit 13-1, 13-2 and the fine carrier frequency error detection circuit 15-1, 15-2 of each branch. Carrier frequency that weights and synthesizes the carrier frequency error amount calculated by the adder circuits 16-1, 16-2 and the adder circuits 16-1, 16-2, which add the carrier frequency errors to be added, based on the reception level of each branch. It includes an error estimation circuit 12 and subtraction circuits 17-1, 17-2 that subtract the outputs of the coarse carrier frequency error detection circuits 13-1, 13-2 from the output of the carrier frequency error estimation circuit 12, respectively. ..

【0032】

With this configuration, the carrier frequency error correction circuits 7-1 and 7-2 are already in the carrier frequency error correction circuits 14-1 and 14-2 from the carrier frequency error amount estimated with high accuracy by the carrier frequency error estimation circuit 12. The correction can be performed with high accuracy based on the value obtained by subtracting the corrected carrier frequency error correction amount.

【0033】

Specifically, first, the signals received by the antennas 1-1 and 1-2 are input to the reception circuits 3-1 and 3-2 and the reception level detection circuits 2-1 and 2-2, respectively. The received signals (S1) and (S2) obtained by the receiving circuits 3-1 and 3-2 are the coarse-tuned carrier frequency error detection circuit 13-1, 13-2 and the carrier frequency error correction circuit 14-1, respectively. Entered in 14-2. The coarse carrier frequency error correction circuits 13-1 and 13-2 detect the carrier frequency error amounts (C1) and (C2) from the received signals (S1) and (S2), respectively, and use the detected carrier frequency error amount as the carrier. Output to frequency error correction circuit 14-1, 14-2, adder circuit 16-1, 16-2 and subtraction circuit 17-1, 17-2, respectively.

【0034】

In the carrier frequency error correction circuits 14-1 and 14-2, the carrier frequency error is corrected for the received signals (S1) and (S2) based on the carrier frequency error amounts (C1) and (C2), respectively, and the carrier frequency is corrected. The error correction signals (S11) and (S12) are output to the timing detection circuits 4-1 and 4-2 and the timing synchronization circuits 5-1 and 5-2, respectively.

【0035】

Then, the timing detection circuits 4-1 and 4-2 detect the timing information required for the timing synchronization processing from the carrier frequency error correction signals (S11) and (S12), and the timing synchronization circuits 5-1 and 5-2 are used, respectively. Output. These timing synchronization circuits 5-1 and 5-2 use the timing information given by the timing detection circuits 4-1 and 4-2, respectively, for the carrier frequency error correction signals (S11) and (S12). Perform timing synchronization processing. The timing synchronization signals (S3) and (S4) output from the timing synchronization circuits 5-1 and 5-2 are the fine adjustment carrier frequency error detection circuit 15-1, 15-2 and the carrier frequency error correction circuit 7-1, respectively. It is output to, 7-2.

【0036】

Next, the fine-tuning carrier frequency error detection circuits 15-1 and 15-2 detect the carrier frequency error amounts (D1) and (D2) of the timing synchronization signals (S3) and (S4), respectively, and add circuits 16 respectively. Output to -1,16-2. Then, in the adder circuits 16-1 and 16-2, the carrier frequency error amounts (C1) and (C2) detected by the coarse carrier frequency error circuit and the carrier frequency error amount detected by the fine carrier frequency error detection circuit ( D1) and (D2) are added, and the addition results (C1) + (D1) and (C2) + (D2) are given to the carrier frequency error estimation circuit 12.

【0037】

Next, the carrier frequency error estimation circuit 12 has a carrier frequency error amount (C1) + (D1), (C2) + (D2) based on the reception level detected by the reception level detection circuits 2-1, 2-2. The carrier frequency error amount is estimated with high accuracy by weighting and synthesizing, and the carrier frequency error estimation result (E) is given to the subtraction circuits 17-1 and 17-2.

【0038】

These subtraction circuits 17-1 and 17-2 subtract the carrier frequency error amounts (C1) and (C2) from the carrier frequency error estimation result (E), respectively, and the subtraction results (E)-(C1). , (E)-(C2) are given to the carrier frequency error correction circuits 7-1 and 7-2. In the carrier frequency error correction circuits 7-1 and 7-2, the carrier frequency error of the timing synchronization signals (S3) and (S4) is based on the subtraction results (E)-(C1) and (E)-(C2), respectively. Make corrections.

【0039】

Since the conventional diversity receiver circuit independently detects and corrects the carrier frequency error amount at each branch, the detection accuracy of the carrier frequency error amount is lowered by noise in a low C / N environment.

【0040】

According to the diversity receiving circuit of this embodiment, it is calculated by adding the carrier frequency error amount detected by the coarse carrier frequency error detecting means of each branch and the carrier frequency error amount detected by the fine carrier frequency error detecting means. The total carrier frequency error amount of each branch is weighted and combined based on the reception level of each branch. By performing this weighted synthesis, the detection error of the carrier frequency error amount becomes small, and the carrier frequency error amount can be estimated with higher accuracy than in the case where the carrier frequency error amount is detected independently at each branch.

【0041】

Since this weighted and synthesized carrier frequency error amount is used as the carrier frequency error correction amount common to each branch, the carrier frequency error detected by the coarse carrier frequency error detection circuit of each branch from the weighted and synthesized carrier frequency error correction amount. By performing carrier frequency error correction for each branch only by the value obtained by subtracting the amount, carrier frequency error correction for each branch can be performed with high accuracy. Therefore, the accuracy of the carrier frequency error correction is improved, and the code error rate characteristic of the diversity receiving circuit is improved.

【0042】

Next, FIG. 3 shows and describes a configuration example of the diversity receiving circuit according to the third embodiment of the present invention. In this embodiment, the residual carrier frequency error correction circuit 18 is provided on the output side of the signal synthesis circuit 11 in the configuration of the first embodiment shown in FIG. 1 described above. Here, among the constituent parts shown in FIG. 3, the parts having the same functions as the constituent parts shown in FIG. 1 are designated by the same reference numerals, and detailed description up to the signal synthesis circuit 11 will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0043】

This diversity receiving circuit calculates the amount of carrier frequency error detected in each branch I, II described in the first embodiment based on the receiving level of each branch detected by the receiving level detection circuits 2-1, 2-2. , A carrier frequency error estimation circuit 12 that performs weighted synthesis to estimate the carrier frequency error with high accuracy is provided, and further, a residual carrier frequency that corrects the residual carrier frequency error of the signal output from the signal synthesis circuit 11 with high accuracy. An error correction circuit 18 is provided.

【0044】

The residual carrier frequency error correction circuit 18 calculates the difference of the carrier frequency error amount corrected from the actual carrier frequency error amount generated by the circuit configuration as the residual carrier frequency error amount, and performs the residual carrier frequency error correction based on this. ing.

【0045】

That is, since the same amount of carrier frequency error correction is performed in each branch based on the carrier frequency error amount estimated by the carrier frequency error estimation circuit 12, the residual carrier frequency error amount of each branch becomes equal. As a result, unlike the conventional circuit configuration in which it is necessary to correct the residual carrier frequency error for each branch, it is possible to correct the residual carrier frequency error of the signal after weighting synthesis output from the signal synthesis circuit 11. .. Based on this weighted synthesis, the residual carrier frequency error correction circuit 18 can detect the residual carrier frequency error of the composite signal (S13) and correct the signal with improved S / N with high accuracy.

【0046】

As described above, the diversity receiving circuit of the present embodiment weights and synthesizes the carrier frequency error amount detected in each branch based on the receiving level of each branch. Since the detection error of the carrier frequency error amount is reduced by this weighted synthesis, the carrier frequency error amount can be estimated with higher accuracy than when the carrier frequency error amount is detected independently at each branch.

【0047】

By setting the weighted and synthesized carrier frequency error amount as the carrier frequency error correction amount common to each branch, the carrier frequency error correction of each branch can be performed with high accuracy. Further, in the diversity receiving circuit according to the present embodiment, since the same amount of carrier frequency error correction is performed in each branch, the amount of residual carrier frequency error in each branch becomes equal.

【0048】

Therefore, it is not necessary to correct the residual carrier frequency error for each branch, and the residual carrier frequency error can be collectively corrected for the signal after the diversity synthesis. Since the S / N is improved in the signal after diversity synthesis, it is possible to correct the residual carrier frequency error with high accuracy. In this embodiment, the code error rate characteristic of the diversity receiving circuit can be improved by improving the accuracy of carrier frequency error detection and the accuracy of residual carrier frequency error correction.

【0049】

Next, FIG. 4 shows and describes a configuration example of the diversity receiving circuit according to the fourth embodiment of the present invention. This embodiment is a configuration example in which the residual carrier frequency error correction circuit 18 described in the third embodiment is provided on the output side of the signal synthesis circuit 11 of the second embodiment described above. Here, the same reference numerals are given to the parts having the same functions as the constituent parts shown in FIGS. 1 and 2, and the detailed description up to the signal synthesis circuit 11 is omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0050】

This diversity receiving circuit is an addition circuit that adds the carrier frequency errors detected from the coarse-tuned carrier frequency error detection circuits 13-1, 13-2 and the fine-tuned carrier frequency error detection circuits 15-1, 15-2 of each branch. 16-1, 16-2, carrier frequency error estimation circuit 12 that weights and synthesizes the carrier frequency error amount calculated by the addition circuits 16-1, 16-2 based on the reception level of each branch, and carrier frequency error estimation circuit. The subtraction circuit 17-1, 17-2 that subtracts the output of the coarse carrier frequency error detection circuit 13-1, 13-2 from the output of 12, and the signal residual carrier frequency error output from the signal synthesis circuit 11 are corrected. The residual carrier frequency error correction circuit 18 is provided.

【0051】

With such a configuration, since the same amount of carrier frequency error correction is performed in each branch based on the carrier frequency error amount estimated by the carrier frequency error estimation circuit 12, the residual carrier frequency error of each branch becomes equal. Therefore, unlike the conventional circuit configuration in which the residual carrier frequency error correction needs to be performed for each branch, the residual carrier frequency error correction circuit is used for the weighted composite signal (S13) output from the signal synthesis circuit 11. Correct the residual carrier frequency error by 18. That is, the residual carrier frequency error is corrected with high accuracy by correcting the residual carrier frequency error of the signal with improved S / N by weighting synthesis.

【0052】

According to the diversity receiving circuit of the fourth embodiment described above, the carrier frequency error detected by the coarse carrier frequency error correction circuit of each branch is first compared to the decrease in the improvement amount of the code error rate characteristic by the prior art. The total carrier frequency error amount of each branch calculated by adding the amount and the carrier frequency error amount detected by the fine adjustment carrier frequency error correction circuit is weighted and synthesized based on the reception level of each branch.

【0053】

Since the detection error of the carrier frequency error amount is reduced by this weighted synthesis, the carrier frequency error amount can be estimated with higher accuracy than when the carrier frequency error amount is detected independently at each branch. In order to make the weighted and synthesized carrier frequency error amount the carrier frequency error correction amount common to each branch, the carrier frequency error detected by the coarse carrier frequency error detecting means of each branch from the weighted carrier frequency error correction amount. By performing carrier frequency error correction for each branch only by the value obtained by subtracting the amount, carrier frequency error correction for each branch can be performed with high accuracy.

【0054】

Further, when correcting the residual carrier frequency error included in the signal after the equalization process, in the conventional configuration in which the carrier frequency error is corrected independently for each branch, the amount of the residual carrier frequency error differs for each branch, so that each branch has a different amount of residual carrier frequency error. It is necessary to correct the residual carrier frequency error.

【0055】

In the diversity receiving circuit of the present embodiment, the same amount of carrier frequency error correction is performed in each branch, so that the amount of residual carrier frequency error in each branch is equal. Therefore, it is not necessary to correct the residual carrier frequency error for each branch, and it is possible to collectively correct the residual carrier frequency error for the signal after diversity synthesis. Since the S / N of the signal after diversity synthesis is improved, the residual carrier frequency error can be corrected with high accuracy. Therefore, the code error rate characteristic of the diversity receiving circuit can be improved by improving the accuracy of carrier frequency error detection and the accuracy of residual carrier frequency error correction.

【0056】

Next, FIG. 5 shows and describes a configuration example of the diversity receiving circuit according to the fifth embodiment of the present invention. In this embodiment, a phase tracking circuit is added to the output side of the configuration of the first embodiment described above. Here, among the constituent parts shown in FIG. 5, the parts having the same functions as the constituent parts shown in FIGS. 1 and 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0057】

This fifth embodiment includes the phase tracking circuit 19 instead of the residual carrier frequency error correction circuit 18 in the configuration of the third embodiment described above.

【0058】

In this diversity receiving circuit, the carrier frequency error estimation circuit 12 weights and synthesizes the carrier frequency error amount detected in each branch based on the reception level of each branch, and estimates the carrier frequency error with high accuracy. Further, since the same amount of carrier frequency error correction is performed in each branch based on the carrier frequency error estimated by the carrier frequency error estimation circuit 12, the residual phase error of each branch due to the residual carrier frequency error becomes equal.

【0059】

Therefore, unlike the conventional circuit configuration in which it is necessary to correct the residual phase error for each branch, the signal synthesis circuit 11 has the reception level and the channel detected by the reception level detection circuits 2-1 and 2-2. Based on the amplitude information of each subcarrier detected by the characteristic detection circuits 9-1, 9-2, the channel equalization signals (S9) and (S10) from each branch are weighted and synthesized to obtain S / N. It is output to the phase tracking circuit 19 as an improved composite signal (S13). Since the output signal of the signal synthesis circuit 11 is one composite signal, the residual phase error of the composite signal can be corrected with high accuracy by the tracking circuit 19.

【0060】

As described above, the diversity receiving circuit of the fifth embodiment weights and synthesizes the carrier frequency error amount detected in each branch based on the receiving level of each branch. Since the detection error of the carrier frequency error amount is reduced by this weighted synthesis, the carrier frequency error amount can be estimated with higher accuracy than when the carrier frequency error amount is detected independently at each branch. By setting the weighted and synthesized carrier frequency error amount as the carrier frequency error correction amount common to each branch, the carrier frequency error correction of each branch can be performed with high accuracy.

【0061】

As described above, when correcting the residual phase error caused by the residual carrier frequency error included in the signal after the equalization process, in the conventional configuration in which the residual phase error is corrected independently for each branch, the residual carrier frequency is corrected for each branch. Since the amount of error is different, it is necessary to correct the residual phase error for each branch. In this conventional configuration, the accuracy of residual phase error correction of each branch is reduced by noise in a low C / N environment. Therefore, the amount of improvement in the bit error rate characteristic due to diversity has decreased.

【0062】

On the other hand, in the diversity receiving circuit according to the present embodiment, the same amount of carrier frequency error correction is performed in each branch, so that the amount of residual carrier frequency error in each branch is equal. That is, the amount of residual phase error caused by the residual carrier frequency error becomes equal.

【0063】

Therefore, it is not necessary to correct the residual phase error for each branch, and it is possible to collectively correct the residual phase difference for the signal after diversity synthesis. Since the S / N is improved in the signal after diversity synthesis, the residual phase error can be corrected with high accuracy. From the above, according to the present embodiment, the code error rate characteristic of the diversity receiving circuit can be improved by improving the accuracy of carrier frequency error detection and the accuracy of residual phase error correction.

【0064】

Next, FIG. 6 shows and describes a configuration example of the diversity receiving circuit according to the sixth embodiment of the present invention. In this embodiment, a phase tracking circuit is added to the output side of the signal synthesis circuit 11 in the configuration of the second embodiment described above. Here, among the constituent parts shown in FIG. 6, the parts having the same functions as the constituent parts shown in FIGS. 1 and 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0065】

This embodiment is a configuration example in which the phase tracking circuit 19 described in the fifth embodiment is provided on the output side of the signal synthesis circuit 11 of the second embodiment described above. Here, the same reference numerals are given to the parts having the same functions as the constituent parts shown in FIGS. 1 and 2, and the detailed description up to the signal synthesis circuit 11 is omitted. The present embodiment will be described with reference to a configuration example of the number of branches 2 as in the first embodiment described above, but the present embodiment is not limited to the number of branches.

【0066】

The present embodiment includes the carrier frequency error estimation circuit 12 that estimates the carrier frequency error with high accuracy as described above, and as a means for correcting the residual phase error with higher accuracy, the signal output from the signal synthesis circuit 11 The configuration includes a phase tracking circuit 19 that corrects the residual phase error.

【0067】

The signal synthesis circuit 11 detects the channel equalization signals (S9) and (S10) by the reception level and channel characteristic detection circuits 9-1, 9-2 detected by the reception level detection circuits 2-1 and 2-2. Weighted synthesis is performed based on the amplitude information of each subcarrier, and the synthesized composite signal (S13) is given to the phase tracking circuit 19.

【0068】

Therefore, unlike the conventional configuration in which the residual phase error correction needs to be performed for each branch, the residual phase error correction can be performed with high accuracy by the signal phase tracking circuit 19 after the weighted synthesis output from the signal synthesis circuit 11. it can.

【0069】

Therefore, as a measure to prevent a decrease in the amount of improvement in the code error rate characteristic by the diversity receiving circuit, which has been a problem in the prior art, according to the diversity receiving circuit of the sixth embodiment, first, the coarse carrier frequency error correction of each branch is corrected. The total of each branch calculated by adding the carrier frequency error amount detected by circuits 13-1, 13-2 and the carrier frequency error amount detected by fine adjustment carrier frequency error correction circuits 15-1, 15-2. The carrier frequency error amount is weighted and combined based on the reception level of each branch.

【0070】

Next, since the detection error of the carrier frequency error amount is reduced by this weighted synthesis, the carrier frequency error amount can be estimated with higher accuracy than in the case where the carrier frequency error amount is detected independently at each branch.

【0071】

In order to use this weighted combined carrier frequency error amount as the carrier frequency error correction amount common to each branch, the coarse carrier frequency error detection circuit 13-1, 13- of each branch is used from the weighted carrier frequency error correction amount. By performing carrier frequency error correction for each branch based on the value obtained by subtracting the carrier frequency error amount detected in 2, carrier frequency error correction for each branch can be performed with high accuracy.

【0072】

Further, when correcting the residual phase error caused by the residual carrier frequency error included in the signal after the equalization process, in the conventional configuration in which the residual phase error is corrected independently for each branch, the amount of the residual carrier frequency error is different for each branch. Since they are different, it is necessary to perform residual phase error correction for each, and in such a conventional configuration, the accuracy of residual phase error correction of each branch is lowered by noise in a low C / N environment.

【0073】

On the other hand, in the diversity receiving circuit of the present embodiment, since the same amount of carrier frequency error correction is performed in each branch, the amount of residual carrier frequency error in each branch is equal. That is, the amount of residual phase error caused by the residual carrier frequency error becomes equal. Therefore, it is not necessary to correct the residual phase error for each branch, and it is possible to collectively correct the residual phase error for the signal after diversity synthesis.

【0074】

In addition to the effects obtained by the second embodiment described above, in the present embodiment, since the S / N is improved in the signal after the diversity synthesis, the residual phase error can be corrected with high accuracy, and the carrier can be corrected. By improving the accuracy of frequency error detection and the accuracy of residual phase error correction, it is possible to improve the code error rate characteristic of the diversity receiving circuit.

【0075】

Next, FIG. 7 shows and describes a configuration example of the diversity receiving circuit according to the seventh embodiment of the present invention.

【0076】

This embodiment is illustrated by applying a configuration example of the carrier frequency error estimation circuit 12 in the configuration of the first embodiment, the third embodiment, or the fifth embodiment described above to the configuration shown in FIG. In the constituent parts shown in FIG. 7, the parts having the same functions as the constituent parts shown in FIGS. 1 and 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0077】

The carrier frequency error estimation circuit 12 includes a weighting coefficient calculation circuit 20 that calculates the weighting coefficients (W1) and (W2) of each branch from the receiving levels output from the reception level detection circuits 2-1 and 2-2, and the weighting coefficient calculation circuit 20. Multiplication circuit 21-1, 21-2 that multiplies the weighting factors (W1), (W2) of each branch and the carrier frequency error amounts (A1), (A2) from the carrier frequency error detection circuits 6-1, 6-2. And the addition circuit 22 that adds these multiplication results and outputs the addition result to the carrier frequency error correction circuits 7-1 and 7-2.

【0078】

First, the reception level output from the reception level detection circuits 2-1 and 2-2 is input to the weighting coefficient calculation circuit 20. The weighting coefficient calculation circuit 20 calculates the weighting coefficients (W1) and (W2) of each branch based on the reception level of each branch, and outputs them to the multiplication circuits 21-1 and 21-2, respectively.

【0079】

On the other hand, the carrier frequency error detection circuits 6-1, 6-2 detect the carrier frequency error amounts (A1) and (A2) from the timing synchronization signals (S3) and (S4), respectively, and the carrier frequency error amount (A1). , (A2) are output to the multiplication circuits 21-1, 21-2, respectively. These multiplication circuits 21-1, 21-2 multiply the carrier frequency error amounts (A1) and (A2) by the weighting coefficients (W1) and (W2), respectively, and the multiplication result (A1) × (W1). , (A2) × (W2) is output to the adder circuit 22. The addition circuit 22 adds the given (A1) × (W1) and (A2) × (W2), and corrects the addition result (A1) × (W1) + (A2) × (W2) for carrier frequency error. Output to circuits 7-1 and 7-2.

【0080】

As for the action and effect of this embodiment, the same effect as that of the third embodiment described above can be obtained.

【0081】

Next, FIG. 8 shows and describes a configuration example of the diversity receiving circuit according to the eighth embodiment of the present invention. This embodiment is illustrated by applying a configuration example of the carrier frequency error estimation circuit 12 in the configuration of the second embodiment, the fourth embodiment, or the sixth embodiment described above to the configuration shown in FIG. Is what you are doing. Here, among the constituent parts shown in FIG. 8, the parts having the same functions as the constituent parts shown in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0082】

The carrier frequency error estimation circuit 12 includes a weighting coefficient calculation circuit 20 that calculates the weighting coefficients (W1) and (W2) of each branch from the receiving levels output from the reception level detection circuits 2-1 and 2-2, and the weighting coefficient calculation circuit 20. Carrier frequency error amount (C1), (C2) of coarse carrier frequency error detection circuits 13-1, 13-2 and carrier frequency error amount (D1), (D1), of fine carrier frequency error detection circuits 15-1, 15-2. Multiplication circuits 21-2 and 21-2 that multiply the sum of D2) and the weighting coefficients (W1) and (W2) of each branch, and the carrier frequency error correction circuit 7- that adds the multiplication results. It is composed of an addition circuit 22 that outputs the addition result to 1 and 7-2.

【0083】

First, the reception level output from the reception level detection circuits 2-1 and 2-2 is input to the weighting coefficient calculation circuit 20. The weighting coefficient calculation circuit 20 calculates the weighting coefficients (W1) and (W2) of each branch based on the reception level of each branch I and II, and outputs them to the multiplication circuits 21-2 and 21-2, respectively. On the other hand, the adder circuits 16-1 and 16-2 are the carrier frequency error amounts (C1) and (C2) of the coarse carrier frequency error detection circuits 13-1, 13-2 and the fine carrier frequency error detection circuits 15-1, 16-2. The carrier frequency error amounts (D1) and (D2) of 15-2 are added, and the addition results (C1) + (D1) and (C2) + (D2) are multiplied by the multiplication circuits 21-1, 21-2, respectively. Output to.

【0084】

This multiplication circuit 21-1, 21-2 multiplies the carrier frequency error amount (C1) + (D1), (C2) + (D2) by the weighting factors (W1) and (W2), respectively, and the multiplication result { (C1) + (D1)} × (W1), {(C2) + (D2)} × (W2) are output to the adder circuit 22. The addition circuit 22 adds each of the input multiplication values {(C1) + (D1)} × (W1) and {(C2) + (D2)} × (W2), and the addition result {(C1) ) + (D1)} × (W1) + {(C2) + (D2)} × (W2) to carrier frequency error correction circuits 7-1 and 7-2 via subtraction circuits 17-1, 17-2 And output. The effects of the present embodiment described above can be the same as those of the fourth embodiment described above.

【0085】

Next, FIG. 9 shows and describes a configuration example of the diversity receiving circuit according to the ninth embodiment of the present invention. This embodiment is illustrated by applying a configuration example of the signal synthesis circuit 11 in the configurations of the first to eighth embodiments described above to the configuration shown in FIG. Here, among the constituent parts shown in FIG. 9, the parts having the same functions as the constituent parts shown in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0086】

This signal synthesis circuit 11 is each branch from the reception level output from the reception level detection circuits 2-1, 2-2 and the amplitude information of each subcarrier detected by the channel characteristic detection circuits 9-1, 9-2. The weight coefficient calculation circuit 23 that calculates the weight coefficients (W3) and (W4) of, and the multiplication by multiplying the weight coefficients (W3) and (W4) of each branch by the channel equalization signals (S9) and (S10). It is composed of circuits 24-1 and 24-2, and an addition circuit 25 that adds the multiplication results and outputs the addition result to the residual carrier frequency error correction circuit 18.

【0087】

First, the reception level output from the reception level detection circuits 2-1, 2-2 and the amplitude information of each subcarrier detected by the channel characteristic detection circuits 9-1, 9-2 are input to the weighting coefficient calculation circuit 23. Will be done. In this weighting coefficient calculation circuit 23, the weighting coefficients (W3) and (W4) for each subcarrier of each branch are calculated based on the reception level of each branch and the amplitude information of each subcarrier, and the multiplication circuits 24-2, respectively. Output to 24-2. On the other hand, the channel equalization circuits 10-1, 10-2 output the channel equalization signals (S9) and (S10) to the multiplication circuits 24-1, 24-2, respectively.

【0088】

Then, the multiplication circuits 24-1 and 24-2 multiply the channel equalization signals (S9) and (S10) by the weighting coefficients (W3) and (W4), respectively, and the multiplication result (S9) × (W3), (S10) × (W4) is output to the adder circuit 25. The adder circuit 25 adds the given (S9) × (W3) and (S10) × (W4), and adds the addition result (S9) × (W3) + (S10) × (W4) to the residual carrier frequency error. It is given to the correction circuit 18.

【0089】

Therefore, according to the present embodiment, the channel equalization signals (S9) and (S10) are weighted and synthesized based on the reception level and the amplitude information of each subcarrier, and the combined signal (S13) with improved S / N is obtained. To generate.

【0090】

Next, FIG. 10 shows and describes a configuration example of the diversity receiving circuit according to the tenth embodiment of the present invention. In this embodiment, the timing estimation circuit 26 is added to the configurations of the first to sixth embodiments described above, and the timing estimation circuit 26 is applied to the third embodiment (FIG. 3) and illustrated. is there. Here, among the constituent parts shown in FIG. 10, the parts having the same functions as the constituent parts shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0091】

In each of the above-described embodiments, the timing information detected by the timing detection circuits 4-1 and 4-2 is output to the timing synchronization circuit of each branch. The timing detection circuits 4-1 and 4-2 cause different errors in the timing information detected due to noise and fading, respectively. Therefore, in the present embodiment, a timing estimation circuit 26 is provided to suppress the occurrence of this deviation.

【0092】

This timing estimation circuit 26 is based on the reception level output from the reception level detection circuits 2-1 and 2-2 of each branch, and each timing information detected by the timing detection circuits 4-1 and 4-2 of each branch. Is weighted and synthesized, and the synthesized timing information (F) is output to the timing synchronization circuits 27-1 and 27-2, respectively.

【0093】

According to the present embodiment, the timing synchronization circuits 27-1 and 27-2 operate together according to the weighted and synthesized timing information (F), so that the timing deviation between the branches is eliminated and the signal is obtained at a highly accurate timing. Therefore, the carrier frequency error is estimated, and the correction can be performed with high accuracy.

【0094】

Next, FIG. 11 shows and describes a configuration example of the diversity receiving circuit according to the eleventh embodiment of the present invention. In the present embodiment, the selectors 29-1 and 29-2 are either (S14-1) and (S14-3) or (S14-2) and (S14-4), respectively, depending on the reception level. It has a function to select the combination, and improves the timing accuracy. In this configuration, in the configurations of the carrier frequency error correction circuit 7-1,7-2 and the carrier frequency error detection circuits 6-1,6-2 and later, the configurations of the first to sixth embodiments described above are configured. This embodiment is described as an example of applying this to the third embodiment (FIG. 3). Parts having the same functions as the constituent parts shown in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0095】

In this diversity receiving circuit, the received signal (S1) output from the receiving circuit 3-1 is input to the timing detection circuit 4-1 and the timing synchronization circuits 28-1 and 28-2, respectively. The received signal (S2) output from the receiving circuit 3-2 is input to the timing detection circuit 4-2 and the timing synchronization circuits 28-3 and 28-4, respectively.

【0096】

The timing detection circuits 4-1 and 4-2 detect the timing information (G1) and (G2) required for the synchronization processing from the input received signals (S1) and (S2), respectively.

【0097】

This timing information (G1) is output to the timing synchronization circuit 28-1 and the timing synchronization circuit 28-3 in the other branch, and the timing information (G2) is in the timing synchronization circuit 28-4 and the other branch. Output to the timing synchronization circuit 28-2.

【0098】

These timing synchronization circuits 28-1, 28-2, 28-3, 28-4 each perform timing synchronization processing based on the given timing information, and each of them performs timing synchronization processing (S14-). 1), (S14-2), (S14-3), (S14-4) are output.

【0099】

Of these, the timing synchronization signals (S14-1) and (S14-2) are output to the selector 29-1, and the timing synchronization signals (S14-3) and (S14-4) are input to the selector 29-2. ..

【0100】

On the other hand, the reception level output from the reception level detection circuits 2-1, 2-2 is input to the reception level comparison circuit 30. The reception level comparison circuit 30 compares the input reception levels and outputs an instruction to select the branch side having the maximum reception level to the selectors 29-1 and 29-2 as branch information. The selectors 29-1 and 29-2 operate to select the same branch side based on the given branch information, select the timing synchronization signal, and use the timing signal as the carrier frequency error detection circuit 6-1. Output to 6-2 and carrier frequency error correction circuits 7-1 and 7-2.

【0101】

As a result, a signal obtained by performing timing synchronization processing with accurate timing information can be obtained.

【0102】

Next, FIG. 12 shows and describes a configuration example of the diversity receiving circuit according to the twelfth embodiment of the present invention. This embodiment is configured by adding a selection circuit 31 that performs the same estimation process in place of the carrier frequency error estimation circuit 12 in the first to sixth embodiments described above. The configuration shown in FIG. 12 is an example in which a selection circuit 31 that can be realized by a simple logic circuit configuration is arranged in place of the carrier frequency error estimation circuit 12 in the configuration of the eighth embodiment, for example. In the constituent parts shown in FIG. 12, parts having the same functions as those shown in FIG. 8 are designated by the same reference numerals, and detailed description thereof will be omitted. The present embodiment will be described with reference to a configuration example in which the number of branches is 2, but the present embodiment is not limited to the number of branches.

【0103】

This selection circuit 31 is an addition result (C1 + D1) indicating the reception level output from the reception level detection circuits 2-1, 2-2 and the carrier frequency error output from the addition circuits 16-1, 16-2. , (C2 + D2) is entered.

【0104】

In this selection circuit 31, one of the branches is selected according to the magnitude of the reception level, and the addition result output from the addition circuit on the selected side is output to the subtraction circuits 17-1 and 17-2. Then, the subtraction circuits 17-1 and 17-2 perform a predetermined subtraction process, and the subtraction circuits 17-1, 7-2 are output to the carrier frequency error correction circuits 7-1 and 7-2, respectively.

【0105】

As a result, by selecting the branch side with a high reception level, it is possible to perform correction using a more accurate carrier frequency error amount.

【0106】

Weighted synthesis is performed based on the reception level of the switch, and by this weighted synthesis, the detection error of the carrier frequency error amount can be reduced and the carrier frequency error amount can be estimated with high accuracy. By setting the correction amount, the carrier frequency error correction of each branch can be performed with high accuracy, and the code error rate characteristic of the diversity receiving circuit can be improved by improving the accuracy of the carrier frequency error correction.

【0107】

[Effect of the invention]

As described in detail above, according to the present invention, the carrier frequency error amount detection accuracy of the carrier frequency error detection circuit is improved by weighting and synthesizing the carrier frequency error amount detected from each branch based on the reception level of each branch. , A diversity receiving circuit that improves the code error rate can be provided.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 1st Embodiment.

[Figure 2]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 2nd Embodiment.

[Fig. 3]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 3rd Embodiment.

[Fig. 4]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 4th Embodiment.

[Fig. 5]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 5th Embodiment.

[Fig. 6]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 6th Embodiment.

[Fig. 7]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 7th Embodiment.

[Fig. 8]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 8th Embodiment.

[Fig. 9]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 9th Embodiment.

[Fig. 10]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on tenth embodiment.

[Fig. 11]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on eleventh embodiment.

[Fig. 12]

It is a figure which shows the structural example of the diversity receiving circuit which concerns on 12th Embodiment.

[Fig. 13]

It is a figure which shows the configuration example of the diversity receiving circuit suitable for the conventional OFDM modulation / demodulation system.

[Explanation of symbols]

1-1, 1-2 ... Antenna 2-1, 2-2 ... Reception level detection circuit 3-1,3-2 ... Receive circuit 4-1, 4-2 ... Timing detection circuit 5-1,5-2 ... Timing synchronization circuit 6-1, 6-2 ... Carrier frequency error detection circuit 7-1,7-2 ... Carrier frequency error correction circuit 8-1,8-2 ... Fourier transform circuit 9-1, 9-2 ... Channel characteristic detection circuit 10-1,10-2 ... Channel equalization circuit 11 ... Signal synthesis circuit 12 ... Carrier frequency error estimation circuit