Transmission system having space diversity, time diversity and frequency diversity

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a terrestrial transmission system for digital signals conforming to the MPEG2-TS and DVB-T standards.

【0002】

[Conventional technology]

Transmission systems of the above types are implemented to solve the shortcomings caused by Gaussian noise, numerous propagation paths between transmitters and receivers, interference between adjacent channels, and the like.

【0003】

[Problems to be Solved by the Invention]

However, these systems are unable to provide good transmission performance for transmitters and receivers that are mobile or in poor propagation environments.

【0004】

[Means for solving problems]

Accordingly, it is an object of the present invention to provide a terrestrial transmission system for digital signals that allows transmission between mobile transmitters and / or receivers. This system complies with the MPEG2-TS standard and is better suited for digital signals that carry synchronization information according to the TS101191 standard.

【0005】

For the above, the present invention relates to a system having spatial, time, and / or frequency diversity, and the receiving side of the digital signal selects an error-free digital signal or selects an error-free digital signal. If this is not possible, means is provided to select the digital signal corresponding to the transmission with the lowest error rate.

【0006】

The present invention further relates to a system that transmits a digital signal that carries synchronization information by terrestrial waves in accordance with the MPEG2-TS standard and the DVB-T standard and in accordance with the TS101191 standard, and at least N different frequencies (F1 to F1 to N transmitters or transmission channels, each operating on FN) and receiving the same digital signal to transmit in packet format in compliance with the MPEG2-TS standard, and N frequencies (F1 to N), respectively. N receivers or receive channels that operate and each supply a series of packets in compliance with the MPEG2-TS standard, and N error detectors that detect errors in the packets supplied by each receiver, and each Select N synchronizers that synchronize the packets supplied by the receiver and one of the N available packets that contains no errors, or, if that is not possible, the lowest error rate. It is characterized by including a selection device that selects one corresponding packet.

【0007】

The N transmitting antennas can be located geographically separated, and the P receiving antennas can be similarly geographically separated, thereby providing space. Diversity is brought.

【0008】

To provide time diversity, each transmitting channel includes a shift device that shifts packets from one channel in time with respect to another, and each receiving channel rearranges packets received on each channel in time. Includes synchronous device.

【0009】

Time shift and time synchronization of packets are obtained, for example, by a FIFO (first in, first out) type buffer memory. The buffer memory causes a calibrated delay on the transmitting side and aligns the beginning of the megaframe on each receiving channel on the receiving side, regardless of the delay caused by the transmitting side's time diversity.

【0010】

To recognize the beginning of a megaframe, the system sets the 9th bit of the first octet (bytes) of the first packet of the megaframe to be logical level 1.

【0011】

The selection from the available packets in the output of the buffer memory sets the ninth bit of the last octet of the packet preceding any packet containing the error to logic level 1 and thus contains the above error. Packets are not selected for reading.

【0012】

If all available packets contain errors at the same time, the present invention has means of selecting the packet corresponding to the receiving channel with the lowest error rate.

【0013】

BEST MODE FOR CARRYING OUT THE INVENTION

Other features and advantages of the present invention will become apparent by referring to the accompanying drawings and reading the description of the examples below.

【0014】

In the present invention, the frequency diversity is limited to N = 2 frequencies (F1 and F2), the time diversity is limited to the delay value of N = 2 (T1 and T2), and the spatial diversity is N = 2. A specific case limited to the transmitting antenna and the receiving antenna of P = 3 will be described.

【0015】

The digital signal 10 transmitted by the terrestrial transmission network conforms to the MPEG2-TS standard and contains synchronization information conforming to the TS101191 standard.

【0016】

In the present invention, these digital signals are supplied to the two transmission channels 12 and 14 at the same time. Each transmitter 12 (or 14) has a delay circuit 12D (or 14D) that results in a delay T1 (or T2), a COFDM (Orthogonal Frequency Division Multiplexing) modulator 12M (or 14M), and a center frequency of F1 (or 14M). It includes a frequency change and amplifier circuit 12C (or 14C), which is F2), and a transmitting antenna 12A (or 14A) that radiates toward the receiving antenna of the transmission network. Antennas 12A and 14A are placed in geographically different locations to create the first spatial diversity.

【0017】

The receiving antennas (S1, S2 and S3) having P = 3 receive signals from the transmitting antennas 12A and 14A, respectively, and the received signals are combined by the combinational circuit 16. The combined signal is supplied to the separation circuit 18, and the signal is distributed to the receivers 22 and 24.

【0018】

Each receiver 22 (or 24) has a receiver 22R (or 24R) that receives a COFDM signal and generates a digital signal at the output, an error detection circuit 22E (or 24E), and a synchronization circuit 22S (or 24S). ) And.

【0019】

The digital signals at the output of the synchronous circuit 22S or 24S are synchronized with each other, i.e. the delays T1, T2 and any other deviations are zeroed and fed to the selection circuit 20 to select the error-free digital signal coming from the receive channel. Or, if the above is not possible, select the digital signal coming from the receiving channel with the lowest error rate. The error rate for each channel is measured by the receiver 22R (or 24R). At the output of the selection circuit 20, a digital signal 26 conforming to the MPEG2-TS standard corresponding to the digital signal 10 is supplied at the input of the transmission channel.

【0020】

Delays T1 and T2 are introduced into digital signals conforming to the MPEG2-TS standard, for example by one buffer memory in each transmission channel. Each buffer memory has a capacity capable of containing, for example, M packets conforming to the MPEG2-TS standard, and each packet contains 188 to 204 octets (bytes).

【0021】

Generally, if there are N transmit channels, there are N delays (T1, ..., Ti, ..., TN), where Ti is the delay of the i-th channel.

【0022】

Each memory operates in a FIFO (first in, first out) type, so the first stored packet is read first with a delay T1 (or T2). The time delay T1 can be zero, i.e. the buffer memory can not be used, while the time delay T2 should be equal to the time of at least 25 packets. If a third transmit channel is used, the delay T3 should be at least equal to 50 packets for the first channel and 25 packets for the second channel.

【0023】

The delay value of 25 packets between two consecutive transmission channels is the maximum depth of interleaving that occurs when the system is operating in the so-called (8K, 64QAM) mode of the MPEG2-TS standard. Is obtained in consideration of.

【0024】

For different modes, the delay between the two transmit channels can be 25 packets or less.

【0025】

On the receiving side, the time lag due to delays T1, T2 and all other time delays allowed or failed to select error-free digital signals on one receiving channel or another receiving channel. In some cases, the digital signal of the receiving channel with the lowest error rate must be resynchronized so that it can be selected.

【0026】

Synchronization is obtained by a buffer memory operating in a FIFO type in each receiving device.

【0027】

Synchronization takes advantage of the features of the TS101191 standard, which determines the configuration of a frame called a megaframe containing N packets, where the number of packets N depends on the mode used, for example 64QAM or 16QAM mode. Megaframes include megaframe initialization packets (MIPs).

【0028】

A MIP packet has a certain number of information items, including the number of packets between MIP packets and a 16-bit "pointer" indicating the beginning of a subsequent megaframe (see Figure 3).

【0029】

Each packet further contains a carrier error indicator indicating the presence of at least one uncorrected bit error when in logical state 1. Using these two information items, namely pointers and carry error markers, the present invention is advantageously practiced.

【0030】

As shown in FIG. 2, the MPEG2-TS packets of each receiving channel are supplied to the corresponding error detection circuits 22E or 24E. This circuit has the function of analyzing the error indicator of each packet and setting the 9th bit D9 of the last octet of all packets preceding the packet containing the error to 1. By shifting the error information forward, the ninth bit D9 of the last octet of the packet can be analyzed to determine if the subsequent packet is erroneous.

【0031】

To cause such a shift, the error detection circuit 22E or 24E includes a register that stores several consecutive octets.

【0032】

As explained above, except for the first octet of the first packet of the megaframe, the ninth bit of the octet other than the last octet of the packet is not considered and can therefore take any value, 0 or 1. Clarify that.

【0033】

The packets supplied by the error detection circuits 22E and 24E are supplied to the FIFO type memory 22M or 24M and the synchronization circuits 22S and 24S including the detection / write circuits 22A or 24A, respectively.

【0034】

Each detection / write circuit 22A or 24A has the function of detecting a MIP packet and reading a pointer indicating the beginning of a subsequent megaframe. The information from the pointer allows the circuit to place the beginning of a subsequent megaframe, thus setting the ninth bit D9 to 1 in the first octet of the first packet of the megaframe. ..

【0035】

When the above arrangement and setting are achieved, the first packet of the megaframe is stored in the memory 22M or 24M (signal WR), and the subsequent packets are stored. When both memories M22 or M24 are half full, a sign indicates that (HF signal), the other half of the memory is read (signal RD), and the selection of packets held by selection circuit 20 precedes. It is performed as a function of the error bit of the last octet of the packet to be error-free, and the packet without error is selected.

【0036】

However, this read of memory 22M or 24M will not occur if the 9th bit of the first octet of each memory megaframe is not set as 1, which means that the two megaframes will not be synchronized. To do. In this case, the detection / write circuit 22A or 24A is restarted to detect the beginning of a new megaframe for each channel. In this case, the selection circuit 20 sends a reset signal (RAZ) to reset to zero to the two detection / write circuits 22A and 24A to start searching for subsequent megaframes. Since writing to the memories 22M and 24M does not start in the same frame, one of the two memories 22M and 24M may become full. In this case, the full memory supplies a labeled FF signal that restarts the detection / write circuit 22A or 24A that detects the megaframe.

【0037】

The two packets that can be read into memory 22M and 24M may be erroneous. In this case, the selection circuit 20 selects the packet from the channel with the lowest error rate. Information about error rates TE1 and TE2 is provided by receivers 22R and 24R, respectively.

【0038】

The present invention has been described by a particular embodiment having N = 2 transmitters and receivers, 2 transmitting antennas in geographically different locations and N = 3 receiving antennas. However, the present invention is applicable to systems that include multiple transmitters and receivers of different frequencies.

【0039】

Further, although it is explained that the time lag on the transmitting side is obtained by using a FIFO type buffer memory, other devices can be used for the same purpose.

【0040】

The same is true for the temporal rearrangement or synchronization obtained by the FIFO type buffer memory on the receiving side.

【0041】

Adding the ninth bit D9 to the packet's octet to indicate whether the subsequent packet contains an erroneous value in the last octet of the packet, or to indicate the beginning of a megaframe in the first octet of the packet. The process containing the above can also be replaced by another process without departing from the scope of the present invention.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the terrestrial transmission system of the digital signal by this invention.

[Figure 2]

It is a block diagram which shows the mechanism which selects the received digital signal as a function of the measured error rate.

[Fig. 3]

It is a figure which shows the series of three megaframes containing each MIP packet.

[Explanation of symbols]

10, 26 digital signals 12, 14 transmission channels 12D, 14D delay circuit 12M, 14M COFDM modulator 12C, 14C frequency change and amplifier circuit 12A, 14A transmitting antenna F1, F2 center frequency S1, S2, S3 receiving antenna 20 selection circuit 22, 24 receive channels 22R, 24R receiver 22E, 24E error detection circuit 22S, 24S synchronous circuit 22A, 24A detection / write circuit 22M, 24M FIFO type memory