Frequency synthesizing device, communication equipment, frequency modulation device and frequency modulation method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention uses a phase-locked loop circuit (hereinafter referred to as a PLL circuit) to control a fractional part (also referred to as a fractional part) of the number of divisions input to the variable frequency divider in the PLL circuit. The present invention relates to a frequency synthesizer device provided with a control circuit, a communication device and a frequency modulation device provided with the above-mentioned frequency synthesizer device, respectively, and a frequency modulation method.

【0002】

[Conventional technology]

Generally, the output frequency of a frequency synthesizer device using a PLL circuit is expressed by the quotient obtained by dividing the reference signal frequency by the number of divisions set in the variable frequency divider. Since a normal variable frequency divider can only set the number of divisions of integer data, the output frequency is an integral multiple of the reference signal frequency and cannot be set in units finer than the reference signal frequency. Therefore, when it is necessary to set the output frequency at fine frequency intervals, it is necessary to lower the reference signal frequency. However, when the reference signal frequency is lowered, the number of divisions of the variable frequency divider increases, and the noise appearing in the output signal also increases as the number of divisions increases. Also, since the response bandwidth of the PLL circuit cannot be wider than the reference signal frequency, the response speed of the loop in the PLL circuit becomes slower, and the frequency switching cycle becomes longer.

【0003】

As a method for solving such a problem, a method of obtaining a frequency division with an accuracy after the decimal point by using an ordinary variable frequency divider is known. This is a method that realizes the number of divisions with accuracy below the decimal point as average data by periodically changing the number of divisions. Delta-sigma modulation circuit (Δ-Σ modulation circuit; sigma-delta modulation circuit (Σ-)) It is also called a delta-sigma circuit).

【0004】

FIG. 19 is a block diagram showing a circuit configuration of a frequency synthesizer device of the prior art, and this frequency synthesizer device is a frequency synthesizer device that realizes a frequency division with an accuracy after the decimal point. As shown in FIG. 19, this frequency synthesizer device includes a voltage controlled oscillator (hereinafter referred to as VCO) 1, a variable frequency divider 2, a phase comparator 3, and a low frequency pass filter 4 which is a loop filter. It is configured to be connected in a loop, and further includes a fractional control circuit 80 and an adder 6. Here, the variable frequency divider 2 divides the output signal from the VCO 1 according to the input divided frequency data, and outputs the divided signal to the phase comparator 3. The phase comparator 3 compares the phase of the input reference signal with the output signal from the variable frequency divider 2, and outputs a signal indicating the phase comparison result to the VCO1 via the low frequency pass filter 4. As a result, the PLL circuit is feedback-controlled so that the output frequency of VCO1 becomes stable.

【0005】

In FIG. 19, the decimal part control circuit 80 includes an adder 81 and a delay circuit 82. The adder 81 adds the data of the decimal part F input from the external device and the output data from the delay circuit 82, and outputs the data of the addition result to the delay circuit 82. The delay circuit 82 is a latch circuit that operates using the output signal from the variable divider 2 as a clock. The carry signal (which shows the data of the controlled decimal part F) which is an output signal indicating the overflow of the adder 81 and the data of the integer part M input from the external device are added by the adder 6. The data of the addition result is input to the variable frequency divider 2 as the data of the number of divisions and set.

【0006】

In the frequency synthesizer device of FIG. 19 configured as described above, when the decimal part is F, the data of the addition output signal from the adder 81 increases by the decimal part F for each clock. When the adder 81 overflows with data L, it overflows F times during this period with L clocks as a cycle, and a carry signal is generated.

【0007】

FIG. 20 is a block diagram represented by z-transform showing a detailed configuration of the decimal part control circuit 80 of FIG. In Figure 20, z^-1Represents a delay of 1 clock. The output data Y from the decimal part control circuit 80 is expressed by the following equation.

【0008】

[Number 1]

Y = F / L + (1-z^-1) Q [0009]

The operation of the decimal part control circuit 80 is equivalent to the operation of the first-order delta-sigma modulation circuit, and the generation of the carry signal is equivalent to the quantization in the quantization step L. In FIG. 20, the decimal part control circuit 80 includes an adder 91, a delay circuit 92, a quantizer 93, a multiplier 94, and a subtractor 95. Here, the adder 91 corresponds to the adder 81 of FIG. 19, and the delay circuit 92 corresponds to the delay circuit 82 of FIG. The subtractor 95 subtracts the output data from the multiplier 94 from the data of the decimal part F input from the external device, and outputs the subtraction result data to the adder 91. The adder 91 adds the output signal from the delay circuit 92 and the output signal from the subtractor 95, and outputs the addition result to the delay circuit 92 and the quantizer 93. The quantizer 93 quantizes the output signal from the adder 91 in the quantization step L and outputs the signal. The output signal from the quantization device 93 is multiplied by the quantization step L by the multiplier 94, and the signal of the multiplication result is output to the subtractor 95.

【0010】

FIG. 21 is a timing chart showing the operation of the frequency synthesizer device of FIG. 19, and FIG. 21 (a) is a timing chart showing the temporal change of the number of frequency dividers input to the variable frequency divider 2. 21 (b) is a timing chart showing the temporal change of the control voltage to VCO1. As is clear from FIG. 21 (a), the frequency division data when the carry signal is not generated is M, and the frequency division data when the carry signal is not generated is M + 1. Therefore, the average data between L clocks is (M + F / L). Therefore, the output frequency of VCO1 becomes (M + F / L) times the reference signal frequency, and by changing the data of the decimal part F, the output frequency of VCO1 is changed to the output frequency at 1 / L intervals of the reference signal frequency. Can be set to.

【0011】

[Problems to be Solved by the Invention]

In a frequency synthesizer device that realizes an output frequency that is a non-integer multiple of the reference signal frequency with precision below the decimal point using this conventional delta-sigma modulation circuit, as shown in Fig. 21 (a), the frequency division data. Changes L clocks periodically in the basic period (variation period ΔP). At this time, as shown in FIG. 21 (b), the output signal of the phase comparator 3 fluctuates according to this change, and the spectrum of the control voltage to VCO1 becomes FIG. 23. At this time, the output of VCO1 is frequency-modulated. The spectrum is shown in Fig. 22. As is clear from FIG. 22, the spectrum of the output signal from VCO1 has a large spurious, which is a bilateral wave band signal located above and below the fluctuation frequency Δf corresponding to the fluctuation period ΔP from the reference frequency. .. Here, when the data of the decimal part F is small, the frequency component of the fluctuation is low and the spurious level is high, so that it is difficult to sufficiently reduce this with the low-pass filter 4.

【0012】

An object of the present invention is to solve the above problems and to provide a frequency synthesizer device that realizes an output frequency that is a non-integer multiple of the reference signal frequency with an accuracy after the decimal point and reduces spurious.

【0013】

Another object of the present invention is to provide a communication device and a frequency modulation device using the frequency synthesizer device.

【0014】

Furthermore, a further object of the present invention is to provide a frequency modulation method using the frequency synthesizer device.

【0015】

[Means for solving problems]

The frequency synthesizer device according to the present invention divides the output signal from the voltage control oscillator according to the data of the input frequency division and the voltage control oscillator that generates the output signal having the frequency corresponding to the input control voltage. The phase between the variable divider that divides and outputs the divided signal, the output signal from the variable divider, and the input reference signal is compared, and a signal showing the comparison result is generated. And the low frequency pass filter that outputs the signal from the phase comparator to the low frequency pass filter and outputs the signal after the low frequency pass filter to the voltage control oscillator. The fractional part control circuit that controls the fractional part data and outputs the controlled fractional part data, the input integer part data, and the controlled minor part data output from the fractional part control circuit. A frequency synthesizer device including an adding means for adding and outputting the addition result data as frequency dividing data to the variable frequency divider, and the fractional part control circuit is an input fractional part. The data output from the multiple n-th order integrators and the data output from the multiple n-th order integrators are quantized and quantized in a predetermined quantization step. A plurality of n configured with a quantizer for outputting the data obtained and a feedback circuit for feeding back the data from the quantizer to the plurality of n-th order integrators together with the input fractional data. The next delta sigma modulation circuit, the fractional part control circuit periodically changes the input fractional part data, thereby according to the average data of the period, and the frequency of the output signal of the voltage control oscillator. Is characterized by setting.

【0016】

In the frequency synthesizer device, preferably, the quantizer generates the data of the integer part of the quotient obtained by dividing the data output from the plurality of nth-order adders by a predetermined quantization step, and the controlled fraction. The frequency synthesizer device outputs the data of the unit, and the frequency synthesizer device multiplies the data output from the feedback circuit with the quantization step, and outputs the data of the multiplication result. It is characterized by further including a first adder that adds the data output from the multiplier and the data of the fractional part to be input and outputs the data of the addition result to the plurality of n-th order integrators. ..

【0017】

Further, in the frequency synthesizer device, preferably, the fractional part control circuit is a circuit composed of a binary logic circuit and showing a negative number as a complement of 2, and the quantization step is represented by a power of 2. The quantizer outputs the data of the high-order bits indicating the data of the quantization step or higher among the quantized data, and the plural n-th order integrator outputs the output data from the feedback circuit of the high-order bits. It is characterized in that it is input as data and by combining the input fractional data as low-order bit data.

【0018】

Further, in the frequency synthesizer device, preferably, the reference signal or the output signal from the variable frequency divider is used as a clock, and a delay of 1 clock is z.^-1In the z-transform shown by, the transfer function of the above multiple n-th order integrator is 1 / (1-z) in the z-transform.^-1)ⁿThe transfer function of the above feedback circuit is z-transform (1-z).^-1)ⁿIt is characterized by being represented by -1.

【0019】

Furthermore, in the frequency synthesizer device, preferably, the plurality of n-th order integrators include a plurality of n first-order integrators connected in cascade, and each of the first-order integrators includes a second adder and a second adder. A one-clock delay circuit is provided, and the second adder adds the data input to each of the first-order integrators and the output data from the one-clock delay circuit, and the data of the addition result is the next stage. The 1-clock delay circuit delays the output data from the 2nd adder by 1 clock and outputs the delayed data to the 2nd adder. It is characterized by that.

【0020】

Further, in the frequency synthesizer device, the multiple n-th order integrator z the second adder and the delay of one clock.^-1In the z-transform shown by, 1- (1-z^-1)ⁿThe second adder includes a composite delay circuit having a transfer function represented by the above, and the second adder adds and adds the data input to the plurality of nth integrators and the output data from the composite delay circuit. The result data is output to the composite delay circuit and is output as output data from the plurality of n-th order integrators.

【0021】

Further, in the frequency synthesizer device, preferably, the reference signal or the output signal from the variable frequency divider is used as a clock, and a delay of 1 clock is z.^-1In the z-transform shown by, the transfer function of the above multiple n-th order integrator is z-transform.^-1/ (1-z^-1)ⁿIt is represented by, and the transfer function of the above feedback circuit is z-transform ((1-z).^-1)ⁿ-1) / z^-1It is characterized by being represented by.

【0022】

Furthermore, in the frequency synthesizer device, preferably, the plurality of n-th order integrators include a plurality of n first-order integrators connected in cascade, and each of the first-order integrators includes a second adder. A 1-clock delay circuit is provided, and the second adder adds the data input to each of the first-order integrators and the output data from the 1-clock delay circuit, and outputs the data of the addition result. The one-clock delay circuit delays the output data from the second adder by one clock and outputs the delayed data, and any one of the n first-order integrators The output data from the 1-clock delay circuit of the first-order integrator is output to the first-order integrator of the next stage, while the other first-order integrators output the output data from the second adder to the next-stage 1 It is characterized by outputting to the next integrator.

【0023】

Further, in the frequency synthesizer device, preferably, among the plurality of n first-order integrators, the one-clock delay circuit of the first-stage first-order integrator operates at the first clock, and at least one of the second and subsequent stages. The 1-clock delay circuit of one first-order integrator operates on the second clock, the periods of the first clock and the second clock are substantially equal, and the rising or falling timings are substantially different. It is characterized by.

【0024】

Further, in the frequency synthesizer device, preferably, each of the first-order integrators connected in cascade is composed of a binary logic circuit, and the bit length of at least one first-order integrator after the second stage is the first-order of the first stage. It is characterized in that it is configured to be smaller than the bit length of the integrator.

【0025】

Furthermore, in the frequency synthesizer device, preferably, the plurality of n-th order integrators z the second adder, the 1-clock delay circuit, and the 1-clock delay.^-1In the z-transform shown by, (1- (1-z^-1)ⁿ) / Z^-1The second adder includes a composite delay circuit having a transfer function represented by the above, and the second adder adds and adds the data input to the plurality of nth integrators and the output data from the composite delay circuit. The result data is output to the composite delay circuit via the 1-clock delay circuit, and the output data from the 1-clock delay circuit is output as output data from the plurality of n-th order integrators.

【0026】

Further, in the frequency synthesizer device, preferably, the decimal part control circuit has a first delta-sigma modulation circuit, a second delta-sigma modulation circuit, and one clock delay.^-1In the z-transform shown by, (1-z^-1)ⁿThe first delta sigma modulation circuit includes a natural number n-th order integrator having a transfer function represented by, and the first delta sigma integrator is a first integrator, a first integrator, and a first integrator. The second delta sigma modulation circuit including one feedback circuit includes a second integrator which is a natural number m-th order integrator, a second integrator, and a second feedback circuit. The output data from the second integrator of the second delta sigma modulation circuit is input to the natural number nth-order integrator, and the fractional control circuit is further combined with the output data from the first integrator. The output data from the second integrator is subtracted from the output data from the first integrator and the second integrator that multiplies the predetermined quantization step and outputs the data of the multiplication result. The output data from the first subtractor that outputs the subtraction result data to the second delta sigma modulation circuit and the first integrator of the first delta sigma modulation circuit is the natural number nth order differential circuit. The delay means for delaying to synchronize with the timing of the output data from the above, the output data delayed by the delay means, and the output data from the natural number nth-order differential circuit are added, and the data of the addition result is obtained. It is provided with another integrator means for outputting as output data from the integrator control circuit, and the integrator control circuit is characterized in that it operates as a plurality of (n + m) next-order delta sigma modulation circuits.

【0027】

Further, in the frequency synthesizer device, preferably, the first delta-sigma modulation circuit operates on the first clock, the second delta-sigma modulation circuit operates on the second clock, and the first clock operates. The second clock period is substantially the same as that of the second clock, and the rising or falling timings are substantially different.

【0028】

Furthermore, in the frequency synthesizer device, preferably, the first clock is generated from one of the reference signal or the output of the variable frequency divider, and the second clock is generated from the other.

【0029】

Further, in the frequency synthesizer device, preferably, the fractional part control circuit is composed of a binary logic circuit, and the output data of the second integrator contains data less than the quantization step of the second integrator. The indicated bit length is characterized in that it is configured to be shorter than the bit length indicating the data less than the quantization step of the first integrator in the output data of the first integrator.

【0030】

Further, in the frequency synthesizer device, preferably, among the output data of each one clock delay circuit of the plurality of n linear integrators connected in cascade, the data of the number of bits indicating the data less than the quantization step is displayed. It is characterized in that it is configured to be set to the number of bits or less in the previous stage in order.

【0031】

The communication device according to the present invention is a communication device including the frequency synthesizer device, the transmission circuit, and the reception circuit, and the output signal of the voltage control oscillator, which is the output signal of the frequency synthesizer device, is the transmission circuit. And is supplied to the receiving circuit as a local oscillation signal, the transmitting circuit transmits a radio signal on a frequency channel corresponding to the frequency of the locally oscillating signal, and the receiving circuit is another one corresponding to the frequency of the locally oscillating signal. It is characterized by receiving another radio signal on a frequency channel.

【0032】

Further, the frequency modulation device according to the present invention adds the frequency synthesizer device, the input fractional data, and the input modulation data, and outputs the addition result data to the fractional control circuit. A third adder is provided, whereby the output signal from the voltage controlled oscillator of the frequency synthesizer device is frequency-modulated according to the modulation data.

【0033】

Furthermore, the frequency modulation method according to the present invention is a frequency modulation method using the frequency synthesizer device, in which the input fractional data and the input modulation data are added, and the data of the addition result is obtained. Is included in the fractional control circuit, whereby the output signal from the voltage controlled oscillator of the frequency synthesizer device is frequency-modulated according to the modulation data.

【0034】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In the following embodiments, similar circuit components are designated by the same reference numerals and detailed description thereof will be omitted.

【0035】

First Embodiment. FIG. 1 is a block diagram showing a circuit configuration of a frequency synthesizer device according to the first embodiment of the present invention. In FIG. 1, the frequency synthesizer device of the first embodiment is configured by connecting a VCO 1, a variable frequency divider 2, a phase comparator 3, and a low-pass filter 4 which is a loop filter in a loop. Further, it is provided with a decimal part control circuit 5 and an adder 6. Here, in particular, the frequency synthesizer device of the first embodiment is characterized by including a decimal part control circuit 5 having a second-order integrator 7 and a feedback circuit 9. The decimal part control circuit 5 provided in the frequency synthesizer device provided with the PLL circuit is a circuit that controls the data of the decimal part F of the data of the number of divisions to the variable frequency divider 2 of the PLL circuit.

【0036】

In FIG. 1, the variable frequency divider 2 divides the output signal of VCO1 according to the data of the number of divisions input from the adder 6, and outputs the divided signal to the phase comparator 3. The phase comparator 3 compares each phase of the input reference signal and the output signal from the variable frequency divider 2, and outputs a signal indicating the phase comparison result to the VCO1 via the low-pass filter 4. As a result, the PLL circuit is feedback-controlled so that the output frequency of VCO1 becomes stable. On the other hand, the adder 6 adds the data of the integer part M input from the external device and the data of the controlled decimal part F from the decimal part control circuit 5, and divides the data of the addition result into the data of the number of divisions. Is output to the variable frequency divider 2.

【0037】

The decimal part control circuit 5 includes a second-order integrator 7, a quantizer 8, a feedback circuit 9, a multiplier 14, and an adder 15, and controls the input data of the decimal part F. Then, the data of the controlled decimal part F is output to the adder 6. Here, Q is the quantization error added to the data to be quantized in the quantizer 8. The data of the fractional part F input from the external device is input to the adder 15, and the adder 15 adds the data of the fractional part F and the output data from the multiplier 14 and inputs the data of the addition result. Data X₁Is output to the quadratic integrator 7. Output data from second-order integrator 7 X₂Is quantized by the quantizer 8 in a predetermined quantization step L, and the quantized output data is output to the feedback circuit 9 and the adder 6. The output data from the feedback circuit 9 is multiplied by the quantization step L by the multiplier 14, and the data of the multiplication result is output to the adder 15.

【0038】

The feedback circuit 9 includes two delay circuits 10 and 11, a double multiplier 12, and a subtractor 13. The output data from the quantizer 8 is input to the delay circuit 10, and the output data from the delay circuit 10 is input to the delay circuit 11 and the double multiplier 12. The subtractor 13 subtracts the output data from the double multiplier 12 from the output data of the delay circuit 11 and outputs the subtraction result data to the multiplier 14. Here, the double multiplier 12 is a circuit that doubles the input data and outputs the doubled data, and in the binary logic circuit, the entire bit data is simply shifted to the uppermost bit by one bit and the least significant bit. This can be achieved with a configuration that sets (LSB) to zero. The delay circuits 10 and 11 use the output signal of the variable frequency divider 2 as a clock, and output the input data with a delay of one clock.

【0039】

The decimal part control circuit 5 operates using the output signal from the variable divider 2 as a clock. Here, z the delay of 1 clock^-1Using the z-transform represented by, the transfer function of the quadratic integrator 7 is expressed by the z-transform as follows.

【0040】

[Number 2]

1 / (1-z^-1)² 【0041】

FIG. 2 is a block diagram showing a circuit configuration of the second integrator 7 of FIG. In FIG. 2, the adder 21 and the delay circuit 22 constitute a first-order integrator 101. In the drawings after FIG. 2, the delay circuit, the integrator, and the clock supply line to the quantizer are not shown. Adder 21 is input data X₁And the output data of the delay circuit 22 are added, and the data of the addition result is output to the delay circuit 22 and the adder 23 of the next stage. The transfer function of this first-order integrator 101 is expressed by the following equation by z-transform.

【0042】

[Number 3]

1 / (1-z^-1) 【0043】

Then, similarly, the adder 23 and the delay circuit 24 form the next-stage first-order integrator 102. The adder 23 adds the data from the adder 21 and the data from the delay circuit 24, outputs the data of the addition result to the delay circuit 24, and outputs the data of the addition result to the second integrator 7. Data X₂Will be. Here, the delay circuits 22 and 24 use the output signal of the variable frequency divider 2 as a clock, delay the input data by one clock, and output the delayed data.

【0044】

FIG. 3 is a block diagram showing a circuit configuration of a modified second-order integrator 7a instead of the second-order integrator 7 of FIG. In FIG. 3, the second-order integrator 7a includes an adder 31 and a composite delay circuit 30. Adder 31 is input data X₁And the output data from the composite delay circuit 30 are added, and the data of the addition result is output to the delay circuit 32 of the composite delay circuit 30, and the data of the addition result is the output data X of the second integrator 7a.₂Will be. Further, the composite delay circuit 30 includes two delay circuits 32 and 33, a double multiplier 34, and a subtractor 35. The delay circuits 32 and 33 are circuits that use the output signal from the variable frequency divider 2 as a clock to delay the input data by one clock and output it, and the double multiplier 34 doubles the input data. It is a circuit that outputs doubled data. The input data to the composite delay circuit 30, which is the output from the adder 31, is input to the delay circuit 32, and the output data from the delay circuit 32 is input to the delay circuit 33 and the double multiplier 34. Further, the subtractor 35 subtracts the output data from the delay circuit 33 from the output data from the double multiplier 34, and outputs the subtraction result data to the adder 31.

【0045】

The operation of the frequency synthesizer device of FIG. 1 configured as described above will be described below.

【0046】

The data of the integer part M input to the adder 6 is the data of the integer part of the quotient obtained by dividing the desired output signal frequency by the reference signal frequency, and the data of the fractional part F is quantum to the data after the decimal point of the quotient. It is the data obtained by multiplying the quantization step L of the chemical device 8. Quantizer 8 is the input data X₂Is divided by the quantization step L, and only the data of the integer part of the quotient is output. The transfer function of the feedback circuit 9 is expressed by the following equation by z-transform.

【0047】

[Number 4]

z^-2-2z^-1= (1-z^-1)²-1 【0048】

Next, the output data Y of the decimal part control circuit 5 is expressed by the following equation by z-transform.

【0049】

[Number 5]

Y = F / L + (1-z^-1)²Q [0050]

As is clear from the above equation, the decimal part control circuit 5 operates as a second-order delta-sigma modulation circuit. The frequency division data input to the variable frequency divider 2 is the sum of the data of the integer part M and the data of the controlled decimal part F which is the output data from the decimal part control circuit 5, and is the decimal part. It changes according to the change of the output data from the control circuit 5, but (1-z in the above equation^-1)²Since the average value of the Q term is zero, the average of the frequency division data is M + F / L. Therefore, by changing the data of the decimal part F, the data of the number of divisions can be changed in 1 / L units, and the output signal frequency of VCO1 can be set at 1 / L intervals of the reference signal frequency.

【0051】

On the other hand, the amplitude of the transfer function in the z-transform | 1-z^-1The frequency characteristic for | is | 2sin (πf / f)_s) | Where f_sIs the frequency of the clock, which is equal to the reference signal frequency. In the circuit configuration of FIG. 1 with the quadratic integrator 7, the quantization error Q of the output signal is | 2sin (πf / f)._s)|²The frequency characteristics of will be multiplied. FIG. 18 shows the frequency characteristics of each order-order delta-sigma modulation circuit according to the embodiment, and the coefficient multiplied by the quantization error Q in the second-order delta-sigma modulation circuit is clear from FIG. Compared to the coefficient multiplied by the quantization error Q in the first-order delta-sigma modulation circuit, the degree of suppression of the quantization error in the low frequency region is large. Further, as a characteristic of the quantization error Q, the first-order delta-sigma modulation circuit has a strong periodic component L times the clock period, but the second-order delta-sigma modulation circuit has a weak periodic component. Therefore, by using the second-order delta-sigma modulation circuit, the change in the frequency division data has a small low frequency component and a large high frequency component.

【0052】

The change in the number of divisions data changes the phase of the output signal of the variable frequency divider 2, the change component is extracted by the phase comparator 3, and the high frequency component is reduced by the low-pass filter 4. Therefore, the level of the originally unnecessary frequency component generated by the change of the frequency division data decreases from the low frequency component to the high frequency component. Therefore, the unnecessary signal applied to VCO1 is small, and the spurious generated at the output due to frequency modulation is greatly reduced.

【0053】

Second Embodiment. FIG. 4 is a block diagram showing a circuit configuration of the decimal part control circuit 5a according to the second embodiment of the present invention. In the second embodiment, the circuit configurations other than the decimal part control circuit 5a are the same as those shown in FIG. In FIG. 4, the decimal part control circuit 5a according to the second embodiment includes a second-order integrator 7b, a quantizer 8, a feedback circuit 9a, a multiplier 14, and an adder 15. To. Here, the decimal part control circuit 5a according to the second embodiment moves the delay circuit 10 in the feedback circuit 9 into the second integrator 7b as compared with the decimal part control circuit 5 in FIG. It is characterized by. That is, the decimal part control circuit 5a has the same circuit configuration as the decimal part control circuit 5 in FIG. 1, except that the circuit configurations of the second-order integrator 7b and the feedback circuit 9a are different, and the same operation is performed. Have.

【0054】

In FIG. 4, the adder 15 adds the data of the fractional part F input from the external device and the output data from the multiplier 14, and outputs the data of the addition result to the quadratic integrator 7b. The output data from the second-order integrator 7b is quantized by the quantizer 8, and the quantized output data is input to the feedback circuit 9a and becomes the data of the controlled fractional part F. The output data from the feedback circuit 9a is input to the multiplier 14, which multiplies the output data from the feedback circuit 9a with the quantization step L, and outputs the multiplication result data to the adder 15. Further, the feedback circuit 9a includes a delay circuit 11, a double multiplier 12, and a subtractor 13. The output data from the quantizer 8 is input to the delay circuit 11 and the double multiplier 12. The subtractor 13 subtracts the output data from the double multiplier 12 from the output data from the delay circuit 11 and outputs the subtraction result data to the multiplier 14. In this embodiment, the delay of 1 clock is z.^-1Using the z-transform represented by, the transfer function of the second-order integrator 7b is expressed by the following equation.

【0055】

[Number 6]

z^-1/ (1-z^-1)² 【0056】

FIG. 5 is a block diagram showing a circuit configuration of the second integrator 7b of FIG. In FIG. 5, the adder 21 and the delay circuit 22 constitute the first-order integrator 101. Adder 21 is input data X₁And the output data from the delay circuit 22 are added, and the data of the addition result is output to the delay circuit 22 and the adder 23 in the next stage. The transfer function of this first-order integrator 101 is expressed by the following equation by z-transform.

【0057】

[Number 7]

1 / (1-z^-1) 【0058】

Then, similarly, the adder 23 and the delay circuit 24 constitute the next-stage first-order integrator 102. The output data from the adder 21 is input to the adder 23, the adder 23 adds the output data from the adder 21 and the output data from the delay circuit 24, and the data of the addition result is sent to the delay circuit 24. Output. The output data from the delay circuit 24 is input to the adder 23, and the output data X of the second integrator 7b₂Will be. The delay circuits 22 and 24 output the input data with a delay of one clock. Since the output data of the delay circuit 24 is used as the output data of the second-order integrator 7b, the transfer function of the entire circuit of the second-order integrator 7b is expressed by the z-transform as follows.

【0059】

[Number 8]

z^-1/ (1-z^-1)² 【0060】

FIG. 6 is a block diagram showing a circuit configuration of a modified second-order integrator 7c instead of the second-order integrator 7b of FIG. The second-order integrator 7c in FIG. 6 has a different connection between the two first-order integrators 101 and 102 as compared with the second-order integrator 7b in FIG. The feature is that it is input to the integrator 23 of the stage. In FIG. 6, the adder 21 and the delay circuit 22 constitute the first-order integrator 101. Adder 21 is input data X₁Then, the output data from the delay circuit 22 is added, and the data of the addition result is output to the adder 21 and the adder 23 via the delay circuit 22. The transfer function of this first-order integrator 101 is expressed by the following equation by z-transform.

【0061】

[Number 9]

1 / (1-z^-1) 【0062】

Then, similarly, the adder 23 and the delay circuit 24 constitute the next-stage first-order integrator 102. The adder 23 adds the output data from the delay circuit 22 and the output data from the delay circuit 24, outputs the data of the addition result to the adder 23 via the delay circuit 24, and outputs the data of the addition result to the adder 23. The data is the output data X of the second-order integrator 7c.₂Will be. In the circuit configuration of the second-order integrator 7c of FIG. 6 configured as described above, since the output data of the delay circuit 22 is used as the output data of the first-stage integrator 101 of the first stage, the second-order integrator The transfer function of the entire circuit of 7c is expressed by the following equation by z conversion.

【0063】

[Number 10]

z^-1/ (1-z^-1)² 【0064】

In the second-order integrators 7b and 7c of FIGS. 5 and 6 above, the clock to the first-order integrator 101 and the clock to the first-order integrator 102 use the output signal from the variable frequency divider 2 as a clock. Although used, the present invention is not limited to this, and two clocks that are synchronized with the reference signal or the output signal from the variable divider 2 and have substantially the same period but different rising or falling timings are used. You may use it. This has the effect of preventing the phenomenon that when the circuits constituting the decimal part control circuit 5a operate at the same timing, the instantaneous operating current concentrates at that timing and a large power supply voltage fluctuation occurs.

【0065】

FIG. 7 is a block diagram showing a circuit configuration of a modified second-order integrator 7d instead of the second-order integrator 7b of FIG. In FIG. 7, the second-order integrator 7d includes an adder 31, a delay circuit 32a, and a composite delay circuit 30a. Compared with the second integrator 7a in FIG. 3, the second integrator 7d in FIG. 7 combines the delay circuit 32 in the composite delay circuit 30 with the adder 31 and the output terminal of the second integrator 7d. The feature is that it is moved so as to be inserted between the delay circuit 30a and the connection point.

【0066】

In FIG. 7, the adder 31 is the input data X.₁And the output data from the subtractor 35 in the composite delay circuit 30a are added, and the data of the addition result is output to the delay circuit 33 and the double multiplier 34 in the composite delay circuit 30a via the delay circuit 32a. , The output data from the delay circuit 32a is the output data X of the quadratic integrator 7d.₂Will be. The composite delay circuit 30a includes a delay circuit 33, a double multiplier 34, and a subtractor 35. The subtractor 35 subtracts the output data from the delay circuit 33 from the output data from the double multiplier 34, and outputs the subtraction result data to the adder 31. The transfer function of the entire circuit of the quadratic integrator 7d of FIG. 7 configured as described above is expressed by the following equation by the z-transform.

【0067】

[Number 11]

z^-1/ (1-z^-1)² 【0068】

The operation of the decimal part control circuit 5a of FIG. 4 according to the second embodiment, which is configured as described above, will be described below. Quantizer 8 is the input data X₂Is divided by the quantization step L, and only the integer part of the quotient is output. The transfer function of the feedback circuit 9a is expressed by the following equation by z-transform.

【0069】

[Number 12]

z^-1-2 = ((1-z^-1)²-1) / z^-1 【0070】

The transfer function of the second-order integrator 7b (or 7c, 7d) is expressed by the following equation by z-transform.

【0071】

[Number 13]

z^-1/ (1-z^-1)² 【0072】

Therefore, the output data from the decimal part control circuit 5a in FIG. 4 is expressed by the following equation by z-transform.

【0073】

[Number 14]

Y = z^-1F / L + (1-z^-1)²Q [0074]

As is clear from the above equation, the output data Y from the decimal part control circuit 5a is delayed by only one clock and has the same notation as the decimal part control circuit 5 in FIG. 1, and the decimal part control circuit 5a in FIG. 4 is 2. Operates as a next delta-sigma modulation circuit. Therefore, in a frequency synthesizer device using the fractional control circuit 5a shown in FIG. 4 instead of the fractional control circuit 5 in FIG. 1, the output signal frequency can be set at 1 / L intervals of the reference signal frequency, and the frequency. Spurious generated in the output signal due to modulation can be significantly reduced.

【0075】

Third Embodiment. FIG. 8 is a block diagram showing a circuit configuration of the decimal part control circuit 5b according to the third embodiment of the present invention. The circuit configuration other than the decimal part control circuit 5b is the same as that shown in FIG. The decimal part control circuit 5b according to the third embodiment includes a second-order integrator 7e and a feedback circuit 9. Here, the second-order integrator 7e and the feedback circuit 9 are composed of binary logic circuits, and negative numbers are represented by two's complement. The quantization step L is the data indicated by the power of 2. In the following embodiment, the number of high-order bits is, for example, 4 bits, and the number of low-order bits is, for example, 20 bits. The present invention is not limited to these number of bits, and may be limited to a predetermined number of bits.

【0076】

The data in which the data of the fractional part F input from the external device is the low-order bit and the output data of the feedback circuit 9 is the high-order bit is input to the second-order integrator 7e. The second-order integrator 7e secondarily integrates the input data, and outputs the data of the upper bits corresponding to the digits of the quantization step L or more to the delay circuit 10 in the feedback circuit 9 among the data after the second-order integration. At the same time, it is output as the data of the controlled fractional part from the fractional part control circuit 5b. The feedback circuit 9 includes two delay circuits 10 and 11, a double multiplier 12, and a subtractor 13. The output data of the high-order bits from the second-order integrator 7e is input to the delay circuit 11 and the double multiplier 12 via the delay circuit 10. The subtractor 13 subtracts the output data from the double multiplier 12 from the output data from the delay circuit 11, and outputs the subtraction result data to the second-order integrator 7e as high-order bit data. Here, the second-order integrator 7e may have the circuit configuration of the second-order integrator 7 of FIG. 2, or may have the circuit configuration of the second-order integrator 7a of FIG.

【0077】

The decimal part control circuit 5b of FIG. 8 for the frequency synthesizer device configured as described above can be basically regarded as having the same circuit configuration as the decimal part control circuit 5 of FIG. By making the quantization step L the data of the power of 2, the circuit that simply selects only the high-order bits indicating the data of the quantization step L or higher from the output data of the second-order integrator 7e. It is realized by the configuration. Here, the data of the selected high-order bit is input to the feedback circuit 9 and fed back, and becomes the output data of the decimal part control circuit 5b. In addition, the output data of the feedback circuit 9 is used as the high-order bit, combined with the data of the fractional part F, and the combined data is input to the second-order integrator 7e. The same function as the vessel 15 can be realized. The settable interval of the output signal frequency is limited to 1 / power of 2 of the reference signal frequency and cannot be set to 1 / of an arbitrary integer, but it is significant that the configuration can be greatly simplified.

【0078】

Fourth Embodiment. FIG. 9 is a block diagram showing a circuit configuration of the decimal part control circuit 5c according to the fourth embodiment of the present invention. In the fourth embodiment, the circuit configuration in which the same circuit configuration of the third embodiment is applied to the decimal part control circuit 5a of FIG. 4 is shown. The decimal part control circuit 5c according to the fourth embodiment includes a second-order integrator 7f and a feedback circuit 9a. Here, the second-order integrator 7f and the feedback circuit 9a are composed of binary logic circuits, and negative numbers are represented by two's complement. The quantization step L is the data indicated by the power of 2.

【0079】

The data in which the data of the fractional part F input from the external device is the low-order bit and the output data of the feedback circuit 9a is the high-order bit is input to the second-order integrator 7f. The second-order integrator 7f second-order-integrates the input data, and among the data after the second-order integration, the data of the upper bits corresponding to the digits of the quantization step L or more is input to the delay circuits 11 and 2 in the feedback circuit 9a. It is output to the multiplier 12 and is output as the data of the controlled fractional part from the fractional part control circuit 5c. The feedback circuit 9a includes a delay circuit 11, a double multiplier 12, and a subtractor 13. The output data of the high-order bits from the second-order integrator 7f is input to the delay circuit 11 and the double multiplier 12. The subtractor 13 subtracts the output data from the double multiplier 12 from the output data from the delay circuit 11, and outputs the subtraction result data to the second-order integrator 7f as high-order bit data. Here, the second-order integrator 7f may have the circuit configuration of the second-order integrator 7b of FIG. 5, may have the circuit configuration of the second-order integrator 7c of FIG. 6, and may have the circuit configuration of the second-order integrator 7c of FIG. It may have the circuit configuration of the second-order integrator 7d.

【0080】

The decimal part control circuit 5c of FIG. 9 for the frequency synthesizer device configured as described above can be basically regarded as having the same circuit configuration as the decimal part control circuit 5a shown in FIG. By setting the quantization step L to the power of 2 data, the quantizer is realized by a circuit configuration that simply selects only the high-order bits indicating the data of the quantization step L or higher of the output data of the second-order integrator 7f. doing. Here, the data of the selected high-order bit is input to the feedback circuit 9a and fed back, and becomes the output data of the decimal part control circuit 5c. In addition, the output data of the feedback circuit 9a is used as the high-order bit, combined with the data of the fractional part F, and the combined data is input to the second-order integrator 7f. Achieves the same function as the vessel 15. The settable interval of the output signal frequency is limited to 1 / power of 2 of the reference signal frequency and cannot be set to 1 / of an arbitrary integer, but it is significant that the configuration can be greatly simplified.

【0081】

Fifth embodiment FIG. 10 is a block diagram showing a circuit configuration of the decimal part control circuit 5d according to the fifth embodiment of the present invention. The circuit configuration other than the decimal part control circuit 5d is the same as that shown in FIG. In FIG. 10, the decimal part control circuit 5d according to the fifth embodiment includes a third-order integrator 40, a quantizer 8, a feedback circuit 41, a multiplier 14, and an adder 15. To. Compared with the decimal part control circuit 5a in FIG. 4, this decimal part control circuit 5d uses the third-order integrator 40 instead of the second-order integrator 7b, but is similar except that the circuit configuration of the feedback circuit 41 is different. It has a circuit configuration.

【0082】

The data of the fractional part F input from the external device is input to the adder 15, and the adder 15 adds the input data of the fractional part F and the output data from the multiplier 14, and the data of the addition result. Is output to the cubic adder 40. The third-order integrator 40 is the input data X₁3rd order integral, and the data X after the 3rd order integration₂Is output to the quantizer 8. In response, the quantizer 8 receives the input data X₂Is quantized in a predetermined quantization step L, and the output data after quantization is fed back to the feedback circuit 41 and becomes the data of the controlled decimal part F of the decimal part control circuit 5d. Here, the feedback circuit 41 is configured to include three delay circuits 42,43,44, two triple multipliers 45,46, and two subtractors 47,48. The output data from the quantizer 8 is output to the subtractor 47 via the two delay circuits 42 and 43, and is output to the subtractor 47 via the delay circuit 44 and the triple multiplier 45. The output data from the quantizer 8 is also output to the subtractor 48 via the triple multiplier 46. The subtractor 47 subtracts the output data from the delay circuit 43 from the output data from the triple multiplier 45, and outputs the subtraction result data to the subtractor 48. Next, the subtractor 48 subtracts the output data from the triple multiplier 46 from the output data from the subtractor 47, and outputs the subtraction result data to the multiplier 14. Further, the multiplier 14 multiplies the output data from the subtractor 48 by the quantization step L, and outputs the data of the multiplication result to the adder 15.

【0083】

In this embodiment, the delay of 1 clock is z.^-1Using the z-transform represented by, the transfer function of the cubic integrator 40 is expressed by the z-transform as follows.

【0084】

[Number 15]

z^-1/ (1-z^-1)³ 【0085】

FIG. 11 is a block diagram showing a circuit configuration of the third-order integrator 40 of FIG. In FIG. 11, the adder 51 and the delay circuit 52 form a first-order integrator 111, the adder 53 and the delay circuit 54 form a first-order integrator 112, and the adder 55 and the delay circuit 56 form 1 It constitutes the next integrator 113. The transfer function of each first-order integrator 111,112,113 is expressed by the following equation by z-transform.

【0086】

[Number 16]

1 / (1-z^-1) 【0087】

In FIG. 11, the input data X₁Is added to the output data from the delay circuit 52 by the adder 51, and the output data from the adder 51 is input to the delay circuit 52 and also to the adder 53 in the next stage. Next, the adder 53 adds the output data from the adder 51 and the output data from the delay circuit 54, and outputs the data of the addition result to the delay circuit 54 and the adder 55 in the next stage. Further, the adder 55 adds the output data from the adder 53 and the output data from the delay circuit 56, outputs the data of the addition result to the adder 55 via the delay circuit 56, and outputs the data from the delay circuit 56. The output data is the output data X of the third-order integrator 40.₂Will be. Here, each delay circuit 52, 54, 56 delays the input data by one clock and outputs it. Since the output data from the delay circuit 56 is used as the output data from the third-order integrator 40, the transfer function of the entire circuit of the third-order integrator 40 is expressed by the z-transform as follows.

【0088】

[Number 17]

z^-1/ (1-z^-1)³ 【0089】

In the third-order integrator 40 of FIG. 11, only the first-stage integrator 113 in the final stage has the output data from the delay circuit 56 as the output data from the first-stage integrator 113, but only the first-stage integrator 111 has. The output data from the delay circuit 52 may be used as the output data from the first-order integrator 111, or instead, only the second-stage first-order integrator 112 and the output data from the delay circuit 54 may be used as the first-order integrator. It may be output data from 112. The transfer function of each cubic integrator 40 constructed in this way is expressed by the following equation by z-transform.

【0090】

[Number 18]

z^-1/ (1-z^-1)³ 【0091】

FIG. 12 is a block diagram showing a circuit configuration of a modified third-order integrator 40a instead of the third-order integrator 40 of FIG. The third-order integrator 40a is characterized in that it is configured by longitudinally connecting the first-order integrator 111 and the second-order integrator 114. In FIG. 12, the adder 51 and the delay circuit 52 constitute a first-order integrator 111. Further, the adder 53, the subtractor 60, the two delay circuits 57 and 58, and the double multiplier 59 constitute the quadratic integrator 114. Here, the second-order integrator 114 has the same circuit configuration as the second-order integrator 7d of FIG. 7, and detailed description thereof will be omitted. The transfer function of the first-order integrator 111 is expressed by the following equation by z-transform.

【0092】

[Number 19]

1 / (1-z^-1) 【0093】

The transfer function of the second-order integrator 114 is expressed by the following equation by z-transform.

【0094】

[Number 20]

z^-1/ (1-z^-1)² 【0095】

Therefore, the transfer function of the entire circuit of the cubic integrator 40a in FIG. 12 is expressed by the following equation by the z-transform.

【0096】

[Number 21]

z^-1/ (1-z^-1)³ 【0097】

In the third-order integrators 40 and 40a of FIGS. 11 and 12 above, the clock to the first-order integrator 111,112,113 and the clock to the second-order integrator 114 use the output signal from the variable frequency divider 2 as a clock. Although used, the present invention is not limited to this, and three or two that are synchronized with the reference signal or the output signal from the integrator 2 and have substantially the same period but different rising or falling timings. One clock (for the third-order integrator 40 in FIG. 11) or two clocks (for the third-order integrator 40a in FIG. 12) may be used. This has the effect of preventing the phenomenon that when the circuits constituting the decimal part control circuit 5d operate at the same timing, the instantaneous operating current concentrates at that timing and a large power supply voltage fluctuation occurs.

【0098】

FIG. 13 is a block diagram showing a circuit configuration of a modified third-order integrator 40b instead of the third-order integrator 40 of FIG. In FIG. 13, the third-order integrator 40b includes an adder 71, a delay circuit 72, and a composite delay circuit 70.

【0099】

In FIG. 13, the adder 71 is the input data X.₁And the output data from the composite delay circuit 70 are added, and the addition result is output to the composite delay circuit 70 via the delay circuit 72, and the output data from the delay circuit 72 is the output data X from the third-order integrator 40b.₂Will be. The composite delay circuit 70 includes three delay circuits 73,74,75, two triple multipliers 76,77, a subtractor 78, and an adder 79. Here, each delay circuit 73,74,75 is a circuit that delays the input data by one clock and outputs it, and each triple multiplier 76,77 is a circuit that triples the input data and outputs it. The output data from the delay circuit 72 is output to the subtractor 78 via the two delay circuits 73 and 74 in the composite delay circuit 70, and to the subtractor 78 via the delay circuit 75 and the triple multiplier 76. It is output. Further, the output data from the delay circuit 72 is output to the adder 79 via the triple multiplier 77. Further, the subtractor 78 subtracts the output data from the triple multiplier 76 from the output data from the delay circuit 74, and outputs the subtraction result data to the adder 79. Further, the adder 79 adds the output data from the subtractor 78 and the output data from the triple multiplier 77, and outputs the data of the addition result to the adder 71.

【0100】

The transfer function of the entire circuit of the cubic integrator 40b of FIG. 13 configured as described above is expressed by the following equation by the z-transform.

【0101】

[Number 22]

z^-1/ (1-z^-1)³ 【0102】

The operation of the decimal part control circuit 5d of FIG. 10 according to the fifth embodiment, which is configured as described above, will be described below. Quantizer 8 is input data X₂Is divided by the quantization step L, and only the data of the integer part of the quotient is output. The transfer function of the feedback circuit 41 is expressed by the following equation by z-transform.

【0103】

[Number 23]

-3 + 3z^-1-z^-2= ((1-z^-1)³-1) / z^-1 【0104】

Here, the transfer function of the cubic integrator 40 is expressed by the following equation by the z-transform.

【0105】

[Number 24]

z^-1/ (1-z^-1)³ 【0106】

Therefore, the output data from the decimal part control circuit 5d in FIG. 10 is expressed by the following equation by z-transform.

【0107】

[Number 25]

Y = z^-1F / L + (1-z^-1)³Q [0108]

As is clear from the above equation, the decimal part control circuit 5d in FIG. 10 operates as a third-order delta-sigma modulation circuit.

【0109】

As mentioned above, the amplitude of the transfer function in the z-transform | 1-z^-1The frequency characteristic for | is | 2sin (πf / f)_s) | Where f_sIs the frequency of the clock, which is equal to the reference signal frequency. Therefore, in the third-order delta-sigma modulation circuit configured by the decimal part control circuit 5d in FIG. 10, the quantization error Q is | 2sin (πf / f)._s)|³The frequency characteristics of will be multiplied. Therefore, as is clear from the frequency characteristics of the delta-sigma modulation circuit of FIG. 18, the coefficient multiplied by the quantization error Q in the third-order delta-sigma modulation circuit is the quantization in the above-mentioned second-order delta-sigma modulation circuit. Since it is smaller in the low frequency domain than the coefficient multiplied by the error Q, the degree of suppression of the quantization error in the low frequency domain is further increased.

【0110】

Therefore, in a frequency synthesizer device using the fractional control circuit 5d shown in FIG. 10 instead of the fractional control circuit 5 in FIG. 1, the output signal frequency can be set at 1 / L intervals of the reference signal frequency, and frequency modulation is performed. It has a peculiar effect that the spurious generated in the output can be further significantly reduced.

【0111】

Sixth Embodiment. FIG. 14 is a block diagram showing a circuit configuration of the decimal part control circuit 5e according to the sixth embodiment of the present invention. The circuit configuration other than the decimal part control circuit 5e is the same as that shown in FIG. The decimal part control circuit 5e shown in FIG. 14 basically has a circuit configuration using two second-order delta-sigma modulation circuits. In FIG. 14, the decimal part control circuit 5e includes two second-order delta-sigma modulation circuits 200 and 220, a second-order differentiating circuit 230, a delay circuit 209, a subtractor 210, a multiplier 211, and an adder 240. Be prepared.

【0112】

In FIG. 14, the second-order delta-sigma modulation circuit 200 includes a second-order integrator 201, a quantizer 202, a feedback circuit 203, a multiplier 207, and an adder 208. , The delay circuit 204, the double multiplier 205, and the subtractor 206 are provided. Further, the second-order delta-sigma modulation circuit 220 includes a second-order integrator 221, a quantizer 222, a feedback circuit 223, a multiplier 227, and an adder 228, and the feedback circuit 223 is delayed. It is composed of a circuit 224, a double multiplier 225, and a subtractor 226. The two second-order delta-sigma modulation circuits 200 and 220 have the same configuration as the decimal part control circuit 5a of FIG. 4, and detailed description thereof will be omitted.

【0113】

In FIG. 14, the data of the decimal part F input from the external device is input to the adder 208 of the second-order delta-sigma modulation circuit 200. Further, the output data from the quantizer 202 of the second-order delta-sigma modulation circuit 200 is output to the multiplier 211 and also to the adder 240 via the delay circuit 209. The multiplier 211 multiplies the output data from the quantizer 202 with the quantization step L, and outputs the data of the multiplication result to the subtractor 210. The subtractor 210 subtracts the output data from the multiplier 211 from the output data from the second integrator 201 of the second-order delta-sigma modulation circuit 200, and adds the subtraction result data to the adder of the second-order delta-sigma modulation circuit 220. Output to 228.

【0114】

The output data from the quantizer 222 of the second-order delta-sigma modulation circuit 220 is output to the adder 240 via the second-order differentiating circuit 230. Here, the second-order differentiating circuit 230 includes a delay circuit 231, a subtractor 232, a delay circuit 233, and a subtractor 234. The delay circuit 231 and the subtractor 232 form a first-order differentiating circuit 241, the delay circuit 233 and the subtractor 234 form a first-order differentiating circuit 242, and the second-order differentiating circuit 230 is two first-order differentiating circuits. It consists of 241,242 connected in series. The output data from the quantizer 222 of the second-order delta-sigma modulation circuit 220 is input to the delay circuit 231 and the subtractor 232 of the second-order differentiating circuit 230. The subtractor 232 subtracts the output data from the delay circuit 231 from the input data of the second differentiating circuit 230, and outputs the subtraction result data to the delay circuit 233 and the subtractor 234 in the next stage. The subtractor 234 subtracts the output data from the delay circuit 233 from the output data from the subtractor 232 in the previous stage, and outputs the subtraction result data to the adder 240.

【0115】

Further, the adder 240 adds the output data from the delay circuit 209 and the output data from the subtractor 234 of the second differentiating circuit 230, and the data of the addition result becomes the data of the controlled fractional part F, which is a fractional number. This is the output data of the entire circuit of the cross-control circuit 5e.

【0116】

The operation of the decimal part control circuit of FIG. 14 configured as described above will be described below. Output data from the second-order delta-sigma modulation circuit 200 Y₁Q Q the quantization error applied by the quantization device 202₁Then, in the z-transform, it is expressed by the following equation.

【0117】

[Number 26]

Y₁= z^-1F / L + (1-z^-1)²Q₁ 【0118】

In addition, the output data Y from the second-order delta-sigma modulation circuit 220₂Sets the input data to the second-order delta-sigma modulation circuit 220 to F.₂And the quantization error applied by the quantization device 222 is Q.₂Then, in the z-transform, it is expressed by the following equation.

【0119】

[Number 27]

Y₂= z^-1F₂/ L + (1-z^-1)²Q₂here, [Number 28]

F₂=-LQ₁Therefore, the following equation is obtained.

【0120】

[Number 29]

Y₂= -z^-1Q₁+ (1-z^-1)²Q₂ 【0121】

The transfer function of the second differentiating circuit 230 is expressed by the following equation by z-transform.

【0122】

[Number 30]

(1-z^-1)² 【0123】

Therefore, the output data Y from the second differentiating circuit 230₃Is expressed by the following equation in the z-transform.

【0124】

[Number 31]

Y₃= (1-z^-1)²Y₂= -z^-1(1-z^-1)²Q₁+ (1-z^-1)⁴Q₂ 【0125】

Therefore, the output data Y from the adder 240₄Is expressed by the following equation in the z-transform.

【0126】

[Number 32]

Y₄= z^-1Y₁+ Y₃= -z^-2F / L + (1-z^-1)⁴Q₂ 【0127】

As is clear from the above equation, the decimal part control circuit 5e in FIG. 14 operates as a fourth-order delta-sigma modulation circuit.

【0128】

As mentioned above, the amplitude of the transfer function in the z-transform | 1-z^-1The frequency characteristic for | is | 2sin (πf / f)_s) | Where f_sIs the frequency of the clock, which is equal to the reference signal frequency. Therefore, in the 4th-order delta-sigma modulation circuit shown in Fig. 14, the quantization error Q is | 2sin (πf / f)._s)|⁴The frequency characteristics of will be multiplied. Therefore, as is clear from the frequency characteristics of the delta-sigma modulation circuit of FIG. 18, the coefficient multiplied by the quantization error Q in the fourth-order delta-sigma modulation circuit is the above-mentioned second-order and third-order delta-sigma modulation circuit. Since it is smaller in the low frequency region than the coefficient multiplied by the quantization error Q in, the degree of suppression of the quantization error in the low frequency region is further increased.

【0129】

Therefore, in a frequency synthesizer device using the fractional control circuit 5e shown in FIG. 14 instead of the fractional control circuit 5 in FIG. 1, the output signal frequency can be set at 1 / L intervals of the reference signal frequency, and frequency modulation is performed. It has a unique effect that the spurious generated in the output can be further significantly reduced.

【0130】

In the sixth embodiment described above, the fourth-order delta-sigma modulation circuit is configured by combining the second-order delta-sigma modulation circuit 200, the second-order delta-sigma modulation circuit 220, and the second-order differentiating circuit 230. .. Generally, when combining a natural number n-th order delta-sigma modulation circuit and a natural number m-th order delta-sigma modulation circuit, a natural number n-th order differentiator circuit is provided in the output stage of the m-th order delta-sigma modulation circuit, and the n-th order delta-sigma modulation circuit is used. By inserting a delay circuit in the output stage of the n-th order delta-sigma modulation circuit so that the output data of is synchronized with the output data from the natural number n-th order differentiator circuit, the (n + m) order delta-sigma modulation is performed as a whole. The circuit can be configured. Here, m and n are both natural numbers of 1 or more. Therefore, with such a configuration, a (n + m) order delta-sigma modulation circuit may be configured and used as a decimal part control circuit for a frequency synthesizer device.

【0131】

Seventh Embodiment. FIG. 15 is a block diagram showing a circuit configuration of a frequency synthesizer device according to a seventh embodiment of the present invention. In this embodiment, since the circuit configurations other than the decimal part control circuit 5f are the same as those shown in FIG. 1, the same components are numbered the same and detailed description thereof will be omitted. Further, the decimal part control circuit 5f shown in FIG. 15 replaces the second-order delta-sigma modulation circuit 200 and the second-order delta-sigma modulation circuit 220 of FIG. 14 with the circuit configuration shown in FIG. Omit. All the latches 304,306,307,324,326,327,310,341,343 in FIG. 15 correspond to delay circuits that delay the input data by one clock. Each circuit constituting the decimal part control circuit 5f is composed of a binary logic circuit, and a negative number is represented by a two's complement. The quantization step L is the data indicated by the power of 2.

【0132】

In FIG. 15, the decimal part control circuit 5f according to the seventh embodiment includes two second-order delta-sigma modulation circuits 300 and 320, a second-order differentiating circuit 340, a latch 310, and an adder 345. To. Here, the second-order delta sigma modulation circuit 300 is configured to include a second-order integrator 301 and a feedback circuit 302, and the second-order integrator 301 includes a first-order integrator 351 including an adder 303 and a latch 304. , A first-order integrator 352 composed of an adder 305 and a latch 306 is connected in series, and the feedback circuit 302 includes a latch 307, a double multiplier 308, and a subtractor 309. Further, the second-order delta sigma modulation circuit 320 includes a second-order integrator 321 and a feedback circuit 322, and the second-order integrator 321 includes a first-order integrator 353 including an adder 323 and a latch 324. It is configured by longitudinally connecting a first-order integrator 354 composed of an adder 325 and a latch 326, and a feedback circuit 322 includes a latch 327, a double multiplier 328, and a subtractor 329. Further, the second-order differentiating circuit 340 is configured by longitudinally connecting the first-order differentiating circuit 355 including the subtractor 342 and the latch 341 and the first-order differentiating circuit 356 including the subtractor 344 and the latch 343.

【0133】

The second-order delta-sigma modulation circuit 300 uses the quantization step L as the power of 2 data, and as a quantizer, simply performs the quantization step L or higher of the output data from the second-order integrator 301. It has a circuit configuration that selects only the high-order bits that indicate data. The data of the selected high-order bit is input to the feedback circuit 302 and fed back, becomes output data of the second-order delta-sigma modulation circuit 300, and is output to the adder 345 via the latch 310. Further, in FIG. 14, a simple circuit configuration in which the output data from the feedback circuit 302 is used as the upper bit, combined with the data of the fractional part F, and the combined data is used as the input data to the second-order adder 301, is shown in FIG. It achieves the same function as the multiplier 207 and the adder 208. Similarly, the second second-order delta-sigma modulation circuit 320 simply selects, as the quantizer, only the high-order bits indicating the data of the quantization step L or higher from the output data of the second-order integrator 321. Has a configuration. Here, the data of the selected high-order bit is input to the feedback circuit 322 and fed back, and becomes the output data of the second-order delta-sigma modulation circuit 320, which is input to the second-order differentiating circuit 340. Further, the output data from the feedback circuit 322 is used as the upper bit and is coupled to the input data of the second-order delta sigma modulation circuit 320 (the lower bit of the output data from the second-order integrator 301 of the second-order delta sigma modulation circuit 300). However, with a simple circuit configuration in which the combined data is used as the input data to the quadratic integrator 321, the same functions as the multiplier 227 and the adder 228 in FIG. 14 are realized.

【0134】

In the connection from the second-order delta-sigma modulation circuit 300 to the second second-order delta-sigma modulation circuit 320, among the output data from the latch 306 of the second-order integrator 301, the data of the lower bits less than the quantization step L are selected. By inputting to the quadratic integrator 321, the functions of the multiplier 211 and the subtractor 210 in FIG. 14 are realized. Further, the output data from the second differentiating circuit 340 is input to the adder 345, and the adder 345 adds the two input data and uses the data of the addition result as the data of the controlled fractional part F. Output to adder 6.

【0135】

According to the frequency synthesizer device of FIG. 15 configured as described above, the settable interval of the output signal frequency is limited to 1 / power of 2 of the reference signal frequency, and cannot be set to 1 / arbitrary integer. However, it is significant that the circuit configuration can be greatly simplified.

【0136】

In the circuit configuration of FIG. 15, the clock is the output of the variable frequency divider 2, but the reference signal may be the clock. Further, the rising or falling timings of the clocks of the second-order delta-sigma modulation circuit 300 and the second-order delta-sigma modulation circuit 320 can be set to different timings. This has the effect of preventing the phenomenon that when the circuits constituting the decimal part control circuit 5f operate at the same timing, the instantaneous operating current concentrates at that timing and a large power supply voltage fluctuation occurs. In addition to the method of simply delaying one clock out of a plurality of clocks to generate clocks with different timings, as a phase comparator 3, in a normal stable state, the output timing of the variable frequency divider 2 and the reference signal In the case of an exclusive logic sum circuit whose timings do not match, the second-order delta sigma modulation circuit 300 is operated with the reference signal as the first clock, and the output signal from the variable divider 2 is used as the second clock for the second-order delta. There is a way to operate the sigma modulation circuit 320. Further, instead, the latch 304 and the latch 324 may be configured to operate on the first clock, and the other circuits may be configured to operate on the second clock. In this case as well, the same effect can be obtained.

【0137】

Furthermore, among the output data of the latch 304, the latch 306, the latch 324, and the latch 326, the data having the number of bits indicating the data less than the quantization step L is configured to be sequentially set to the number of bits or less in the previous stage. can do. Here, the accuracy of the frequency division data is determined by the number of bits of the first adder 303 and latch 304. Therefore, the accuracy does not change even if the number of bits of the adder and the latch that follow is reduced. Therefore, by truncating the bit from the least significant bit (LSB) side, the quantization error due to truncation increases, but the circuit scale can be reduced. At this time, since the effect of the reduction is smaller in the later stages, the circuit scale can be significantly reduced in the later stages.

【0138】

In the above embodiment, the fractional control circuit 5f is composed of a binary logic circuit, and the bit length indicating the data less than the quantization step L of the integrator at the output terminal of the second-order integrator 321 is second-order. The output terminal of the integrator 301 is configured to be shorter than the bit length indicating the data less than the quantization step L of the integrator. Here, the accuracy of the frequency division data is determined by the number of bits of the output data of the first quadratic integrator 301. Therefore, even if the number of bits of the output data of the second-order integrator 321 that follows is reduced, the accuracy does not change. Therefore, by truncating the bit from the least significant bit (LSB) side, the quantization error due to truncation increases, but the circuit scale can be reduced. At this time, since the effect of the reduction is smaller in the later stages, the circuit scale can be significantly reduced in the later stages.

【0139】

Eighth Embodiment. FIG. 16 is a block diagram showing a circuit configuration of a wireless communication device according to the eighth embodiment of the present invention. In FIG. 16, the wireless communication device according to the present embodiment includes a reference oscillator 401, a frequency synthesizer device 402, a transmission circuit 403, a reception circuit 404, an antenna duplexer 405, and an antenna 406. .. Here, the frequency synthesizer device 402 is a frequency synthesizer device according to any one of the first to seventh embodiments described above.

【0140】

The reference oscillator 401 is a stable crystal oscillator that generates a reference signal and supplies it to the frequency synthesizer apparatus 402. The output signal of the frequency synthesizer device 402 is input to the transmission circuit 403 and the reception circuit 404 as a local oscillation signal. In the transmission circuit 403, the radio signal is frequency-converted (up-converted) to the upper frequency band using the local oscillation signal from the frequency synthesizer device 402, and the transmission circuit 403 is generated according to the input data signal. The radio signal is modulated, and the modulated radio signal is radiated from the antenna 406 toward the other party via the antenna duplexer 405. On the other hand, the radio signal received by the antenna 406 is input to the receiving circuit 404 via the antenna duplexer 405, and the receiving circuit 404 uses the local oscillation signal from the frequency synthesizer device 402 with respect to the input radio signal. Then, frequency conversion (down conversion) is performed to the lower frequency band, and the intermediate frequency signal after frequency conversion is demodulated into a data signal and output.

【0141】

In the wireless communication device configured as described above, the transmission circuit 403 and the reception circuit 404 transmit or receive each wireless signal on a frequency channel corresponding to the frequency of the local oscillation signal.

【0142】

Since the frequency synthesizer device 402 can set the output signal frequency with an accuracy of 1 / L of the reference signal frequency, it is possible to use a reference frequency higher than the interval between the transmission or reception frequency channels. Therefore, the response speed of the phase-locked loop of the PLL circuit is fast, and the switching time of the output frequency can be shortened. Further, the spurious appearing in the output signal of the frequency synthesizer device 402 can be significantly reduced.

【0143】

Generally, in a mobile communication system using a digital modulation method, when a slave station moves between a plurality of base stations, it is necessary to monitor frequencies other than the communication channel in order to observe the signal strength of the base station. There are many systems. Therefore, it is necessary to check other frequencies by utilizing the short free time between transmission and reception, and high-speed frequency switching is required. By using the frequency synthesizer device according to the present invention as a local oscillation signal source, a high-performance wireless communication device can be realized.

【0144】

Although the wireless communication device is described in the above embodiments, it may be a wired communication device that communicates by using a wired transmission method that is performed via a wired communication cable such as an optical fiber cable or a coaxial cable.

【0145】

Ninth Embodiment. FIG. 17 is a block diagram showing a circuit configuration of a frequency modulation device according to a ninth embodiment of the present invention. In FIG. 17, the same components as those in FIGS. 1 and 15 are numbered the same, and detailed description thereof will be omitted. As shown in FIG. 17, the frequency modulator of the present embodiment addser the input data to the decimal part control circuit 5 and the data of the decimal part F and the modulation data as compared with the frequency synthesizer device of FIG. The feature is that the data is added by 16. Here, the data of the decimal part F determines the center frequency of the output signal from VCO1, while the modulated data is the data for frequency-modulating the output signal. Here, the decimal part control circuit 5 may be a decimal part control circuit of any one of the decimal part control circuits 5 to 5f according to the first to seventh embodiments.

【0146】

In the frequency modulation device configured as described above, the output signal from VCO1 is frequency-modulated according to the modulation data input to the adder 16.

【0147】

Normally, in order to perform frequency modulation with a frequency synthesizer device, it is necessary to add an analog modulation signal to the reference signal or the control terminal of VCO1. However, in recent years, the digital modulation method has become the mainstream as the modulation method, and the modulation data is created by a digital circuit. Therefore, in order to perform modulation with a frequency synthesizer device as described above, it is necessary to convert digital modulation data into analog modulation data using a D / A converter and add it to a reference signal or a control terminal of VCO1. However, there are problems that the noise of the D / A converter is added and the signal transmission characteristics are easily deteriorated, and that the circuit scale is increased.

【0148】

As shown in FIG. 17, according to the method of using the frequency synthesizer device of the embodiment according to the present invention, the modulation data is added to the data of the decimal part F, and the data of the addition result is added to the decimal part control circuit 5. , It is only necessary to add the digital modulation data as the digital data to the data of the decimal part F. Therefore, a D / A converter is not required, the circuit configuration is simplified, and there is almost no deterioration in signal transmission characteristics.

【0149】

In the above embodiments, embodiments and modifications have been described, but the present invention is not limited to these individual detailed forms. For example, in the above embodiments, a second-order integrator or a third-order integrator is used, but a fourth-order or higher-order integrator may be used.

【0150】

[Effect of the invention]

As described in detail above, according to the present invention, in a frequency synthesizer device provided with a PLL circuit, a fractional part control circuit that controls input fractional data and outputs controlled fractional data, The input integer part data and the controlled fraction part data output from the fraction part control circuit are added, and the data of the addition result is used as the frequency division data of the variable divider of the PLL circuit. The fractional part control circuit is a plurality of nth-order delta sigma modulation circuits, and the input fractional part data is periodically changed, thereby according to the average data of the period. , Set the frequency of the output signal of the voltage control oscillator.

【0151】

Therefore, according to the present invention, by using a high-order delta-sigma modulation circuit, an output frequency can be set at frequency intervals finer than the reference frequency, and an output signal with significantly reduced unnecessary spurious can be obtained. It has a unique effect.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the circuit structure of the frequency synthesizer apparatus which is 1st Embodiment which concerns on this invention.

[Figure 2]

It is a block diagram which shows the circuit structure of the 2nd order integrator 7 of FIG.

[Fig. 3]

It is a block diagram which shows the circuit structure of the 2nd integrator 7a of a modification example which replaces the 2nd integrator 7 of FIG.

[Fig. 4]

It is a block diagram which shows the circuit structure of the decimal part control circuit 5a which is 2nd Embodiment which concerns on this invention.

[Fig. 5]

It is a block diagram which shows the circuit structure of the 2nd order integrator 7b of FIG.

[Fig. 6]

It is a block diagram which shows the circuit structure of the 2nd integrator 7c of a modification example which replaces the 2nd integrator 7b of FIG.

[Fig. 7]

It is a block diagram which shows the circuit structure of the 2nd integrator 7d of a modification example which replaces the 2nd integrator 7b of FIG.

[Fig. 8]

It is a block diagram which shows the circuit structure of the decimal part control circuit 5b which is the 3rd Embodiment which concerns on this invention.

[Fig. 9]

It is a block diagram which shows the circuit structure of the decimal part control circuit 5c which is the 4th Embodiment which concerns on this invention.

[Fig. 10]

It is a block diagram which shows the circuit structure of the decimal part control circuit 5d which is 5th Embodiment which concerns on this invention.

[Fig. 11]

It is a block diagram which shows the circuit structure of the 3rd order integrator 40 of FIG.

[Fig. 12]

It is a block diagram which shows the circuit structure of the 3rd order integrator 40a of a modification which replaces the 3rd order integrator 40 of FIG.

[Fig. 13]

It is a block diagram which shows the circuit structure of the 3rd order integrator 40b of a modification example which replaces the 3rd order integrator 40 of FIG.

[Fig. 14]

It is a block diagram which shows the circuit structure of the decimal part control circuit 5e which is the 6th Embodiment which concerns on this invention.

[Fig. 15]

It is a block diagram which shows the circuit structure of the frequency synthesizer apparatus which is 7th Embodiment which concerns on this invention.

[Fig. 16]

It is a block diagram which shows the circuit structure of the wireless communication apparatus which is 8th Embodiment which concerns on this invention.

[Fig. 17]

It is a block diagram which shows the circuit structure of the frequency modulation apparatus which is 9th Embodiment which concerns on this invention.

[Fig. 18]

It is a spectrum diagram which shows the frequency characteristic of the delta sigma modulation circuit which concerns on embodiment.

[Fig. 19]

It is a block diagram which shows the circuit structure of the frequency synthesizer apparatus of the prior art.

[Fig. 20]

It is a block diagram which shows the detailed structure of the decimal part control circuit 80 of FIG.

[Fig. 21]

It is a timing chart showing the operation of the frequency synthesizer device of FIG. 19, (a) is a timing chart showing the temporal change of the number of divisions input to the variable frequency divider 2, and (b) is a timing chart to VCO1. It is a timing chart which shows the time change of a control voltage.

[Fig. 22]

It is a spectrum diagram which shows the frequency characteristic of the output signal from VCO1 of FIG.

[Fig. 23]

It is a spectrum diagram which shows the frequency characteristic of the control voltage to VCO1 of FIG.

[Explanation of symbols]

1 ... voltage controlled oscillator, 2 ... Variable divider, 3 ... Phase comparator, 4 ... Low-pass filter, 5,5a, 5b, 5c, 5d, 5e, 5f ... decimal control circuit, 6 ... adder, 7,7a, 7b, 7c, 7d, 7e, 7f ... 2nd order integrator, 8 ... Quantizer, 9,9a ... feedback circuit, 10,11,22,24,32,32a, 33 ... Delay circuit, 12,34 ... 2x multiplier, 13,35 ... subtractor, 14 ... multiplier, 15,16,21,23,31 ... adder, 30,30a ... Composite delay circuit, 40,40b ... 3rd order integrator, 41 ... feedback circuit, 42,43,44 ... Delay circuit, 45,46 ... 3x multiplier, 47,48 ... subtractor, 51,53,55 ... adder, 52,54,56,57,58 ... Delay circuit, 59 ... 2x multiplier, 60 ... subtractor, 71,79 ... adder, 72,73,74,75 ... Delay circuit, 76,77 ... 3x multiplier, 78 ... subtractor, 101,102,111,112,113 ... First-order integrator, 114 ... 2nd order integrator, 200,220 ... 2nd order delta sigma modulation circuit, 201,221 ... 2nd order integrator, 202,222 ... Quantizer, 203,223 ... Feedback circuit, 204,209,224 ... Delay circuit, 205,225 ... 2x multiplier, 206,210,226 ... subtractor, 207,211,227 ... Multiplier, 208,228 ... adder, 230 ... 2nd differentiating circuit, 231,233 ... Delay circuit, 232,234 ... subtractor, 240 ... adder, 241,242 ... 1st order differentiating circuit, 300,320 ... 2nd order delta sigma modulation circuit, 301,321 ... 2nd order integrator, 302 ... feedback circuit, 303,305,323,325,345 ... adder, 304,306,307,310,324,326,327 ... Latch, 308,328 ... 2x multiplier, 309,329 ... subtractor, 340 ... 2nd differentiating circuit, 341,343 ... Latch, 342,344 ... subtractor, 345 ... adder, 351,352,353,354 ... 1st order integrator, 355,356 ... 1st order differentiating circuit, 401 ... reference oscillator, 402 ... Frequency synthesizer device, 403 ... Transmit circuit, 404 ... receiver circuit, 405 ... Antenna commoner, 406 ... Antenna.