Solid-state image pickup element and its manufacturing method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a solid-state image sensor and a method for manufacturing the same, and more particularly to a solid-state image sensor and a method for manufacturing the same, which can obtain high sensitivity even when the unit pixel size is reduced by increasing the conversion efficiency of the output circuit.

【0002】

[Conventional technology]

FIG. 1 shows an overall view of a conventional CCD solid-state image sensor. As shown in FIG. 1, the CCD solid-state image sensor is transferred from a photosensor 101 that receives incident light and performs photoelectric conversion, an imaging region 103 including a vertical transfer CCD register (V register) 102, and a V register 102. It has a horizontal transfer CCD register (H register) 105 that transfers a signal charge to the output circuit 104. The unit pixel 107 is formed by the photosensor 101, the V register 102, and the read gate 106 formed between them.

【0003】

At present, in a CCD solid-state image sensor, it is strongly desired to reduce the size of the optical system, that is, the chip size, and to increase the number of pixels. If an attempt is made to reduce the size of the optical system without reducing the unit pixel size, the number of pixels must be reduced, which causes a problem of reduction in resolution. Further, if an attempt is made to increase the number of pixels without reducing the unit pixel size, it is inevitable that the optical system will be expanded and the manufacturing cost will increase accordingly. Therefore, in order to reduce the size of the optical system while maintaining the resolution, or to realize the increase in the number of pixels without increasing the manufacturing cost, it is the most effective means to reduce the unit pixel size.

【0004】

However, when the unit pixel size is simply reduced, the amount of incident light per unit area does not change, so that the sensitivity decreases substantially in proportion to the unit pixel size. In addition, the amount of saturation signal and the amount of electric charge handled in the vertical transfer register (V register) also decrease in proportion to the unit pixel size.

【0005】

As a method of improving the sensitivity, a method of changing or optimizing the structure on the sensor to improve the light collection efficiency of the incident light can be considered. Further, it is conceivable to change the structure of the output circuit built in the CCD solid-state image sensor to improve the conversion efficiency. Here, the conversion efficiency is a value indicating how many volts a single signal electron can be converted into.

【0006】

As a method of increasing the saturation signal amount, for example, a method of increasing the potential of the sensor unit that accumulates the signal charge obtained by photoelectrically converting the incident light can be considered. Alternatively, a method of forming the sensor portion near the surface of the silicon substrate can be considered. Further, a method of increasing the conversion efficiency of the output circuit is also conceivable.

【0007】

However, if the potential of the sensor portion is deepened or the sensor portion is formed near the surface of the silicon substrate, the electric field at the pn junction of the sensor becomes large. As a result, there is a problem that electron-hole pairs are generated and the noise component increases.

【0008】

As a method of increasing the amount of electric charge handled by the V register, for example, a method of increasing the potential of the V register can be considered in the same manner as the method of increasing the saturation signal amount. Alternatively, a method of forming a signal charge transfer region near the surface of the silicon substrate can be considered. Further, a method of increasing the conversion efficiency of the output circuit can be considered. Further, a method of increasing the capacitance by thinning the insulating film formed between the transfer gate of the V register and the silicon substrate is also conceivable.

【0009】

However, if the potential of the V register is deepened or the signal charge transfer region is formed near the surface of the silicon substrate, the electric field near the surface of the silicon substrate becomes large, and unnecessary electron-hole pairs are generated to generate noise. There is a problem that the components increase. Further, the thinning of the insulating film formed between the transfer gate and the silicon substrate causes a decrease in the withstand voltage, so that there is a limit to the thinning of the insulating film.

【0010】

In order to solve the above-mentioned problems associated with the reduction of the unit pixel size at the same time, it is most effective to improve the conversion efficiency. When the conversion efficiency is increased, a large output can be obtained with a small amount of signal charge. Therefore, the amount of saturation signal and the amount of charge handled by the V register can be increased to increase the sensitivity of the solid-state image sensor.

【0011】

The circuit diagram of the output circuit 104 part of the CCD solid-state image sensor shown in FIG. 1 is shown in FIG. As shown in FIG. 2, the output circuit of the CCD solid-state image sensor is formed with a three-stage source follower amplifier in which a set of drive transistors 21 and a constant current transistor 22 are used as a one-stage source follower amplifier.

【0012】

Conventionally, various methods have been tried for the purpose of improving the conversion efficiency of the output circuit. For example, in the MOS transistor constituting the CCD solid-state image sensor output circuit of FIG. 2, there is a method of reducing the gate width and / or the gate length. FIG. 9 shows a top view of the source region S, drain region D, and gate electrode G of the MOS transistor, which is the drive transistor 21 of the first-stage source follower amplifier surrounded by the broken line in FIG.

【0013】

FIG. 9 (a) shows the case where the gate width (W) and / or the gate length (L) is relatively large, and FIG. 9 (b) shows the case where the gate width (W) and / or the gate length (L) is relative. Shows a small case. The conversion efficiency is higher in the case of FIG. 9 (b) than in the case of FIG. 9 (a).

【0014】

Further, as shown in FIGS. 10A to 10D, the conversion efficiency is also improved by reducing the area of the Al wiring 23 in the floating diffusion layer 9 (floating diffusion; FD). A cross-sectional view of X-X'in FIG. 10 (a) is shown in FIG. 10 (c), and a cross-sectional view of X-X'in FIG. 10 (b) is shown in FIG. 10 (d).

【0015】

As shown in FIGS. 10 (c) and 10 (d), a floating diffusion layer 9 containing an n-type impurity is formed on the surface layer portion of the silicon substrate 1. In the floating diffusion layer 9, the signal charge transferred from the H register is voltage-converted. A gate electrode 12 is formed on the upper part of the silicon substrate 1 via an insulating film (gate oxide film) 4.

【0016】

An interlayer insulating film 24 made of, for example, a BPSG (borophosphosilicate glass) film or a PSG (phosphosilicate glass) film is formed on the gate electrode 12 or on the silicon substrate 1 via the insulating film 4. A contact hole 25 is formed in the interlayer insulating film 24. The Al wiring 23 is formed in the contact hole 25 and on the interlayer insulating film 24 around the contact hole 25, and connects the floating diffusion layer 9 formed on the surface of the silicon substrate 1 and the gate electrode 12 made of polysilicon.

【0017】

10 (a) and 10 (c) show the case where the area of the Al wiring 23 seen from the upper surface is relatively large, and FIGS. 10 (b) and 10 (d) show the relative area of the Al wiring 23 seen from the upper surface. Shows a small case. Compared with the cases of FIGS. 10 (a) and 10 (c), in the cases of FIGS. 10 (b) and 10 (d), the parasitic capacitance between the Al wiring 23 and the interlayer insulating film 24 is small, and the conversion efficiency is high.

【0018】

Furthermore, as shown in FIGS. 11 (a) and 11 (b), n⁺The conversion efficiency can also be increased by reducing the area of the floating diffusion layer 9, which is a diffusion layer. The cross-sectional view of FIG. 11 has the same configuration as that of FIGS. 11 (c) and 11 (d). FIG. 11A shows a case where the area of the floating diffusion layer 9 is relatively large, and FIG. 11B shows a case where the area of the floating diffusion layer 9 is relatively small. The floating diffusion layer (n) in the case of FIG. 11 (b) as compared with the case of FIG. 11 (a).⁺Diffusion layer) 9 has a smaller parasitic capacitance and higher conversion efficiency.

【0019】

A cross-sectional view including the source / drain region and the gate electrode of the conventional output circuit MOS transistor is shown in FIG. 12 (a). As shown in FIG. 12 (a), the p-well 2 is formed on the surface layer portion of the n-type silicon substrate 1. An n-type drain region 13 and an n-type source region 14 are formed on the surface layer of the p-well 2. A gate electrode 12 is formed on the n-type silicon substrate 1 between the n-type drain region 13 and the n-type source region 14 via a gate oxide film 4.

【0020】

The method for forming the above MOS transistor will be described below with reference to FIGS. 12 and 13. First, as shown in FIG. 12 (b), p-type impurities are diffused on the surface portion of the n-type silicon substrate 1 to form p-well 2. Further, the element separation region 15 is formed by, for example, selectively oxidizing the surface of the silicon substrate 1 other than the active region. Further, a silicon oxide film to be a gate oxide film 4 is formed on the n-type silicon substrate 1 on which the p-well 2 is formed.

【0021】

Next, as shown in FIG. 12 (c), a polysilicon layer 12a to be a gate electrode 12 or a transfer electrode (not shown) is formed on the upper layer of the gate oxide film 4. Subsequently, as shown in FIG. 12 (d), the polysilicon layer 12a is etched using a resist (not shown) as a mask to form a gate electrode 12 and a transfer electrode.

【0022】

Next, as shown in FIG. 13 (a), the surfaces of the gate electrode 12 and the transfer electrode made of polysilicon are oxidized to form the insulating film 16. At this time, the oxide film 16 is also formed on the surface of the source / drain forming region of the MOS transistor. Therefore, as shown in FIG. 13 (b), light etching using, for example, hydrofluoric acid (HF) is performed to remove the oxide film 16 on the source / drain forming region.

【0023】

Subsequently, as shown in FIG. 13 (c), the surface of the silicon substrate 1 is oxidized again to form an oxide film 17 having a desired film thickness and film quality. Then, as shown in FIG. 13 (d), the n-type source region 14 and the n-type drain region 13 are formed by ion-implanting the n-type impurities and then thermally diffusing the n-type impurities.

【0024】

[Problems to be Solved by the Invention]

However, as shown in FIG. 9, if the gate width (W) and gate length (L) of the MOS transistor are reduced, the conversion efficiency is improved, but there is a problem that 1 / f noise increases and a short channel effect occurs. .. Therefore, it is difficult to reduce the gate width (W) and gate length (L) of the MOS transistor from the current size.

【0025】

Further, as shown in FIG. 10, when the area of the Al wiring 23 connected to the floating diffusion layer 9 is reduced, the contact hole 25 of the floating diffusion layer 9 and the Al wiring 23 can be aligned with high accuracy. It will be difficult. The Al wiring 23 of the floating diffusion layer 9 is formed by depositing the Al film on the interlayer insulating film 24 including the inside of the contact hole 25 and then etching the Al film.

【0026】

When the Al wiring is miniaturized, it becomes difficult to perform alignment with high accuracy in the lithography process for forming the etching mask. Therefore, it is difficult to reduce the Al wiring to the current size or less while preventing the connection failure of the Al wiring.

【0027】

Further, as shown in FIG. 11, n of the floating diffusion layer 9⁺Even when the area of the diffusion layer is reduced, n⁺It becomes difficult to align the diffusion layer with the contact hole 25, and n⁺The reliability of the electrical connection between the diffusion layer and the contact hole is reduced. Further, as the area of the floating diffusion layer is reduced, the contact holes also need to be miniaturized. At present, the aspect ratio of the contact hole of the floating diffusion layer is reduced to about 1, and if the contact hole diameter is further reduced, Al wiring cannot be formed in the contact hole with good coverage. This causes n⁺The reliability of the electrical connection between the diffusion layer and the Al wiring is reduced. Therefore, the floating diffusion layer (n)⁺It is also difficult to reduce the area of the diffusion layer) to less than the current size.

【0028】

As described above, since there is no effective means for improving the conversion efficiency beyond the current level, the conversion efficiency of the output circuit has reached a plateau at present. As described above, the sensitivity, the amount of saturation signal, and the amount of electric charge handled cannot be increased at the same time unless the conversion efficiency of the output circuit is improved.

【0029】

In order to reduce the unit pixel size of the CCD solid-state image sensor to reduce the size of the optical system and increase the number of pixels, it is necessary to increase the sensitivity, the amount of saturation signals, and the amount of electric charge handled by the register. Therefore, in a CCD solid-state image sensor, a means for improving the conversion efficiency of an output circuit without deteriorating other characteristics is strongly desired.

【0030】

According to the above-mentioned conventional output circuit MOS transistor forming method, as shown in FIG. 12A, the gate electrode 12 and the n-type drain region 13 having a high impurity concentration are formed at a very short distance L1. .. Therefore, the parasitic capacitance between the gate electrode 12 and the drain region is large, and the withstand voltage is low.

【0031】

The present invention has been made in view of the above problems. Therefore, the present invention is a solid-state image sensor in which sensitivity, saturation signal amount, and handling charge amount are increased by improving the conversion efficiency of the output circuit. It is an object of the present invention to provide a manufacturing method.

【0032】

[Means for solving problems]

In order to achieve the above object, in the solid-state imaging device of the present invention, a plurality of light receiving units that receive light incident and photoelectrically convert the light into an electric signal, a floating diffusion layer that receives the electric signal, and the floating diffusion layer. A solid-state imaging device in which a source follower amplifier having a drive transistor and a constant current transistor for detecting a change in the potential of the source follower is integrated, and the drive transistor of the source follower amplifier is a boundary portion between a gate electrode and a drain region. In the above, a part of the gate electrode including the side surface of the gate electrode and a part of the drain region are covered with an insulating film, and the drain region below the insulating film is not formed with the insulating film. It is characterized in that it is a region containing impurities having a relatively low concentration as compared with the drain region of the portion.

【0033】

The solid-state image sensor of the present invention is preferably characterized in that the drain region under the insulating film covering the side surface of the gate electrode is a region into which the impurities are not introduced. In the solid-state image sensor of the present invention, preferably, the source follower amplifier is a multi-stage source follower amplifier in which a plurality of one-stage source follower amplifiers having one drive transistor and one constant current transistor are connected, and the insulation thereof. The drain region containing the film and low-concentration impurities is formed in the drive transistor of the first-stage source follower amplifier closest to the floating diffusion layer.

【0034】

The solid-state imaging device of the present invention is preferably characterized in that the insulating film is a silicon nitride film. The solid-state image sensor of the present invention preferably has a low-reflection film on the light-receiving portion that reduces the reflectance of the surface, and the low-reflection film and the insulating film are made of the same layer. ..

【0035】

As a result, in the source follower amplifier of the output circuit of the solid-state image sensor, the parasitic capacitance between the gate electrode and the drain region of the drive transistor can be reduced, and the withstand voltage of the transistor can be improved. Therefore, the conversion efficiency of the output circuit can be improved, and the characteristics such as the sensitivity and the signal saturation amount of the solid-state image sensor can be improved. Further, by improving the conversion efficiency of the output circuit, the unit pixel size can be reduced, so that the optical system can be reduced and the number of pixels can be increased.

【0036】

Further, in order to achieve the above object, the method for manufacturing a solid-state imaging device of the present invention includes a plurality of light receiving units that receive light incident and photoelectrically convert the light into an electric signal, and a floating diffusion layer that receives the electric signal. A method for manufacturing a solid-state imaging device in which a source follower amplifier having a drive transistor and a constant current transistor for detecting a potential change in the floating diffusion layer is integrated, and the step of forming the drive transistor is a source. A step of forming a gate electrode on the substrate between the forming region and the drain forming region, a part of the gate electrode including the side surface of the gate electrode at the boundary portion between the gate electrode and the drain forming region, and the above. The step of forming an insulating film that covers a part of the drain forming region and the drain forming of the source forming region and the portion where the insulating film is not formed by introducing impurities into the substrate via the insulating film. A step of forming a source region and a drain region each containing a relatively high concentration of impurities in the region, and forming a low concentration drain region containing a relatively low concentration of impurities in the drain forming region under the insulating film. It is characterized by having and.

【0037】

The method for manufacturing a solid-state image sensor of the present invention is preferably characterized in that the impurities are not introduced into the drain forming region under the insulating film that covers the side surface of the gate electrode. According to the method for manufacturing a solid-state image sensor of the present invention, preferably, the source follower amplifier is a multi-stage source follower amplifier in which a plurality of one-stage source follower amplifiers having one drive transistor and one constant current transistor are connected. The insulating film and the low-concentration drain region are formed on the drive transistor of the first-stage source follower amplifier closest to the floating diffusion layer.

【0038】

The method for manufacturing a solid-state image sensor of the present invention is preferably characterized in that the insulating film is a silicon nitride film. The method for manufacturing a solid-state image sensor of the present invention preferably includes a step of forming a low-reflection film for reducing the reflectance of the surface on the light-receiving portion, and forming the low-reflection film and the insulating film. Is characterized in that it is carried out in the same process.

【0039】

This makes it possible to form a drive transistor in the source follower amplifier of the output circuit of the solid-state image sensor, in which the parasitic capacitance between the gate electrode and the drain region is reduced and the withstand voltage is improved. Therefore, it is possible to manufacture a solid-state image sensor in which the conversion efficiency of the output circuit is improved and the characteristics such as sensitivity and signal saturation are improved. Further, since the unit pixel size can be reduced by improving the conversion efficiency of the output circuit, it is possible to form a solid-state image sensor in which the optical system is reduced or the number of pixels is increased.

【0040】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the solid-state image sensor of the present invention and the method for manufacturing the same will be described with reference to the drawings. (Embodiment 1) FIG. 1 is an overall view of the CCD solid-state image sensor of the present embodiment. The CCD solid-state image sensor shown in FIG. 1 has an imaging region 103 consisting of a photosensor 101 that receives incident light and performs photoelectric conversion, a vertically transferred CCD register (V register) 102, and a signal transferred from the V register 102. It has a horizontal transfer CCD register (H register) 105 that transfers a charge to the output circuit 104. The unit pixel 107 is formed by the photosensor 101, the V register 102, and the read gate 106 formed between them.

【0041】

The circuit diagram of the output circuit 104 part of the CCD solid-state image sensor shown in FIG. 1 is shown in FIG. As shown in FIG. 2, the output circuit of the CCD solid-state image sensor is formed with a three-stage source follower amplifier in which a set of drive transistors 21 and a constant current transistor 22 are used as a one-stage source follower amplifier.

【0042】

FIG. 3 is a cross-sectional view and a circuit diagram of the CCD solid-state image sensor shown in FIG. 1 from the H register 105 to the output circuit 11. The structure from the final stage of the H register to the output circuit in the CCD solid-state image sensor will be described with reference to FIG. As shown in FIG. 3, a p-well 2 containing a p-type impurity is formed on the surface portion of the n-type silicon substrate 1, and a transfer channel region 3 of an embedded CCD is formed in the p-well 2. Transfer electrodes 5 and 6, an output gate electrode 7 and a reset gate electrode 8 are formed on the p-well 2 via an insulating film (gate oxide film) 4. The output gate electrode 7 is grounded.

【0043】

By applying the transfer pulses Hφ1 and Hφ2 to the transfer electrodes 5 and 6, respectively, the signal charge is transferred from the B side to the A side in the transfer channel region 3. The signal charge transferred from the B side to the A side passes through the lower part of the output gate electrode 7 and is converted into a voltage by the output circuit through the floating diffusion layer (FD) 9. After that, when a high level pulse voltage is applied to the reset gate electrode 8, the signal charge converted into the voltage is discharged to the reset drain region 10 to which the VRG voltage is applied.

【0044】

Assuming that the amount of signal charge transferred to the floating diffusion layer 9 is Q and the capacity of the floating diffusion layer is C, the voltage change amount V of the floating diffusion layer 9 is represented by V = Q / C. This voltage change amount V is obtained as an output voltage VOUT through the output circuit 11 which is a three-stage source follower amplifier circuit. The smaller the floating diffusion layer capacitance C, the higher the conversion efficiency from charge to voltage, so the voltage change amount V becomes larger and the VOUT change amount also becomes larger. That is, a large output voltage can be obtained from a small amount of signal charge.

【0045】

This stray diffusion layer capacitance C is a parasitic capacitance C1 between the stray diffusion layer 9 and the reset gate electrode 8, a parasitic capacitance C2 between the stray diffusion layer 9 and the output gate electrode 7, a stray diffusion layer 9 and a p-well. The parasitic capacitance C4, which is the parasitic capacitance C4 that the Al wiring that connects the stray diffusion layer 9 and the gate electrode of the first stage drive MOS transistor M1 between the silicon substrate and nearby metal wiring, insulating film, output gate electrode, etc. It is represented by the sum of the parasitic capacitance C5 between the gate electrode and drain region of the drive MOS transistor M1 and the parasitic capacitance C6 between the gate electrode and source region of the first stage drive MOS transistor M1.

【0046】

According to the CCD solid-state image sensor of the present embodiment, the conversion efficiency is improved by reducing the parasitic capacitance C5 between the gate electrode and the drain region of the first-stage drive transistor M1 described above, and at the same time, the gate electrode and the drain region. The withstand voltage between and can be improved.

【0047】

In the source follower amplifier, the source terminals of the drive transistors M1, M3, and M5 are connected to the drain terminals of the constant current transistors M2, M4, and M6, respectively. Assuming that the amplification factor of the source follower amplifier in the first stage is A, the input capacitance CIN is CIN = C5 + C6 (1-A) (1) It is expressed as.

【0048】

Here, since A is generally very close to 1, the second term of Eq. (1) can be almost ignored. Therefore, CIN depends almost entirely on C5, that is, the parasitic capacitance between the gate electrode and the drain region of the first-stage drive transistor M1. Therefore, in order to reduce the input capacitance, it is desirable to make the parasitic capacitance C5 between the gate electrode and the drain region of the first stage drive transistor M1 as small as possible.

【0049】

FIG. 4A shows a cross-sectional view of the output circuit MOS transistor of the CCD solid-state image sensor of this embodiment. The MOS transistor shown in FIG. 4A has an insulating film 18 having a shape that covers a part 13a of the drain region and a side surface and a part of the gate electrode 12. As the insulating film 18, for example, a silicon nitride film is used.

【0050】

A relatively high concentration of n-type impurities is diffused in the n-type drain region 13b of the portion where the silicon nitride film is not formed. On the other hand, the n-type drain region under the insulating film 18 is a low-concentration n-type drain region 13a in which relatively low-concentration n-type impurities are diffused.

【0051】

Further, since almost no n-type impurities are introduced into the lower portion of the insulating film 18 that covers the side surface of the gate electrode 12, the n-type impurity concentration is further lower than that of the low-concentration n-type drain region 13a. Therefore, in the MOS transistor shown in FIG. 4A, the distance between the gate electrode 12 and the n-type drain regions 13a and 13b is substantially represented by L2.

【0052】

As described above, the output circuit MOS transistor of the CCD solid-state image sensor of the present embodiment has a low impurity concentration in the drain region near the gate electrode and a large distance between the gate electrode and the drain region. As a result, the parasitic capacitance between the gate electrode and the drain region is reduced, and the withstand voltage of the MOS transistor is improved. Therefore, the conversion efficiency of the output circuit can be improved without deteriorating other characteristics of the CCD solid-state image sensor. That is, it is possible to reduce the size and increase the number of pixels of the CCD solid-state image sensor.

【0053】

Hereinafter, a method of forming an output circuit MOS transistor having the above structure will be described with reference to the drawings. First, as shown in FIG. 4 (b), p-type impurities are diffused on the surface portion of the n-type silicon substrate 1 to form p-well 2. Further, the element separation region 15 is formed by, for example, selectively oxidizing the surface of the silicon substrate 1 other than the active region. A silicon oxide film to be a gate oxide film 4 is formed on the n-type silicon substrate 1 on which the p-well 2 is formed.

【0054】

Subsequently, as shown in FIG. 4C, a polysilicon layer 12a to be a gate electrode 12 or a transfer electrode (not shown) is formed on the upper layer of the gate oxide film 4. Then, as shown in FIG. 5A, the polysilicon layer 12a is etched using a resist (not shown) as a mask to form a gate electrode 12 and a transfer electrode.

【0055】

Next, as shown in FIG. 5 (b), the surfaces of the gate electrode 12 and the transfer electrode made of polysilicon are oxidized to form the insulating film 16. At this time, the oxide film 16 is also formed on the surface of the source / drain forming region of the MOS transistor. Therefore, as shown in FIG. 5 (c), for example, light etching using hydrofluoric acid (HF) is performed to remove the oxide film 16 on the surfaces of the source / drain regions 13 and 14. Subsequently, as shown in FIG. 5D, the surface of the silicon substrate 1 is oxidized again to form an oxide film 17 having a desired film thickness and film quality.

【0056】

Next, as shown in FIG. 6A, the silicon nitride film 18a is deposited by, for example, the CVD method. Subsequently, as shown in FIG. 6 (b), the silicon nitride film 18a is etched to form a silicon nitride film 18 having a shape that covers a part of each of the n-type drain forming region and the gate electrode 12.

【0057】

Next, as shown in Fig. 6 (c), the film thickness is t.₁N-type impurities are ion-implanted through the oxide film 17 which is. As a result, a high concentration of n-type impurities is ion-implanted into the n-type drain forming region and the n-type source forming region in the portion where the silicon nitride film 18 is not formed. After ion implantation, the impurities are thermally diffused to form the n-type drain region 13b and the n-type source region 14.

【0058】

On the other hand, only the ions that have passed through the silicon nitride film 18 and the oxide film 17 are injected into the n-type drain forming region of the portion where the silicon nitride film 18 is formed. As shown in Fig. 6 (c), the total film thickness is t₂(t₂> t₁), Ion implantation is performed through the insulating film. As a result, a lower concentration of n-type impurities is introduced as compared with the n-type drain region 13b. After ion implantation, the impurities are thermally diffused to form a low-concentration n-type drain region 13a having a lower n-type impurity concentration than the n-type drain region 13b.

【0059】

According to the above-mentioned method for forming a MOS transistor, an n-type drain region 13a having a reduced impurity concentration can be formed in the vicinity of the gate electrode 12, so that the short-channel effect of the MOS transistor can be prevented. Further, as shown in FIG. 4A, the distance L2 between the gate electrode 12 and the n-type drain region 13 can be made larger than that of the conventional structure, so that the parasitic capacitance between the gate electrode 12 and the n-type drain region 13 is large. Can be reduced and the withstand voltage between the gate electrode and the drain region can be improved.

【0060】

According to the method for manufacturing a solid-state image sensor of the present embodiment, a MOS transistor having a reduced parasitic capacitance and an improved withstand voltage can be formed in the output circuit, so that a solid-state image sensor with improved conversion efficiency can be manufactured. It becomes possible. Therefore, it is possible to manufacture a solid-state image sensor in which the optical system is miniaturized and the number of pixels is increased.

【0061】

(Embodiment 2) The solid-state image sensor of the present embodiment has the MOS transistor shown in the first embodiment in the output circuit, and further has a silicon nitride film as a low reflection film in the photo sensor. As a result, the amount of light incident on the light receiving portion can be increased.

【0062】

Similar to the solid-state image sensor of the first embodiment shown in FIG. 1, the solid-state image sensor of the present embodiment includes a photo sensor 101 that receives incident light and performs photoelectric conversion, and an image pickup region 103 including a V register 102. It has an H register 105 that transfers the signal charge transferred from the V register 102 to the output circuit 104. The unit pixel 107 is formed by the photosensor 101, the V register 102, and the read gate 106 formed between them.

【0063】

FIG. 7 shows an enlarged view of the imaging region of the solid-state image sensor of the present embodiment. The photosensor 101 in the imaging region is provided with an opening 109 in a light-shielding film 108 made of Al or the like. Further, transfer electrodes 110a and 110b for reading and transferring the photoelectrically converted signal are formed. Low-reflection films 111a, 111b, 111c, and 111d, which are made of a silicon nitride film and prevent reflection of incident light, are formed on the upper portion of each opening 109.

【0064】

FIG. 8 shows a cross-sectional view of the opening 107. As shown in FIG. 8, the transfer electrode 110 is formed on the silicon substrate 1 via the insulating film 4. The transfer electrode 110 is covered with an interlayer insulating film 112. Low-reflection films 111a, b, c, and d, which are made of a silicon nitride film and prevent reflection of incident light, are formed on the interlayer insulating film 112 of the opening 109. An insulating film 114 that flattens the surface is formed on the upper layer via the protective film 113. An on-chip lens 116 is formed on the insulating film 114 via a color filter 115.

【0065】

A magenta, cyan, yellow, or green color filter 115 is formed in each opening 107. The film thickness and the refractive index of the low-reflection films 111a, b, c, and d of each opening 107 may be adjusted to different values corresponding to the four colors of the color filter 115.

【0066】

As described above, a solid-state image sensor whose sensitivity is improved by forming a low-reflection film at the opening of the photosensor is described in Japanese Patent Application Laid-Open No. 10-256518. In the solid-state image sensor of the first embodiment, the silicon nitride film that covers a part of each of the gate electrode and the drain region of the output circuit is a process common to the low-reflection film formed in the photosensor of the solid-state image sensor of the present embodiment. It is possible to form with.

【0067】

According to the solid-state image sensor of the present embodiment described above, the sensitivity of the solid-state image sensor can be further improved by improving the conversion efficiency in the output circuit and increasing the amount of incident light. Further, according to the above-mentioned manufacturing method of the solid-state image sensor of the present embodiment, a silicon nitride film covering the boundary portion between the gate electrode and the drain region of the MOS transistor of the output circuit and a low reflection film are formed on the light receiving portion. Since the silicon nitride film can be formed by a common process, it is possible to avoid an increase in the number of manufacturing steps.

【0068】

Embodiments of the solid-state image sensor of the present invention and a method for manufacturing the same are not limited to the above description. For example, the silicon nitride film that covers a part and the side surface of the gate electrode of the drive transistor formed in the source follower amplifier and the low concentration drain region can be changed to an insulating film made of another material. In addition, various modifications can be made without departing from the gist of the present invention.

【0069】

[Effect of the invention]

According to the solid-state image sensor of the present invention, in the source follower amplifier of the output circuit, the parasitic capacitance between the gate electrode and the drain region of the drive transistor can be reduced, and the withstand voltage of the transistor can be improved. Therefore, the conversion efficiency of the output circuit of the solid-state image sensor can be improved, and the characteristics such as the sensitivity and signal saturation of the solid-state image sensor can be improved.

【0070】

Further, according to the method for manufacturing a solid-state image sensor of the present invention, it is possible to form a drive transistor in which the parasitic capacitance between the gate electrode and the drain region is reduced and the withstand voltage is improved in the source follower amplifier. Therefore, the conversion efficiency of the output circuit can be improved. As a result, the unit pixel size can be reduced, so that it is possible to manufacture a solid-state image sensor in which the optical system is reduced and the number of pixels is increased.

[Simple explanation of drawings]

[Figure 1]

It is the schematic which shows the whole of this invention and the conventional solid-state image sensor.

[Figure 2]

It is a figure which shows the output circuit of this invention and the conventional solid-state image sensor.

[Fig. 3]

A cross-sectional view and a circuit diagram from the H register of the solid-state image sensor of the present invention to the output circuit are shown.

[Fig. 4]

(a) is a cross-sectional view of a driving MOS transistor of an output circuit of a solid-state image sensor according to the first embodiment of the present invention, and (b) and (c) are cross-sectional views showing a manufacturing process of the manufacturing method.

[Fig. 5]

(a) to (d) are cross-sectional views showing a manufacturing process of a driving MOS transistor of an output circuit in the method of manufacturing a solid-state image sensor according to the first embodiment of the present invention.

[Fig. 6]

(a) to (c) are cross-sectional views showing the manufacturing process of the driving MOS transistor of the output circuit in the manufacturing method of the solid-state image sensor according to the first embodiment of the present invention.

[Fig. 7]

It is an enlarged view of the image pickup area of the solid-state image pickup device which concerns on Embodiment 2 of this invention.

[Fig. 8]

It is sectional drawing around the opening of the image pickup region of the solid-state image pickup device which concerns on Embodiment 2 of this invention.

[Fig. 9]

It is a top view of a MOS transistor for explaining the conventional method for improving the conversion efficiency of the output circuit of a solid-state image sensor, (a) is the gate length and / or when the gate width is large, (b) is the gate length. And / or when the gate width is small.

[Fig. 10]

Top views ((a), (b)) and cross-sectional views ((b) and (d)) of a MOS transistor for explaining a conventional method for improving the conversion efficiency of an output circuit of a solid-state image sensor. (a) and (c) indicate that the area of the Al wiring is large, and (b) and (d) indicate that the area of the Al wiring is small.

[Fig. 11]

It is sectional drawing of the MOS transistor for demonstrating the conventional method for improving the conversion efficiency of the output circuit of a solid-state image sensor. The case where the area is small is shown.

[Fig. 12]

(a) is a cross-sectional view of a driving MOS transistor of an output circuit of a conventional solid-state image sensor, and (b) to (d) are cross-sectional views showing a manufacturing process of the manufacturing method.

[Fig. 13]

(a) to (d) are cross-sectional views showing a manufacturing process of a driving MOS transistor of an output circuit in a conventional manufacturing method of a solid-state image sensor.

[Explanation of symbols]

1 ... n-type silicon substrate, 2 ... p well, 3 ... transfer channel region, 4 ... insulating film (gate oxide film), 5, 6 ... transfer electrode, 7 ... output Gate electrode, 8 ... reset gate electrode, 9 ... floating diffusion layer, 10 ... reset drain region, 11 ... output circuit, 12 ... gate electrode, 12a ... polysilicon layer, 13 , 13b ... n-type drain region, 13a ... low-concentration n-type drain region, 14 ... n-type source region, 15 ... element separation region, 16 ... insulating film, 17 ... oxidation Membrane, 18, 18a ... Insulating film (silicon nitride film), 21 ... Drive transistor, 22 ... Constant current transistor, 23 ... Al wiring, 24 ... Interlayer insulating film, 25 ... Contact hole, 101 ... Photosensor, 102 ... V register, 103 ... Imaging area, 104 ... Output circuit, 105 ... H register, 106 ... Read gate, 107 ... Unit Pixels, 108 ... light-shielding film, 109 ... opening, 110a, 110b ... transfer electrode, 111a, b, c, d ... low-reflection film, 112 ... interlayer insulating film, 113 .. .Protective film, 114 ... insulating film, 115 ... color filter, 116 ... on-chip lens.