Method of manufacturing capacitor of semiconductor device
Abstract
[Task] A main object of the present invention is to provide a method for manufacturing a capacitor of a semiconductor device, which has excellent electrical characteristics and can secure a high capacity.
Solution.After forming the lower electrode on the lower structure of the semiconductor substrate and forming the amorphous TaON thin film on the lower electrode, NH3Perform the heat treatment process in the atmosphere and Ta3N5The stage of forming the dielectric film and the Ta3N5A method for manufacturing a capacitor of a semiconductor device, which comprises a step of forming an upper electrode on a dielectric film.

Term
Term ended
Projected expiry passed 20 December 2020, 5.8 years ago.
- Priority
- Filed
- Published
- Projected expiry
- Today
20 claims: 5 independent, 15 dependent
- 1【特許請求の範囲】 【請求項1】半導体基板上に下部電極を形成する段階と、前記下部電極上に非晶質TaON薄膜を形成した後、NH 3 雰囲気中で熱処理工程を実施してTa 3 N 5 誘電体膜を形成する段階と、前記Ta 3 N 5 誘電体膜上に上部電極を形成する段階とを含むことを特徴とする半導体装置のキャパシターの製造方法。
- 2【請求項2】前記下部電極と上部電極とを、それぞれドープドポリシリコンと金属物質単独により形成するか、又はこれらを積層して形成することを特徴とする請求項1記載の半導体装置のキャパシターの製造方法。
- 3【請求項3】前記金属物質が、TiN、Ti、TaN、W、WN、WSi、Ru、RuO 2 、IrおよびPtからなる群から選択される1種であることを特徴とする請求項2記載の半導体装置のキャパシターの製造方法。
- 4【請求項4】前記下部電極形成材料としてドープドポリシリコンを使用する場合に、前記下部電極の表面に凸状半球形状のポリシリコンを成長させる工程を実施することを特徴とする請求項2記載の半導体装置のキャパシターの製造方法。
- 5【請求項5】前記下部電極形成材料としてドープドポリシリコンを使用する場合に、Ta 3 N 5 誘電体膜の形成前に1~5分間NH 3 雰囲気中で窒化処理する工程を更に含むことを特徴とする請求項2記載の半導体装置のキャパシターの製造方法。
- 6【請求項6】前記Ta 3 N 5 を蒸着する前に、HF蒸気を用いる乾式洗浄工程又はHF溶液を用いる湿式洗浄工程のいずれか一つの洗浄工程により、下部電極表面の自然酸化膜及びパーティクルを除去する段階を更に含むことを特徴とする請求項1記載の半導体装置のキャパシターの製造方法。
- 7【請求項7】前記熱処理工程を600~950°Cの温度で実施することを特徴とする請求項1記載の半導体装置のキャパシターの製造方法。
- 8【請求項8】前記非晶質TaON膜を、Ta(OC 2 H 5 ) 5 又はTa(N(CH 3 ) 2 ) 5 を150~200°Cの温度に維持されている蒸発器又は蒸発管により低圧化学気相蒸着(LP-CVD)チャンバー内に注入して蒸着形成することを特徴とする請求項1記載の半導体装置のキャパシターの製造方法。
- 9【請求項9】前記非晶質TaON膜を、300~600°Cの低圧化学気相蒸着チャンバー内にTaの化学蒸気とその反応ガスであるNH 3 ガスとを流量調節器を通じてそれぞれ定量供給した後、これらを100torr以下の雰囲気中で表面反応させることにより、蒸着形成することを特徴とする請求項8記載の半導体装置のキャパシターの製造方法。
- 10【請求項10】前記Ta 3 N 5 誘電体膜内のN含有量を調節するために、前記Ta 3 N 5 誘電体膜をアニーリング工程に供する段階を更に含むことを特徴とする請求項1記載の半導体装置のキャパシターの製造方法。
- 11【請求項11】前記アニーリング工程を、O 2 又はN 2 O雰囲気中で実施するプラズマ又は急速熱処理工程、又はUV-O 3 又はO 3 雰囲気中でアニーリングする工程により行うことを特徴とする請求項10記載の半導体装置のキャパシターの製造方法。
- 12【請求項12】前記アニーリング工程により前記Ta 3 N 5 誘電体膜上に酸化膜を形成する工程を更に含むことを特徴とする請求項10記載の半導体装置のキャパシターの製造方法。
- 13【請求項13】前記熱処理工程を、急速熱処理工程により行うか、又は低圧又は常圧方式の電気炉を用いることにより実施することを特徴とする請求項1記載の半導体装置のキャパシターの製造方法。
- 14【請求項14】半導体基板の下部構造物上に下部電極を形成する段階と、前記下部電極上に非晶質TaON薄膜を形成した後、600~950°Cの温度及びNH 3 雰囲気中で熱処理工程を実施してTa 3 N 5 誘電体膜を形成する段階と、前記Ta 3 N 5 誘電体膜をアニーリング処理する段階と、前記Ta 3 N 5 誘電体膜上に上部電極を形成する段階とを含むことを特徴とする半導体装置のキャパシターの製造方法。
- 15【請求項15】前記アニーリング工程を、O 2 又はN 2 O雰囲気中で実施するプラズマ又は急速熱処理工程、又はUV-O 3 又はO 3 雰囲気でアニーリングする工程により行うことを特徴とする請求項14記載の半導体装置のキャパシターの製造方法。
- 16【請求項16】前記下部電極と上部電極とを、それぞれドープドポリシリコン、TiN、Ti、TaN、W、WN、WSi、Ru、RuO 2 、IrおよびPtからなる群から選択される1種の金属物質単独により形成するか、又はこれらを積層して形成することを特徴とする請求項14記載の半導体装置のキャパシターの製造方法。
- 17【請求項17】前記下部電極形成材料としてドープドポリシリコンを使用する場合に、前記下部電極の表面に凸状半球形状のポリシリコンを成長させる工程を実施することを特徴とする請求項14記載の半導体装置のキャパシターの製造方法。
- 18【請求項18】前記下部電極形成材料としてドープドポリシリコンを使用する場合に、Ta 3 N 5 誘電体膜の形成前に1~5分間NH 3 雰囲気中で窒化処理する工程を更に含むことを特徴とする請求項14記載の半導体装置のキャパシターの製造方法。
- 19【請求項19】半導体基板上に下部電極を形成する段階と、前記下部電極上にNH 3 雰囲気中で窒化処理する段階と、前記下部電極の表面を非晶質TaONN薄膜を形成した後、600~950°Cの温度及びNH 3 雰囲気中で熱処理工程を実施してTa 3 N 5 誘電体膜を形成する段階と、前記Ta 3 N 5 誘電体膜をアニーリング処理する段階と、前記Ta 3 N 5 誘電体膜上に上部電極を形成する段階とを含むことを特徴とする半導体装置のキャパシターの製造方法。
- 20【請求項20】前記下部電極と上部電極とを、それぞれドープドポリシリコン、TiN、Ti、TaN、W、WN、WSi、Ru、RuO 2 、IrおよびPtからなる群から選択される1種の金属物質単独により形成するか、又はこれらを積層して形成することを特徴とする請求項19記載の半導体装置のキャパシターの製造方法。
Independent claims20
125 paragraphs in 1 section, as filed
Description: TECHNICAL FIELD [Detailed description of the invention]
【0001】
[Technical field to which the invention belongs]
The present invention relates to a method for manufacturing a capacitor of a semiconductor device, and more specifically, to a method for manufacturing a capacitor of a semiconductor device capable of sufficiently securing a charging capacity required for the semiconductor device.
【0002】
[Conventional technology]
Currently, in order to achieve high integration of semiconductor devices, research and development on reduction of cell area and reduction of operating voltage are being actively carried out.
【0003】
The area of capacitors decreases rapidly with the progress of high integration. However, the charge capacity required for the operation of the storage element must be 25 fF / cell or more in order to prevent the occurrence of soft errors and the shortening of the refresh time, despite the decrease in cell area. is there.
【0004】
Therefore, various methods have been proposed so far in order to secure a sufficient capacity of a DRAM capacitor. For example, a method has been proposed in which a sufficient capacitor capacity is secured by increasing the area of the capacitor or reducing the thickness of the dielectric film by changing the normal cylinder structure.
【0005】
Recently, instead of the conventionally used silicon oxide, a dielectric film having a NO (Nitride-Oxide) or ONO (Oxide-Nitride-Oxide) structure is formed, or a high capacitance (dielectric constant; Ta that can secure ε: 20 ~ 25)<sub>2</sub>O<sub>5</sub>Or BST (BaSrTiO<sub>3</sub>) Etc., research is underway to replace the dielectric film made of silicon oxide.
【0006】
However, a capacitor having a NO dielectric film has a limit in securing the capacity required for a next-generation memory of 256 M or more, so a next-generation dielectric material such as Ta<sub>2</sub>O<sub></sub><sub>5</sub>Research and development of dielectrics is underway.
【0007】
However, the Ta<sub>2</sub>O<sub>5</sub>Since the thin film has an unstable stoichiometry ratio, substituted Ta atoms due to the difference in composition ratio between Ta and O are inevitably present in the thin film.
【0008】
Also, Ta<sub>2</sub>O<sub>5</sub>When forming the dielectric film, Ta<sub>2</sub>O<sub>5</sub>Organic compound Ta (OC) which is a precursor of<sub>2</sub>H<sub>5</sub>)<sub>5</sub>And O<sub>2</sub>(Or N<sub>2</sub>O) By reacting with gas, carbon atoms, which are impurities, and carbon compounds (C, CH)<sub>4</sub>, C<sub>2</sub>H<sub>4</sub>Etc.) and water is formed.
【0009】
As a result, Ta<sub>2</sub>O<sub>5</sub>Oxygen vacancies existing in the thin film and carbon atoms, ions and radicals existing as impurities increase the leakage current of the capacitor and deteriorate the dielectric properties.
【0010】
Ta like this<sub>2</sub>O<sub>5</sub>Impurities in the thin film are low temperature heat treated (eg Plasma N)<sub>2</sub>O or UV-O<sub>3</sub>Although it can be removed by performing the treatment) two or three times, this heat treatment step is complicated. In addition, Ta<sub>2</sub>O<sub>5</sub>Due to the low oxidation resistance of the thin film, this step has the disadvantage that oxidation of the lower electrode occurs.
【0011】
[Problems to be Solved by the Invention]
Therefore, it is a main object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device which has excellent electrical characteristics and can secure a high capacity by solving various problems of the prior art. To do.
【0012】
Further, the present invention omits the manufacturing process for increasing the cross-sectional area of the lower electrode required to secure a high capacity of the capacitor, and reduces the number of unit processes and shortens the process time. It is also an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device, which can reduce the production cost.
【0013】
[Means for solving problems]
The first method for manufacturing a capacitor of a semiconductor device according to the present invention is a step of forming a lower electrode on a lower structure of a semiconductor substrate, and after forming an amorphous TaON thin film on the lower electrode, NH<sub>3</sub>Perform the heat treatment process in the atmosphere and Ta<sub>3</sub>N<sub>5</sub>The stage of forming the dielectric film and the Ta<sub>3</sub>N<sub>5</sub>It is characterized by including a step of forming an upper electrode on a dielectric film.
【0014】
Further, the second method for manufacturing a capacitor of a semiconductor device according to the present invention is a step of forming a lower electrode on a lower structure of a semiconductor substrate, and after forming an amorphous TaON thin film on the lower electrode, 600 to 950. ° C temperature and NH<sub>3</sub>Perform the heat treatment process in the atmosphere and Ta<sub>3</sub>N<sub>5</sub>The stage of forming the dielectric film and the Ta<sub>3</sub>N<sub>5</sub>The stage of annealing the dielectric film and the Ta<sub>3</sub>N<sub>5</sub>It is characterized by including a step of forming an upper electrode on a dielectric film.
【0015】
Further, the third method for manufacturing a capacitor of a semiconductor device according to the present invention includes a stage of forming a lower electrode on a lower structure of a semiconductor substrate and NH.<sub>3</sub>After nitriding in the atmosphere and forming an amorphous TaON thin film on the lower electrode, the temperature and NH are 600 to 950 ° C.<sub>3</sub>Perform the heat treatment process in the atmosphere and Ta<sub>3</sub>N<sub>5</sub>The stage of forming the dielectric film and the Ta<sub>3</sub>N<sub>5</sub>The stage of annealing the dielectric film and the Ta<sub>3</sub>N<sub>5</sub>It is characterized by including a step of forming an upper electrode on a dielectric film.
【0016】
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a method for manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
【0017】
1 to 4 show Ta with a high dielectric constant according to the present invention.<sub>3</sub>N<sub>5</sub>It is sectional drawing which shows a series of steps for manufacturing the capacitor of the semiconductor device provided with the dielectric thin film. In the method for manufacturing a capacitor of a semiconductor device according to the present invention, although not shown, a predetermined circuit element or circuit element such as a gate electrode, a source / drain, etc. is first formed on the upper surface of an active region of a silicon substrate 10 as a semiconductor substrate according to a conventional method. (Not shown) is formed.
【0018】
Thereafter, as shown in FIG. 1, silicon entire surface USG (Undoped Silicate Glass) of emission substrate 10, BPSG (Boro Phospho Silicate Glass ) and was deposited on selected materials from SiON, chemical mechanical polishing the surface (Chemical Mechanical The interlayer insulating film 20 is formed by polishing in the polishing) step.
【0019】
Then, in order to secure a desired cross-sectional area of the capacitor in contact with the relevant active region of the silicon substrate 10, a part of the interlayer insulating film 20 is selectively removed by an exposure and development step using photolithography. Form a contact hole (not shown).
【0020】
Then, a conductive substance such as doped polysilicon or amorphous doped polysilicon is deposited in the contact hole, and then the vapor-deposited conductive substance is selectively removed by an exposure and development process using photolithography. The lower electrode 30 is formed on the corresponding portion of the interlayer insulating film 20 in which the contact hole is formed. At this time, each of the lower electrodes 30 formed by the method of the present invention has a stack structure.
【0021】
The structure of the lower electrode 30 can be formed by selecting any one of a stack shape, a cylinder shape, a fin shape, and a stack cylinder shape.
【0022】
Then, as shown in FIG. 2, after depositing an amorphous TaON thin film on the upper surface of the lower electrode 30, NH<sub>3</sub>By subjecting to the heat treatment process in the atmosphere, Ta<sub>3</sub>N<sub>5</sub>The dielectric film 32 is formed.
【0023】
At this time, in the vapor deposition step of the amorphous TaON thin film, the low-pressure chemical vapor phase maintained at a temperature of about 300 to 600 ° C (preferably about 350 to 550 ° C, more preferably about 370 to 540 ° C). Ta (OC) as a precursor of an organometallic compound in a vapor deposition chamber<sub>2</sub>H<sub>5</sub>)<sub>5</sub>Or Ta (N (CH)<sub>3</sub>)<sub>2</sub>)<sub>5</sub>After vaporizing by the chemical vapor deposition method, NH<sub>3</sub>It is preferable to react with gas.
【0024】
Further, the chemical vapor of the Ta component (vapor of the Ta compound) used in the vapor deposition process of the amorphous TaON thin film is obtained by the following process.
【0025】
First, liquid Ta (OC) with a purity of 99.999% or higher<sub>2</sub>H<sub>5</sub>)<sub>5</sub>Or Ta (N (CH)<sub>3</sub>)<sub>2</sub>)<sub>5</sub>Is maintained at a temperature of about 150 ° C to 300 ° C (preferably about 160 to 250 ° C, more preferably about 170 to 200 ° C) through a mass flow controller or an evaporator. A fixed amount of about 300 to 1000 mg / min (preferably about 320 to 800 mg / min, more preferably about 330 to 700 mg / min) is supplied to the evaporation tube.
【0026】
At this time, the Ta (OC)<sub>2</sub>H<sub>5</sub>)<sub>5</sub>Or Ta (N (CH)<sub>3</sub>)<sub>2</sub>)<sub>5</sub>The evaporator containing the orifice or nozzle used to completely evaporate and the supply pipe that serves as the flow path for Ta steam are always maintained in the temperature range of 150 to 200 ° C to prevent condensation of Ta steam. To do. A predetermined amount of Ta vapor supplied into the low-pressure chemical vapor deposition chamber is a predetermined amount of NH.<sub>3</sub>The surface reacts with the reaction gas (5 to 500 sccm) at a pressure of 100 torr or less to form an amorphous TaON thin film.
【0027】
Also, NH<sub>3</sub>The heat treatment step performed in the atmosphere is carried out in the temperature range of 600 to 950 ° C for crystallization of the amorphous TaON thin film. This heat treatment step is performed using a rapid thermal process or a constant pressure / normal pressure electric furnace.
【0028】
Then, as shown in FIG. 3, the NH<sub>3</sub>Ta heat treated in the atmosphere<sub>3</sub>N<sub>5</sub>A subsequent heat treatment (annealing) step is performed on the dielectric film 32, and the Ta<sub>3</sub>N<sub>5</sub>A homogeneous oxide film 34 is further formed on the surface of the dielectric film 32.
【0029】
The subsequent annealing step is O<sub>2</sub>Or N<sub>2</sub>Performed in an O atmosphere using a plasma or rapid heat treatment step, or UV-O<sub>3</sub>Or O<sub>3</sub>Conduct in an atmosphere. By such an annealing process, Ta<sub>3</sub>N<sub>5</sub>Since the N content in the dielectric film 32 can be adjusted, various characteristics of the capacitor related to the leakage current or the breakdown voltage can be improved.
【0030】
Then, as shown in FIG. 4, the Ta<sub>3</sub>N<sub>5</sub>By depositing a conductive substance such as doped polysilicon on the upper surface of the dielectric film 32 and patterning it to form the upper electrode 36, Ta according to the illustrated embodiment<sub>3</sub>N<sub>5</sub>Complete the manufacturing process of a high capacity capacitor with a dielectric film.
【0031】
In the manufacturing process of a capacitor of a semiconductor device according to an embodiment of the present invention, Ta<sub>3</sub>N<sub></sub><sub>5</sub>Prior to the formation of the dielectric film 32, a dry cleaning step using HF vapor or a wet cleaning step using an HF solution was carried out in-situ or ex-situ on the surface of the lower electrode 30. Natural oxide films and particles that may be present can be removed.
【0032】
In addition, the Ta<sub>3</sub>N<sub>5</sub>When forming the dielectric film 32, the lower electrode and Ta<sub>3</sub>N<sub>5</sub>The surface of the lower electrode 30 is nitrided in order to prevent the formation of a natural oxide film with the dielectric film.
【0033】
The nitriding process includes NH.<sub>3</sub>It is preferable to perform plasma treatment in an atmosphere for 1 to 5 minutes. By this nitriding treatment, it is possible to prevent the interface between the lower electrode and the high dielectric film from being oxidized, so that a good quality dielectric film can be obtained.
【0034】
5 and 6 show the case where the amorphous TaON dielectric film is formed in the capacitor of the present invention (Fig. 5), and the case where the amorphous TaON dielectric film is NH.<sub>3</sub>Ta after annealing in the atmosphere<sub>3</sub>O<sub>5</sub>It is a graph comparing the concentrations of various elements existing in two dielectric films when a dielectric film is formed (Fig. 6).
【0035】
As is clear from the comparison between Fig. 5 and Fig. 6, after depositing the amorphous TaON thin film, NH<sub>3</sub>By performing annealing in an atmosphere, the O component in the amorphous TaON thin film can be reduced and the activated N component can be increased. Thus, Ta is a ferroelectric substance having a dielectric constant of about 100 (ε) or more.<sub>3</sub>N<sub>5</sub>Since a film can be obtained, a capacitor having a significantly increased capacitance can be obtained.
【0036】
FIG. 7 shows Ta according to another embodiment of the present invention.<sub>3</sub>N<sub>5</sub>It is sectional drawing which shows the capacitor structure of the semiconductor device which has a dielectric film.
【0037】
Ta according to another embodiment of the present invention<sub>3</sub>N<sub>5</sub>In the method for manufacturing a capacitor of a semiconductor device having a dielectric film, as shown in FIG. 7, the interlayer insulating film 50 and the lower electrode are first placed on a silicon substrate 40 by the same method as in the manufacturing steps of FIGS. 1 and 2. 60 and Ta<sub>3</sub>N<sub>5</sub>The dielectric film 62 is sequentially formed.
【0038】
After that, the Ta<sub>3</sub>N<sub>5</sub>A metal layer 65 acting as a conduction barrier and a doped polysilicon layer 66 acting as a buffer are sequentially laminated on the upper surface of the dielectric film 62 to have a MIS (Metal-Insulator-Silicon) structure. It constitutes the upper electrode.
【0039】
In another embodiment of the present invention, each of the upper electrode and the lower electrode is TiN, Ti, TaN, W, WN, Wsi, Ru, RuO instead of doped polysilicon.<sub>2</sub>, Ir, Pt, and any other metal-based material.
【0040】
Therefore, when such a metal-based material is used as the upper electrode and the lower electrode, Ta of the entire structure of MIM (Metal-Insulator-Metal)<sub>3</sub>N<sub>5</sub>Capacitors can be formed.
【0041】
FIG. 8 shows Ta according to still another embodiment of the present invention.<sub>3</sub>N<sub>5</sub>It is sectional drawing which shows the capacitor structure of the semiconductor device which has a dielectric film.
【0042】
In the method for manufacturing a capacitor according to still another embodiment of the present invention, first, an interlayer insulating film 80 and a lower electrode 90 are formed on a silicon substrate 70 by the same method as in the manufacturing steps of FIGS. 1 and 2.
【0043】
In this embodiment, the upper surface of the lower electrode 90 has an HSG (Hemi Spherical Grain) morphology in which polysilicon is grown in a convex hemispherical shape. Next, Ta is applied to the upper surface of the lower electrode 90 by the same method as in the manufacturing process of FIG.<sub>3</sub>N<sub></sub><sub>5</sub>The dielectric film 92 is formed.
【0044】
Then, the Ta<sub>3</sub>N<sub>5</sub>By forming the upper electrode 96 on the dielectric film 92, the production of the capacitor is completed.
【0045】
[Effect of the invention]
According to the method for manufacturing a capacitor of a semiconductor device according to the present invention, the following effects are achieved.
【0046】
In the manufacturing process of the capacitor dielectric film, after depositing amorphous TaON, this is NH.<sub>3</sub>By annealing in the atmosphere, the oxygen component in the initially deposited amorphous TaON is completely replaced by the activated nitrogen component, so that a high dielectric having a dielectric constant of about 100 (ε) or more. Ta<sub>3</sub>N<sub>5</sub>A membrane can be obtained.
【0047】
Therefore, Ta in the present invention<sub>3</sub>N<sub>5</sub>The dielectric is the conventional Ta<sub>2</sub>O<sub>5</sub>Since it has a dielectric constant four times or more higher than that of a capacitor, it can replace the dielectric of a capacitor of a next-generation semiconductor memory device of 256M class or higher.
【0048】
In addition, Ta in the present invention<sub>3</sub>N<sub>5</sub>Since the dielectric has a high dielectric constant, Ta of the capacitor of the existing MIS structure<sub>2</sub>O<sub>5</sub>Compared to the dielectric film, it has the effect of reducing the thickness of the oxide film (Tox) of the dielectric film to about 25 Å or less.
【0049】
Further, in the present invention, even when a lower electrode having a simple stack structure is used without increasing the area of the lower electrode, Ta with a high dielectric constant is used.<sub>3</sub>N<sub>5</sub>Since the desired high capacity can be obtained from the film, it is possible to manufacture a capacitor for a highly integrated semiconductor device.
【0050】
Further, Ta in the present invention<sub>3</sub>N<sub>5</sub>Since the dielectric film has a high dielectric constant, the manufacturing process for increasing the cross-sectional area of the lower electrode can be omitted. Therefore, the effect of reducing the number of unit processes and shortening the manufacturing process time is achieved.
[Simple explanation of drawings]
[Figure 1]
High Dielectric Ta according to an embodiment of the present invention<sub>3</sub>N<sub>5</sub>It is a part of the process drawing for explaining the manufacturing method of the capacitor of the semiconductor device which has.
[Figure 2]
High Dielectric Ta according to an embodiment of the present invention<sub>3</sub>N<sub>5</sub>It is a part of the process drawing for demonstrating the manufacturing method of the capacitor of the semiconductor device which has, and is the drawing which shows the stage following FIG.
[Fig. 3]
High Dielectric Ta according to an embodiment of the present invention<sub>3</sub>N<sub>5</sub>It is a part of the process drawing for demonstrating the manufacturing method of the capacitor of the semiconductor device which has, and is the drawing which shows the stage following FIG.
[Fig. 4]
High Dielectric Ta according to an embodiment of the present invention<sub>3</sub>N<sub>5</sub>It is a part of the process drawing for demonstrating the manufacturing method of the capacitor of the semiconductor device which has, and is the drawing which shows the final stage following FIG.
[Fig. 5]
It is a graph which shows the concentration of various elements existing in the formed amorphous TaON dielectric film in a capacitor.
[Fig. 6]
In the capacitor according to the manufacturing method of the present invention, the amorphous TaON dielectric film is NH.<sub></sub><sub>3</sub>Ta by annealing in the atmosphere<sub>3</sub>N<sub>5</sub>It is a graph which shows the concentration of various elements existing in a dielectric film when it is changed to a dielectric film.
[Fig. 7]
It is sectional drawing of the semiconductor element for demonstrating the manufacturing method of the capacitor of the semiconductor apparatus by another Example of this invention.
[Fig. 8]
It is sectional drawing of the semiconductor element for demonstrating the manufacturing method of the capacitor of the semiconductor apparatus by still another Example of this invention.
[Explanation of symbols]
10 Silicon substrate 20 interlayer insulating film 30 Lower electrode 32 Ta<sub>3</sub>N<sub>5</sub>Dielectric film 34 Oxidation film 36 Upper electrode 40 Silicon substrate 50 interlayer insulating film 60 Lower electrode 62 Ta<sub>3</sub>N<sub>5</sub>Dielectric film 65 metal layer 66 polysilicon layer 70 Silicon substrate 80 interlayer insulating film 90 Lower electrode 92 Ta<sub>3</sub>N<sub>5</sub>Dielectric film 96 Upper electrode
9 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9
14 members in 7 offices
Priority claims2
| Document | Office | Kind | Date |
|---|---|---|---|
| 199961345 | Republic of Korea | – | |
| 19990061345 | Republic of Korea | A |
Members14
| Document | Office | Kind | |
|---|---|---|---|
| GB0031318D0 | United Kingdom | D0 | |
| US2001005612A1 | United States of America | A1 | |
| KR20010057926A | Republic of Korea | A | |
| DE10064067A1 | Germany | A1 | |
| CN1307359A | China | A | |
| JP2001237399AThis record | Japan | A | |
| US6287910B2 | United States of America | B2 | |
| TW466677B | Taiwan Province of China | B | |
| GB2364825A | United Kingdom | A | |
| KR100386447B1 | Republic of Korea | B1 | |
| GB2364825B | United Kingdom | B | |
| CN1181529C | China | C | |
| DE10064067B4 | Germany | B4 | |
| JP4247421B2 | Japan | B2 |
15 legal events, as the office reported them to INPADOC
Over the term
Point at a mark for the eventEvents
| Event | Code | |
|---|---|---|
| Cancellation because of no payment of annual feesLAPS | LAPS | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Receipt of annual feesJAPANESE INTERMEDIATE CODE: R250R250 | R250 | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Renewal fee payment (event date is renewal date of database)FPAY | FPAY | |
| Certificate of patent or registration of utility modelJAPANESE INTERMEDIATE CODE: R150R150 | R150 | |
| First payment of annual fees (during grant procedure)JAPANESE INTERMEDIATE CODE: A61A61 | A61 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Written decision to grant a patent or to grant a registration (utility model)JAPANESE INTERMEDIATE CODE: A01A01 | A01 | |
| Written amendmentJAPANESE INTERMEDIATE CODE: A523A521 | A521 | |
| Notification of reasons for refusalJAPANESE INTERMEDIATE CODE: A131A131 | A131 | |
| Report on retrievalJAPANESE INTERMEDIATE CODE: A971007A977 | A977 | |
| Written request for application examinationJAPANESE INTERMEDIATE CODE: A621A621 | A621 |
Numbers
- Publication
- 2001-237399
- Application
- 387573
Titles2
- Japanese
- 半導体装置のキャパシターの製造方法
- English
- PROBLEM TO BE SOLVED: To manufacture a capacitor of a semiconductor device.
Classification
- CPC, 8
- H10D1/68
- H10D1/041
- H10B12/03
- H10D1/684
- H10D1/712
- H10D1/716
- H10P14/69433
- H10P14/69393
- IPC, 4
- H01L21 02
- H01L21 318
- H10B12 00
- C23C16 40