Method of manufacturing semiconductor structure device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to the method for manufacturing a semiconductor structural element according to claim 1. In particular, the present invention is non-volatile, comprising a switching transistor and a memory capacitor, the capacitor plate containing a platinum group metal and a ferroelectric or isoelectric material used as the dielectric between them. It relates to a method of manufacturing a memory cell.

【0002】

Conventional microelectronic semiconductor memory structural elements (DRAMs) consist roughly of selective or switching transistors and memory capacitors, in which a dielectric material is inserted between two capacitor plates. As the dielectric, an oxide layer or a nitride layer having a maximum dielectric constant of about 8 is usually used. In order to reduce the size of memory capacitors and to manufacture non-volatile memories, a new capacitor material (ferroelectric or ordinary dielectric) having a clearly high dielectric constant is required. A pair of these materials is listed in the publication W. Hoenlein, "NeueDielektrika fuer Gbit-Speicherchips", Phys. B1.55 (1999). In order to manufacture a ferroelectric capacitor for use in a high integration density non-volatile semiconductor memory structural element, for example, a ferroelectric material, for example SrBi₂(Ta, Nb)₂O₉(SBT or SBTN), Pb (Zr, Ti) O₃(PZT) or Bi₄Ti₃O₁₂(BTO) can be used as a dielectric between capacitor plates. But also, a dielectric material such as (Ba, Sr) TiO₃You can also use (BST).

【0003】

However, the use of these new dielectrics, ferroelectrics or constant dielectrics poses new challenges to semiconductor manufacturing technology. That is, first of all, these new materials can no longer be combined with the traditional electrode material polycrystalline silicon. Therefore, an inert electrode material, such as a platinum group metal or a conductive oxide thereof (eg, RuO).₂) Must be used. The reason for this is that after the ferroelectric substance is deposited, the ferroelectric substance must be heat-treated (state-adjusted) several times at a temperature of about 550 to 800 ° C. in an oxygen-containing atmosphere. Therefore, in order to avoid undesired chemical reactions between the ferroelectric and the electrode, the electrode should be at least platinum or another sufficiently thermally stable and inert material, such as another platinum group metal (Pd, Ir, Rh). , Ru, Os).

【0004】

In order to integrate the memory capacitors, a manufacturing process performed in a hydrogen-containing atmosphere is required. For example, 95% is nitrogen (N) for adjusting the state of metallized parts and transistors.₂) And 5% hydrogen (H₂) Needs heat treatment in a protective gas (Formier gas). However, the intrusion of hydrogen into the processed memory capacitor, that is, the dielectric, may cause the oxide ceramic of the dielectric to collapse due to the reduction reaction. In addition, plasma assisted deposition (PECVD) of silicon nitride passivation layers or intermetallic oxides induces reduction of dielectric ferroelectric or paradielectric materials based on the high hydrogen content in the layer.

【0005】

In the present state of technology, conventionally, it has been attempted to solve the above problem by depositing a passivation layer on a memory capacitor. For example, US-PS 5,523,595 describes a method for manufacturing a semiconductor structural element, in which a switching transistor is formed in a semiconductor substrate, a first isolation layer is deposited on the switching transistor, and the first isolation layer is deposited. A ferroelectric memory capacitor coupled with a switching transistor is formed on the isolation layer of 1, a second isolation layer is provided above the memory capacitor, and a barrier layer against the intrusion of hydrogen composed of TiON is deposited on the second isolation layer. Let me. This conventionally known barrier layer prevents hydrogen from entering through the upper electrode of the memory capacitor. Of course, it is possible to diffuse hydrogen through the first isolation layer, and it is also possible to diffuse into the dielectric through the first electrode and the lower electrode, which causes the collapse of the memory capacitor. Sometimes. On the other hand, the hydrogen component in the protective gas cannot be abandoned. Because it is a free union with hydrogen (dangling bond dangling This is because bonds ) should be saturated in the semiconductor, especially at the interface to the electrodes and in the gate oxide. In this case, the diffusion of hydrogen through the lower electrode of the memory capacitor and the subsequent saturation of the ferroelectric substance. Is not excluded.

【0006】

[Problems to be Solved by the Invention]

Therefore, an object of the present invention is to provide a method for producing a semiconductor memory capable of sufficiently protecting a memory capacitor using a ferroelectric or ordinary dielectric material for a dielectric against the intrusion of hydrogen. Is.

【0007】

[Means for solving problems]

This problem is solved by the present invention. a) Form a switching transistor on the semiconductor substrate, b) An isolation layer is provided on the switching transistor, and a first barrier layer, especially against hydrogen intrusion, is embedded in the isolation layer. c) A memory capacitor coupled to a switching transistor, including a lower electrode and an upper electrode and a metal oxide-containing layer deposited between them, is applied on the isolation layer. d) In the vertical etching process, the isolation layer is removed to a certain depth outside the memory capacitor, exposing the first barrier layer outward. e) It is solved by a method for manufacturing a semiconductor structural element, which comprises applying a second barrier layer particularly against hydrogen intrusion on a memory capacitor, an isolation layer, and a first barrier layer.

【0008】

In this case, the metal oxide-containing layer is preferably a ferroelectric or paradielectric material.

【0009】

Preferably, after the isolation layer is applied, a contact hole is etched in the isolation layer to the connection region of the switching transistor, for example, the drain region of the MOS switching transistor and filled with a conductive material, and the lower electrode of the switching transistor is subsequently formed. The switching transistor and the memory capacitor are connected at least partially above the contact hole. In this case, additionally, the inner wall of the contact hole can be lined with a third barrier layer, particularly against the ingress of hydrogen, before filling the contact hole. As a result, hydrogen is prevented from diffusing and invading the contact hole (plug) filled with the conductive material and entering the metal oxide layer through the conductive material and the lower electrode of the contact hole. .. As a result, the manufactured memory capacitor is completely enclosed by the barrier layer.

【0010】

Optionally, the first isolation layer can be removed to the depth of the first barrier layer in manufacturing step d), and in some cases the barrier layer can be used as the etch stopper layer. On the other hand, selectively, the isolation layer can be removed to a depth below the first barrier layer in the manufacturing step d).

【0011】

The first barrier layer is advantageously Si₃N₄Manufactured from, under reduced pressure chemical vapor deposition (LPCVD) gives particularly good results. As the material of the first barrier layer, ZrO₂Or SiO₂/ ZrO₂You can also select. Material Al, which is known in the current state of technology₂O₃, TiO₂, Ta₂O₅Can also be used as a material for the first barrier layer.

【0012】

For the third barrier layer, which linings the inner wall of the contact holes etched into the first isolation layer, in principle the same materials as for the first barrier layer can be used. Si as a material for the third barrier layer₃N₄To select the layers, the deposition is again carried out by LPCVD.

【0013】

The second barrier layer deposited on the memory capacitor is SiO_x-SiON-Si₃N₄It may be composed of a layer combination, and in this case, SiO is preferably produced by CVD (chemical vapor deposition)._xThe layer is grown and the SiON layer is subsequently deposited similarly preferably by CVD and finally Si by LPCVD.₃N₄Apply layers. In this case, the ferroelectric ferroelectric or ordinary dielectric material is Si.₃N₄An oxide or nitride barrier layer (X layer) is additionally deposited under the layer combination or between the individual layers of the layer combination to protect against the relatively large amount of hydrogen generated during LPCVD deposition of the layer. be able to. Therefore, the layer structure of the layer combination is, for example, X-SiO.₂-SiON-Si₃N₄Or SiO₂-X-SiON-Si₃N₄Is. As a material for the X layer, for example, Ta₂O₅, Bi₂O₃, TiO₂, Al₂O₃, Nb₂O₅, MgO, V₂O₅, CeO₂, Y₂O₃, ZrO₂, BN, AlN and any rare earth oxide can be used. Further preferably, SiO is added to anneal the damage to the ferroelectric or normal dielectric as a result of the CVD deposition of the silicon oxide layer._xHeat treatment is performed after deposition.

【0014】

[Example]

Hereinafter, examples of the present invention will be described in detail with reference to the drawings. The drawings show cross-sectional views of the semiconductor structural elements at different stages of the method according to the invention.

【0015】

According to the embodiment shown in FIG. 1, the MOS switching transistor 2 is first formed on a semiconductor substrate 1 (for example, made of silicon) by doping to form a drain region and a source region, and are arranged above the passage between them. Manufactured by creating a channel whose conductivity can be controlled by the gate. The gate may be formed by the word line WL of the memory structural element or may be connected to the word line. Subsequently, the MOS switching transistor 2 is usually an oxide, for example SiO.₂Coat with (TEOS) or BPSG (borosilicate glass).

【0016】

Based on the present invention, the first barrier layer 5 is embedded in the isolation layer 4. Therefore, the first sublayer of the isolation layer 4 is first applied, then the barrier layer 5 is deposited on the first sublayer, and the second sublayer of the isolation layer 4 is subsequently deposited on the barrier layer 5. To give. For barrier layer 5, select a material that is as impermeable to hydrogen as possible. Very suitable for this is silicon nitride, especially Si, which can be deposited by vacuum chemical vapor deposition (LPCVD) with particularly good quality and no pores.₃N₄Is. However, another nitride layer or H₂Another layer that acts as a barrier can be used.

【0017】

Subsequently, the layer structure formed by the isolation layer 4 and the barrier layer 5 is vertically etched with contact holes on the drain region of the MOS switching transistor 2 and filled with a conductive material such as doped polycrystalline silicon. Subsequently, an oxidation barrier 6 is applied on the filled contact hole 3.

【0018】

Subsequently, on the isolation layer 4, a lower electrode 7 made of platinum or another platinum group metal or a conductive oxide thereof is first applied above the contact hole and structured in a mesa shape as shown in the figure. .. As a result, the lower electrode 7 is electrically coupled to the drain region of the MOS switching transistor 2 and the contact hole 3 filled with conductive polycrystalline silicon. Next, a dielectric layer 8 of a ferroelectric or normal dielectric material forming a capacitor dielectric is deposited on the lower electrode 7. This layer 8 completely covers the structured lower electrode 7 toward all surfaces and extends laterally stepwise over the lower electrode 7. An upper electrode 9 made of platinum or another platinum group metal or a conductive oxide thereof was deposited on the dielectric layer 8 so as to cover the entire front surface in the same manner, and thus was similarly structured in a stepped manner. It extends laterally on both sides of the lower electrode 7.

【0019】

Therefore, the semiconductor structural element as shown in FIG. 1 is manufactured.

【0020】

Subsequently, the vertical mesa-like structure of the memory capacitor will be implemented. This can be done in two different embodiments, as shown by FIGS. 2a and 2b.

【0021】

In the first embodiment (FIG. 2a), a vertical mesa structure is etched into the isolation layer 4 around the memory capacitor, and the vertical etching step is accurately carried out up to the barrier layer 5. In this case, the barrier layer 3 can simultaneously serve as an etch stopper. This vertical etching process results in the upper surface of the outer barrier layer 5 of the etched mesa structure being exposed outward. Next, the obtained structure is subjected to the second barrier layer 10.

【0022】

In the second embodiment (FIG. 2b), a mesa-like structure is similarly formed around the memory capacitor by a vertical etching step. However, in this case, since the vertical etching step into the isolation layer 4 is performed beyond the barrier layer 5, the barrier layer 5 outside the mesa structure is completely removed. The etching process is performed to a certain depth below the barrier layer 5 and then stopped. Next, the obtained structure is subjected to the second barrier layer 10. Accordingly, in the second embodiment, the etch stopper on the barrier layer 5 is unnecessary. However, this is purchased by increasing the height of the topology, the etched mesa structure.

【0023】

In both embodiments, the application of the second barrier layer 10 evokes that the barrier layer is bound to the first barrier layer 5 in certain compartments. This section extends on a closed orbit around the mesa structure and forms an external contour in the lower region of the etched mesa structure, as it were. In the first embodiment, the second barrier layer 10 is applied completely on the first barrier layer 5 which is still completely obtained in the outer region of the mesa structure. In contrast, in the second embodiment, the contact is made in a narrow section where the first barrier layer 5 is exposed to the outside on the side surface etched in the vertical direction.

【0024】

The second barrier layer 10 is first made of SiO_xA first layer consisting of, then a second layer consisting of SiON, and finally Si₃N₄It is formed by a layer combination in which a third layer consisting of is applied. The first two layers can be formed by CVD (Chemical Vapor Deposition), while Si₃N₄Can be formed by LPCVD (low pressure chemical vapor deposition). Dielectric of memory capacitor, Si₃N₄A relatively large amount of hydrogen (H) generated during LPCVD deposition of the layer₂), An additional oxide or nitride barrier layer (X layer) can be deposited. This X layer is as the first layer and therefore still SiO₂Can be applied before deposition or inside the layer combination. Therefore, as a layer combination, for example, X-SiO₂-SiON-SiN or SiO₂-A layer structure based on X-SiON-SiN can be selected. The X layer can also be applied after the formation of SiON. Oxides or Nitrides X barrier layer materials include all heat-stable non-conductive oxides or nitrides, such as Ta.₂O₅, Bi₂O₃, TiO₂, Al₂O₃, Nb₂O₅, MgO, V₂O₅, CeO₂, Y₂O₃, ZrO₂, BN, one of AlN and any rare earth oxide can be used. After the CVD deposition of silicon oxide, a heat treatment step can be performed to anneal any damage to the capacitor dielectric as a result of this deposition.

【0025】

FIG. 3 shows a semiconductor structural element finally completed based on the present invention. As is apparent, this is derived from the method according to the invention based on the first embodiment (FIG. 2a), in which case the barrier layers 5 and 10 outside the mesa structure in another etching step. Has been removed.

【0026】

However, the semiconductor structural element shown in FIG. 3 is still different in features different from the embodiments shown so far. That is, in this case, the contact hole 3 is provided with a third barrier layer 5A, whereby hydrogen penetrates into the conductive material of the contact hole 3 through the isolation layer 4 and the memory is upward from there. It prevents the capacitor from being diffusely invaded. The third barrier layer 5A is deposited immediately after the contact hole etching. Preferably, the third barrier layer 5A is Si as well as the first barrier layer 5.₃N₄And more preferably the LPCVD method is produced in the same manner. The third barrier layer 5A completely covers the inner wall of the contact hole 3. In this way, after the contact hole 3 is lined with the third barrier layer 5A, the contact hole 3 is filled with a conductive material, for example, doped polycrystalline silicon.

【0027】

Therefore, using the method according to the present invention, the memory capacitor can be completely encapsulated by the barrier layers 5, 5A and 10, whereby hydrogen, which is always present after the formation of the memory capacitor in the manufacturing process, penetrates into the structural element. However, it is possible to prevent the possibility of causing damage to the capacitor dielectric in the ferroelectric or normal dielectric material. In many cases, it is sufficient to form barrier layers 5 and 10. This is because the contact hole 3 itself only forms an extremely narrow diffusion path for hydrogen. However, in order to achieve complete encapsulation, a third barrier layer 5A can still be applied to the inner wall of the contact hole 3 as shown to complete encapsulation of the memory capacitor.

[Simple explanation of drawings]

[Figure 1]

It is sectional drawing of the semiconductor structural element manufactured based on this invention after carrying out manufacturing process c).

[Figure 2]

a is a cross-sectional view (first embodiment) of the semiconductor structural element manufactured based on the present invention after the manufacturing step d), and b is a semiconductor manufactured based on the present invention after the manufacturing step d). It is sectional drawing (second embodiment) of a structural element.

[Fig. 3]

It is sectional drawing (first embodiment) of the semiconductor structural element manufactured based on this invention after carrying out manufacturing process e).

[Explanation of symbols]

1 Semiconductor substrate, 2 MOS switching transistor, 3 Contact hole, 4 Isolation layer, 5 1st barrier layer, 5A 3rd barrier layer, 6 Oxidation barrier, 7 Lower electrode, 8 Dielectric layer, 9 Upper electrode, 10 Second barrier layer, WL word line