Semiconductor integrated circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having an improved parasitic capacitance of a voltage dividing resistor in a high voltage generation circuit of a memory.

【0002】

[Conventional technology]

In the development of non-volatile memory, absolute accuracy of high voltage output level is required depending on the device withstand voltage, level range at the time of writing and erasing, and the like. As a device for realizing such a circuit, there is a circuit of Conventional Example 1 shown in FIG.

【0003】

In this conventional example 1, a booster circuit 1 that inputs a boost clock CLK and a control signal Vc and outputs a high voltage output Vo, voltage dividing resistors R1 and R2 that divide the output of the boost circuit 1, and these voltage dividing resistors R1 and R2. It is a high voltage generation circuit consisting of a comparator 2 that compares the voltage Vi divided by the resistors R1 and R2 with the reference voltage Vr and outputs the control signal Vc.

【0004】

However, since the voltage dividing resistors R1 and R2 used here have a low current supply capacity of the booster circuit 1, it is necessary to set a high resistance value so that the current flowing through the voltage dividing resistors R1 and R2 is as small as possible. Since the relative accuracy of the resistance element is also required, a polysilicon resistance element that can realize a higher layer resistance than the diffusion resistance element and has less bias dependence is usually used.

【0005】

However, these voltage-dividing resistance elements (R1 and R2) also need to be considered in the layout configuration and arrangement, and these voltage-dividing resistance elements require a larger area than other resistors. As a result, the parasitic capacitance of these voltage dividing resistors against SUB increases, and the accuracy of the high voltage level determined by the time constant of the voltage divider resistors deteriorates.

【0006】

In this conventional example 1, as shown in the ripple waveform diagram of FIG. 7, the time constant of the voltage dividing resistor element R1 and the SUB capacitance C2 causes a delay in the change of the voltage dividing level Vi, so that the high voltage output Vo is used as a comparator. The delay time of the feedback path to the output Vc of 2 increases, and as a result, the booster circuit cannot be controlled by this delay time, and the ripple width v of the high voltage level is large and an inaccurate level can be obtained.

【0007】

The ripple width v of this conventional example 1 is as shown in the following equation (1).

【0008】

v = {Voltage resistor delay (R1 × C2) s + Comparator delay s} × Boosting capacity v / s ............ (1) FIG. 8 shows the simulation execution result in the circuit configuration of the conventional example 1, and the ripple width of the high voltage level is 700 mv.

【0009】

As a means for improving the accuracy of the ripple width, there is a circuit shown in the circuit diagram of Conventional Example 2 in FIG. In this circuit, it is necessary to add a capacitance element C1 generally called a speed-up capacitance. According to this circuit, there is a problem that the area of the high voltage generation circuit increases by the area of the speed-up capacitance element C1.

【0010】

Fig. 10 shows the simulation execution result in the circuit configuration of the conventional example 2 (Fig. 9), and the ripple width when 0.3PF is added as the speed-up capacitance C1 is improved to 300 mv.

【0011】

[Problems to be Solved by the Invention]

In the case of the above-mentioned conventional example 2, the ripple width is improved by adding the speed-up capacitance element C1, but the problem is that the area of the high voltage generation circuit increases by the area of the speed-up capacitance element C1. There was a point.

【0012】

An object of the present invention is to solve such a problem, to suppress an increase in the area of the speed-up capacitance element C1, and to provide a semiconductor integrated circuit including a high voltage generation circuit having an improved ripple width.

【0013】

[Means for solving problems]

The configuration of the present invention consists of a booster circuit that inputs a booster clock and a control signal and outputs a high voltage output, and first and second voltage dividing resistors R1 and R2 that divide the output of this booster circuit. In a semiconductor integrated circuit having a high voltage generation circuit including a comparator that compares the voltage divided voltage divided by the pressure resistors R1 and R2 with a reference voltage and outputs the control signal, the parasitic capacitance of the voltage dividing resistor R1 is measured. , It is characterized in that it is connected to the high voltage output line.

【0014】

In the present invention, the parasitic capacitance of the first voltage divider resistor R1 is directly connected to the connection line of the voltage divider voltage that is the input of the comparator and can function as a speed-up capacitance, and the first voltage divider resistor R1 The parasitic capacitance of is composed of the substrate capacitance parasitic on the lower layer of the first voltage dividing resistor, and a well connected to the high voltage output line can be formed in this substrate capacitance region.

【0015】

Further, in the present invention, the parasitic capacitance of the first voltage dividing resistor R1 is provided on the semiconductor substrate and is provided via the well connected to the high voltage output line and the first insulating film. It can also be formed between the first polysilicon resistor element that serves as a resistor.

【0016】

Further, in the present invention, the parasitic capacitance of the first voltage dividing resistor R1 is provided on the semiconductor substrate and connected to the high voltage output line via a well and a first insulating film on the well. The well and the first poly in a structure including one polysilicon resistance element and a second polysilicon resistance element provided on the first polysilicon resistance element via a second insulating film. It is formed between the silicon resistance element and between the first polysilicon resistance element and the second polysilicon resistance element, and the first voltage dividing resistance is formed between the first polysilicon resistance element and the first polysilicon resistance element. It can also be formed by the second polysilicon resistance element.

【0017】

According to the configuration of the present invention, in contrast to the configuration of anti-SUB capacitance parasitic under the voltage dividing resistor element, by forming a well connected to the high voltage output line in the anti-SUB parasitic capacitance region according to the present invention, the speed is increased. Serves as an up capacity. Therefore, it is not necessary to provide the speed-up capacitance element in a new region.

【0018】

BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 1 shows a circuit diagram of a high voltage generation circuit according to an embodiment of the present invention. This high-voltage generation circuit receives a boosting clock signal CLK as an input and outputs a high-voltage output Vo with a control signal Vc as an input, and a voltage dividing resistor R1 connecting the high-voltage output Vo of the booster circuit 1 to the booster circuit 1. A comparator that inputs the voltage dividing resistor R2 connected between the voltage dividing resistor R1 and the ground GND, the voltage dividing output Vi of the voltage dividing resistors R1 and R2, and the reference voltage Vr, and outputs the control signal Vc. It is composed of 2 and is characterized by having a parasitic capacitance C1 in the portion of the voltage dividing resistor element R1.

【0019】

The portion of the voltage dividing resistor element R1 is shown in the plan view and the cross-sectional view of the voltage dividing resistance R1 and R2 portions in FIGS. 2 (a) and 2 (b). That is, the polysilicon layer 13 having the N well 11 on the P-type substrate 10 and serving as the voltage dividing resistance element R1 is formed on the N well 11 via the first insulating film 12, and the polysilicon layer 13 and the polysilicon layer 13 thereof. There is a parasitic capacitance C1 between the lower N well 11 and this N well 11 is connected to the high voltage output Vo line.

【0020】

Further, since the polysilicon layer 13 serving as the voltage dividing resistor element R2 is provided on the P-type substrate 10 adjacent to the N well 11, there is a parasitic capacitance C3 in the portion of the polysilicon layer 13 serving as the voltage dividing resistor element R2. , This will be connected to the grounded P-type board 10.

【0021】

The polysilicon layers 13 to be the voltage dividing resistor elements R1 and R2 are connected to the aluminum wiring 18 provided on the insulating film 12 via the contacts 19, respectively. That is, one end of the voltage dividing resistor R1 is connected to the aluminum wiring 18 connected to the output end Vo via the contact 19, and the polysilicon layer 13 serving as the connection point of the voltage dividing resistor elements R1 and R2 is connected via the contact 19. Then, it is connected to the aluminum wiring 18 connected to the voltage dividing end Vi, and the other end of the voltage dividing resistor R2 is connected to the aluminum wiring 18 connected to the grounding end GND via the contact 19.

【0022】

According to FIG. 1 of this embodiment, as shown in the ripple waveform diagram of FIG. 3, the capacitance C1 is directly connected to the connection line of the voltage divider output Vi regardless of the time constant between the voltage dividing resistor element R1 and the parasitic capacitance C1. High voltage level transmission can be performed through this, and the delay in the feedback path can be significantly shortened, and therefore the ripple width of the high voltage output Vo can be reduced.

【0023】

The ripple width v according to this embodiment is shown in the following equation (2).

【0024】

v = Comparator delay s x boosting capacity v / s ............ (2) Here, in order to show the effect of this embodiment, paying attention to the ripple width that determines the absolute accuracy of the high voltage level, the simulation result of the high voltage generation circuit having the same booster circuit, comparator, and voltage dividing resistor is shown in FIG. Shown in. In the circuit configuration of FIG. 1 of this embodiment, when 1PF is added as the parasitic capacitance component C1 of the voltage dividing resistor R1, the ripple width becomes 350 mv as shown in FIG.

【0025】

Therefore, according to this embodiment, it is clear that the effect of reducing the ripple width can be obtained with the anti-SUB parasitic capacitance C1 equivalent to the speed-up capacitance, and the area of the speed-up capacitance element can be reduced or deleted.

【0026】

FIG. 5 shows a cross-sectional view of the voltage dividing resistor R1 portion of the second embodiment of the present invention. With respect to the first embodiment of FIG. 4, the voltage dividing resistance element polysilicon layer 13 has an N well 11 at the lower part thereof, and the second pressure dividing resistance element poly via the second insulating film 15 at the upper part thereof. It has a silicon layer 16, and the N well 11 and the second polysilicon layer 16 are connected to a high voltage output line.

【0027】

In the structure shown in FIG. 5, an N-well 11 connected to a high voltage output level is formed at the lower part of the voltage dividing resistor element polysilicon R1, and a second polysilicon layer 16 connected to the high voltage output line is formed at the upper part. Feedback is applied to the connection line of the voltage dividing output Vi via C1. This has the same effect as the speed-up capacity and serves as the speed-up capacity C1.

【0028】

The embodiment of FIG. 5 has a feature that a larger speed-up capacitance value can be obtained than that of the first embodiment in the same element area as that of the first embodiment.

【0029】

[Effect of the invention]

As described above, according to the configuration of the present invention, it is effective to obtain a high voltage generation circuit having an improved ripple width without increasing the area of the speed-up capacitance element C1. Further, the second embodiment is characterized in that more speed-up capacitance values can be obtained in the same element area than in the case of the first embodiment.

[Simple explanation of drawings]

[Figure 1]

The circuit diagram which shows the 1st Embodiment of this invention.

[Figure 2]

(a) and (b) are a plan view and a cross-sectional view of the voltage dividing resistors R1 and R2 in the embodiment of FIG.

[Fig. 3]

The ripple waveform diagram explaining the operation of the circuit of FIG.

[Fig. 4]

Waveform diagram at the time of simulation execution in the circuit configuration of Fig. 1.

[Fig. 5]

FIG. 3 is a cross-sectional view of a voltage dividing resistor R1 portion according to a second embodiment of the present invention.

[Fig. 6]

The circuit diagram explaining the circuit structure of the prior art example 1.

[Fig. 7]

The ripple waveform diagram explaining the operation of the circuit configuration of FIG.

[Fig. 8]

Waveform diagram at the time of simulation execution in the circuit configuration of FIG.

[Fig. 9]

The circuit diagram explaining the circuit structure of the prior art example 2.

[Fig. 10]

Waveform diagram at the time of simulation execution in the circuit configuration of FIG.

[Explanation of symbols]

1 Booster circuit 2 comparator 10 P-type board 11 N well 12,15 Insulating film 13,16 polysilicon resistor element 14,17 Interlayer capacity 18 Aluminum wiring 19 contacts C1 speedup capacity C2, C3 SUB capacity R1, R2 voltage divider resistor Vo high voltage output Vc control voltage