Semiconductor device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device, and particularly relates to a semiconductor device in which semiconductor modules having a build-up wiring layer capable of increasing the mounting density are laminated.

【0002】

[Conventional technology]

In recent years, semiconductor chips have become highly integrated, and semiconductor mounting technology is also required to have a high density. Wire bonding technology, TAB technology, etc. are typical examples of this high-density mounting technology for semiconductor chips, but as the highest-density mounting technology, flip-chip mounting technology provides high-density semiconductor chips for computer equipment and the like. It is often used as a technology to be implemented in.

【0003】

Furthermore, a semiconductor package as a semiconductor device has been developed by BGA (Ball Grid Array), which can handle multiple pins, as described in, for example, Journal of Electronics Packaging Society Vol.1, No.1, pp19-23, 1998. Currently, CSP (Chip Scale Package), whose package size is almost the same as the chip size, is the mainstream of high-density mounting technology.

【0004】

However, since these high-density mounting technologies are for arranging semiconductor chips in two dimensions in a plane on a circuit wiring board, there is a physical limit to the area in which the semiconductor device is mounted on the circuit wiring board. There is a limit to the mounting area as a technology for compactly and high-density mounting of system electronic devices that require a large number of components to be mounted on a semiconductor.

【0005】

For this reason, in the current advanced mounting technology, the development of a three-dimensional mounting technology in which the spatial direction is also the mounting area of the semiconductor device is being developed in contrast to the conventional two-dimensional mounting technology.

【0006】

As an example, Fig. 10 shows an implementation example in which MCM (Multichip Module) is stacked. As a method of three-dimensionally mounting different types of semiconductor chips, as shown in FIG. 10, a plurality of semiconductor chips 103 are flip-chip mounted on the circuit wiring board 104 to form vertical wiring 109 on the side surface of the circuit wiring board. Is generally done. As a proposal for three-dimensionally mounting an MCM unit substrate on which a semiconductor chip as described above is mounted, for example, Japanese Patent Application Laid-Open No. 5-235255 can be mentioned.

【0007】

However, although the method of laminating the MCM circuit wiring board or TCP semiconductor package described above and mounting them in three dimensions can be structurally easily realized by the extension technology of the conventional two-dimensional mounting technology, MCM The connection area for stacking in the direction perpendicular to the plane wiring area of the circuit wiring board and the mounting area for connecting in the direction perpendicular to the sealing area of the TCP semiconductor package are factors that hinder the improvement of the mounting density, and the semiconductor chip is mounted. There was a limit to achieving the ultimate high density of.

【0008】

In response to this problem, JP-A-8-279588 and JP-A-8-316408 address the vertical direction after using the multilayer wiring metal exposed on the side surface of the MCM multilayer circuit wiring board as the side electrode of the three-dimensional mounting block. It describes a proposal to increase the density of the mounting area in the vertical direction by connecting a circuit board that connects the two to each other to the side electrode of the block. This structure is an application of the bare-chip semiconductor device shown in Fig. 11 to a multilayer wiring board, and was described in the 8th Microelectronics Symposium Proceedings pp165-168, December 1998 as a method for realizing high-density mounting. There is.

【0009】

The semiconductor device shown in FIG. 11 is a stack of semiconductor modules in which a circuit wiring layer 115 connected to a semiconductor chip 113 mounted on a circuit wiring board 114 is extended to the peripheral end of the board 114. 116 side electrodes are formed on the side surface (laminated surface) of the above.

【0010】

However, although vertical electrode connection using side electrodes can increase the density of the vertical wiring area, it cannot basically improve the two-dimensional mounting density. Therefore, a circuit that mounts a semiconductor chip that is a stacking unit unit. As the wiring board, a build-up wiring board capable of increasing the density of circuit wiring is often used as a laminated unit unit board.

【0011】

However, when this build-up multilayer board is used as a laminated unit substrate, the Cu wiring film thickness cannot be increased in the manufacturing process, so that a sufficient electrode terminal area cannot be secured to use the Cu multilayer wiring cross section as a block side electrode. was there. Furthermore, when the build-up multi-layer wiring is used as the block side electrode, the stress strain generated in the block side electrode due to the different thermal expansion coefficients of the base board part, the build-up wiring part, and the side wiring board part is built. There was a problem in connection reliability that stress strain could not be sufficiently relaxed by concentrating on the up-multilayer wiring layer portion.

【0012】

[Problems to be Solved by the Invention]

As described above, it is effective to use a build-up wiring board as a technique for mounting a semiconductor chip at a high density, but on the other hand, the wiring in the build-up wiring board has a large film thickness due to its manufacturing method. This is difficult, or the coefficient of thermal expansion differs between the stacking direction of the wiring and the surface direction of the side electrode substrate, so that stress strain is applied, which causes a problem in connection reliability.

【0013】

The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor device having high connection reliability between a build-up wiring board and a side electrode board.

【0014】

[Means for solving problems]

The semiconductor device of the present invention is formed on a base substrate, a first conductor layer having a circuit wiring formed on the base substrate and having an end portion extending to the peripheral end portion of the base substrate, and the base substrate. , The interlayer insulating layer and the second conductor layer are laminated, and the first conductor layer and each of the second conductor layers are connected by via holes at the peripheral end of the substrate, and the via holes are formed on the laminated surface. It is characterized in that a semiconductor module including an exposed build-up wiring layer and a semiconductor chip mounted on the build-up wiring layer is laminated.

【0015】

It is also possible to provide a side wiring board that is electrically connected at the end of the base substrate of the first conductive layer.

【0016】

Further, it can be exposed on the laminated surface of the build-up wiring layer and electrically connected to the side wiring board via the via hole.

【0017】

That is, in the present invention, it has been noticed that the stress due to the difference in the coefficient of thermal expansion between the semiconductor module having the build-up wiring layer and the side wiring board increases as the distance from the base board increases. According to the present invention, by electrically connecting the side wiring board and the semiconductor module in the conductive layer closest to the base substrate, it is possible to reduce the decrease in connection reliability due to stress strain.

【0018】

Further, since the via hole portion connecting the conductive layer formed on the surface of the base substrate and each conductive layer in the build-up wiring has a larger film thickness than the single-layer conductive layer, the semiconductor module and the side portion in the via hole portion. By connecting to the wiring board, it is possible to strengthen the strength and further improve the connection reliability.

【0019】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described with reference to FIGS. 1 to 5.

【0020】

FIG. 1 is a cross-sectional view showing an embodiment of the semiconductor device according to the present invention, FIG. 2 is a first cross-sectional process diagram showing a method for manufacturing the semiconductor device according to the present invention, and FIG. 3 is a semiconductor device of the present invention for CCD. FIG. 4 is a circuit block diagram when used in the above, and FIG. 4 is a second process sectional view showing a method for manufacturing a semiconductor device according to the present invention. FIG. 5 is a partially enlarged cross-sectional view of the semiconductor device according to the present invention.

【0021】

In the semiconductor device shown in FIG. 1, a first semiconductor module 1 and a second semiconductor module are laminated, and a side wiring board 15 is adhered to a side surface (laminated surface) of the laminate.

【0022】

In the semiconductor modules 1 and 2, a base substrate wiring layer 10 serving as a first conductive layer is formed on the surface of the base substrate 7 provided with the through holes 9, and an interlayer insulating layer 12 is further formed on the surface of the base substrate wiring layer 10. Further, a build-up multilayer wiring layer 8 in which the build-up wiring layers 11 composed of conductive layers are sequentially laminated is formed. Further, the build-up wiring layers 11 are partially connected to each other, or the build-up wiring layer 11 and the base wiring layer 10 are partially connected by a via hole 22. Further, semiconductor chips 3, 4, 5 and chip components 6 are mounted on the build-up multilayer wiring layer 8, and each of them is connected to the base board wiring 10 via a ball electrode 14. Further, the semiconductor chips 4 and 5 are mounted on the opposite surfaces of the first semiconductor module 1 and the second semiconductor module 2, respectively, and by arranging them so as not to overlap in the stacking direction, the mounting density in the stacking direction can be increased. I'm raising it.

【0023】

Further, the semiconductor modules 1 and 2 are laminated with an insulating resin 18 made of an adhesive.

【0024】

The side wiring board 15 joined to the side surface of the laminate composed of the semiconductor modules 1 and 2 has the board 23 and the multilayer wiring 24 formed on the joint surface side of the board 23. Further, the multilayer wiring 24 is connected to the external connection terminal 25 via a through hole 9 formed in the substrate 23.

【0025】

The laminate and the side wiring board 15 are reinforced by the sealing resin 21, and the end portion (side electrode) of the base substrate wiring layer 10 exposed on the laminated surface of the laminate composed of the semiconductor modules 1 and 2. It is connected to the multilayer wiring 24 on the side surface base substrate 25 via the ball electrode 14 arranged in.

【0026】

Next, a method of manufacturing a semiconductor device as shown in FIG. 1 will be described with reference to FIG.

【0027】

First, a circuit wiring board on which the semiconductor chips 3 and 4 and the chip component 6 are mounted is prepared (Fig. 2f). This circuit board material is general from the gist of the present invention. For example, a printed circuit board SLC in which an insulating layer and a conductor layer are mutually built up on a US Patent No. 4811082 or a normal glass epoxy board. (Surface Laminar Circuit) Substrates can be used. Therefore, for example, it is possible to use a multi-layer flexible substrate in which copper wiring is built-up formed on the surface of a polyimide resin as a substrate main material, or a build-up ceramic multilayer substrate, and the material of the multi-layer circuit wiring board is Although not particularly limited, in this embodiment, for the sake of explanation, a multilayer circuit wiring board having an SLC substrate as a base plate with glass epoxy as a base plate was used as the multilayer circuit wiring board material.

【0028】

The semiconductor module constituting the semiconductor device according to the present invention using this multilayer wiring board can be manufactured by the following method.

【0029】

First, a 96 m × 96 mm double-sided copper-clad glass epoxy board is prepared by laminating an 18 μm-thick copper foil 10'on a base substrate 7 made of 0.39 mm-thick glass epoxy by a known method (Fig. 2a).

【0030】

Next, a 250 μmφ through hole is formed at a required portion of the base substrate 7 with a drill, and plating is performed by a known method using an electroless plating method and an electroplating method to form a through hole 9. Due to this copper through-hole plating, the film thickness of 18 μm copper foil has increased to 22 μm (Fig. 2b).

【0031】

Next, the copper foil 10'on the base substrate on which the through holes 9 are formed is coated with a resist film to form the base substrate wiring layer 10 by a known method using iron (III) chloride (FIG. 2c). This wiring pattern is not particularly limited, but in this embodiment, in consideration of the manufacturing yield, the layout is such that 72 semiconductor modules of 11.5 mm × 5.2 mm are arranged, and the copper wiring is exposed on the cut surface. As described above, the pattern was designed with copper wiring extending to the split dicing line, with Line / Space = 100 μm / 100 μm and a sulhole land diameter of 550 μm.

【0032】

Next, a photosensitive epoxy resist was applied to the entire surface of the substrate on which the base substrate wiring 10 was formed by a known technique, and then an interlayer insulating layer 12 having vias 22 formed at necessary positions was formed by exposure / development. The arrangement of the vias 22 is not particularly limited, but in this embodiment, the via diameter is 75 μm and the land diameter is 150 μm. However, from the gist of the present invention, the via hole 22 provided in the wiring portion on the dicing line is designed to have an opening of 100 μm × 400 μm in order to improve the manufacturing yield.

【0033】

Further, a copper build-up wiring layer 11 having a thickness of 18 μm is formed on the interlayer insulating layer 12 by a known method. This wiring pattern is also not particularly limited, but in this embodiment, Line / Space = 75 μm / 75 μm was set (Fig. 2d).

【0034】

Using the same method, a plurality of layers of the interlayer insulating layer 12 and the build-up wiring layer 11 were sequentially laminated to form a build-up multilayer wiring layer 8. The build-up wiring layer 12 formed on the uppermost layer was set to Line / Space = 50 μ / 50 μm in consideration of the I / O pitch of the semiconductor chip to be mounted (Fig. 2e).

【0035】

Further, 120 μm solder resist 25 was formed on the front surface and the back surface of the build-up substrate excluding the electrode portion.

【0036】

In addition, a build-up multilayer wiring layer and a semiconductor chip were mounted on the back surface of the base substrate in the same manner.

【0037】

Next, the semiconductor chips 3 and 4 and the chip component 6 are mounted on the obtained multilayer circuit wiring board.

【0038】

In this way, a semiconductor module block as shown in FIG. 2f is created, and by stacking the semiconductor module blocks and dividing and dying, a semiconductor device in which the first semiconductor module and the second semiconductor module are laminated can be obtained. Created.

【0039】

The semiconductor chip and chip component mounted on this semiconductor module are general and not particularly limited from the gist of the present invention, but in the present invention, the micro visual module which is the ultra-small CCD camera shown in FIG. 3 is used. It is assumed that the CCD imaging signal processing circuit to be mounted is configured. The semiconductor chips that make up the stacked semiconductor modules are the CCD element 44, the amplifier element 45 that amplifies the analog signal from the CCD element 44, and the digital / analog conversion element (CDS) that digitally converts the analog imaging signal from the CCD element 44. It consists of / AD) 46, a driver element (v-driver) 47 that drives the CCD element, and a gate array element (GPA) 48 that wirelessly controls the digital signal-converted CCD imaging signal.

【0040】

2.0mm x 3.25mm V-driver with I / O = 19 as the first semiconductor chip, 3.38mm x 3.23mm CDS / AD chip with I / O = 64 as the second semiconductor chip, third As semiconductor chips, 3.8 mm x 3.8 mm G / A chips with I / O = 80, 14 chips of 1005 chip capacitors, 2 chips of 2012 chip capacitors, and 4 chips of 1005 chip resistors were used.

【0041】

A method of manufacturing a semiconductor module by mounting a semiconductor chip and chip components on a multilayer circuit wiring board will be specifically described below.

【0042】

First, the solder paste is screen-printed on the electrode terminals provided on the circuit wiring board using a metal mask for screen printing, and then the chip components are mounted and the whole is reflowed. Use Pb / Sn = 95/5 solder paste for this solder paste, and wash the BGA circuit wiring board with isopropyl alcohol for 10 minutes after solder reflow.

【0043】

One semiconductor chip is mounted on a multilayer circuit wiring board by flip-chip mounting using known bump electrodes. Specifically, it is composed of a V-driver semiconductor chip on which solder bump electrodes are formed and circuit wiring on a multi-layer circuit wiring board using a flip-chip bonder that has a half mirror, which is a known technology, for alignment. Align the electrode terminals to be used. The semiconductor chip is held in a collet having a heating mechanism and preheated in a nitrogen atmosphere at 350 ° C.

【0044】

Next, with the bump electrode of the semiconductor chip and the electrode terminal of the circuit wiring board in contact, the collet is further moved downward, and the pressure is 30 kg / mm.²Is added, and the electrode terminals of the circuit wiring board and the bump electrodes are brought into contact with each other under mechanical pressure. Further, in this state, the temperature is raised to 370 ° C to melt the solder, and the electrode terminals of the circuit wiring board and the bump electrodes of the semiconductor chip are connected.

【0045】

Using the same method, the CDS / AD, which is the second semiconductor chip, and the GA, which is the third semiconductor chip, are flip-chip mounted on the circuit wiring board. This solder bump electrode uses Pb / Sn = 37/63 eutectic solder as the electrode material.

【0046】

By this method, it is possible to realize a semiconductor device in which a semiconductor chip is flip-chip mounted on a multilayer circuit wiring board.

【0047】

Further, it is also possible to arrange a sealing resin, which is a known technique, in a gap portion formed between the semiconductor chip and the multilayer circuit wiring board. The resin to be sealed is not particularly limited, and for example, an epoxy resin containing a bisphenol-based epoxy and an imidazole curing catalyst, an acid anhydride curing agent and a spherical quartz filler in a weight ratio of 45 wt% may be used. it can.

【0048】

Next, the first semiconductor module and the second semiconductor module are laminated and connected to the side wiring board to complete the semiconductor device. The method will be described with reference to FIG.

【0049】

For example, after aligning the first semiconductor module 1 and the second semiconductor module 2 using a known mounter (FIG. 4a), the insulating resin 18 for adhesion is arranged on the surface of the first semiconductor module. Further, the second semiconductor module 2 is pressed against the first semiconductor module 1 with the insulating resin 18 sandwiched between them, and then the insulating resin is thermoset (FIG. 4b).

【0050】

The insulating resin 18 for adhesion is not particularly limited, but in the present embodiment, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.) and a phenol resin 54 as a curing agent. Epoxy resin melted by crushing, mixing, and melting parts by weight, 100 parts by weight of molten silica as a filler, 0.5 parts by weight of benzyldimethylamine as a catalyst, 3 parts by weight of carbon black as other additives, and 3 parts by weight of a silane coupling agent. The body was used.

【0051】

In the present embodiment, as the first semiconductor module 1, a V-driver, G / A, 5 chips of 1005 chip capacitors, 1 chip of 2012 chip capacitors, and 1 chip of 1005 chip resistors are mounted to form a second semiconductor module. As a result, CDS / AD, 9 chips of 1005 chip capacitor, 1 chip of 2012 chip capacitor, and 1 chip of 1005 chip resistor are mounted, but these configurations are not particularly limited.

【0052】

Further, when carrying out the step of laminating the semiconductor modules shown in FIG. 4A, it is preferable to arrange a spacer or the like between the first semiconductor module and the second semiconductor module, if necessary. As a result, the thickness of the insulating resin for stacking blocks can be made uniform, and as a result, the thickness of the blocks to be laminated can be made uniform. The stacking spacer is not particularly limited, but in this embodiment, for example, a rectangular parallelepiped block of 5 mmW × 1 mmD × 0.18 mmH made of a silicon material was used.

【0053】

Further, if necessary, for example, a sealing resin made of the same material as the insulating resin for stacking blocks is arranged on the front surface portion of the first semiconductor module unit and the back surface portion of the second semiconductor module unit. This sealing resin material is also not particularly limited, but the same material as the insulating resin for block lamination is effective for alleviating stress strain concentrated on the ball electrode, and is preferable from the viewpoint of connection reliability. is there.

【0054】

Next, split dicing is performed using a dicing device which is a known method. FIG. 5 is a diagram for explaining split dying.

【0055】

FIG. 5 is a partially enlarged view of a cross section of a region where the divided dicing line 17 of the semiconductor module and the base substrate 7 intersect.

【0056】

As described above, since the via 22 is formed on the first base board wiring 10, it is integrated with the build-up wiring layer and its film thickness is increased.

【0057】

Along the division dicing line 17, the laminated module substrate blocks are divided into 72 pieces as a semiconductor module of 11.5 mm × 5.2 mm. By dividing the module substrate along this dicing line, it is possible to realize a 98 I / O semiconductor device having a sufficient connection area as a block side electrode and an exposed Cu wiring cross section having a thickness of 40 μm.

【0058】

The semiconductor device manufactured by the above steps has an external dimension of 5.2 mmW × 5.2 mmH × 11.5 mmD, but the block side electrode and the block external dimension can be made highly accurate by the following method as needed.

【0059】

Specifically, the glass epoxy substrate and the epoxy sealing resin are mechanically polished. In mechanical polishing, it is preferable to make the unevenness to an accuracy of about ± 3 μm or less by micro polishing after making it uniform to ± 5 μm by macro polishing in order to improve the accuracy of the block external dimensions. For macro polishing, for example, cerium oxide having a particle size of about 5 μm to 10 μm or water-resistant abrasive paper of about # 1000 may be used, and for micro polishing, cerium oxide or alumina oxide or diamond having a particle size of about 0.3 μm may be used. preferable. At this time, if a wet polishing method using a liquid polishing paste as an abrasive is used, a difference in polishing speed occurs between the glass fiber and the epoxy resin, causing unevenness. Therefore, diamond or the like is embedded in the finishing micropolishing. It is preferable to use a dry polishing method using a disk board.

【0060】

By using the above polishing method, the semiconductor device according to the present invention can be made highly accurate to the dimensions of 5.2 mm ± 0.1 mm × 5.2 mm ± 0.1 mm × 11.5 mm ± 0.1 mm, and the block side electrodes. The unevenness of the surface could be improved to ± 1 μm.

【0061】

Further, as shown in FIG. 4c, the semiconductor device is mounted on the side wiring board 15.

【0062】

The process of mounting the semiconductor device on the side wiring board 15 is as follows.

【0063】

Specifically, first, the side wiring board 15 is prepared. The configuration of this side wiring board is not particularly limited, but in the present embodiment, a printing method in which an insulating layer and a conductor layer are mutually built up on a US Pat. No. 4,811082 or a normal glass epoxy board is printed. Substrate An SLC (Surface Laminar Circuit) substrate was used. Therefore, for example, it is possible to use a multi-layer flexible substrate of a type in which copper wiring is built-up formed on the surface using a polyimide resin as a substrate main material, a ceramic multilayer substrate of a build-up method, or the like.

【0064】

Further, 98 I / O solder ball electrodes 20 having a size of 200 μmφ corresponding to the block side electrodes of the three-dimensional mounting semiconductor device are arranged on the surface of the side wiring board, and are interconnected with the solder balls inside the wiring board. The circuit wiring for this is formed. The internal circuit wiring is also not particularly limited, but the wiring material is a metal selected from Al, Au, W, Cu, Ni, Cr, Pt, Pd, etc., a laminated metal selected from these metals, or these. An alloy containing a metal as a main component is preferable, and a solder resist is preferably coated except for a region connected to a semiconductor chip of the circuit wiring formed on the main surface of the multilayer circuit wiring board. In this embodiment, a circuit board having a circuit wiring pattern having a Cu wiring thickness of 20 μm as a build-up layer is used as the side wiring board.

【0065】

For mounting the semiconductor device on the side wiring board, a bonder having a half mirror and performing alignment can be used. At this time, the heater on which the vertical connection wiring board is mounted and the collet holding the semiconductor device are heated to 180 ° C, but since this temperature is lower than the eutectic temperature of the solder that constitutes the ball electrode, the ball electrode is It is in an unmelted state. Further, the ball electrode 20 on the side wiring board is aligned. In this way, with the semiconductor device and the ball electrode on the circuit wiring board in contact, the collet is further moved downward, and the pressure is 30 kg / mm.²Is added, and the ball electrode 20 and the side electrode (cross section of the base substrate wiring layer) of the semiconductor device are brought into contact with each other under mechanical pressure. Further, in this state, the temperature is raised to 250 ° C. to melt the solder, and the side electrode terminals and the ball electrodes are connected. The composition of the solder balls 20 at this time is Pb / Sn = 37/63, and the composition of the solder bumps on which the semiconductor chips are flip-chip mounted is also Pb / Sn = 37/63. Since the semiconductor chip is firmly fixed by the sealing resin, the solder bump electrode of the semiconductor chip does not remelt and a connection failure does not occur.

【0066】

It is possible to arrange the solder balls directly on the side surface of the semiconductor device instead of arranging the solder balls on the side wiring board. In this case, the side electrode arrangement of the semiconductor device can be optimized by forming a Cu / polyimide multilayer wiring, which is a known technique on the side surface of the semiconductor device, and performing the connection wiring in the vertical direction.

【0067】

By carrying out the above steps, it is possible to realize a CCD imaging signal processing circuit block for a microvisual module in which a 5.2 mmW × 5.2 mmH × 11.5 mmD semiconductor device is mounted on a circuit wiring board as shown in FIG.

【0068】

Furthermore, when the performance of the semiconductor device according to the present invention manufactured by the above steps was evaluated, the following results could be obtained.

【0069】

FIG. 6 shows a 11.5 mm × 5.2 mm V-driver, a first semiconductor module equipped with a G / A, and a 11.5 mm × 5.2 mm CDS / AD used to explain an embodiment of the semiconductor device according to the present invention. The mounting density of the second semiconductor module on which the This is the result of comparing the mounting densities manufactured by (secondary current mounting).

【0070】

As is clear from FIG. 6, in the conventional two-dimensional mounting technology, the mounting density decreases as the number of semiconductor chips mounted increases. This is because the peripheral circuit area required for mounting a semiconductor chip is extremely large, and as the number of semiconductor chips mounted on the circuit wiring board increases, the peripheral circuit area increases and the mounting density decreases.

【0071】

However, when the three-dimensional mounting technology is used as the mounting method of the semiconductor chip, it is possible to secure one or more regions as the mounting density, which cannot be realized by the two-dimensional mounting technology. However, when the MCM circuit wiring board and TCP are laminated as a laminated structure, the circuit wiring area, package sealing area, and vertical wiring connection area of the circuit wiring board cannot be ignored as the number of semiconductor chips mounted increases. Therefore, there is a limit to the improvement of the mounting density as compared with the case of laminating semiconductor bare chips of the same size.

【0072】

To solve this problem, in the semiconductor device according to the present invention, a build-up multilayer wiring board is used as a wiring board on which the semiconductor module is mounted, and a block side electrode that does not have a problem of a decrease in mounting density due to a vertical connection region is used for connection. Therefore, it is possible to bring the mounting density of the semiconductor device close to the value of stacking semiconductor bare chips of the same size, which enables the highest density.

【0073】

Further, when the reliability of the semiconductor device according to the present invention was evaluated, the results shown in FIG. 7 below were obtained.

【0074】

FIG. 7 shows the connection reliability of a sample in which the 5.2 mmW × 5.2 mmH × 11.5 mmD semiconductor device obtained as described above is mounted on a side wiring board composed of a glass epoxy multilayer wiring board using solder balls. This is the result of the evaluation, and is shown by the solid line.

【0075】

For comparison, only the build-up wiring layer is extended to the end of the semiconductor device, and the results when the build-up wiring layer single layer and the side wiring board are connected using solder balls are shown together with dotted lines. To do.

【0076】

The case where the connection is opened even at one of the 98 pins is regarded as a defect, and the vertical axis shows the cumulative defective rate and the horizontal axis shows the number of temperature cycles. The number of samples was 1000, and the temperature cycle conditions were (-55 ° C (30 min) to 25 ° C (5 min) to 125 ° C (30 min) to 25 ° C (5 min)).

【0077】

In the structure using only the build-up multilayer wiring layer as the side electrode, about 20% of the connection failure occurred in 1000 cycles, and the connection failure became 100% in 2000 cycles. From the graph, it is considered that there are two types of connection failure in particular, and the connection failure in the initial stage up to 1000 cycles is the initial connection failure that occurs because the build-up wiring film thickness is thin, and occurs after 1000 cycles. Poor connection is considered to be fatigue failure due to stress strain of the ball electrode. In order to confirm this consideration, samples of poor connection at each stage were extracted and analyzed by cross-sectional observation. As a result, the connection failure in the initial stage up to 1000 cycles occurs at the interface between the block side electrode and the solder ball, and the connection failure after 1000 cycles occurs inside the solder ball, and the connection failure up to 1000 cycles occurs. Is a defect that occurs because the build-up wiring film thickness is thin, and it was confirmed that the defect that occurs after 1000 cycles is the fatigue failure of the ball electrode.

【0078】

Further, in a structure in which the build-up multilayer wiring layer is used as a side electrode, a known sealing resin is placed on the solder ball portion. As a result, although the reliability of the semiconductor device is slightly improved, two types of connection defects occur as in the structure in which the sealing resin is not arranged, and the connection reliability of the block side electrodes cannot be sufficiently ensured. confirmed.

【0079】

On the other hand, it was confirmed that in the structure in which the side electrodes are used on the base substrate according to the present invention, connection failure does not occur up to 3500 cycles, and the connection reliability is extremely improved. In particular, when compared with the experimental results in which the structure when the semiconductor chip is not sealed by the block side electrode structure according to the present invention does not cause a connection failure up to 3000 cycles, it can be seen that the connection reliability is extremely improved. This is because the semiconductor device according to the present invention has an electrode cross section of the wiring film thickness which is the sum of the wiring film thickness on the base substrate and the build-up wiring film thickness, so that the wiring cross section can be secured to a sufficient value as the block side electrode area. Since the wiring arranged on the base board constitutes the side electrode of the block, the coefficient of thermal expansion of the vertical connection wiring board and the base board are the same, and the buildups with different coefficients of thermal expansion are different. It is considered that the layer acts as a layer for relaxing the stress strain caused by the difference in the coefficient of thermal expansion.

【0080】

From the above results, the semiconductor device according to the present invention can easily increase the mounting density and has extremely high connection reliability for different types of semiconductor chips having different external dimensions. It was confirmed that it is highly effective in solving the problem.

【0081】

The present invention is not limited to the above embodiment, and can be variously modified without departing from the gist thereof. For example, in this embodiment, three types of semiconductor chips are described, but the number and types of semiconductor chips to be mounted and the chip components to be mounted are not particularly limited, and the semiconductors to be laminated are not particularly limited. The module is also not particularly limited. Further, as a matter of course, the sealing resin arranged between the semiconductor chips, the ball electrode connected to the circuit wiring board, and the like are not limited.

【0082】

For example, FIG. 8 shows a schematic cross-sectional view of the semiconductor device as a modification thereof.

【0083】

In the semiconductor device shown in FIG. 8, metal heat dissipation paths 31, 32, and 33 are formed on the front surface of each semiconductor module, and the heat generated from the semiconductor chip is generated by contacting the back surfaces of the semiconductor chips 3, 4, and 5, respectively. Is released to the outside of the semiconductor device.

【0084】

When the reliability of this semiconductor device was evaluated, the results shown in Fig. 9 were obtained.

【0085】

FIG. 9 shows the results of evaluating the connection reliability of the sample in which the side wiring board is mounted on the semiconductor device shown in FIG. 8 as shown in FIG.

【0086】

When the semiconductor chip and the passive chip component were arranged so that they overlap each other on the opposite semiconductor module surfaces, a connection failure occurred in 3000 cycles and the connection failure became about 50% in 4000 cycles. Furthermore, in the resin-sealed sample in this layout arrangement, the connection reliability was improved up to 3500 cycles. From the graph, it is considered that there are two types of connection failure, and the connection failure in the initial stage up to 3500 cycles is caused by the malfunction caused by the local concentration of heat generated from the semiconductor chip. It is a fracture, and the connection failure that occurs after 3500 cycles is considered to be fatigue fracture due to the stress strain of the ball electrode formed on the side electrode of the block. In order to confirm this consideration, the electrical characteristics of the module were evaluated after the samples at each defective stage were extracted and the semiconductor device was disassembled. As a result, in the initial stage of connection failure up to 3500 cycles, the semiconductor chips were broken in the portion where the semiconductor chips overlap each other, and in the connection failure after 3500 cycles, the solder balls of the block side electrodes were broken. From this, the connection failure up to 3500 cycles is the failure failure of the semiconductor chip caused by the local concentration of heat generated from the semiconductor chip, and the connection failure that occurs after 1000 cycles is the fatigue failure of the ball electrode. I was able to confirm the sex.

【0087】

On the other hand, in the semiconductor device in which the semiconductor chip and the passive chip component of the present embodiment are arranged so as not to overlap each other on the surface of the semiconductor module unit facing each other, connection failure does not occur up to 4500 cycles and the connection reliability is extremely improved. It was confirmed that. In particular, in the layout arrangement in which the semiconductor chip and the passive chip component according to the present invention do not overlap each other, the connection reliability is compared with the experimental result in which the structure without resin sealing around the side electrode of the block does not cause a connection failure up to 5000 cycles. It can be seen that the sex is extremely improved. It is considered that this is because the semiconductor device according to the present invention is uniformly distributed and arranged on the surface of the semiconductor module in which the heat generated from the semiconductor chip is laminated, and the heat is efficiently dispersed and dissipated over the entire block. From the above results, it was confirmed that the semiconductor device according to the present invention is a highly effective technique capable of easily improving the mounting density and heat dissipation in the module stacking direction.

【0088】

[Effect of the invention]

As described above, according to the present invention, it is possible to obtain a semiconductor device having a high mounting density and high connection reliability with a side wiring board.

[Simple explanation of drawings]

[Figure 1]

The cross-sectional view which shows the embodiment of the semiconductor device which concerns on this invention.

[Figure 2]

The first cross-sectional process diagram which shows the manufacturing method of the semiconductor device which concerns on this invention.

[Fig. 3]

Explanatory drawing when the semiconductor layer of this invention was used for CCD.

[Fig. 4]

The second cross-sectional process diagram which shows the manufacturing method of the semiconductor device which concerns on this invention.

[Fig. 5]

A partially enlarged cross-sectional view showing an embodiment of the semiconductor device according to the present invention.

[Fig. 6]

The figure which shows the mounting density of the semiconductor device of this invention.

[Fig. 7]

The figure which shows the connection reliability of the semiconductor device of this invention.

[Fig. 8]

FIG. 5 is a cross-sectional view showing another embodiment of the semiconductor device of the present invention.

[Fig. 9]

The figure which shows the connection reliability of the semiconductor device of this invention.

[Fig. 10]

Sectional drawing of the conventional semiconductor device.

[Fig. 11]

Sectional view of another conventional semiconductor device.

[Explanation of symbols]

1 ...... 1st semiconductor module 2 ...... Second semiconductor module 3, 4, 5 ...... Semiconductor chips 7 ...... Base board 8 ...... Build-up multi-layer wiring layer 9 ...... Through hole 10 ...... Base board wiring 11 ...... Build-up wiring layer 12 ...... Interlayer insulation layer 14 ...... Ball electrode 15 ...... Side wiring board