Mutual connection layer and method of manufacturing semiconductor device having the layer

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Field to which the invention belongs]

The present invention relates to the field of manufacturing integrated circuits, and more particularly to dummy packed structures in interconnect layers.

【0002】

[Conventional technology]

Chemical mechanical polishing (CMP) is a technique for flattening an interconnect layer provided on a semiconductor substrate. Typically, multiple interconnect layers are deposited on the semiconductor substrate, where each interconnect layer comprises an active interconnect structure connecting the active areas of the semiconductor substrate. The active area is the part of the semiconductor substrate on which components such as transistors, capacitors, and resistors are formed.

【0003】

Prior to forming the interconnect layers, it is desirable that each interconnect layer have a flat or flattened top surface. A CMP is required because the top surface is not always flat after depositing the dielectric material due to the density of the area occupied by the active interconnect structure.

【0004】

The active interconnect structures within the interconnect layer are separated by trenches. Referring to FIG. 1, trenches 10 and 12 provided between active interconnect structures 20, 22 and 24 are much narrower than trench 14 provided between active interconnect structures 24 and 26. is there. One approach to filling trenches 10, 12, and 14 with dielectric material is high density plasma vapor deposition, especially when the trenches are between multiple active interconnect structures that are closely spaced. There is an HDP-CVD) method. If the deposited dielectric material 34 is thick enough, the interconnect layer 30 can be flattened by a single-step deposition method.

【0005】

As a result of carrying out the HDP-CVD method, protrusions 32 are formed on the upper surface of the dielectric material 34 on each of the active interconnect structures 20 to 26. Each of the protrusions 32 has its own associated bias. This bias can be defined as either positive or negative. In the HDP-CVD process as shown in FIG. 1, each of the protrusions 32 has a negative bias. That is, the width of the protrusion is shorter than the width of the underlying active interconnect structure or the lateral length of 90. In areas where there is no active interconnect structure, such as between active interconnect structures 24 and 26, the top surface of the dielectric material 34 is relatively flat.

【0006】

Another method of depositing the dielectric material is by the two-step method, as shown in FIG. The first step is by the HDP-CVD method of filling trenches 10-14 between active interconnect structures 20-26 with dielectric material 34. Once trenches 10-14 are filled, plasma vapor deposition (PE-CVD) adds more dielectric material 35 to ensure that the combined thickness is sufficient for flattening. After the PE-CVD method, the protrusions 42 formed on each of the active interconnect structures 20-26 have a positive bias. Positive bias occurs when the width of the protrusion 42 is greater than the width or lateral length of the underlying active interconnect structure.

【0007】

[Problems to be Solved by the Invention]

Some deposition methods use a CMP to remove the positively biased protrusions 42 and the negatively biased protrusions 32. However, when the pattern density change of the active interconnection structures 20 to 26 is large, CMP is not suitable for sufficiently flattening the interconnection layer 30. For example, flattening a relatively flat dielectric material provided on active interconnect structures 24, 26 will result in overpolishing. This causes significant depressions in the dielectric material 34 or 35 and the surface is not flattened. The unflattened surface of the interconnect layer 30 can cause problems with the reliability of the interconnect layer on top of it.

【0008】

One method of preventing excessive polishing is to place a dummy filling structure in an open region close to the active interconnect structure to prevent changes in the pattern density of the active interconnect structure. The placement of the dummy filling structure is typically done using a layout algorithm as part of a layout editor or automatic pattern generator.

【0009】

Conventional layout algorithms for placing dummy packed structures in the open area of the interconnect layer are implemented based on a predetermined set density. Each open area filled with a dummy filling structure will also have the same density. In other words, the dummy packed structure density is independent of the density of adjacent active interconnect structures. An open area is defined in any metal-free area within its interconnect layer. The packed structure density is defined as the ratio of the area occupied by the metal to the total area.

【0010】

However, if the density of the active interconnect structure is higher than that of the adjacent open area, it is not always necessary to place the dummy filling structure within the relevant open area with the same predetermined set density. Unnecessarily arranging the dummy filling structure increases the parasitic capacitance of the interconnect layer. Moreover, there is no constant overall packing density between the open areas of the interconnect layers. Further, this change in the density of the interconnect layer causes deflection when the interconnect layer is flattened. Therefore, in order to obtain a uniform density over the entire interconnect layer, it is necessary to form a layout for the interconnect layer that determines the arrangement of the dummy packed structure.

【0011】

An object of the present invention is to provide a method of forming a layout for an interconnect layer having a uniform density throughout to facilitate flattening during the manufacture of a semiconductor device.

【0012】

Another object of the present invention is to place a dummy packed structure within the interconnect layer to minimize parasitic capacitance with adjacent interconnect structures.

【0013】

[Means for solving problems]

These and other purposes, advantages, and features according to the present invention are methods for forming a layout for an interconnect layer of a semiconductor device, which facilitates uniform flattening during the manufacture of the semiconductor device. Active interconnect structure and dummy filling structure to facilitate the process of determining the active interconnect structure density of each of the multiple layout regions of the interconnect layout and the equalization of flattening performed during the manufacture of semiconductor devices. It is obtained by a method having a step of adding a dummy filling structure to each layout region in order to obtain the desired density of the above.

【0014】

One important feature of the present invention is that each layout area preferably has a uniform density. By adding the dummy packed structure to obtain the desired density of the active interconnect structure and the dummy packed structure, the dummy packed structure is not added unnecessarily. Unnecessarily adding a dummy filling structure is not preferable because the parasitic capacitance of the interconnect layer increases.

【0015】

If each of the layout areas has a uniform density, the dummy filling structure facilitates the uniformization of flattening during the manufacture of the semiconductor device. Another important feature of the present invention is that the placement of the dummy filling structure is preferably based on the capacitance with the adjacent active interconnect structure. Similarly, the dummy packed structure is preferably arranged based on its capacitance with the adjacent active interconnect structure within the adjacent interconnect layer.

【0016】

Yet another important feature of the present invention is to define the minimum lateral length of the dummy packed structure based on the dielectric layer deposition bias of the dielectric layer overlaid on the interconnect layer. .. After the single-step HDP-CVD process, the protrusions of the dielectric material on each active interconnect structure have a negative bias. Negative bias occurs when the width of the protrusion is shorter than the width or lateral length of the underlying active interconnect structure. In some embodiments, the lateral length of the dummy weighted structure is preferably at least twice the absolute value of the negative dielectric layer deposition bias.

【0017】

Another aspect of the invention relates to a semiconductor device manufacturing method, which comprises the steps of forming an active area within a semiconductor substrate, with active interconnect structure densities for each of the plurality of layout regions of the interconnect layout. To facilitate the step of determining and the homogenization of flattening during the manufacture of the semiconductor device, each layout region is provided with a dummy filling structure to obtain the desired density of active interconnect layout and dummy filling structure. It further has a step of forming an interconnect layer layout with a step of adding. The method further preferably includes a step of using the layout to form an interconnect layer on top of the semiconductor substrate.

【0018】

Yet another aspect of the invention is a semiconductor device, which has a semiconductor substrate, is provided on the semiconductor substrate, and has at least one interconnect layer with a plurality of layout areas. Each of these layout regions includes an active interconnect structure region and a dummy filling structure region in close proximity thereof to facilitate uniform flattening during the manufacture of the semiconductor device.

【0019】

Each of the dummy packed structure regions has a different density with respect to another dummy packed structure region, so that the combined density of the active interconnected structure region and the dummy filled structure region for each layout region is other. It is preferable that the layout area is substantially uniform with respect to the combined density. The interconnect layer preferably has a metal and each layout region preferably has a uniform density.

【0020】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described more completely with reference to the accompanying drawings showing preferred embodiments of the present invention. However, the present invention can be implemented in a number of different forms and should not be construed as limited to the examples described herein. Rather, these examples are presented to complete the disclosure and to fully convey the scope of the invention to those skilled in the art. Throughout all drawings, the same elements are indicated by the same reference numerals.

【0021】

With reference to FIGS. 3 to 5, a layout forming method for the interconnection layer of the semiconductor device that promotes the uniformity of flattening performed during the manufacture of the semiconductor device will be described. The method begins at the start (block 50), at block 52, and as shown in FIG. 4, the structure of the active interconnect for each of the plurality of layout areas 60 (1) to 60 (n) of the interconnect layout 30. Determine the density.

【0022】

The size of each layout area 60 (1) to 60 (n) is preferably the same, and the exemplary size may be 100 × 100 μm. Further, the layout areas 60 (1) to 60 (n) are close to each other. However, as will be easily understood by those skilled in the art, other sizes may be adopted, and the size of each layout area does not have to be the same. For the purposes of illustration, the active interconnect structures 70 (1)-70 (n) are generally indicated by an area filled with a single diagonal line within each layout area 60 (1)-60 (n). As will be readily appreciated by those skilled in the art, each shaded area will have a plurality of metal wires or traces, which will connect the active areas within the semiconductor substrate 82 to each other.

【0023】

The densities of the active interconnect structures 70 (1) to 70 (n) are determined using a layout algorithm for each of the layout areas 60 (1) to 60 (n). As will be readily appreciated by those skilled in the art, this layout algorithm may be the same as the algorithm used to perform the steps shown in FIG. 3 to form the desired layout of the interconnect layers.

【0024】

The method further includes in block 54 each layout area 60 to obtain the desired density of active interconnect structures and dummy packed structures to facilitate uniform flattening during the manufacture of the semiconductor device 80. It is provided with a step of adding dummy filling structures 74 (1) to 74 (n) to (1) to 60 (n). For the purposes of illustration, the dummy filling structures 74 (1) to 74 (n) are generally shown as an area filled with a single diagonal line within each layout area 60 (1) to 60 (n). Therefore, each shaded area is provided with a dummy metal wire or trace for easy understanding by those skilled in the art. The method beneficially adds dummy packed structures 74 (1) to 74 (n), which results in a uniform density for each layout area 60 (1) to 60 (n). The formation of the interconnect layer 30 ends at block 56.

【0025】

For example, if the density of the active interconnect structure 70 (1) in the layout area 60 (1) is 50%, and the desired target density of the active interconnect structure and dummy packed structure is also 50%, it is added. The density of the dummy packed structure 74 (1) is also 50%. However, if the density of the active interconnect structure 70 (1) is less than 50% in the layout area 60 (2), the density of the added dummy filling structure 74 (2) will be higher than 50%. The desired target density of the active interconnect structure and dummy filling structure in the layout area is again 50%. By minimizing the overall density change between the layout areas 60 (1) to 60 (n) of the interconnect layer 30, it is easy to flatten by chemical mechanical polishing (CMP) during the manufacture of the semiconductor device 80. Become.

【0026】

When the densities of the respective layout areas 60 (1) to 60 (n) are the same, the dummy filling structures 74 (1) to 74 (n) thus make the flattening uniform during semiconductor device manufacturing. It becomes easy to change. However, each semiconductor device may have significantly different densities of active areas within the semiconductor substrate 82, which affects the layout of the active interconnect structure of the interconnect layer 30 above it, so layout area 60 (1). ) ~ 60 (n) need not have the same density.

【0027】

Nevertheless, it is preferable that the densities between the layout areas 60 (1) to 60 (n) are the same. By adding the dummy packed structures 74 (1) to 74 (n) to obtain the desired density of the active interconnect structure and the dummy packed structure, the dummy packed structure is not added unnecessarily. Unnecessarily adding a dummy filling structure is not preferable because the parasitic capacitance of the interconnection layer 30 increases.

【0028】

Another important feature of the present invention is that the arrangement of dummy packed structures 74 (1) to 74 (n) is based on the capacitance with the adjacent active interconnect structures 70 (1) to 70 (n). It is a point to be told. Similarly, dummy packed structures 74 (1)-74 (n) are also preferably based on capacitance with adjacent active interconnect structures in adjacent interconnect layers. In other words, the dummy filling structure can be selectively placed to minimize the resulting additional parasitic capacitance.

【0029】

As is known to those skilled in the art, there are two types of dummy filling structures, a grounded type and a floating type. When using the grounded form, place all dummy filling structures in a well-known location, eg, on the ground. This allows the layout algorithm to calculate the capacitance after the dummy filling structure has been placed. In the floating form, a dummy packed structure is added to the low density area. However, the floating dummy packing structure acts as an additional coupling passage and affects the total parasitic capacitance of the interconnect layer 30. It is difficult to calculate the capacitance from the floating form because there is no passage to the ground.

【0030】

The layout algorithm used in the present invention to form the layout for the interconnect layer 30 has dummy packed structures 74 (1) to 74 (n) in order to minimize the total parasitic capacitance resulting from the addition of the dummy packed structure. ) Is determined. This algorithm limits the floating dummy packed structures 74 (1) to 74 (n), thereby limiting them within a specific range from the active interconnect structures 70 (1) to 70 (n). Make sure the structure connects to the ground.

【0031】

This range may be the buffer length, which is the shortest allowable distance between any active interconnect structure region 70 (1) to 70 (n) and the dummy packed structure region specified by the algorithm. In this case, all dummy filling structures 74 (1) to 74 (n) that directly surround the active interconnect structure are grounded. In general, this range can be optimized for the best trade-off between the available design resources and the capacitive addition component introduced due to the coupling effect of the dummy filling structure. ..

【0032】

Yet another important feature of the method of the invention is at least based on the dielectric layer deposition bias of the dielectric material 34 or 35 deposited on the interconnect layer 30, as shown in FIGS. 1 and 2. It is to define the lateral length 90 of the limit dummy filling structure. The dielectric material is silicon dioxide. After the single-step HDP-CVD process shown in FIG. 1, the protrusions 32 of the dielectric material over each active interconnect structure have a negative bias. Negative bias occurs when the width of the protrusion 32 is shorter than the width of the underlying active interconnect structures 20-26 or the lateral length 90.

【0033】

Referring to FIG. 1, a dummy packed structure is required between the active interconnect structures 24 and 26 to create another protrusion 32 on the top surface of the dielectric material 34 to facilitate flattening of the interconnect layer 30. Is. Ideally, the protrusions 32 are placed within the dielectric material 34 to prevent depressions during the flattening process.

【0034】

For negative dielectric layer bias, any lateral length 90 of the added dummy filling structure must be minimal to produce the desired protrusions. For example, if the negative bias is -1.5 microns, the lateral length of the dummy packed structure should be at least twice the absolute value of the negative dielectric layer deposition bias. In other words, the lateral length requires at least 3 microns to produce a negative bias of -1.5 on the top surface of the dielectric material.

【0035】

For the positive dielectric layer deposition bias, it is not necessary to set the minimum lateral length of the dummy packed structure to create the protrusions 42 on the top surface of the dielectric material 35, as shown in FIG. This is because the positive bias is always greater than the lateral length of each dummy filling structure.

【0036】

Another aspect of the present invention relates to a semiconductor device comprising a semiconductor substrate 82 and at least one interconnect layer 30 provided on the semiconductor substrate. The interconnect layer 30 includes a semiconductor substrate 82 and at least one interconnect layer provided on the semiconductor substrate and having a plurality of layout areas 60 (1) to 60 (n).

【0037】

Each layout area 60 (1) to 60 (n) is an active interconnect layer structure area 70 (1) to 70 (n) and this, in order to promote the uniformity of flattening during the manufacture of the semiconductor device. It has dummy packed structure regions 74 (1) to 74 (n) in close proximity to. The dummy packed structure regions 74 (1) to 74 (n) have different densities with respect to different dummy packed structure regions, whereby the active interconnect structural region 70 (for each layout area 60 (1) to 60 (n)) ( The combined density of 1) to 70 (n) and the dummy packed structure region is substantially uniform with respect to the combined density of another layout region. The interconnect layer 30 contains metal and each layout area 60 (1) -60 (n) has a uniform density.

【0038】

Many modifications and other embodiments of the present invention will be conceivable to those skilled in the art who have obtained the teachings of the drawings associated with the above description. Therefore, it should be understood that the present invention is not limited to the specified embodiments disclosed, and that modifications and examples are within the scope of the appended claims.

【0039】

[Effect of the invention]

According to the present invention, flattening performed during manufacturing of a semiconductor device is facilitated, and parasitic capacitance with an adjacent interconnect structure is minimized.

[Simple explanation of drawings]

[Figure 1]

FIG. 6 is a partial cross-sectional view of a semiconductor device showing a negative bias of the interconnect layer produced by the single-step deposition method prior to flattening by the prior art.

[Figure 2]

FIG. 6 is a partial cross-sectional view of a semiconductor device showing a positive bias of an interconnect layer produced by a two-step deposition method prior to flattening by prior art.

[Fig. 3]

It is a flowchart which shows the method of forming the layout for an interconnect layer by this invention.

[Fig. 4]

It is a partial upper plan view of the interconnection layer divided into a layout area according to this invention.

[Fig. 5]

It is a partial cross-sectional view of the semiconductor device provided with the interconnect layer shown in FIG.

[Explanation of symbols]

10, 12, 14 trench 20 ~ 26 Active interconnect structure 30 interconnect layer 32 protrusions 34, 35 Dielectric material 42 protrusions 50 blocks 50 52 block 52 54 block 54 56 blocks 56 60 (1) ~ 60 (n) Layout area 70 (1) ~ 70 (n) Active interconnect structure 74 (1) ~ 74 (n) Dummy filling structure 80 semiconductor device 82 Semiconductor substrate