Method of manufacturing semiconductor device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for forming a gate electrode of a MOSFET.

【0002】

[Conventional technology]

With the increasing integration of semiconductor devices, a technique has been proposed in which the gate electrode of the MOSFET is reduced to form a gate electrode having a width smaller than the minimum size that can be formed by the photolithography technique currently available. In this technique, a gate electrode is formed from a polysilicon film formed on a gate insulating film by patterning using photolithography and dry etching techniques. The polysilicon film is a gate oxide film (SiO).₂) Is etched to a predetermined thickness by main etching, and then the surface of the gate oxide film is etched by overetching, which has a high selectivity with the gate oxide film.

【0003】

However, when the gate electrode is formed by dry etching according to the above-proposed technique, there is a problem that the pattern size varies due to the difference in the density of the pattern on the wafer, that is, a so-called in-plane shape difference occurs.

【0004】

Japanese Unexamined Patent Publication No. 11-260799 describes a thin film microfabrication method for solving the above problems. The method described in the publication will be described with reference to FIG. 3 nm oxide film (SiO) on silicon wafer 301₂Membrane) 302, 200 nm doped polysilicon (DOPOS) film 303, and 200 nm silicon nitride film 304 are formed in this order. The silicon nitride film 304 is processed by photolithography and has a minimum line width of 0.13 μm.

【0005】

The DOPOS film 303 is etched in a plurality of steps using the silicon nitride film 304 as a mask. In the first step, for example, chlorine gas (Cl)₂) At a flow rate of 120 ml / min, etching for 5 seconds under the conditions of a furnace pressure of 0.1 Pa, RF power of 160 mW, and microwave power of 500 mW to remove the natural oxide film generated on the surface of the DOPOS film. Remove. The second step is the main etching, and in this main etching process, Cl₂Flow rate 108 ml / min, oxygen gas (0₂) The DOPOS film 303 is etched by setting the flow rate to 12 ml / min and reducing the selectivity between the DOPOS film 303 and the oxide film 302.

【0006】

During the main etching process, the remaining film thickness of the DOPOS film 303 is measured by an optical interference type real-time film thickness monitor, and when the film thickness reaches 30 nm, the over-etching process, which is the third step from the main etching process, is performed. Move to. In this overetching step, O is used to increase the selectivity between DOPOS film 303 and oxide film 302.₂The flow rate is 3 ml / min and the HBr flow rate is 100 ml / min.

【0007】

When etching the DOPOS film 303, the etching damage that occurs in the gate oxide film 302 is prevented by combining the main etching step having a low selectivity with the gate oxide film 301 and the overetching step having a high selectivity. In particular, by measuring the film thickness in real time with an optical interference type film thickness monitor, switching between the main etching process and the overetching process is controlled according to the film thickness of the remaining DOPOS film.

【0008】

[Problems to be Solved by the Invention]

In the thin film microfabrication method described in the above publication, there is a problem that an undesired sub-trench is generated in the DOPOS film due to the difference in the pattern density on the wafer, and therefore the film thickness of the remaining DOPOS film can be different. is there. This situation is shown in FIGS. 10 (a) to 10 (c).

【0009】

First, as shown in FIG. 10A, a small amount of sub-trench 305 is generated in the side wall portion of the DOPOS film 303 during the main etching, especially in the area where the pattern density is large. At the end of the main etching, the sub-trench 305 progresses to the surface of the gate oxide film 302, and then to the surface of the substrate 301 in the subsequent overetching step, as shown in FIG. It causes damage to the surface. That is, the sub-trench 305 formed on the gate oxide film 302 by the main etching proceeds to the substrate surface by the subsequent over-etching to cause substrate damage and deteriorate the characteristics of the obtained MOSFET.

【0010】

The cause of sub-trench generation during main etching is that the ion density increases at the edge of the gate electrode due to the reflection of ions on the side wall of the photoresist or nitride film, and the pattern density is particularly large. In the region, it is conceivable that electron shading affects the ion incident orbit. The degree of occurrence of sub-trench varies depending on the deposit type, its amount, or coverage, and as a result, it greatly affects the variation in the residual film thickness of the DOPOS film. However, conventionally, effective measures have not been taken to suppress the variation in the residual film thickness.

【0011】

In view of the above, the present invention provides a method for manufacturing a semiconductor device, particularly a method for patterning a gate electrode of a MOSFET in which damage due to etching is unlikely to occur on a substrate or a gate oxide film when manufacturing a semiconductor device having a MOSFET. With the goal.

【0012】

[Means for solving problems]

In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention is a patterning in which an oxide film and a polysilicon film are sequentially formed on a substrate, and the polysilicon film is selectively dry-etched using a mask. In a method for manufacturing a semiconductor device having a step, the patterning step is Cl.₂, HBr and CF₄The main etching process for dry etching the polysilicon film in the presence of HBr and O₂It is characterized by sequentially having an overetching step of dry etching the polysilicon film in the presence of. In the method for manufacturing a semiconductor device of the present invention, the gate electrode film is etched by main etching with good dimensional controllability, and by overetching to increase the selectivity with the gate oxide film. CF by deposit in the sub-trench formed during the main etching process₄Is attached, so that the formation of sub-trench formed on the polysilicon film can be prevented, and the film thickness of the polysilicon film is averaged after the main etching step. Due to this averaged film thickness, it is possible to prevent damage to the oxide film and the substrate surface, which tend to occur due to subsequent overetching.

【0013】

In Japanese Patent Application Laid-Open No. 11-176804, when the titanium silicide film and the polysilicon film are sequentially etched, CF is added to HBr as the etching gas.₄Is described to be mixed. However, in the publication, CF₄The purpose of mixing is TiSi₂This is to prevent the residue generated during etching by bringing the etching rates of Si and Si close to each other, and to prevent the formation of sub-trench in the present invention.₄It is different from the purpose of use. In a preferred example of the method for manufacturing a semiconductor device according to the present invention, the thickness of the remaining polysilicon film was measured with an optical interferometer monitor during the main etching step, and the output of the optical interferometer monitor was first-order differentiated. In response to the change in the differential waveform, the main etching step is switched to the overetching step. By detecting the change in the first-order differential waveform in this way, it is possible to particularly effectively detect that the film thickness of the remaining polysilicon has reached a predetermined value.

【0014】

Further, in the main etching process, CF₄It is also a preferred embodiment of the present invention that the flow rate is in the range of 30 to 50 sccm and the atmospheric pressure is 10 m Torr. In this case, the generation of sub-trench can be prevented particularly well, and etching can be performed with good throughput. CF₄If the flow rate is below this range, the sub-trench cannot be effectively suppressed, and above this range, the dimensions of the obtained gate electrode will vary.

【0015】

Further, in the overetching, the atmospheric pressure is 50 mTorr or more, and HBr and O₂It is also a preferable aspect of the present invention that the flow rates of the above are 100 to 200 sccm and 1 to 3 sccm, respectively. In this case, the selection ratio between the oxide film and the polysilicon film is particularly large, and the damage given to the oxide film is further reduced.

【0016】

According to the method for manufacturing a semiconductor device of the present invention, a gate electrode having a width of 0.1 μm or less can be formed from a polysilicon film, and a gate electrode having a shape particularly suitable for a next-generation fine MOSFET can be obtained. As a mask used when etching the polysilicon film, a photoresist film, a silicon nitride film, or the like can be used.

【0017】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the present invention will be described in more detail with reference to the drawings based on preferred embodiments of the present invention.

【0018】

1 (a) to 1 (c) are cross-sectional views of a semiconductor device, respectively, showing steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention in sequence. In the manufacturing method of the present embodiment, first, as shown in FIG. 3A, a silicon oxide film 11 having a film thickness of 60 Å and a gate electrode film 12 having a film thickness of 1500 Å are formed on the silicon substrate 10. The photoresist film 13 is applied onto the photoresist film 13 and the photoresist film 13 is patterned by a photolithography technique. For the gate electrode film 12, for example, a doped polysilicon (DOPOS) film is used.

【0019】

Next, the temperature of the wafer stage (board temperature) was set to 60 ° C, Cl.₂Etching is performed for 5 seconds with an atmospheric pressure of 5 mTorr, a source power of 200 W, and a bias power of 100 W to remove the natural oxide film formed on the DOPOS film 12.

【0020】

Next, the process proceeds to the main etching step of dry etching the gate electrode film 12. The main etching process is Cl₂Flow rate is 50sccm, HBr flow rate is 90sccm, CF₄The flow rate is 40 sccm, the atmospheric pressure is 5 mTorr, the source power is 300 W, and the bias power is 60 W. According to this condition, the etch rate of the gate electrode film 12 is 1700 Å and the uniformity is ± 4.4%. The selectivity between the gate electrode film 12 and the gate oxide film 11 is about 4. By reducing the selectivity with the gate oxide film 11 in this way, the dimensional controllability of the obtained gate electrode 12 is improved. That is, the side wall of the gate electrode 12 has a vertical shape, and for example, a gate electrode having a width of 0.1 μm or less can be formed with good dimensional controllability.

【0021】

While performing the main etching, the remaining film thickness of the gate electrode film 12 is measured. The film thickness is measured in real time using an optical interferometer. When the signal of the optical interferometer shows a predetermined change, it is assumed that the film thickness of the remaining gate electrode film 12 is, for example, 100 Å at the minimum and 230 Å at the maximum, and the process proceeds to the overetching step. In this overetching process, the HBr flow rate is 150 sccm, O₂The flow rate is 1.5 sccm, the atmospheric pressure is 60 mTorr, the source power is 250 W, and the bias power is 75 W, and the operation is performed for about 45 seconds. According to this condition, the etch rate of the gate electrode film 12 is 1200 Å and the uniformity is ± 3.4%. Further, the selection ratio between the gate electrode film 12 and the gate oxide film 11 is as high as 200 or more.

【0022】

At the end of the overetching step, the gate electrode film 12 is completely etched by adopting a high selectivity in the overetching step, and most of the gate oxide film 11 remains as it is and is exposed on the surface. Further, the surface of the substrate 10 is protected by the gate oxide film 11, and the damage generated on the substrate surface is reduced.

【0023】

As described above, when switching from the main etching process to the over-etching process, if the thickness of the remaining gate electrode film 12 is set to 100 Å at the minimum, due to the uniformity condition in the main etching process, due to the slowest etching rate. The thickness of the gate electrode film 12 remaining at the position to be etched is about 230 Å. If the gate electrode film 12 is left thick in the main etching step, the verticality of the side wall of the gate electrode is impaired by the subsequent overetching of the high selectivity. Therefore, it is preferable that the gate electrode film 12 to be left is small, and on the other hand, it is necessary to prevent the gate electrode film 12 from becoming zero in thickness at the end of the main etching process and damaging the gate oxide film 11. If good verticality is obtained on the side wall of the gate electrode film 12 in the main etching step, the good verticality is maintained in the subsequent overetching step. According to the experiment, the duration of the main etching in which the desired film thickness was obtained for the gate electrode film under the above conditions was 45 seconds.

【0024】

FIG. 2 shows a state of real-time measurement of the film thickness of the remaining gate oxide film 12 by an optical interferometer. The light from the mercury lamp 21 is irradiated to the mirror 23 by the optical fiber 22, and the reflected light from the mirror 23 is projected onto the wafer 27 mounted on the lower electrode 28 in the etching chamber 26 via the lens 24 and the quartz window 25. doing. The light reflected from the wafer 27 irradiates the mirror 23 again through the quartz window 25 and the lens 24, and the light reflected from the mirror 23 is incident on the interference detector 29 via the optical fiber 22. Here, the presence or absence of mutual interference between the light reflected on the front surface of the optically transparent polysilicon film forming the gate electrode film on the wafer 27 and the light transmitted through the polysilicon film and reflected on the back surface thereof causes optical interference. Detected by detector 29.

【0025】

In the main etching step, interference measurement was performed by changing the wavelength of the projected light, and a wavelength at which a good optical interference signal was obtained was obtained. The observation results of light interference between light having a wavelength of 245 nm, light having a wavelength of 365 nm, and light having a wavelength of 435 nm when the gate electrode film having a film thickness of 1500 Å is etched are shown in FIGS. The horizontal axis shows the etching progress time, and the vertical axis shows the intensity of the observed interference signal in arbitrary units. The intensity of plasma emission is also shown. In each case, observation was continued until the polysilicon film was completely etched.

【0026】

As can be understood from the comparison of FIGS. 3 to 5, no effective optical interference signal was obtained in the interference observation with the light having a wavelength of 254 nm shown in FIG. It was presumed that this was because deposits adhered to the inside of the quartz window 25 of the etching chamber 26 and a valid signal could not be obtained.

【0027】

In FIG. 4, it can be understood that the interference signal generated about 40 seconds after the start of etching indicates the switching time of the etching process, which is calculated backward from the time when the polysilicon film is completely etched. The maximum residual film thickness of the polysilicon film at this point is 500 Å, and the switching time of the etching process is detected relatively effectively.

【0028】

In FIG. 5, a signal indicating optical interference is generated about 20 seconds after the start of etching, but at this point, the maximum residual film thickness was 1000 Å. That is, it was found that the detected signal is not a signal at a time suitable for process switching, and therefore, effective optical interference signal cannot be obtained with light of this wavelength.

【0029】

From the above observation results, it can be seen that when light having a wavelength of 365 nm is used for observing optical interference, the switching time (endpoint) of the etching process can be effectively detected.

【0030】

FIG. 6 shows a differential signal obtained by first-order differentiation of the optical interference signal observed with light having a wavelength of 365 nm when etching a polysilicon film having a thickness of 1000 Å. The endpoint indicating the switching time of the etching process was generated 54 seconds after the start of etching. At that time, the results of measuring the film thickness distribution before and after the main etching process are shown in FIG. FIG. 7 (a) shows the original film thickness distribution of the gate electrode before etching, and FIG. 7 (b) shows the film thickness distribution at the endpoint. Film thicknesses at the endpoints ranged from 119 to 174 Å, with an average of 252 Å. From this result, it can be understood that the endpoint can be detected particularly effectively by the differential signal obtained by first-order differentiation of the optical signal observed with light having a wavelength of 365 nm.

【0031】

In the gate electrode forming process of the above embodiment, Cl is obtained in the natural oxide film removing step.₂Was used as the etching gas, but instead of this, for example, a CF of 100 sccm₄Can be used as an etching gas. Example The method of the present invention and the conventional method were compared. In each case, when the line width / space was 0.18 / 0.24 μm, the above-described embodiment of the present invention and the method according to the prior art were used.

【0032】

In the prior art method, as an etching condition, in the natural oxide film removal step, Cl₂The flow rate was 50 sccm, the atmospheric pressure was 5 m Torr, the source / bias power was 200/100 W, and the operation was performed for 5 seconds. Cl in main etching₂/ HBr / O₂The flow rate was 100/150 / 3sccm, the atmospheric pressure was 10mTorr, the source / bias power was 300 / 25W, the film thickness was measured, and overetching was switched. As a result, the etching time of the main etching was 45 seconds. In overetching, HBr / O₂The flow rate was 150 / 1.5sccm, the atmospheric pressure was 60mTorr, the source / bias power was 250 / 75W, and the operation was performed for 45 seconds. The substrate temperature was 60 ° C.

【0033】

In the method of the embodiment, the natural oxide film removal step was the same as that of the conventional method. In the main etching, Cl₂/ HBr / CF₄The flow rate was 50/90 / 40sccm, the atmospheric pressure was 5mTorr, the source / bias power was 300 / 60W, and etching was performed for 45 seconds, which is the same as the conventional method. In overetching, HBr / O₂The flow rate was 150 / 1.5sccm, the atmospheric pressure was 60mTorr, and the source / bias power was 250 / 75W for 5 seconds. The substrate temperature was kept at 60 ° C.

【0034】

The observation results are shown in FIGS. 8 (a) to 8 (d). Figures (a) and (b) show the shape of the gate electrode after main etching and over-etching of the conventional method, and FIGS. (C) and (d) show the shape of the gate electrode after main etching and over-etching of the method of the present invention. Indicates the electrode shape.

【0035】

In the gate electrode formed by the conventional method, after the main etching, the side etching and the tail etching shapes, and the formation of the sub-trench in the area where the pattern density is particularly high were observed. Due to this, a hemming shape was observed after overetching. On the other hand, in the gate electrode obtained by the method of the present invention, side etching, hem etching shape, and sub-trench formation after main etching are not observed. Therefore, after over-etching, a good vertical side wall surface is formed. The gate electrode to have was obtained.

【0036】

The preferred etching conditions in the method of the present invention are CF in the main etching step.₄The flow rate is in the range of 30 to 50 sccm, and the atmospheric pressure is 10 m Torr. In the over-etching process, the atmospheric pressure is set to 50 mTorr or more, and HBr and O₂The flow rate is in the range of 100 to 200 sccm and 1 to 3 sccm, respectively. According to the above conditions, dimensional controllability having a preferable shape can be obtained particularly when forming a gate electrode having a width of 0.1 μm or less.

【0037】

Although the present invention has been described above based on the preferred embodiment, the method of forming the gate electrode in the present invention is not limited to the configuration of the embodiment, and the configuration of the embodiment is used. Those with various modifications and changes are also included in the scope of the present invention.

【0038】

[Effect of the invention]

As described above, according to the method for manufacturing a semiconductor device of the present invention, there is an effect that the gate electrode can be formed with good shape controllability and high throughput without causing damage to the gate oxide film and the substrate.

[Simple explanation of drawings]

[Figure 1]

(a) to (c) are cross-sectional views showing sequentially the manufacturing methods of the semiconductor device according to the embodiment of the present invention, respectively.

[Figure 2]

Schematic cross-sectional view showing the state of film thickness observation by a real-time optical interferometer type film thickness monitor.

[Fig. 3]

The graph which shows the output of the optical interferometer when the light of the wavelength 254 nm is used.

[Fig. 4]

The graph which shows the output of the optical interferometer when the light of the wavelength 365 nm is used.

[Fig. 5]

The graph which shows the output of the optical interferometer when the light of the wavelength 435 nm is used.

[Fig. 6]

A graph showing a signal obtained by differentiating the output of an optical interferometer using light having a wavelength of 365 nm.

[Fig. 7]

The plan view which shows the film thickness distribution obtained by the endpoint shown in FIG. 6 in comparison with the original film thickness distribution.

[Fig. 8]

Scanning micrographs showing the cross-sectional shapes of the gate electrodes obtained by the methods of Examples and Comparative Examples in comparison.

[Fig. 9]

The cross-sectional view which shows the gate electrode structure obtained by the manufacturing method of the conventional semiconductor device.

[Fig. 10]

The cross-sectional view which sequentially shows the shape of the gate electrode obtained by the manufacturing method of the conventional semiconductor device.

[Explanation of symbols]

10: Silicon substrate 11: Gate oxide film 12: polysilicon film 13: photoresist film 21: Mercury lamp 22: Optical fiber 23: Mirror 24: Lens 25: Quartz window 26: Etching chamber 27: Wafer 28: Lower electrode 29: Interference detector