Packet transfer device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a packet transfer device that assembles a logical channel-multiplexed ATM cell into a packet and transmits the packet to the destination logical channel according to the packet header information. In particular, the present invention relates to a packet transfer device in which a transfer by hardware processing and a transfer by software processing are separated and combined.

【0002】

In recent years, in ATM networks that transfer IP packets and the like, the speed of packet transfer devices has been required to increase with the increase in packet traffic.

【0003】

In response to this request, a series of packet transfer processes from packet assembly, transfer destination search, and packet transmission are becoming hardware.

【0004】

On the other hand, traffic such as upper layer protocol packets that require packet transfer processing by software is also increasing, and it is required to speed up the packet transfer device by hardware and improve the processing capacity of packet transfer processing by software.

【0005】

Therefore, the hardware of the packet transfer processing is provided by providing a coupling mechanism in which the packet transfer processing by the hardware and the packet transfer processing by the software do not affect each other's throughput and a mechanism for assisting the packet reception processing and the transmission processing by the software. It is necessary to improve the processing capacity of packet transfer processing by software as well as speeding up by hardware.

【0006】

[Conventional technology]

FIG. 14 shows the location of the packet transfer module on the network to which the packet transfer device of the present invention is applied. A plurality of packet transfer modules are arranged in the ATM network, and these packet transfer modules are connected to each other and are connected to the router of the user network via the multiplexing device.

【0007】

Each packet transfer module, the multiplexing device, and the router are connected by an interface of Asynchronous Transfer Mode (ATM). Packets transmitted from each user network are converted into ATM cells by AAL type 5 in the router, and ATM cells from multiple users are multiplexed in a multiplexing device accommodating a plurality of routers, and packets are packetized from this multiplexing device. Input to the transfer module.

【0008】

The packet transfer module assembles a packet from the input ATM cell, searches for the destination address in the packet header, and follows the destination address in the search result toward another packet transfer module that accommodates the destination user network. Alternatively, the packet is transferred to the destination user network housed in the own packet transfer module. On the other hand, if the destination is not found as a result of searching the destination address in the packet header, or if the packet has a protocol terminated by the own packet transfer module, or a packet that violates the protocol, the packet is sent to another packet. It does not transfer and terminates with its own packet transfer module.

【0009】

FIG. 15 is an explanatory diagram of the principle of the conventional packet transfer device. In the figure, 30 is a packet assembly transmitter that receives ATM cells from the line and sends them to the line, 31 is a buffer memory that stores packets to be sent and received, 32 is an upper layer processing unit that processes packet header information, 33. Is a processor (software processing unit) that performs software processing on required packets.

【0010】

When the packet assembly transmission unit 30 receives an ATM cell whose logical channel is multiplexed from the line, the upper layer processing unit 32 decomposes the cell and buffers it while searching the transfer destination based on the packet header and checking the packet normality. Packets are assembled and stored in memory 31. When the transfer destination is resolved by the upper layer processing unit 32, the packet on the buffer memory 31 is cellized by the packet assembly transmission unit 30 and transmitted to the line without going through software processing by the processor 33.

【0011】

On the other hand, if the packet transfer by hardware is not possible because the transfer destination is not resolved by the upper layer processing unit 32, the software processing unit 33 is notified of the packet reception. As a result, the software processing unit 33 reads the corresponding packet on the buffer memory 31, analyzes the cause of the packet being transferred, and determines the next processing.

【0012】

When transmitting a packet from the software processing unit 33, the software processing unit 33 searches the destination of the packet in advance using the destination search table 34, and after the transfer destination is resolved, writes the packet to be transmitted on the buffer memory 31. The transmission is instructed by notifying the packet assembly transmission unit 30 of the address and the like of the packet to be transmitted.

【0013】

The packet assembly transmission unit 30 instructed to transmit the packet in the buffer memory 31 into a cell and transmits the packet to the line.

【0014】

In this packet transfer device, the same bus 35 is used for access to the buffer memory 31 from the hardware (packet assembly transmission unit 30) and software (software processing unit 33) while performing contention arbitration.

【0015】

In this way, in the conventional packet transfer device, when an ATM cell is received, the packet is assembled and accumulated in the buffer memory while the transfer destination is searched and the packet normality is confirmed by hardware processing, and the transfer destination is solved. If so, the packet on the buffer memory is transmitted without going through software processing.

【0016】

On the other hand, a packet that requires processing by software, such as when the transfer destination is not resolved, is received by the software accessing the same buffer memory as the buffer memory used for hardware transfer. is there.

【0017】

In this case, the software needs to analyze the cause of the packet being forwarded and determine the next processing. Further, when the packet is transmitted from the software, the packet is prepared and transmitted on the buffer memory by accessing the same buffer memory as the buffer memory used in the hardware transfer. Further, the software needs to perform a process of searching and determining a forwarding destination in advance based on the destination information of the packet to be transmitted.

【0018】

[Problems to be Solved by the Invention]

In such a conventional packet transfer device, a bus conflict occurs between the buffer memory access by the hardware and the buffer memory access by the software. Therefore, the increase in the number of buffer memory accesses by the software increases the buffer memory access by the hardware. This has caused problems such as a decrease in the throughput of hardware transfer.

【0019】

Further, when the buffer memory access of the hardware has a higher priority than the access of the software and the number of buffer memory accesses from the software is limited, there is a problem that the processing capacity of the software is lowered.

【0020】

Furthermore, the software needs to determine the protocol type of the packet transferred to the software, analyze the cause of the error, etc., and when transferring the packet from the software, it is necessary to search the destination in advance using the destination search table. These processing loads are one of the factors that reduce the processing capacity of software.

【0021】

The present invention has been made in view of the above-mentioned problems and the recent technological trends of the above-mentioned packet transfer device, and it is possible to improve the processing capacity of packet transfer processing by software as well as speed up by hardware for packet transfer processing. It is the purpose. It is also an object of the present invention to expand the capacity of the packet transfer device by providing a mechanism for combining a plurality of packet transfer devices.

【0022】

[Means for solving problems]

In order to solve the above problems, in the packet transfer device according to the present invention, the packet transfer mechanism by the hardware processing unit is provided with an expansion line for connecting to the software processing unit in addition to the main line connected to the external device. Packets to be transmitted to the main line are read and transmitted from the buffer memory, and packets that require software processing are read from the buffer memory by the hardware processing unit and transmitted to the software processing unit via the expansion line. ..

【0023】

In this packet transfer device, the hardware processing unit writes and assembles the packet received from the main line to the buffer memory, and the software processing unit receives the packet transmitted to the expansion line from the expansion line. I write it to the buffer memory and assemble it on my own.

【0024】

Further, this hardware processing unit sends packet header information to the layer processing unit when the packet assembly is completed or the assembly of the packet header unit is completed, and based on the packet header information, packet normality confirmation and transfer destination search are performed. The line type and logical channel to be transmitted are determined based on the result of the upper layer processing such as.

【0025】

Further, in the buffer memory of the hardware processing unit, packets can be assembled in the form of ATM cells without decomposing the ATM cells, which simplifies buffer pointer control.

【0026】

For access to the buffer memory in the hardware processing unit, the packet assembly unit on the cell receiving side should access the reception from the main line and the reception from the extension line independently, or access them in common by a multiplex mechanism. In addition, the packet determination transmission unit on the cell transmission side accesses the transmission to the main line and the transmission to the extension line independently, or accesses them in common by a separation mechanism.

【0027】

If the software processing unit searches for a destination in advance by software, specifies the destination, and sends the packet to the hardware processing unit via an extension line, the hardware processing unit does not search for the destination. The packet is transmitted to the specified destination, whereby the hardware processing unit can transmit the packet to the destination arbitrarily specified by the software processing unit.

【0028】

Further, when the software transmits a packet in which the destination is not specified in the software processing unit, the hardware processing unit searches for the destination and sends the packet to the resulting destination, which is determined by the software processing unit. No need to search for destinations.

【0029】

When the hardware processing unit sends a packet to the software processing unit via an expansion line, the type of the packet is distributed to the logical channel, and the upper layer processing result in the hardware processing unit is used as detailed information. It is attached to the packet, and the software processing unit that receives this determines the next processing based on the logical channel and detailed tsumugi information of the received packet. This eliminates the need for packet analysis processing that overlaps with the hardware processing unit.

【0030】

In addition, the software processing unit separates the transmission queue to the main line into a plurality of transmission queues for each packet type, and also separates the transmission queue to the expansion line into a plurality of transmission queues, and between each transmission queue of the main line or of the extension line. The transmission schedule should be performed between each transmission queue or between each transmission queue including the main line and the extension line. Further, the packet is transmitted so that the priority can be set for each packet type. As a result, the software processing unit can preferentially receive the packet having a high priority.

【0031】

In addition, the hardware processing unit monitors the congestion status of the buffer memory in the software processing unit, and when the common receive buffer is congested, waits for transmission from all transmission queues for the expansion line on the hardware processing unit side. If the receive buffer of a certain logical channel on the software processing unit side is congested, the transmission from the corresponding logical channel transmission queue on the hardware processing unit side is waited for. As a result, the hardware processing unit prevents packets with low priority of software processing from being transmitted to the software processing unit, thereby preventing the buffer from overflowing in the software processing unit and controlling congestion by the software processing unit. I don't need it.

【0032】

Further, in the packet transfer device of the present invention, the packet transfer mechanism by a plurality of hardware processing units is connected to one software processing unit, whereby one software processing unit is processed by the software processing unit. It is possible to connect multiple hardware processing units suitable for the capacity.

【0033】

Further, in this packet transfer device, a packet whose destination could not be obtained as a result of higher layer processing by the hardware processing unit can be transmitted to another hardware processing unit via the second expansion line. The hardware processing unit enables packets to be received from the second expansion line. As a result, when the transfer destination cannot be obtained by the own upper layer processing unit, each hardware processing unit searches for the destination by the other upper layer processing unit, and the packet received by the own packet transfer device is transmitted. It is possible to send from another packet transfer device.

【0034】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a packet transfer device as an embodiment of the present invention. As shown in the figure, the packet transfer device of this embodiment is composed of a hardware processing unit 1 and a software processing unit 2. The hardware processing unit 1 is connected to the main line 3 and transmits / receives ATM cells to the main line 3. The hardware processing unit 1 and the software processing unit 2 are connected by an expansion line 4, and ATM cells are transmitted and received through the expansion line 4.

【0035】

The hardware processing unit 1 includes a packet assembly unit 10, an upper layer processing unit 11, a buffer memory 12, and a packet determination transmission unit 13.

【0036】

When the packet assembly unit 10 receives an ATM cell in which logical channels are multiplexed from the main line 3 or the expansion line 4, the packet assembly unit 10 assembles the ATM cell into an ATM cell for each logical channel. Here, the "ATM cellized packet" is a packet assembled into a packet in the ATM cell format without decomposing the ATM cell (that is, a row of ATM cells for each packet), and the protocol of the ATM network is AAL type. The case of 5 is referred to as "AAL5 packet in ATM cell" here. The packet assembly unit 10 transmits the packet header to the upper layer processing unit 11 after the packet assembly is completed or when the packet header assembly is completed.

【0037】

The upper layer processing unit 11 receives the packet header of the ATM cellized packet received by the packet assembly unit 10, and based on the packet header, upper layer processing such as confirmation of packet normality, protocol determination, and destination search. Is performed, the line type to be transmitted, the logical channel, and the like are determined, and the processing result is transmitted to the packet determination transmission unit 13.

【0038】

The buffer memory 12 assembles and stores the received AAL5 packets in ATM cells while maintaining the ATM cell format, thereby simplifying the buffer pointer control.

【0039】

When the packet determination transmission unit 13 receives the processing result from the upper layer processing unit 11, the packet determination transmission unit 13 reads the packet corresponding to the processing result from the buffer memory 12 and transmits it to the main line 3 or the extension line 4. At this time, according to the processing result of the upper layer processing unit 11, transmission is performed to the main line 3 or the expansion line 4 on the designated logical channel. This packet is an ATM cellized AAL5 packet.

【0040】

The software processing unit 2 includes a cell assembly / disassembly unit 20, a buffer memory 21, and a processor 22. Here, the cell assembly / disassembly unit 20 disassembles the ATM cell received from the expansion line 4 into cells, assembles them into packets in the buffer memory 21 and stores them, and assembles the packets in the buffer memory 21 into the ATM cells and transmits them to the expansion line 4. To do. The processor 22 is a part that performs software processing, and processes the received packet by software processing.

【0041】

The general operation of this packet transfer device will be described below. When the cell receiving unit 101 of the hardware processing unit 1 receives the AAL5 packet converted into an ATM cell that is logically channel-multiplexed from the main line 3, the packet assembly control unit 102 puts a packet (for each logical channel) on the buffer memory 12. It is assembled into an ATM cell (AAL5 packet), and the packet header of the received packet is transmitted to the upper layer processing unit 11 after the packet assembly is completed or when the packet header assembly is completed.

【0042】

Based on the received packet header, the upper layer processing unit 11 performs processing of checking the normality of the packet, determining the protocol, and searching for the destination, and transmits the processing result to the packet determination transmitting unit 13.

【0043】

When the packet determination transmission unit 13 receives the processing result of the upper layer processing unit 11, the packet determination transmission unit 13 extracts the packet (AAL5 packet converted into an ATM cell) corresponding to the processing result from the buffer memory 12, and mainly follows the upper layer processing result. Sends to line 3 or extension line 4 on the specified logical channel. At this time, the packet whose forwarding destination is resolved by the upper layer processing unit 11 is transmitted to the main line 3. On the other hand, packets that cannot be transferred by hardware because the transfer destination is not resolved are transferred to the software processing unit 2 via the expansion line 4 because packet processing by software is required.

【0044】

In this way, the hardware processing unit 1 provides a hardware packet transfer mechanism with an expansion line 4 connected to the software processing unit 2 in addition to the main line 3 connected to the external device, and connects to the main line 3. The packet to be transmitted is read from the buffer memory 12 and transmitted, and the packet requiring software processing is read from the buffer memory 12 by the hardware and transmitted to the expansion line 4.

【0045】

When the software processing unit 2 receives the AAL5 packet converted into an ATM cell whose transfer destination has not been resolved from the expansion line 4, the software processing unit 2 disassembles the ATM cell and transfers it to the buffer memory 21 by the cell assembly / disassembly unit 20, and this buffer memory Assembles a packet on 21 and notifies processor 22 (software) of packet reception. Upon receiving the notification of packet reception, the processor 22 determines the content of the packet, performs packet reception processing such as determination of the protocol type of the transferred packet and analysis of the cause of the error, and searches for the destination of the packet. It terminates packets whose forwarding destination cannot be resolved.

【0046】

When a packet is transmitted from the processor 22 (software) because the destination is resolved by software processing, the processor 22 prepares the packet to be transmitted on the buffer memory 21 and transmits the packet to the cell assembly / disassembly unit 20. To instruct. The cell assembly / disassembly unit 20 reads a packet having a transmission instruction from the buffer memory 21, converts it into an ATM cell, and transmits it to the hardware processing unit 1 via the expansion line 4.

【0047】

Here, the packet reception processing and the packet transmission processing of the software processing unit 2 and the packet transfer processing of the hardware processing unit 1 are performed independently and in parallel.

【0048】

When the packet assembly unit 10 receives the ATM cellized packet from the expansion line 4, it assembles the ATM cellized packet in the same manner as when it receives it from the main line 3, and gives an instruction from the software processing unit 2 or a higher level. The packet is transmitted to the designated logical channel according to the processing result of the layer processing unit 11.

【0049】

In this way, the hardware processing unit 1 writes and assembles the packet received from the main line 3 to the buffer memory 12, and also receives the packet transmitted by the software processing unit 2 from the expansion line 4, and buffers the hardware independently. I am trying to write to memory 12 and assemble.

【0050】

Next, the packet assembly unit 10, the upper layer processing unit 11, the buffer memory 12, the detailed configuration of the packet determination transmission unit 13 in the hardware processing unit 1 described above, and the cell assembly / disassembly unit 20 and the buffer memory 21 in the software processing unit 2 , The detailed configuration of the processor 22 (software) will be described.

【0051】

First, as shown in FIG. 2, the packet assembly unit 10 includes a cell reception unit 101, a packet assembly control unit 102, a header transmission unit 103, and the like. The hardware processing unit 1 of the embodiment of FIG. 2 is a case where the access speed to the buffer memory 12 is such that the main line 3 and the expansion line 4 can send and receive packets at the same time. That is, the packet assembly unit 10 can receive packets from the main line 3 and the expansion line 4 at the same time without cell loss, and the packet judgment transmission unit 13 has an access speed capable of transmitting the packets to the main line 3 and the extension line 4 at the same time. It is a case.

【0052】

Here, the cell receiving unit 101 receives the ATM cell from the main line 3 or the expansion line 4. The packet assembly control unit 102 controls to assemble a packet on the buffer memory 12 based on the received ATM cell. The header transmission unit 103 transmits the packet header extracted from the received ATM cellized packet to the upper layer processing unit 11.

【0053】

As shown in FIG. 2, the buffer memory 12 includes a main line assembly buffer 121, an expansion line assembly buffer 122, a main line packet transmission queue 123, an expansion line packet transmission queue 124, a packet header transmission queue 125, and the like. It is composed. Here, the main line assembly buffer 121 assembles and stores the ATM cellized packets received from the main line 3 for each logical channel. The expansion line assembly buffer 122 assembles and stores the ATM cellized packets received from the expansion line 4 for each logical channel. The main line packet transmission queue 123 causes the ATM cellized packet from the assembled main line 3 to wait for transmission. The extended line packet transmission queue 124 causes the ATM cellized packet from the assembled extended line 4 to wait for transmission. The packet header transmission queue 125 causes the assembly buffer 121 or 122 to wait to transmit the packet header of the received ATM cellized packet to the header transmission unit 103.

【0054】

Further, as shown in FIG. 2, the packet determination transmission unit 13 includes a packet transmission control unit 131, a determination unit 132, a packet transmission unit 133, and the like. Here, the determination unit 132 distributes the assembled ATM cellized packet of the buffer memory 12 to the main line packet transmission queue 123 or the extended line packet transmission queue 124 based on the processing result from the upper layer processing unit 11. Give instructions. The packet transmission control unit 131 controls to transmit the packet waiting in the packet transmission queue 123 or 124. The packet transmission unit 133 transmits the ATM cellized packet received from the packet transmission control unit 131 to the main line 3 or the extension line 4.

【0055】

In contrast to the embodiment of FIG. 2 above, when the access speed to the buffer memory 12 does not have the speed at which the main line 3 and the expansion line 4 simultaneously receive or transmit, the main line is used for packet assembly and transmission. 3 and expansion line 4 need to be multiplexed and separated. The embodiment of the hardware processing unit 1 shown in FIG. 3 realizes such packet assembly and packet transmission.

【0056】

As shown in FIG. 3, in this case, the cell receiving unit 101 of the packet assembly unit 10 is provided with a multiplexing unit that can select and switch so that only one of the main line 3 and the expansion line 4 can be selected to receive the packet. In addition, a function is provided to notify the software processing unit 2 of the main line free information when the packet is not received from the main line 3. Further, the packet transmission unit 133 of the packet determination transmission unit 13 is provided with a separation unit for selectively switching whether the received ATM cellized AAL5 packet is transmitted to the main line 3 or the extension line 4.

【0057】

FIG. 4 shows a detailed configuration example of the software processing unit 2. This software processing unit 2 is used in combination with the hardware processing unit 1 of FIG. 3 described above, that is, the hardware processing unit 1 having a configuration for transmitting main line free information.

【0058】

As shown in FIG. 4, the cell assembly / disassembly unit 20 includes a cell reception unit 201, a cell disassembly unit 202, a reception DMA control unit 203, a transmission DMA control unit 204, a cell assembly unit 205, a cell transmission unit 206, and the like. To. Here, the cell receiving unit 201 receives the ATM cell from the expansion line 4. The cell decomposition unit 202 decomposes the received ATM cell into cells and takes out the payload unit. The reception DMA control unit 203 controls to write the packet assembled by the received payload unit to the buffer memory 21 by DMA (direct memory access). The transmission DMA control unit 204 controls the packet on the buffer memory 21 to be read by DMA and sent to the cell assembly unit 205. The cell assembly unit 205 assembles the received packet into the ATM cell. The cell transmission unit 206 transmits the received ATM cell to the expansion line 4 when it is notified that the main line 3 is free based on the main line free information.

【0059】

The buffer memory 21 includes a receive packet queue 211, a transmit packet queue 212, a free receive buffer queue 213, and the like. Here, the receive packet queue 211 waits for the received packet, the transmit packet queue 212 waits for the transmit packet, and the free receive buffer queue 213 waits for the vacant receive buffer.

【0060】

The detailed operation of the packet transfer device of this embodiment will be described below. First, it will be described according to FIG. 2 described above. FIG. 2 is a diagram illustrating the process from packet assembly to transmission in the hardware processing unit 1.

【0061】

The ATM cell is received from the main line 3 or the expansion line 4 by the cell receiving unit 101 in the packet assembly unit 10 and sent to the packet assembly control unit 102. The packet assembly control unit 102 assembles and stores packets in ATM cells in the assembly buffers 121 and 122 for each line and each logical channel in the buffer memory 12. This accumulation in the buffer memory 12 simplifies buffer management by maintaining the ATM cell format without disassembling the ATM cell.

【0062】

At this time, the access speed to the buffer memory 12 has an access speed that does not cause cell loss even when the main line 3 and the expansion line 4 receive cells at the same time.

【0063】

After the assembly of the packet is completed or only the packet header is completed, the header transmission unit 103 transmits the packet header to the upper layer processing unit 11 via the packet header transmission queue 125. Further, after the assembly of the packet is completed in the assembly buffer 121 for the main line or the assembly buffer 122 for the expansion line, the packet is put into the assembly completed state and the processing result from the upper layer processing unit 11 is waited for.

【0064】

The upper layer processing unit 11 performs processing of checking the normality of the packet, determining the protocol, and searching for the destination based on the received packet header, and transmits the processing result to the determination unit 132 in the packet determination transmitting unit 13. ..

【0065】

The determination unit 132 that has received the processing result from the upper layer processing unit 11 determines the processing result, and the packet corresponding to the processing result is sent to the main line packet transmission queue when the transfer destination is resolved according to the processing result. It is distributed to 123, or to the packet transmission queue 124 for extended lines when the transfer destination is not resolved. At this time, if the packet is still being assembled, it is distributed to the transmission queue 123 or 124 after the packet assembly is completed.

【0066】

The packet transmission control unit 131 monitors the status of the transmission queues 123 and 124, and if there is a packet in the main line packet transmission queue 123, the packet is sent to the main line 3 or the extended line packet transmission queue 124. If there is, the packet is sent to the extension line 4. At that time, the packetized ATM cell converts the logical channel from the upper layer processing unit 11 to the logical channel instructed through the determination unit 132, and transmits the packet transmission unit 133.

【0067】

At this time, the access speed to the buffer memory 12 is such that the main line 3 and the extension line 4 can simultaneously transmit packets.

【0068】

On the other hand, in the case of the hardware processing unit 1 of the embodiment of FIG. 3, the operation is as follows. As described above, FIG. 3 is a diagram illustrating a method of multiplexing and separating the main line 3 and the expansion line 4 in packet assembly and transmission in the hardware processing unit 1, and the access speed to the buffer memory 1 is high. , This is a method for realizing packet assembly and packet transmission when the main line 3 and the extension line 4 do not have the speed of receiving or transmitting at the same time.

【0069】

In FIG. 3, in the cell receiving unit 101, the ATM cell received from the main line 3 and the ATM cell received from the expansion line 4 are multiplexed by the multiplexing unit, so that the packet can be received from only one of the lines. Switch the multiplex part.

【0070】

The packet assembly control unit 102 distributes the ATM cells received from the main line 3 or the ATM cells received from the expansion line 4 to each line, and stores them in the assembly buffer for each line of the buffer memory 12 and each logical channel.

【0071】

The packet transmission control unit 131 reads either the packet in the main line packet transmission queue 123 or the extended line packet transmission queue 124 from the buffer memory 12. The packet transmission unit 133 separates the packet read from the buffer memory 12 into the main line 3 and the extension line 4 at the separation unit, and transmits the packet.

【0072】

The multiplex method by the cell receiving unit 101 usually raises the priority of the cell received from the main line 3, and gives priority to the cell received from the expansion line 4 that can be waited by the buffer memory 21 of the software processing unit 2. Decrease the degree. Based on this priority, the cell from the expansion line 4 is received only when the cell reception of the main line 3 is free. Therefore, in order to suppress cell transmission from the software processing unit 2, the free information of the main line 3 is always notified to the software processing unit 2.

【0073】

FIG. 4 is a diagram illustrating packet processing in the software processing unit 2. In FIG. 4, the AAL5 packet converted into an ATM cell from the expansion line 4 is received by the cell receiving unit 201 in the cell assembly / disassembling unit 20 and passed to the cell disassembling unit 202. The cell decomposition unit 202 decomposes the received ATM cell into only the payload part of the ATM cell, and the reception DMA control unit 203 refers to the free reception buffer queue 213 and the free reception buffer in the buffer memory 21 (not shown). Assemble the packet by forwarding to, and connect the received packet to the receive packet queue 211. After the packet assembly is completed, the processor 22 (software) is notified that the packet has been received.

【0074】

Upon receiving the packet reception notification, the processor 22 (software) determines the type of the packet in the received packet queue 211, and performs processing such as an upper layer protocol according to the packet type.

【0075】

When the packet in the receive packet queue 211 is no longer needed, the processor 22 (software) releases the receive buffer required to receive the packet as a free receive buffer and connects the free receive buffer to the free receive buffer queue 213. ..

【0076】

When transmitting a packet from the processor 22 (software), the software acquires an empty transmission buffer in the buffer memory 21 and connects the transmitted packet to the transmission packet queue 212.

【0077】

The transmission DMA control unit 204 in the cell assembly / disassembly unit 20 reads the packet in the transmission packet queue 212 from the buffer memory 21 and passes it to the cell assembly unit 205. The cell assembly unit 205 assembles the received packet into an ATM cell, and transmits the ATM cellized packet to the logical channel instructed by the software via the cell transmission unit 206.

【0078】

At this time, the cell transmission unit 206 suppresses cell transmission when there is no space in the main line according to the main line free information from the hardware processing unit 1.

【0079】

5 and 6 are diagrams illustrating the process from packet assembly to transmission in the hardware processing unit 1 when the packet is transmitted from the software processing unit 2. First, FIG. 5 describes the operation of the hardware processing unit 1 when a packet is transmitted by designating the destination logical channel from the software processing unit 2.

【0080】

In FIG. 5, when the packet assembly unit 10 of the hardware processing unit 1 receives the packet transmitted from the software processing unit 2, the packet assembly unit 10 assembles the packet for each logical channel at the time of reception in the buffer memory 12. At this time, the packet assembly unit 10 does not transmit the packet header to the upper layer processing unit 11 for the packet whose destination is specified in advance by the software processing unit 2.

【0081】

When the packet whose destination is specified by the software processing unit 2 in advance in the packet determination transmission unit 13 reaches the assembly completion state after the packet assembly is completed in the buffer memory 12, the packet determination transmission unit 13 does not wait for the processing result of the upper layer processing unit 11. , The packet from the software processing unit 2 is distributed to the packet transmission queue of the specified destination line and transmitted to the specified logical channel.

【0082】

Normally, the destination specified by the software processing unit 2 is the main line 3, but it is also possible to specify the expansion line 4 and loop back to the software processing unit 2.

【0083】

Next, FIG. 6 describes the operation of the hardware processing unit 1 when the software processing unit 2 transmits a packet for which the destination logical channel is not specified.

【0084】

When the packet assembly unit 10 of the hardware processing unit 1 receives the packet transmitted from the software processing unit 2, it assembles the packet for each logical channel at the time of reception. At this time, Sofutou for packets not designated destination from E A, the packet assembling unit 10, like the received packets from the main line 3, sends the packet header of the upper layer processor 11 navel of the packet.

【0085】

After the packet assembly of the packet whose destination is not specified by the software processing unit 2 is completed, the packet determination transmission unit 13 enters the assembly completion state and waits for the processing result from the upper layer processing unit 11. Then, on condition that the processing result is received and the packet assembly is completed, the packet from the software processing unit 2 is distributed to the packet transmission queue of the transmission destination line according to the received processing result, and transmitted to the instructed logical channel. To do.

【0086】

In this way, when the software processing unit 2 sends a packet that does not specify a destination, the hardware processing unit 1 searches for the destination and sends it to the destination obtained as a result. Therefore, it is not necessary for the software processing unit 2 to search for the destination.

【0087】

FIG. 7 shows a modified form of the above-described embodiment, and is a diagram illustrating a method in which the hardware processing unit 1 distributes packets to be transmitted to the software processing unit 2 to logical channels for each packet type.

【0088】

In the hardware processing unit 1, the upper layer processing unit 11 analyzes the received packet header to obtain the packet type of the packet. The packet type includes, for example, protocol packets such as ICMP packet, IGMP packet, OSPF packet, RSVP packet, packet whose destination cannot be resolved, packet which violates packet normality confirmation, etc., and these packet types are logical channels. Classify using. For example, packet type # 0 is classified into logical channel CH1, packet type # 1 is classified into logical channel CH1, and packet types # 2 to # 5 are classified into logical channel CH2.

【0089】

Further, the correspondence between this packet type and the transmission logical channel is set in advance in the determination unit 132. The packet determination transmission unit 13 that has received the processing result from the upper layer processing unit 11 derives the transmission logical channel from the packet type in the processing result by the determination unit 132, and the packet from the software processing unit 2 is the packet of the logical channel. Sort to the send queue. The packet determination transmission unit 13 determines the branch of software processing based on the logical channel, and the packet requiring software processing is transmitted to the software processing unit 2 via the expansion line 4 on the instructed logical channel. To do.

【0090】

The software processing unit 2 determines the next processing based on the logical channel of the received packet. This makes the packet analysis process that overlaps with the hardware processing unit 1 unnecessary.

【0091】

FIG. 8 shows another modified form of the above-described embodiment, and is obtained from the processing result of the upper layer processing unit 11 with respect to the packet transmitted by the hardware processing unit 1 to the software processing unit 2. It is a figure explaining the method of attaching detailed information.

【0092】

In the hardware processing unit 1, the determination unit 132 that has received the processing result from the upper layer processing unit 11 further receives the detailed tsumugi information, and attaches this detailed tsumugi information to the beginning of the packet or associates it with the packet. Connect to the packet transmission queue. The packet detailed information includes, for example, factor information of packet normality confirmation violation, protocol packet type code, and the like, and the packet type is classified in more detail. The packet determination transmission unit 13 determines the branching of software processing based on the content of this detailed information, and for packets that require software processing, attaches this detailed information to the packet and the software processing unit via the extension line 4. Send to 2.

【0093】

The software processing unit 2 determines the next processing based on the detailed information of the received packet, thereby eliminating the need for the packet analysis processing that overlaps with the hardware processing unit 1.

【0094】

9 and 10 show another modification of the above embodiment, in which the software processing unit 2 notifies the hardware processing unit 1 of the free state of the receive buffer, and the hardware processing unit 1 notifies the hardware processing unit 1. An ATM cellized packet is sent to the software processing unit 2 according to the free status.

【0095】

First, FIG. 10 is a diagram illustrating a configuration of a software processing unit 2 that outputs free buffer information. The cell assembly / disassembly unit 20 that receives the packet from the expansion line 4 is configured to acquire a buffer from the free common receive buffer queue common to each logical channel and transfer the packet to the packet receive queue corresponding to the logical channel. Here, the cell assembly / disassembly unit 20 compares the queue length of the free common receive buffer queue with the preset queue length, and determines whether the queue length of the free common receive buffer queue is equal to or less than the preset queue length. It is configured to output the common receive buffer free information indicating the above and transmit it to the hardware processing unit 1.

【0096】

Further, the cell assembly / disassembly unit 20 compares the queue length of the packet reception queue corresponding to each logical channel with the queue length preset for each logical channel, and sets the queue length of each packet reception queue in advance. It also outputs receive buffer free information for each logical channel indicating whether or not it is less than or equal to the queue length.

【0097】

The packet reception processing of the processor 22 (software) in the software processing unit 2 branches the processing based on the detailed information of the logical channel (hence the packet type) or the upper layer processing result.

【0098】

FIG. 9 shows the configuration of the hardware processing unit 1 in which the transmission schedule is performed based on the reception buffer free information received from the software processing unit 2, and the hardware processing unit 1 displays packets for each packet type. It is also configured to separate the transmission queue and schedule the transmission.

【0099】

In the hardware processing unit 1, the determination unit 132 that has received the processing result from the upper layer processing unit 11 distributes the corresponding packet (ATM cellized packet) to the corresponding packet transmission queue according to the packet type indicated by the processing result. ..

【0100】

The packet transmission unit 133 performs transmission scheduling of packets to be transmitted (packet made into ATM cells) in the transmission queue according to the priority of each transmission queue (hence, each packet type) set in advance, and transmits according to the transmission scheduling. Read the packet from the queue and send it to the line.

【0101】

The packet transmission queue separated for each packet type is provided separately for the main line and the extended line, and scheduling is performed independently for each. In addition, when the method of multiplexing the main line and the expansion line is adopted as in the modified form described in FIG. 3, the transmission queue for the main line and the transmission queue for the expansion line are scheduled together. ..

【0102】

In this way, the hardware processing unit 1 separates the transmission queue 123 to the main line 3 into a plurality of packets for each packet type, and similarly separates the transmission queue 124 to the expansion line 4 into a plurality of main lines. Transmission queue for each packet type in 3 or between transmission queues 124 for each packet type in extended line 4 or for each packet type in which main line 3 and extended line 4 are combined The transmission schedule between 123 and 124 is set so that the priority can be set for each packet type, and the software processing unit 2 can receive the packet with high priority with priority. I am doing it.

【0103】

Further, when the packet transmission unit 133 monitors the common reception buffer free information from the software processing unit 2 by the transmission queue length monitoring unit and detects that the common reception buffer on the software processing unit 2 side is full. Suppresses the reading of packets from the transmit queue 124 for the expansion line 4 of the buffer memory 12. As a result, the software processing unit 2 can prevent the loss of the ATM cellized packet from the hardware processing unit 1 due to the overflow of the common reception buffer.

【0104】

Further, when the reception buffer of a certain logical channel is exhausted in the software processing unit 2, the packet transmission unit 133 of the hardware processing unit 1 is notified of the fact by the reception buffer free information for each ethical channel. The packet transmission unit 133 suppresses only reading of packets from the transmission queue for the expansion line corresponding to the logical channel that has run out of space.

【0105】

In this way, in this packet transfer device, the software processing unit 2 monitors the congestion state of the buffer memory 21 in the software processing unit, and when the common reception buffer is congested, the hardware processing unit 1 performs all for the expansion line 4. The transmission from the transmission queue 124 is waited for, and when the receive buffer of the logical channel on the software processing unit 2 side is congested, the hardware processing unit 1 waits for the transmission from the logical channel transmission queue. In addition, packets with low priority for software processing are not transmitted to the software processing unit 2, which prevents the buffer from overflowing in the software processing unit 2 and is performed by the software on the software processing unit 2 side. Congestion control is not required.

【0106】

In this way, the packet transfer device of this modification schedules transmission by combining the preset priority of the transmission queue with the common receive buffer free information of the software processing unit and the receive buffer free information for each logical channel. For example, if the high-priority transmission queue on the hardware processing unit 1 side cannot be transmitted because the receive buffer on the software processing unit 2 side is full, packets in other transmission queues that can be transmitted are sent. Flexible transmission scheduling such as transmission first is possible.

【0107】

The packet type referred to here refers to a protocol type and the like and a combination thereof.

【0108】

FIG. 11 is a configuration diagram showing another embodiment of the packet transfer device of the present invention, and this embodiment is configured to connect a plurality of packet transfer devices to a single software processing unit.

【0109】

As shown in FIG. 11, a plurality of packet transfer devices # 0 to # n consisting of only the hardware processing unit 1 of each of the above-described embodiments are deployed, and the expansion line 4 (# 0) of each packet transfer device # 0 to # n is provided. ) ~ 4 (#n) are connected to a single software processing unit 2.

【0110】

The cell assembly / disassembly unit 20 in the software processing unit 2 accommodates a plurality of expansion lines 4 (# 0) to 4 (# n), and is connected to each expansion line 4 (# 0) to 4 (# n). It is configured so that packet transmission and packet reception can be performed independently of each other. Further, the processor 22 (software) commonly performs packet transmission processing to a plurality of packet transfer devices # 0 to # n, or packet reception processing from a plurality of packet transfer devices # 0 to # n.

【0111】

FIG. 12 is a configuration diagram showing another embodiment of the packet transfer device of the present invention. In this embodiment, as in the above-described embodiment of FIG. 11, a plurality of packet transfer devices are combined into a single software processing unit. Although it is configured to connect to, the embodiment of FIG. 12 is a further improvement of the embodiment of FIG.

【0112】

In this embodiment, second expansion lines 6 (# 0) to 6 (# n) are provided in each packet transfer device # 0 to # n, and these extension lines 6 (# 0) to 6 (# n) are provided. Connect each packet transfer device # 0 to #n in a ring shape.

【0113】

Then, in each packet transfer device # 0 to #n, the packet assembly unit 10 has a function of assembling the ATM cellized packet received from the expansion line 6 of the previous stage packet transfer device into a packet, and the packet header is combined with the upper layer processing unit. It is provided with a function of transmitting to 11, and also has a function of transmitting a packet to a subsequent packet transfer device via an extension line 6 as appropriate according to a higher layer processing result.

【0114】

The functions related to the second expansion line 6 are the same as the functions of the main line 3 and the expansion line 4 described above. Therefore, the packet received from the main line 3 or the expansion line 4 can be transmitted to the subsequent packet transfer device via the extension line 6, and the packet received from the extension line 6 of the previous stage packet transfer device can be transmitted to the main line 3 or the extension line 4. Can be sent to.

【0115】

In this way, a plurality of packet transfer devices # 0 to # n are deployed, the extension line 6 on the transmitting side is connected to the extension line 6 on the receiving side of the subsequent packet transfer device, and the upper layer processing unit 11 of the own packet transfer device is connected. If the result of processing is that the packet (packet made into an ATM cell) is neither transmitted to the main line 3 of the own packet transfer device nor transmitted to the expansion line 4, the packet is sent to the second expansion line 6 Is transmitted to the subsequent packet transfer device using.

【0116】

When the subsequent packet transfer device receives a packet from the extension line 6 on the receiving side, the packet header is passed to the upper layer processing unit 11 to perform upper layer processing, and according to the result, the packet is transferred to the main line 3 or the extension line 4. If it is transmission, it is transmitted to the corresponding line, but if it is neither of them, it is transmitted to the packet transfer device in the subsequent stage using the second expansion line 6 as in the case of the packet transfer device in the previous stage.

【0117】

Here, the packet transfer device that transmits the packet received from the main line 3 or the expansion line 4 to the expansion line 6, that is, the packet transfer device that first starts the transfer to the expansion line 6, is responsible for the transmitted packet. The information indicating the packet transfer device is added, while the packet transfer device that receives the packet from the extension line 6 indicates the packet transfer device added to the received packet and started the transfer to the extension line 6. If the information is confirmed and the information does not indicate the own packet transfer device, the original packet transfer device information is transmitted as it is when the packet is transmitted to the subsequent packet transmission device on the extension line 6, and the original packet transfer device information is transmitted as it is. When the information indicates the own packet transfer device, the packet is transmitted to the software processing unit 2 using the expansion line 4.

【0118】

The operation when the plurality of packet transfer devices shown in FIG. 12 are connected will be described below with reference to FIG. 13.

【0119】

The packet transfer device # 0 that received the packet from the main line 3 cannot resolve the destination of the packet by the upper layer processing, so the packet is extended to the second extension by adding the own packet transfer device number # 0. Transfer to the packet transfer device # 1 in the subsequent stage using line 6.

【0120】

Even in the packet transfer device # 1 that received the transferred packet, the destination could not be resolved, so this packet transfer device # 1 also uses the second expansion line 6 to go to the packet transfer device # 2 in the subsequent stage. Forward. At this time, the information added to the transferred packet indicating the packet transfer device that has started the transfer to the expansion line 6 remains # 0.

【0121】

In the packet transfer device #k that has received the transferred packet, when the upper layer processing result is transmission to the main line 3, the packet is transmitted to the main line 3 of the packet transfer device #k.

【0122】

On the other hand, the packet whose destination cannot be resolved by the upper layer processing in all the packet transfer devices # 0 to #n goes around the ring of the packet transfer device formed by the extension line 6 and goes to the extension line 6. Return to the original packet transfer device # 0 that started transmission. The packet transfer device # 0 sees the transfer start source packet device information of this rounded packet, recognizes that the packet is a packet that the own device has started transfer, and transmits the packet to the software processing unit 2.

【0123】

[Effect of the invention]

As described above, according to the present invention, a packet that requires software processing is distributed to a line for the software processing unit, and the packet transmitted by the software processing unit is multiplexed and transmitted, so that the packet is transferred by the hardware processing unit. The buffer memory for software and the buffer memory for packet transfer by the software processing unit can be separated, and the packet transfer processing by the hardware processing unit and the packet transfer processing by the software processing unit do not affect each other. As a mechanism, the processing capacity of the hardware processing unit and the software processing unit can be maximized.

【0124】

Further, it facilitates the determination of the packet type in the software reception processing, and eliminates the need for the destination search in the software transmission processing, whereby the packet processing capacity of the software processing unit can be improved.

【0125】

Further, the plurality of packet transfer devices can be combined for searching the destination, and the processing capacity of the packet transfer device can be expanded.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of the packet transfer mechanism as one Example of this invention.

[Figure 2]

An embodiment of the hardware processing unit 1 of the packet transfer device of the present invention is shown, and is a diagram illustrating packet assembly transmission in the embodiment.

[Fig. 3]

An embodiment of the hardware processing unit 1 provided with a mechanism for multiplex separation of a main line and an extension line in the packet transfer device of the present invention of the present invention is shown, and packet assembly transmission in this embodiment will be described. It is a figure.

[Fig. 4]

An embodiment of the software processing unit 2 used in combination with the embodiment of the hardware processing unit 1 shown in FIG. 3 is shown, and is an explanatory diagram of packet processing of the software processing unit 2.

[Fig. 5]

It is a figure explaining the operation in the hardware processing unit 1 when the destination is specified from the software processing unit 2 in the Example of this invention.

[Fig. 6]

It is a figure explaining the operation in the hardware processing unit 1 when the destination is not specified from the software processing unit 2 in the Example of this invention.

[Fig. 7]

A modification of the embodiment of the present invention will be described, and is an explanatory diagram in the case where the hardware processing unit 1 distributes transmission logical channels for each packet type.

[Fig. 8]

Explaining another modification of the embodiment of the present invention, it is an explanatory diagram in the case where the hardware processing unit 1 adds detailed information of the upper layer processing result to the packet.

[Fig. 9]

It is a figure explaining another embodiment of the hardware processing unit 1 of this invention, and is explanatory drawing at the time of separating the transmission queue for each packet type in the upper layer processing unit 11.

[Fig. 10]

It is a figure explaining another embodiment of the software processing part 2 of this invention, and is explanatory drawing of the software processing part which outputs free buffer information.

[Fig. 11]

It is a figure explaining another embodiment of this invention, and is the block diagram at the time of connecting a plurality of packet transfer devices and a single software processing unit.

[Fig. 12]

It is a figure explaining another embodiment of this invention, which was composed of a plurality of packet transfer devices and a single software processing unit, and connected these plurality of packet transfer devices in a ring shape by a second expansion line. It is a block diagram of the case.

[Fig. 13]

It is a figure for demonstrating the structure of the Example shown in FIG.

[Fig. 14]

It is a figure which shows the position on the network of the packet transfer module to which the packet transfer device of this invention is applied.

[Fig. 15]

It is a figure which shows the structure of the conventional packet transfer apparatus.

[Explanation of symbols]

1 Hardware processing unit 2 Software processing unit 3 Main line 4 expansion line 6 Second expansion line 10 Packet assembly 11 Upper layer processing unit 12 buffer memory 13 Packet judgment transmitter 20 cell assembly and disassembly 21 Buffer memory 22 Processor (software) 101 cell receiver 102 Packet assembly control unit 103 Header transmitter 121 Main line assembly buffer 122 Expansion line assembly buffer 123 Main line packet transmission queue 124 Extended line packet transmission queue 125 Packet header send queue 131 Packet transmission control unit 132 Judgment unit 133 Packet transmitter 201 cell receiver 202 Cell disassembly part 203 Receive DMA control unit 204 Transmission DMA control unit 205 Cell assembly 206 cell transmitter 211 Packet receive queue 212 Packet transmission queue 213 Free receive buffer queue