Non-volatile semiconductor storage device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a non-volatile semiconductor storage device capable of storing data requiring security.

【0002】

[Conventional technology]

With the widespread use of portable information devices such as digital still cameras, the demand for flash memory cards, which are external storage devices, is increasing. A flash memory card is a storage device having a size of a PC card or smaller, which is equipped with a flash memory as a storage medium.

【0003】

The flash memory is an electrically rewritable non-volatile semiconductor memory suitable for high integration. In addition to the storage medium in the flash memory card, the flash memory is mainly used for storing the BIOS of a PC (Personal Computer) and storing programs and data (address book, etc.) of a mobile phone.

【0004】

Various cell array structures such as AND type and NOR type have been proposed for flash memory, and each has its own characteristics.

【0005】

The AND type flash memory is a flash memory suitable for high integration and low voltage, and is often used as a storage medium for file storage. A known example of the AND type flash memory is JP-A-6-77437. Erasing is performed by applying a high voltage to the control gate, grounding the source and drain and the substrate, and injecting electrons from the channel into the floating gate with a Fowler-Northeim current. As a result, the threshold of the flash memory cell becomes high. Writing is performed by applying a negative voltage to the control gate and a low voltage to the drain, opening the source, and grounding the substrate. At this time, electrons are drawn from the floating gate to the drain by the Fowler-Northeim current, and the threshold value of the memory cell is lowered. In the AND type flash memory, the state where the threshold value of the memory cell is high is the erase state, and the value stored in the memory cell at this time is '1'. Further, the state where the threshold value is low is the write state, and the value stored in the memory cell at this time is '0'.

【0006】

Further, in recent years, as the capacity of flash memory chips has increased, expectations for applications for storing music data and electronic book data have increased. A problem in storing these data in the flash memory is copyright protection for the content stored in the flash memory card.

【0007】

One method of realizing copyright protection of contents is to provide a unique identification number inside the flash memory chip and use this identification number. In other words, to prevent unauthorized copying by such a method that the content cannot be copied to a flash memory chip with another identification number, or even if it can be copied to a flash memory chip with another identification number, it cannot be played back correctly. it can.

【0008】

[Problems to be Solved by the Invention]

The identification number provided in the same chip as the flash memory must be non-rewritable. If the identification number is stored in the mask ROM area, the user cannot write the identification number after the chip is shipped. On the other hand, if the identification number is stored in the conventional flash memory area, it is freely tampered with by erasing or overwriting.

【0009】

The problems when storing data that requires security such as identification number in the flash memory area are (1) it can be erased at least once before writing the identification number, and (2) after writing once. It is to realize a flash memory that cannot be written again, or (3) cannot read or write other data when an overwrite of the identification number is detected.

【0010】

An object of the present invention is to realize a non-volatile semiconductor storage device having a storage area that cannot be erased again after being erased a predetermined number of times.

【0011】

Another object of the present invention is to realize a non-volatile semiconductor storage device having a storage area that cannot be written again after being written once.

【0012】

Still another object of the present invention is to realize a non-volatile semiconductor storage device that cannot read or write other data when overwriting of data is detected.

【0013】

[Means for solving problems]

In order to achieve the above object, a storage area composed of a plurality of erasing unit areas, each erasing unit area having a normal data area, a management information area for storing the management information of the entire erasing unit area, and an external storage area. A selection device that selects a word line, data line, or source line and applies a predetermined voltage based on the address value input, an operation control device that controls operations such as erasing, writing, and reading, and a non-volatile semiconductor storage device. In a non-volatile semiconductor storage device having a temporary storage device for storing a state, information indicating that the erasure unit area has been erased once in the management information area of the erasure unit area in a part or all of the storage area. When this information is a predetermined value, the operation control device controls the selection device to apply the voltage required for erasing to the word line, data line, or source line in a part or all of the area. Provide means to deter.

【0014】

Further, in order to achieve another object of the present invention, information indicating that the erasure unit area has been written once is provided in the management information area of the erasure unit area in a part or all of the storage area. When this information is a predetermined value, the operation control device controls the selection device to apply the voltage required for writing to the word line, data line, or source line in a part or all of the area. Provide means to deter.

【0015】

Further, in order to achieve still another object of the present invention, a device for generating data having a one-to-one mapping relationship with each bit of ordinary data is provided, and for a part or all of the storage area. In the same writing unit area, there is an area for writing normal data and mapping-related data, and when writing and reading to other data areas, the normal data and mapping-related data are in a mapping relationship with each other in advance. If there is no mapping relationship, a means for setting the writing and reading to the data area to be impossible is provided.

【0016】

BEST MODE FOR CARRYING OUT THE INVENTION

(First Example) First, a first embodiment of the present invention will be described. FIG. 2 shows a block configuration of the AND type flash memory chip 201. Hereinafter, each block constituting the AND type flash memory chip 201 will be described.

【0017】

The cell array group 202 of the AND type flash memory is composed of eight cell arrays. Data erasing / writing / reading is performed in parallel on an 8-sided cell array. A cell array is a two-dimensional array of flash memory cells. Figure 3 shows the structure of the NAND flash memory cell array. Selection transistors (301, 302, 303, and 304, 305, 306) are provided on the drain side and the source side, respectively, and M flash memory cells are connected in parallel between the two selection transistors. The storage area sandwiched between the pair of selective transistors, that is, the storage area surrounded by the dotted line in FIG. 3, is hereinafter referred to as a memory block. In addition, a ground voltage Vss is applied to the common source line.

【0018】

The AND type flash memory erases, writes, and reads all the flash memory cells connected to the selected word line. For example, consider the case where the memory cell group M2 connected to the word line W2 is selected in FIG.

【0019】

The erasing operation is performed by applying a power supply voltage Vcc to the gate SD and SS of the selection transistor on the drain side and the source side, a high voltage Vpp to the word line W2, and a ground voltage Vss to the data lines D1 to D528.

【0020】

The writing operation is performed by applying a power supply voltage Vcc to the gate SD of the selection transistor on the drain side, a ground voltage Vss to the gate SS of the selection transistor on the source side, a negative voltage Vnn to the word line W2, and a power supply voltage Vcc to the data line.

【0021】

The read operation is performed by applying a power supply voltage Vcc to the gate SD and SS of the selection tosterrange on the drain side and the source side, a power supply voltage Vcc to the word line W2, and a predetermined positive voltage to the data lines D1 to D528.

【0022】

528 flash memory cells are connected to one word line (Wn) in the cell array. Further, in this embodiment, 1-bit data is stored in one flash memory cell. Since the cell array group 202 is composed of eight cell arrays, the unit of erasing / writing / reading is 528 bytes.

【0023】

FIG. 32 shows the data structure of the cell array group 202. An address is assigned to each word line. The 528-byte data corresponding to one address is composed of a 512-byte sector data area and a 16-byte management information area for storing information for managing the sector data. The sector data is set to 512 bytes in order to make it the same as the sector size of the magnetic disk.

【0024】

Line address 0 is the erase-prohibited area. Line addresses 1 to 16383 are erasable areas.

【0025】

The row decoder 203 of FIG. 2 selects a word line in the cell array group 202 and applies a predetermined voltage. As shown in FIG. 33, the row decoder 203 includes a word line selection circuit 100 in an erasable area, a word line selection circuit 101 in an erasable area, and memory block selection circuits 102 and 103.

【0026】

The word line selection circuit 100 in the erasure prohibited area and the word line selection circuit 101 in the erasable area decode the row address to select the word line, and control the voltage applied to the word line. Although not shown in FIG. 33, the row address is input to the row decoder 203 via the row address buffer 204. When the line address is 0, the word line selection circuit 100 in the erase-prohibited area selects a word line. When the line address is 1 to 16383, the word line selection circuit 101 in the erasable area selects the word line corresponding to the line address. The word line voltage Vw and the ground voltage Vss are supplied to the word line selection circuit 101 in the erasable area, and only the ground voltage Vss is supplied to the word line selection circuit 100 in the erasure prohibition area from the internal power generation circuit 213 shown in FIG. Will be done.

【0027】

FIG. 34 shows the internal configuration of the word line selection circuit 100 in the erasure prohibited area, and FIG. 35 shows a circuit corresponding to one word line among the word line selection circuits 101 in the erasable area. If 0 is entered as the row address from outside the chip, the word line in the erase-prohibited area is selected. At this time, the voltage applied to the word line changes according to the control signal ERS from the control circuit 211. That is, when the control signal ERS is at the'H'level, the ground voltage Vss is applied to the word line, and when the control signal ERS is at the'L' level, the word line voltage Vw is applied to the word line. Moreover, since the word line in the erasable area is not selected, the ground voltage Vss is applied.

【0028】

On the other hand, if 1 to 16383 is entered as the row address, the word line corresponding to the row address in the erasable area is selected. At this time, the word line selection circuit 101 in the erasable area applies the word line voltage Vw to the selected word line. Further, the ground voltage Vss is applied to the non-selected word lines in both the word line selection circuit 100 in the erasure prohibited area and the word line selection circuit 101 in the erasable area.

【0029】

The memory block selection circuits 102 and 103 decode the row address and select the memory block. Although not shown in FIG. 33, row addresses are input to the memory block selection circuits 102 and 103. In addition, the power supply voltage Vcc and the ground voltage Vss are supplied.

【0030】

The memory block selection circuits 102 and 103 control the voltage applied to the gates of the selection transistors on the drain side and the source side in response to the control signal from the control circuit 211. In the erasing operation and the reading operation, the memory block selection circuits 102 and 103 apply the power supply voltage Vcc to the gates of the selection transistors on the drain side and the source side. Further, in the writing operation, the memory block selection circuits 102 and 103 apply the power supply voltage Vcc to the gate of the selection transistor on the drain side and the ground voltage Vss to the gate of the selection transistor on the source side.

【0031】

The latch circuit 205 has a role of holding the write data at the time of writing and amplifying and holding the read voltage as a sense amplifier at the time of reading.

【0032】

The column address counter 206 serves as a buffer for the column address input from the outside of the chip, and increments the column address by the control signal from the control circuit 211 to change the accessed column address.

【0033】

The column decoder 207 decodes the column address and outputs a signal for selecting the data line to access.

【0034】

The column gate 208 selects the data line to access by the output of the column decoder 207.

【0035】

The input data control circuit 209 controls the voltage applied to the data line in the cell array group 202 according to the control signal from the control circuit 211 in the erasing operation or the reading operation. In the case of write operation, the input data from the multiplexer 210 is transmitted to the column gate 208 as it is.

【0036】

The multiplexer 210 switches the bus by the control signal from the control circuit 211.

【0037】

The control circuit 211 is a circuit that controls the operation inside the chip. The control circuit 211 inputs various control signals from the outside of the chip. Further, the control circuit 211 outputs a control signal to each block in the chip at a predetermined timing for each operation.

【0038】

The status register 212 indicates the operating status or operating result of the flash memory chip 201. Figure 7 shows the bit configuration of the status register 212. The status register consists of 8 bits. When the 0th bit (R_B) is '0', the chip is busy, and when it is '1', the chip is ready. Bit 2 (EER) indicates an erase error when it is '1'. Bit 3 (PER) indicates a write error when it is '1'. Bit 4 (EIH) indicates that an error occurred because an erase command was issued for the erase-prohibited area when it was '1'. The other bits are spare bits.

【0039】

The internal power generation circuit 213 inputs the power supply voltage Vcc and the ground voltage Vss from the outside of the chip. The power supply voltage Vcc is, for example, a single power supply of 3.3V. The ground voltage Vss is 0V. The internal power generation circuit 213 boosts the power supply voltage Vcc to a high voltage Vpp or lowers the negative voltage Vnn according to the control signal from the control circuit 211, and outputs the word line voltage Vw. Here, the high voltage Vpp is, for example, 12V, and the negative voltage Vnn is, for example, -7V. The internal power generation circuit 213 outputs the power supply voltage Vcc and the ground voltage Vss to each block, and outputs the word line voltage Vw to the row decoder 203.

【0040】

Hereinafter, the input / output signals of the AND type flash memory chip 201 will be described with reference to FIG.

【0041】

I / O is a data signal bus consisting of eight lines. Command input and data input / output are performed byte by byte via the data input / output signal terminal I / O.

【0042】

ADDR is an address signal bus, which consists of row addresses and column addresses.

【0043】

/ CE is a chip selection signal. The'/' before the signal name indicates that the signal is negative logic.

【0044】

/ OE is a signal to assert when reading memory data or status register.

【0045】

/ WE is a signal that latches a command or address input from the outside.

【0046】

SC is a signal that latches data byte by byte in writing and reading.

【0047】

The R / B outputs '0' when the inside of the flash memory chip 201 is erasing or writing and is in a busy state. On the other hand, in the ready state, high impedance is output.

【0048】

Hereinafter, the erasing operation, writing operation, and reading operation of the AND type flash memory chip 201 will be described.

【0049】

First, the procedure of the erasing operation will be described.

【0050】

(1) After asserting / CE from outside the chip, enter the erase command. The erase command is input to the control circuit 211 via the multiplexer 210.

【0051】

(2) Enter the address (row address + column address) from outside the chip. Of the input addresses, the row address is input to the row address buffer 204 and the control circuit 211, and the column address is input to the column address counter 206.

【0052】

(3) The control circuit 211 sets the control signal ERS to '1'.

【0053】

(4) Enter the erase start command from outside the chip.

【0054】

(5) The ground voltage Vss is applied to the word line of line address 0 regardless of whether the input line address is 0 or not. That is, since there is no potential difference between the word line and the substrate, erasing cannot be performed.

【0055】

For write operation, a negative voltage Vnn is applied to the selected word line and grounded to the unselected word line regardless of whether the word line specified by the line address is in the erase-protected area or the eraseable area. Apply voltage Vss.

【0056】

Therefore, it is possible to write data without distinguishing between an erasable prohibited area and an erasable area.

【0057】

Regarding the read operation, the power supply voltage Vcc is applied to the selected word line and grounded to the non-selected word line regardless of whether the word line specified by the row address is in the erase-prohibited area or the eraseable area. Apply voltage Vss.

【0058】

Therefore, the data can be read without distinguishing between the erasable prohibited area and the erasable area.

【0059】

According to this embodiment, it is possible to provide an erasure prohibited area that cannot be erased even once. However, in the sorting process after manufacturing the flash memory chip, an erasing operation is generally performed.

【0060】

Therefore, as a second embodiment, an AND type flash memory that can be erased only once will be described.

【0061】

(Second Example) Hereinafter, the parts different from those of the first embodiment will be mainly described.

【0062】

FIG. 4 shows the data structure of the cell array group 202.

【0063】

Row address 0 is a re-erasure prohibited area. The management information area of the re-erasure prohibited area stores 1 byte of erased bytes. This byte cannot be read or written from outside the chip 201.

【0064】

Line addresses 1 to 16383 are erasable areas. The management information area of the erasable area also has an area for storing erased bytes, but it is not used.

【0065】

FIG. 1 shows details of the cell array and its surroundings in the second embodiment.

【0066】

The word line selection circuit 100 in the non-erasable area and the word line selection circuit 101 in the erasable area shown in FIG. 1 decode the row address to select the word line, and control the voltage applied to the word line. Although not shown in FIG. 1, the row address is input to the row decoder 203 via the row address buffer 204. When the line address is 0, the word line selection circuit 100 in the re-erasure prohibited area selects a word line. When the line address is 1 to 16383, the word line selection circuit 101 in the erasable area selects the word line corresponding to the line address. The word line voltage Vw and the ground voltage Vss are supplied from the internal power generation circuit 213 to the word line selection circuit 100 in the non-erasable area and the word line selection circuit 101 in the erasable area.

【0067】

FIG. 5 shows the internal configuration of the word line selection circuit 100 in the re-erasable region, and FIG. 6 shows a circuit corresponding to one word line among the word line selection circuits 101 in the erasable area. If 0 is entered as the row address from outside the chip, the word line in the re-erasure prohibited area is selected. At this time, the voltage applied to the word line corresponding to the row address 0 by the word line selection circuit 100 in the re-erasure prohibition region differs depending on the control signal EPH from the outside. As shown in FIG. 1, when all the values stored in the latch corresponding to the data line D528 of each cell array are '1', the control signal EPH becomes '1'. When EPH is '0', the word line voltage Vw is applied to the word line, and when EPH is '1', the ground voltage Vss is applied to the word line. Moreover, since the word line in the erasable area is not selected, the ground voltage Vss is applied.

【0068】

On the other hand, if 1 to 16383 is entered as the row address, the word line corresponding to the row address in the erasable area is selected. At this time, the word line selection circuit 101 in the erasable area applies the word line voltage Vw to the selected word line. Further, the ground voltage Vss is applied to the non-selected word lines in both the word line selection circuit 100 in the re-erasure prohibition area and the word line selection circuit 101 in the erasable area.

【0069】

The memory block selection circuits 102 and 103 decode the row address and select the memory block. Although not shown in FIG. 1, row addresses are input to the memory block selection circuits 102 and 103. In addition, the power supply voltage Vcc and the ground voltage Vss are supplied.

【0070】

Hereinafter, the erasing operation, the writing operation, and the reading operation of the AND type flash memory chip 201 will be described.

【0071】

First, the erasing operation will be described with reference to FIGS. 8 to 11. The detailed procedure of the erasing operation is shown below with reference to FIG.

【0072】

(Step 801) After asserting / CE from outside the chip, input the erase command. The erase command is input to the control circuit 211 via the multiplexer 210.

【0073】

(Step 802) Enter the address (row address + column address) from outside the chip. Of the input addresses, the row address is input to the row address buffer 204 and the control circuit 211, and the column address is input to the column address counter 206.

【0074】

(Step 803) The control circuit 211 determines whether or not the input row address is 0.

【0075】

(Step 804) When the line address is not 0, input the erase start command from outside the chip.

【0076】

(Step 805) On the other hand, when the row address is 0, the control circuit 211 first sets the control signal CNF to '1'. Next, a control signal for reading is output to the internal power generation circuit 213 and the input data control circuit 209, and the erased bytes in the management information area are read to the latch circuit 205. During this time, the R / B signal outputs '0', indicating that the inside of the chip is busy. After the reading is completed, the control circuit 211 sets the control signal CNF to '0'.

【0077】

(Step 806) After the processing of step 805 is completed, the erasing start command is input from the outside of the chip.

【0078】

(Step 807) If at least one of all the bits in the erased byte is '0' (that is, the erase has never been performed), or after the processing of step 804 is completed, the control circuit 211 determines. A control signal for erasing is output to the internal power generation circuit 213 and the input data control circuit 209. At this time, a high voltage Vpp is applied to the selected word line, and a ground voltage Vss is applied to the data lines D1 to D528. This will start erasing the flash memory cells connected to the selected word line. While erasing the flash memory cells, the output signal R / B is '0', indicating that the inside of the chip is busy. Also, if / OE is asserted during erasing, the contents of status register 212 can be read. At this time, bit 0 (R_B) in FIG. 7 is '0'.

【0079】

(Step 808) erasing is completed, the output signal R / B high impedance, sand returns to Wachi ready state. After that, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 7 is '1' and bit 4 (EIH) is '0'.

【0080】

(Step 809) When all the bits of the erased byte are '1' (that is, when erasing is performed once), a control signal for erasing is output to the internal power generation circuit 213 and the input data control circuit 209. To do. At this time, the ground voltage Vss is applied to the selected word line, and no potential difference is generated between the selected word line and the board, so that the erase cannot be performed. Here, the output signal R / B is in a high impedance state. When the status register 212 is read here, bit 0 (R_B) in FIG. 7 is '1' and bit 4 (EIH) is '1'.

【0081】

Figure 9 shows the timing chart when the erase command is issued to the eraseable area. Figure 10 shows the timing chart when the erase command is first issued to the re-erase prohibited area. Figure 11 shows the timing chart when the erase command is issued to the re-erasure prohibited area from the second time onward.

【0082】

Regarding the write operation and the read operation, after inputting the address, the control circuit 211 does not determine whether the row address is 0 or reads the erased byte to the latch circuit 205.

【0083】

For the write operation, a negative voltage Vnn is applied to the selected word line and the non-selected word line is applied to the non-selected word line regardless of whether the word line specified by the line address is in the erasure prohibited area or the erasable area. Apply the ground voltage Vss.

【0084】

Therefore, data can be written without distinguishing between the re-erasable prohibited area and the erasable area.

【0085】

Regarding the read operation, the power supply voltage Vcc is applied to the selected word line regardless of whether the word line specified by the row address is in the re-erasable prohibited area or the erasable area, and the unselected word line is used. Apply the ground voltage Vss.

【0086】

Therefore, the data can be read without distinguishing between the re-erasable prohibited area and the erasable area.

【0087】

According to this embodiment, an area that can be erased only once can be provided for a part of the memory area of the AND type flash memory.

【0088】

In this embodiment, the number of erasures allowed for the re-erasure prohibited area was one. This can be extended to prohibit erasing after erasing a predetermined number of times. At this time, the number of erases is stored in the management information area instead of the erased bytes. The number of erasures is written by the control circuit 211 controlling the input data control circuit 209.

【0089】

Further, although the AND type flash memory has been described in this embodiment, the effect of this embodiment is not limited to the AND type. The re-erasure prohibition area can be provided in the same manner for other flash memory cell structures such as DINOR type, NOR type, and NAND type.

【0090】

Further, the same effect as that of this embodiment can be obtained with the flash memory card 310 composed of the flash memory chip group 311 and the card controller chip 312 as shown in FIG. 36. That is, a means for reading the erasing byte and controlling erasing to the re-erasing prohibited area may be built in the card controller chip 312. It is also possible to display a re-erasure error by using the card status register 313 in the card controller chip 312. As a result, the contents of the card status register 313 can be read from a host device such as a notebook PC. At this time, the flash memory chip group 311 may be composed of a conventional flash memory chip.

【0091】

(Third Example) Next, the third embodiment will be described with reference to FIGS. 12 to 19. This embodiment develops the re-erasure prohibited area described in the first embodiment and further provides a function of preventing overwriting. That is, in addition to being erasable only once, the purpose is to realize an area that can be written only once.

【0092】

FIG. 13 shows the data structure of the cell array group 202 in this example. Line address 0 is a re-erasure / re-write-protected area. In the management information area at row address 0, 1 byte of written bytes is stored in addition to the erased bytes. This written byte cannot be read or written from outside the chip 201.

【0093】

In the write operation, the control circuit 211 reads the written bytes, determines whether or not all the bit data is '0', and sets the control signal OTP to the row decoder 203. Further, in the first write operation for the re-erase / re-write-protected area, the control circuit 211 controls the input data control circuit 209 to store '0' in all the bits of the written byte.

【0094】

FIG. 15 shows the bit configuration of the status register 212. A new rewrite error bit (PIH) is added to bit 5 with respect to the bit configuration of the status register in the first embodiment. Bit 5 (PIH) is set to '1' when a write command is issued for the re-erasure / rewrite-protected area from the second time onward.

【0095】

The writing operation will be described with reference to FIGS. 16 to 19. Hereinafter, the procedure of the writing operation will be described with reference to FIG.

【0096】

(Step 1601) After asserting / CE from outside the chip, enter the write command. The write command is input to the control circuit 211 via the multiplexer 210.

【0097】

(Step 1602) Enter the address (row address + column address) from outside the chip. Of the input addresses, the row address is input to the row address buffer 204 and the control circuit 211, and the column address is input to the column address counter 206.

【0098】

(Step 1603) The control circuit 211 determines whether the input row address is 0.

【0099】

(Step 1604) If it is determined that the row address is not 0, write data is input byte by byte from the outside of the chip. At this time, a maximum of 526 bytes can be input. The input data is stored in the latch circuit 205.

【0100】

(Step 1605) After the input is completed, the writing start command is input from the outside of the chip.

【0101】

(Step 1606) On the other hand, when it is determined in step 1603 that the row address is 0, the control circuit 211 first sets the control signal CNF to '1'. Next, a control signal for reading is output to the internal power generation circuit 213 and the input data control circuit 209, and the erased bytes and the written bytes in the management information area are read into the latch circuit 205. During this time, the output signal R / B outputs '0', indicating that the inside of the chip is busy. After the reading is completed, the control circuit 211 sets the control signal CNF to '0'.

【0102】

(Step 1607) Input the write data byte by byte from the outside of the chip. At this time, a maximum of 526 bytes can be input. The input data is latched in the latch circuit 205. After the input is completed, the input data control circuit 209 latches '0' to the eight latches corresponding to the data line D527 in the cell array group 202.

【0103】

(Step 1608) Enter the write start command from outside the chip.

【0104】

(Step 1609) If all the bits of the erased bytes do not satisfy '1' and all the bits of the written bytes do not satisfy '0', or after the processing of step 1605 is completed, the control circuit 211 sets the internal power generation circuit 213 and Input A control signal for writing to the data control circuit 209 is output. At this time, a negative voltage Vnn is applied to the selected word line. The voltage applied to the data line corresponds to the value stored in the latch circuit 205. As a result, writing of the flash memory cell connected to the selected word line is started. In the first write of the re-erase / rewrite-protected area, '0' is written to all the bits of the written bytes in the management information area. During this period, the output signal R / B is '0', indicating that the inside of the chip is busy. Also, if / OE is asserted during writing, the contents of status register 212 can be read. At this time, bit 0 (R_B) in FIG. 15 is '0'.

【0105】

(Step 1610) When the writing is completed, the output signal R / B returns to the high impedance, that is, the ready state. After that, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 15 is '1' and bit 5 (PIH) is '0'.

【0106】

(Step 1611) If all the bits of the erased byte are '1' and all the bits of the written byte are '0' (that is, if the erase and write have already been performed), the control circuit 211 is an internal power generation circuit. Outputs a control signal for writing to 213 and input data control circuit 209. At this time, the ground voltage Vss is applied to the selected word line, and no potential difference is generated between the selected word line and the data line applied to the ground voltage Vss or the power supply voltage Vcc, or writing does not occur because the potential difference is small. Here, the output signal R / B is in a high impedance state. When the status register 212 is read, bit 0 (R_B) in FIG. 15 is '1' and bit 5 (PIH) is '1'.

【0107】

Figure 17 shows the timing chart when a write command is issued to the erasable / writable area. Figure 18 shows the timing chart when the write command is first issued to the re-erase / re-write-protected area. Figure 19 shows the timing chart when a write command is issued to the re-erase / re-write-protected area from the second time onward.

【0108】

The erasing operation and the reading operation are the same as those in the first embodiment.

【0109】

According to this embodiment, an area that can be written only once can be provided for a part of the memory area of the AND type flash memory. By not allowing not only erasing but also writing of the data in the re-erasure / re-write-protected area, it is possible to prevent data destruction due to overwriting.

【0110】

In this embodiment as well, the same effect can be obtained with the flash memory card 310 composed of the flash memory chip group 311 and the card controller chip 312 as shown in FIG.

【0111】

(Fourth Example) Next, the fourth embodiment will be described with reference to FIGS. 20 to 31. In this embodiment, the re-erasure prohibited area of the second embodiment is developed in a form different from that of the third embodiment.

【0112】

FIG. 20 shows a block configuration of the AND type flash memory chip 901. Hereinafter, the blocks newly added in this embodiment and the blocks having different functions from the blocks described in the first embodiment will be described.

【0113】

The cell array group 902 is composed of eight cell cells as in the first embodiment. FIG. 21 shows the data structure of the cell array group 902.

【0114】

The row address 0 is a re-erasure prohibited area of 528 bits × 8 = 528 bytes as in the second embodiment. The sector data area of the re-erasure prohibited area is composed of an area for storing the identification number within 256 bytes and an area for storing the inverted data of the identification number within 256 bytes. The inversion data of the identification number is the data in which "0" is inverted to "1" and "1" is inverted to "0" when the identification number is expressed by a binary number of "0" and "1".

【0115】

Line addresses 1 to 16383 are erasable areas, and user data is stored in the sector data area.

【0116】

Similar to the second embodiment, the row decoder 903 includes a word line selection circuit in a re-erasable prohibition area, a word line selection circuit in an erasable area, and a memory block selection circuit. FIG. 22 shows a word line selection circuit in the re-erasure prohibited area. Even if the row address input from the outside of the chip is not 0, the word line is selected by the control signal RID from the controller circuit 211, and the power supply voltage Vcc required for reading can be applied. Further, the word line selection circuit in the erasable area is the same as the word line selection circuit 101 in the erasable area shown in FIG. Therefore, the circuit for each word line is the same as in FIG. The memory block selection circuit is also the same as the memory block selection circuits 102 and 103 of FIG.

【0117】

The data line voltage control circuit 906 corresponds to the input data control circuit 209 of FIG. The data line voltage control circuit 906 controls the voltage applied to the data line in response to the control signal OPR from the control circuit 211 in each operation of erasing, writing, and reading.

【0118】

FIG. 23 shows a detailed view of the inverting / collating circuit 907, the multiplexer 904, 905, the gate circuit 908, and the latch circuit 205.

【0119】

The inverting / collating circuit 907 has two roles. One role is to generate inverted data of the identification number inside the inversion / collation circuit 907 in writing the identification number, and output the identification number and the inverted data to the data line. Another role is to check the falsification of the identification number before accessing the user data. The check referred to here is to read out the two data stored in the identification number area and the inverted data area and verify whether or not they are in an inverted relationship with each other. When the two data are in an inverted relationship, the MOS switch in the gate circuit 908 is turned on, so that user data can be read / written. On the contrary, when the two data are not in the inversion relationship, the MOS switch in the gate circuit 908 is turned off, so that the user data cannot be read / written.

【0120】

The multiplexers 904 and 905 perform input / output switching control for the re-erasable prohibited area or input / output for the erasable area. Switching control is performed by the control signal UDID from the control circuit 211.

【0121】

The bit configuration of the status register 212 is shown in FIG. Bit 5 (TMP) is newly added as compared with the case of the first embodiment. When bit 5 (TMP) is '1', it indicates that the user data cannot be accessed because the identification number has been overwritten.

【0122】

The procedure for accessing the identification number will be described below. Here, the procedure will be described using FIG. 25 as an example of writing the identification number.

【0123】

(Step 2501) After asserting / CE from outside the chip, enter the write command. The write command is input to the control circuit 211 via the multiplexer 210.

【0124】

(Step 2502) Enter the address (however, row address = 0) from outside the chip. Of the input addresses, the row address is input to the row address buffer 204 and the control circuit 211, and the column address is input to the column address counter 206.

【0125】

(Step 2503) The control circuit 211 sets the control signal UDID to the multiplexers 904 and 905 to '0'.

【0126】

(Step 2504) The control circuit 211 sets the control signal RID to the row decoder 903 to '0' after determining that the row address is 0.

【0127】

(Step 2505) Input the identification number and management information byte by byte from the outside of the chip. At this time, the maximum number of bytes that can be input is (256 + 15) = 271 bytes. The input identification number and the inverting data of the identification number are stored in the latch circuit inside the inverting / collating circuit 907. Further, the management information is stored in the latch circuit 205.

【0128】

(Step 2506) Enter the write start command from outside the chip.

【0129】

(Step 2507) The controller circuit 211 outputs a control signal for writing to the internal power generation circuit 213 and the data line voltage control circuit 906. At this time, the word line selection circuit in the re-erasure prohibited area in the row decoder 903 applies a negative voltage Vnn to the selected word line. Further, the data line voltage control circuit 906 does not apply a voltage to the data line, and a voltage corresponding to the value stored in the latch inside the inverting / collation circuit 907 and the latch circuit 205 is applied to the data line. As a result, writing to line address 0 starts. During this period, the output signal R / B is '0', indicating that the inside of the chip is busy. Also, if / OE is asserted during writing, the contents of status register 212 can be read. At this time, bit 0 (R_B) in FIG. 24 is '0'.

【0130】

(Step 2508) When the writing is completed, the output signal R / B returns to the high impedance, that is, the ready state. After that, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 24 is '1'.

【0131】

By the above procedure, the identification number and its inverted data are written in each area. FIG. 28 shows a writing timing chart of the identification number.

【0132】

Next, the procedure for accessing user data will be described. Here, the procedure will be described with reference to FIG. 26, taking the writing of user data as an example.

【0133】

(Step 2601) After asserting / CE from outside the chip, enter the write command. The write command is input to the control circuit 211 via the multiplexer 210.

【0134】

(Step 2602) Enter the address (however, the row address 0) from outside the chip. Of the input addresses, the row address is input to the row address buffer 204 and the control circuit 211, and the column address is input to the column address counter 206.

【0135】

(Step 2603) The control circuit 211 sets the control signal UDID to the multiplexers 904 and 905 to '0'.

【0136】

(Step 2604) The control circuit 211 sets the control signal RID to the row decoder 903 to '1' after determining that the row address is not 0. At this time, the word line selection circuit in the re-erasure prohibition area applies the power supply voltage Vcc to the word line at line address 0. Further, the data line voltage control circuit 906 applies a predetermined positive voltage to the data line by the control signal from the control circuit 211, and reads out the data in the identification number area and the inverted data area to the latch in the inverting / collating circuit 907. .. During this time, the output signal R / B outputs '0', indicating that the chip is busy.

【0137】

In the inversion / collation circuit 907, it is determined whether or not the identification number and the inversion data read by the latch are in an inversion relationship.

【0138】

Generally, in flash memory, data can be written only in one direction by a write command. For example, in the AND type flash memory, the value stored in the memory cell in the write state is '0', and in the erase state, it is '1'. At this time, the change of the stored data by the write command occurs only in one direction from '1' to '0'. That is, when the information stored in the memory cell is '0', it cannot be set to '1' by the write command. When overwriting the already stored normal data and its inverted data by utilizing this property, the two overwritten data are not in an inverted relationship as shown in FIG. 27. Therefore, it is possible to know whether or not the identification number has been overwritten by examining whether or not the two data are in an inverted relationship. As a result of the determination, when the two data are in an inverted relationship, the MOS transistor group of the gate circuit 908 is turned ON. If there is no inverting relationship, the MOS transistor group is turned off.

【0139】

(Step 2605) The controller circuit 211 sets the control signal RID to the row decoder 903 to '0' and the control signal UDID to the multiplexers 904 and 905 to '1'. It also returns the output signal R / B to high impedance, indicating that the chip is ready.

【0140】

(Step 2606) Input user data and management information byte by byte from outside the chip. At this time, the maximum number of bytes that can be input is 527 bytes. The input user data is stored in the latch circuit 205.

【0141】

(Step 2607) Enter the write start command from outside the chip. The controller circuit 211 outputs a control signal for writing to the internal power generation circuit 213 and the data line voltage control circuit 906. At this time, the word line selection circuit in the erasable area in the row decoder 903 applies a negative voltage Vnn to the selected word line. Further, the data line voltage control circuit 906 does not apply a voltage to the data line.

【0142】

(Step 2608) If the identification number is not overwritten, that is, if the MOS transistor group in the gate circuit 908 is ON, a voltage corresponding to the value stored in the latch inside the latch circuit 205 is applied to the data line. And user data can be written. At this time, the output signal R / B is '0'. Also, by asserting / OE, the contents of status register 212 can be read. At this time, bit 0 (R_B) in FIG. 24 is '0' and bit 5 (TMP) is '0'.

【0143】

(Step 2609) When the writing is completed, the output signal R / B returns to the high impedance, that is, the ready state. After that, when / OE is asserted and the status register 212 is read, bit 0 (R_B) in FIG. 24 is '1' and bit 5 (TMP) is '0'.

【0144】

(Step 2610) On the other hand, if the identification number is overwritten, that is, if the MOS transistor group in the gate circuit 908 is OFF, data cannot be written to the user data area. At this time, the output signal R / B has high impedance. Also, by asserting / OE, the contents of status register 212 can be read. At this time, bit 0 (R_B) in FIG. 24 is '1', and bit 5 (TMP) is '1'.

【0145】

FIG. 29 shows a write timing chart of user data when the identification number has not been tampered with. Further, FIG. 30 shows a writing timing chart of user data when the identification number has been tampered with.

【0146】

In this embodiment, overwriting of the identification number cannot be prevented, but it is possible to detect that the identification number has been tampered with. Furthermore, if the identification number has been tampered with, it becomes possible to apply such that the user data cannot be accessed, and the user data can be provided with a security function.

【0147】

Further, the same effect as that of this embodiment can be obtained with the flash memory card 310 composed of the flash memory chip group 311 and the card controller chip 312 as shown in FIG. 31. That is, a means for generating inverted data and a means for collating whether or not the normal data and the inverted data are in an inverted relationship may be built in the card controller chip 312. It is also possible to display a re-erase error or an overwrite error by using the card status register 313 in the card controller chip 312. As a result, the contents of the card status register 313 can be read from a host device such as a notebook PC. At this time, the flash memory chip group 311 may be composed of a conventional flash memory chip.

【0148】

[Effect of the invention]

According to the present invention, an area that cannot be erased more than a predetermined number of times and can be written only once can be provided in the storage area of the non-volatile semiconductor storage device.

【0149】

Further, by writing the normal data and its inverted data in the same write unit area in the re-erasure prohibited area, falsification of the normal data can be easily detected. By utilizing this, it is possible to apply such that when falsification of normal data is detected, other data in the chip cannot be accessed.

【0150】

As a result, it is possible to obtain an effect that data requiring security such as an identification number unique to the chip can be stored in the flash memory chip.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the detail of the cell array and its periphery in the 2nd Example of this invention.

[Figure 2]

It is a figure which shows the block structure of the AND type flash memory in 1st to 3rd Examples of this invention.

[Fig. 3]

It is a figure which shows the structure of the cell array of the AND type flash memory.

[Fig. 4]

It is a figure which shows the structure of the cell array group in the 2nd Example of this invention.

[Fig. 5]

It is a figure which shows the word line selection circuit of the re-erasure prohibition region in the 2nd Example of this invention.

[Fig. 6]

It is a figure which shows the selection circuit corresponding to one word line in the word line selection circuit of the erasable area in the 2nd Example of this invention.

[Fig. 7]

It is a figure which shows the bit structure of the status register in 1st to 3rd Examples of this invention.

[Fig. 8]

It is a figure which shows the procedure of the erasing operation in the 2nd Example of this invention.

[Fig. 9]

It is a figure which shows the timing chart of the erasing to the erasable area in the 2nd Example of this invention.

[Fig. 10]

It is a figure which shows the first erasing timing chart to the re-erasing prohibition area in the 2nd Example of this invention.

[Fig. 11]

It is a figure which shows the erasing timing chart after the second time to the re-erasing prohibition area in the 2nd Example of this invention.

[Fig. 12]

It is a figure which shows the detail of the cell array and its periphery in the 3rd Example of this invention.

[Fig. 13]

It is a figure which shows the structure of the cell array group in the 3rd Example of this invention.

[Fig. 14]

It is a figure which shows the word line selection circuit of the re-erasure prohibition region in the 3rd Example of this invention.

[Fig. 15]

It is a figure which shows the bit structure of the status register in the 3rd Example of this invention.

[Fig. 16]

It is a figure which shows the procedure of the writing operation in the 3rd Example of this invention.

[Fig. 17]

It is a figure which shows the timing chart of writing to the erasable / writable area in the 3rd Example of this invention.

[Fig. 18]

It is a figure which shows the first write timing chart to the re-erase / rewritable area in the 3rd Example of this invention.

[Fig. 19]

It is a figure which shows the second and subsequent writing timing charts to the re-erasable / rewritable area in the 3rd Example of this invention.

[Fig. 20]

It is a figure which shows the block structure of the AND type flash memory in the 4th Example of this invention.

[Fig. 21]

It is a figure which shows the structure of the cell array group in 4th Example of this invention.

[Fig. 22]

It is a figure which shows the word line selection circuit of the re-erasure prohibition region in 4th Example of this invention.

[Fig. 23]

It is a figure which shows the detail of the inversion / collation circuit, the multiplexer, etc. in the 4th Example of this invention.

[Fig. 24]

It is a figure which shows the bit structure of the status register in the 4th Example of this invention.

[Fig. 25]

It is a figure which shows the writing procedure of the identification number in 4th Example of this invention.

[Fig. 26]

It is a figure which shows the writing procedure of the user data in 4th Example of this invention.

[Fig. 27]

It is a figure which shows the overwriting with respect to the identification number and the inverted data thereof in 4th Example of this invention.

[Fig. 28]

It is a figure which shows the writing timing chart of the identification number in 4th Example of this invention.

[Fig. 29]

It is a figure which shows the writing timing chart of the user data when the identification number is not falsified in the 4th Example of this invention.

[Fig. 30]

It is a figure which shows the writing timing chart of the user data when the identification number is falsified in the 4th Example of this invention.

[Fig. 31]

It is a figure which shows the internal structure of the flash memory card in 4th Example of this invention.

[Fig. 32]

It is a figure which shows the structure of the cell array group in the 1st Example of this invention.

[Fig. 33]

It is a figure which shows the detail of the cell array and its periphery in the 1st Example of this invention.

[Fig. 34]

It is a figure which shows the word line selection circuit of the erasure prohibition region in 1st Example of this invention.

[Fig. 35]

It is a figure which shows the selection circuit corresponding to one word line in the word line selection circuit of the erasable area in the 1st Example of this invention.

[Fig. 36]

It is a figure which shows the internal structure of the flash memory card in the 2nd Example of this invention.

[Explanation of symbols]

201 AND type flash memory chip 202 cell array group 203 line decoder 211 control circuit 212 status register 907 Inversion / collation circuit