Protocol processing unit and atm cell storage method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a protocol processing device and an ATM cell storage method that can be used in a system used for relaying a network that transmits an ATM (asynchronous transfer mode) cell.

【0002】

[Conventional technology]

As a prior art of an apparatus used for relaying a network for transmitting an ATM cell, for example, Japanese Patent Application Laid-Open No. 9-98189 and Japanese Patent Application Laid-Open No. 11-4226 are known. Japanese Patent Application Laid-Open No. 9-98189 proposes to extract the protocol header of the network layer from the first cell of a packet and extract the information necessary for routing the packet before all the cells of one packet arrive. doing.

【0003】

Further, Japanese Patent Application Laid-Open No. 11-4226 proposes to provide a plurality of processing modules of the AAL layer and parallelize the processing.

【0004】

[Problems to be Solved by the Invention]

However, in the case of processing using a single processor as in JP-A-9-98189, since the processing of all layers is performed in order, improvement in the processing speed of the entire apparatus cannot be expected.

【0005】

In addition, when referencing or changing various information in the upper layer such as TCP / IP (Transmission Control Protocol / Internet Protocol), it is necessary to access multiple ATM cells included in each packet. The technology of Gazette 9-98189 cannot be applied. In an environment where multiple VCs (virtual channels) are transmitted in a multiplexed state, it is necessary to separate the ATM cells that are sequentially received for each VC and store them in the memory. When storing ATM cells in the memory secured as an array as in JP-A-9-98189, it is necessary to secure an area for storing the ATM cell group received in advance for each VC. Therefore, since the memory is secured even for the ATM cell that is not actually received, the memory usage efficiency is poor.

【0006】

The present invention provides a protocol processing device and an ATM cell storage method capable of improving the processing speed of the entire device and improving the usage efficiency of the memory when relaying a network that transmits VC-multiplexed ATM cells. The purpose is.

【0007】

[Means for solving problems]

The protocol processing device according to claim 1 is an ATM framer connected to a transmission line capable of forming a plurality of virtual channels and inputting and outputting an ATM cell to the transmission line, and an ATM input by the ATM framer from the transmission line. Information is extracted from the VC separation module that separates cells for each virtual channel, the ATM cell storage memory for storing the ATM cell input from the transmission line by the ATM framer, and the ATM cell transferred to the ATM cell storage memory. The ATM cell information extraction module, the upper header storage memory for storing at least the payload information of the ATM cell input from the transmission line by the ATM framer, and the ATM cell transferred from the ATM cell to the upper header storage memory. A higher header information extraction module that extracts and corrects header information related to a protocol in a layer higher than the layer processed by the information extraction module is provided, and a communication signal input / output means including the ATM framer and the VC separation module and the ATM. The ATM cell processing means including the cell storage memory and the ATM cell information extraction module and the upper header processing means including the upper header storage memory and the upper header information extraction module are connected side by side in series, and the communication signal input / output means, ATM. It is characterized in that the cell processing means and the upper header processing means are provided with control means that operate independently of each other.

【0008】

The communication signal input / output means performs input / output of the ATM cell and separation of the VC. The ATM cell processing means extracts information for each ATM cell. The upper header processing means extracts and corrects information related to higher layer protocols such as TCP and IP. In claim 1, since the communication signal input / output means, the ATM cell processing means, and the upper header processing means connected in series operate independently, the entire processing can be pipelined. That is, by transferring the information to the next processing device when each processing device has the necessary information, a plurality of processing devices (communication signal input / output means, ATM cell processing means, upper header processing means) are optimal. Processing can be executed in parallel at the timing. As a result, the processing of the entire device is speeded up.

【0009】

According to claim 2, when the ATM cell received by the ATM framer is transferred to the ATM cell storage memory in the protocol processing device of claim 1, unless the virtual channel of the input ATM cell changes. It is characterized by providing a transfer control means for continuously transferring a plurality of accumulated ATM cells after waiting until a predetermined number of a plurality of ATM cells are accumulated in the ATM framer.

【0010】

For example, when using DMA (Direct Memory Access) to realize high-speed data transfer between memories, it is necessary to initialize the DMA control for each transfer, so transfer is performed every time an ATM cell is received. If this is done, a transfer delay will occur due to DMA initialization. According to claim 2, since the plurality of ATM cells are waited until they are accumulated in the ATM framer and then the accumulated ATM cells are continuously transferred, the transfer delay time can be shortened. However, when the virtual channel of the input ATM cell changes, the transfer is started even before the predetermined number of ATM cells are accumulated. As a result, ATM cells can be separated and stored for each virtual channel.

【0011】

According to claim 3, in the protocol processing apparatus of claim 1, a plurality of higher-level header processing means independent of each other are connected to the ATM cell processing means, and a virtual channel to which each ATM cell input to the ATM cell processing means belongs. It is characterized in that the upper header processing means of the transfer destination of the ATM cell is switched according to the difference, and the ATM cells belonging to a plurality of virtual channels are processed in parallel by a plurality of upper header processing means.

【0012】

According to claim 3, when ATM cells of a plurality of packets in which VCs are multiplexed are received in a mixed manner, processing can be executed in parallel by higher-level header processing means independent of each other for each VC, so that each packet can be processed. High-speed processing is possible.

【0013】

A fourth aspect of the protocol processing apparatus of the first aspect is the same hardware including a processor, a program memory, a direct memory access control circuit, a programmable gate array, a bus interface, and an internal bus, each of which executes a program at least. It is characterized in that each hardware is configured as the ATM cell processing means and the upper header processing means by mounting different software.

【0014】

In claim 4, since the ATM cell processing means and the upper header processing means are configured by using the same hardware, the hardware design cost and the manufacturing cost can be reduced by standardization. The fifth aspect is the first CRC calculation means for calculating the CRC information of the packet for each virtual channel received from the transmission line by the ATM framer in the AAL5 layer, and the upper header processing means in the protocol processing apparatus of the first aspect. A second CRC calculation means for calculating the CRC information of the AAL5 layer for each packet for each virtual channel modified by the processing of, and the second CRC calculation means when at least the packet is modified by the processing of the upper header processing means. When the ATM cell to be transmitted is modified by the result calculated by the CRC calculation means of the above and a CRC error is detected based on the calculation result of the first CRC calculation means, the information of the CRC error is transmitted to the transmission target. It is characterized by further providing a CRC control means that reflects on the ATM cell.

【0015】

Generally, CRC (Cyclic Redundancy Check) is used to detect transmission errors. When modifying the contents of a packet when relaying the packet, it is necessary to recalculate the CRC. However, if an error occurs in the received packet and the CRC-modified packet is transmitted, the occurrence of the error in the received packet cannot be known from the content of the transmitted packet.

【0016】

In claim 5, since the CRC error information of the received packet is reflected in the transmitting ATM cell, the CRC error information in the middle of relaying can be recognized by referring to the content of the transmitted packet. A sixth aspect of the present invention is the protocol processing apparatus of the fourth aspect, wherein the plurality of identical hardwares are connected to each other by using a plurality of buses.

【0017】

In the protocol processing apparatus of claim 6, it is necessary to transfer data between the communication signal input / output means and the ATM cell processing means and between the ATM cell processing means and the upper header processing means, respectively. Further, the communication signal input / output means may be transferred toward the ATM cell processing means, or the ATM cell processing means may be transferred toward the communication signal input / output means.

【0018】

The same applies to the data transfer between the ATM cell processing means and the upper header processing means. Further, when a plurality of upper header processing means are prepared, it is necessary to transfer data between each of the plurality of upper header processing means and the ATM cell processing means. When data is transferred at high speed between a plurality of independent units, it is common to transfer the data via a bus which is an aggregate of various signal lines. However, even if there are a plurality of units that use one set of buses, one set of buses cannot be used by a plurality of units at the same time.

【0019】

Therefore, it is necessary to control the priority of a plurality of units regarding the use of the bus. Further, when transferring data processed by a predetermined procedure, the priority of the bus must be controlled according to the data processing procedure. Furthermore, if another unit is using the bus, it may have to wait until the use is completed.

【0020】

In claim 6, since a plurality of sets of buses are provided in parallel, a plurality of sets of buses can be used at the same time. For example, when the communication signal input / output means and the ATM cell processing means are connected by a plurality of sets of buses, data is transferred from the communication signal input / output means to the ATM cell processing means using the first set of buses. At that time, data can be transferred from the ATM cell processing means to the communication signal input / output means using the second set of buses.

【0021】

Therefore, restrictions on the order of data transfer and the timing of starting data transfer are reduced, and data can be transferred efficiently, so that processing can be executed efficiently. In addition, since multiple units connected via multiple buses have the same hardware configuration, there are no restrictions on the placement of multiple units, and even if the placement is changed, the functions required for each unit can be met. If software is installed, the desired function can be realized as a whole device.

【0022】

A seventh aspect of the present invention is an ATM cell storage method for separating ATM cells received from transmission lines capable of forming a plurality of virtual channels for each virtual channel and storing them in a storage device, wherein the header, payload, and the next storage are stored. Using a free list composed of sequentially and logically concatenated fixed-size unused storage areas for holding link information to the area, at least ATM cells are stored for each virtual channel of the received ATM cells. Receiving management data including information indicating the start position of the area is held, each storage area is sequentially secured from the free list for each received ATM cell, and each ATM cell is stored in the secured storage area. , The secured storage area is concatenated at the end of the receive buffer holding each ATM cell received so far.

【0023】

A free list is composed of concatenated fixed-size storage areas. ATM cells can be stored in each storage area. By using the link information, the position (address, etc.) of the next storage area connected to the storage area can be known. That is, the free list is a set of small storage areas, and the positions of the storage areas do not have to be continuous.

【0024】

In claim 7, since the sequential storage area can be secured from this free list, the size of the receive buffer can be adjusted by concatenating the storage area reserved at the end of the receive buffer for storing the received ATM cell. Can be changed dynamically. Each storage area of the free list and the reserved receive buffer may be discontinuous. In the case of VC multiplexing, many ATM cells with different VCs appear in sequence, but the size of the receive buffer required for each VC cannot be specified. However, in claim 7, since it is sufficient to sequentially allocate a storage area for each VC for the actually received ATM cell, it is not necessary to specify the size of the receive buffer, and it is not necessary to allocate a fixed memory in advance. Therefore, the memory utilization efficiency is good.

【0025】

According to claim 8, in the ATM cell storage method of claim 7, a first storage area for storing a plurality of ATM cells is secured from the free list, and the processed ATM cell is stored in the first storage area. The payload is stored, the header of the ATM cell of the same virtual channel stored in the receive buffer is written to the first storage area, and the first transmission buffer holding the ATM cell to be transmitted is stored. Concatenating one storage area, and concatenating the remaining data following the data held in the first storage area among the data of the same virtual channel stored in the receive buffer to the first storage area. It is a feature.

【0026】

The first storage area reserved from the free list is used as a transmission buffer. That is, the first storage area is used to store the processed ATM cells. Since only the payload of the ATM cell is processed in the upper layer such as TCP and IP, in claim 8, the payload of the processed ATM cell is stored in the reserved first storage area, and then the header of the ATM cell is stored. Write. The first storage area is concatenated at the end of the transmit buffer.

【0027】

ATM cells that do not need to be processed in the upper layer remain in the receive buffer as they are. Therefore, by concatenating the storage area of the receive buffer in which the remaining ATM cells are stored at the end of the send buffer, the receive buffer can be used. A part of it is used as it is as a transmission buffer. Therefore, it is not necessary to secure the storage area of the transmission buffer for all ATM cells, and wasteful memory consumption is suppressed.

【0028】

Since the storage area of the transmission buffer for which transmission has been completed is unnecessary, the area can be released and returned to the free list. In addition, the receive buffer area that is not concatenated to the send buffer can be released and returned to the free list when it is no longer needed.

【0029】

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) One embodiment of the protocol processing apparatus and the ATM cell storage method of the present invention will be described with reference to FIGS. 1 to 12. This form corresponds to claims 1 to 5, 7, 7 and 8.

【0030】

FIG. 1 is a block diagram showing a functional configuration of the protocol processing device of this form. FIG. 2 is a block diagram showing the hardware of this type of protocol processing device. FIG. 3 is a memory map showing the configuration of the storage area on the ATM cell storage memory. FIG. 4 is a memory map showing the configuration of the storage area for reception. FIG. 5 is a flowchart showing the operation of the communication signal input / output unit and the ATM cell processing unit at the time of cell reception. FIG. 6 is a flowchart showing the contents of the multi-cell DMA transfer. FIG. 7 is a flowchart showing the operation of the upper header processing unit. FIG. 8 is a flowchart showing a transmission process of the ATM cell processing unit. FIG. 9 is a time chart showing the operation of the communication signal input / output unit when the VC of each cell is different. FIG. 10 is a time chart showing the operation of the communication signal input / output unit when cells of the same VC are consecutive. 11 and 12 are memory maps showing the configuration of the storage area on the ATM cell storage memory.

【0031】

In this form, the ATM framer, VC separation module, ATM cell storage memory, ATM cell information extraction module, upper header storage memory, upper header information extraction module, communication signal input / output means, ATM cell processing means, and upper header according to claim 1. The processing means are ATM framer 110, VC separation module 130, ATM cell storage memory 201, ATM cell information extraction module 202, upper header storage memory 301, upper header information extraction module 302, communication signal input / output unit 100, and ATM cell processing. Corresponds to unit 200 and upper header processing unit 300.

【0032】

Further, the transfer control means of claim 2 corresponds to steps S60 to S66. The processor, program memory, direct memory access control circuit, programmable gate array, bus interface and internal bus of claim 4 are the microprocessor 230, the program memory 240, the DMA control circuit 220, the FPGA 250, the C-PCI bus interface 280 and the local, respectively. Corresponds to bus 270.

【0033】

The first CRC calculation means and the second CRC calculation means of claim 5 correspond to the input CRC calculation circuit 140 and the CRC recalculation module 204, respectively, and the CRC control means of claim 5 correspond to steps S39 to S41. The protocol processing device shown in FIGS. 1 and 2 is used as a relay device for a network including a transmission line for transmitting an ATM cell. As a transmission line, for example, SDH (Synchronous Digital Hierarchy) can be used. In this type of relay device, a function of referring to or correcting the information of each ATM cell or the information of each packet of the relayed signal is required. In this form, it is assumed that information up to the IP and TCP layers is extracted.

【0034】

In addition, here, IP is used as the protocol of the network layer, and the method specified by RFC1577 (Classical IP and ARP over ATM) is used as the delivery method of IP datagrams on the ATM, and the encapsulation method of IP datagrams is used. It is assumed that the method specified in RFC1483 will be used as the ATM adaptation, and the AAL5 format will be used as the ATM adaptation.

【0035】

The protocol processing device shown in FIG. 2 is composed of a communication signal input / output unit 100, an ATM cell processing unit 200, and a plurality of upper header processing units 300. The plurality of upper header processing units 300 have the same configuration and operate independently of each other. The communication signal input / output unit 100 includes an ATM framer 110, a DMA control circuit 120, a VC separation module 130, and an input CRC calculation circuit 140.

【0036】

The ATM cell processing unit 200 includes data memory 210, DMA control circuit 220, microprocessor 230, program memory 240, FPGA (field programmable gate array) 250, Ethernet® interface 260, local bus 270 and C-PCI. (Compact PCI) Equipped with bus interface 280.

【0037】

The upper header processing unit 300 includes a data memory 310, a DMA control circuit 320, a microprocessor 330, a program memory 340, an FPGA 350, an Ethernet interface 360, a local bus 370, and a C-PCI bus interface 380. As shown in FIG. 2, the hardware of the ATM cell processing unit 200 and the hardware of the upper header processing unit 300 are almost the same and are configured according to the same standard. However, since the software installed in the ATM cell processing unit 200 and the software installed in the upper header processing unit 300 are different, each unit realizes different functions.

【0038】

In this example, since two types of units (200,300) can be configured using the same hardware, it is possible to reduce the design cost of the hardware and the manufacturing cost by standardization.

【0039】

From a functional point of view, as shown in FIG. 1, the ATM cell processing unit 200 includes an ATM cell storage memory 201, a DMA control circuit 220, an ATM cell information extraction module 202, a VCI management memory 203, a CRC recalculation module 204, and information input. It is equipped with an output circuit 205. The ATM cell storage memory 201 corresponds to the data memory 210, the ATM cell information extraction module 202 corresponds to the microprocessor 230, the VCI management memory 203 corresponds to the data memory 210, and the CRC recalculation module 204 corresponds to the FPGA 250. However, the information input / output circuit 205 corresponds to the Ethernet interface 260.

【0040】

Similarly, the upper header processing unit 300 includes an upper header storage memory 301, a DMA control circuit 320, an upper header information extraction module 302, and an information input / output circuit 303. The upper header storage memory 301 corresponds to the data memory 310, the upper header information extraction module 302 corresponds to the microprocessor 330, and the information input / output circuit 303 corresponds to the Ethernet interface 360.

【0041】

In this example, the communication signal input / output unit 100, the ATM cell processing unit 200, and the upper header processing unit 300 are connected in series as shown in FIG. 1 so that pipeline processing can be realized. In FIG. 1, only one upper header processing unit 300 is connected to the ATM cell processing unit 200, but in reality, as shown in FIG. 2, a plurality of upper header processing units 300 are connected in parallel to the ATM cell processing unit 200. It is connected to the.

【0042】

The communication signal input / output unit 100 transfers the received ATM cell to the ATM cell processing unit 200 while processing it internally. The ATM cell processing unit 200 transfers the payload to the upper header processing unit 300 while processing the ATM cell transferred from the communication signal input / output unit 100. The upper header processing unit 300 processes the payload information transferred from the ATM cell processing unit 200 to extract or modify the upper layer protocol (IP, TCP) information.

【0043】

The upper header processing unit 300 transfers the payload of the ATM cell whose processing has been completed to the ATM cell processing unit 200. The ATM cell processing unit 200 stores the packet containing the modified ATM cell for transmission and transfers it to the communication signal input / output unit 100. The communication signal input / output unit 100 sends the ATM cell of each packet to the transmission line.

【0044】

The ATM framer 110 assembles the received signal input from the transmission line into the ATM cell. In addition, the ATM cell to be transmitted is decomposed and output as a transmission signal to the transmission line. When the ATM framer 110 receives an ATM cell, the VC isolation module 130 reads the contents of its header from the received ATM cell and identifies the virtual channel of that cell from the VCI (Virtual Channel Identifier) contained in the header (Figure). 5 S11).

【0045】

In this example, the VC separation module 130 acquires a CID (connection ID) for each ATM cell packet received by each VC. Then, a list of CIDs associated with the VCI of each packet is formed on the VCI management memory 203 as a reception management table (see FIG. 4). By searching this reception management table, it is possible to know whether or not the CID of the received packet already exists. That is, when the first cell of a specific VC is received, the CID corresponding to that VC does not exist in the reception management table because the CID has not been acquired yet.

【0046】

Therefore, when the first cell of a specific VC is received, one unused CID prepared in advance is acquired and added to the reception management table (S12, S13 in Fig. 5). For unused CIDs, for example, the required number of CIDs expected in the stack (last-in first-out memory) area may be prepared in advance on the VCI management memory 203.

【0047】

The acquired CID is returned to the stack because it is no longer needed after all the ATM cells of the packet have been sent to the transmission line. Therefore, the acquired CID of each VC is released when the packet transmission is completed. On the VCI management memory 203, information for identifying whether or not the VC of the last received ATM cell matches the VC currently being processed, and information indicating the correspondence between each VCI and each acquired CID. Is retained.

【0048】

In a VC, the cell of the same VC received after the reception of the last cell is set as the first cell of that VC. By referring to the PT value included in the header of the ATM cell, it is possible to identify whether or not the cell is the end cell of each VC. That is, if the "user-user identification" of the least significant bit of the PT value is 1, it is the last cell of the CPCS-PDU of AAL5, otherwise it is not the last cell.

【0049】

Since the size of each ATM cell is fixed, in this example, a receive buffer for holding the received ATM cell on the ATM cell storage memory 201 is configured by concatenating a fixed-length storage area (see FIG. 4). .. As shown in FIG. 4, each fixed-length storage area is an area for storing the header (4 bytes) and payload (48 bytes) of the ATM cell and the link information to the next area (the beginning of the next storage area). It consists of an area for storing a pointer indicating an address (4 bytes).

【0050】

A storage area that is not currently used is a free list. A storage area can be added to the receive buffer by allocating a storage area from the free list as needed. Similarly, as the transmission buffer, an area in which fixed-length storage areas are concatenated is used.

【0051】

As shown in Figure 4, each CID has three pointers to the receive buffer, "Top", "Send", "Tail", and "flag", "CMAX", "ICRC", "OCRC", "reserved". It is included. 4 bytes of memory are allocated to "Top", "Send", "Tail", "flag", "CMAX", "ICRC", "OCRC", and "reserved" respectively.

【0052】

The pointer "Top" holds a value indicating the start address of the start storage area at the beginning of the receive buffer. The pointer "Send" holds a value indicating the start address of the storage area that holds the ATM cell that was last transferred to the upper header processing unit 300 in the storage area on the receive buffer. The pointer "Tail" holds a value indicating the start address of the last storage area of the receive buffer.

【0053】

The input CRC calculation circuit 140 calculates the CRC for the packet received from the transmission line. In the case of VC multiplexing, ATM cells of packets belonging to other VCs appear in the middle of the packet, so it is necessary to interrupt the CRC calculation in the middle. The intermediate result of the calculation in that case is held in the "ICRC" (see Fig. 4) of the corresponding CID (S14 in Fig. 5).

【0054】

When the input of one packet is completed, the input CRC calculation circuit 140 compares the calculation result of CRC with the value of the trailer of CPCS-PDU of AAL5. If the comparison results do not match, an error related to the input packet is detected (S15, S16 in Fig. 5). The information of this input CRC error is reflected in the contents of 1 bit of "flag" of the corresponding CID, for example.

【0055】

When a certain condition is satisfied, the VC separation module 130 transfers one or more ATM cells received by the ATM framer 110 to the ATM cell storage memory 201. The actual transfer is performed by DMA under the control of the DMA control circuit 120. This transfer process corresponds to step S17 in FIG. The details of the processing are as shown in FIG.

【0056】

In step S60, it is determined whether the current cell (the last received ATM cell) is the last cell. If the "user-user identification" of the least significant bit of the PT value is 1, it is the last cell of the CPCS-PDU of AAL5, otherwise it is not the last cell. If the last cell is detected in step S60, the process proceeds to step S61, and the current cell is transferred to the ATM cell storage memory 201 by DMA transfer regardless of the number of cells stored in the cell reception queue of the communication signal input / output unit 100. Transfer to.

【0057】

In step S62, VC is compared between the current cell and the cell accumulated in the cell reception queue of the communication signal input / output unit 100 so far. If the VCs do not match, the process proceeds to step S63, and all the cells stored in the cell reception queue are transferred to the ATM cell storage memory 201 by DMA transfer. If the VCs match in step S62, the process proceeds to step S64 to accumulate the current cell in the cell receive queue. In the next step S65, the number of cells accumulated in the cell reception queue is compared with the transfer specified value (a constant of 2 or more in this example).

【0058】

If the number of stored cells is equal to or greater than the transfer specified value, the process proceeds to step S66, and all the cells stored in the cell reception queue are transferred to the ATM cell storage memory 201 by DMA transfer. When a plurality of ATM cells are continuously transferred by the process shown in FIG. 6, the transfer delay time is reduced because the number of times of repeating the process required for initial setting such as the transfer address and the number of transfer bytes when performing DMA transfer is reduced. It will be shortened.

【0059】

Before performing the transfer in step S17 of FIG. 5, it is necessary to secure the transfer destination memory from the free list on the ATM cell storage memory 201. When the storage area is allocated from the free list, it is necessary to change the pointer indicating the position of the free list so as to reflect the decrease in the free list area due to the allocation of the area.

【0060】

When the ATM cell is transferred in step S17, the storage area of the transfer destination is concatenated after the receive buffer on the ATM cell storage memory 201 in step S18. That is, the first address value of the transfer destination storage area is written in the link information of the last storage area of the receive buffer before concatenation, and the first address of the concatenated last storage area is written in the CID pointer "Tail". Write a value and write a null (NULL: a numerical value that does not indicate a meaningful address) indicating that it is the last in the link information of the last concatenated storage area.

【0061】

A specific example will be described assuming the example shown in FIG. In FIG. 11, fixed-length storage areas M11, M12, M13, and M14 connected to each other exist as a free list, and fixed-length storage areas M21, M22, M23, and M24 connected to each other are allocated as receive buffers. Indicates the state. In the state of FIG. 11, the storage area M11 is located at the beginning of the free list, and its start address T11 is the start address of the free list. Further, the storage area M21 is located at the head of the receive buffer, and its head address T21 is the head address of the receive buffer. In addition, the storage area M24 is located at the end of the receive buffer. The CID pointers "Top", "Send", and "Tail" indicate the start address T21 of the storage area M21, the start address T22 of the storage area M22, and the start address T24 of the storage area M24, respectively. Null is held in the link information of each of the last storage areas M24 and M14.

【0062】

When transferring an ATM cell in step S17, secure an area from the free list. For example, when allocating an area for storing one ATM cell, the storage area M11 at the head of the free list is secured. As the storage area M11 is secured, the start address of the free list is changed to T12. When the ATM cell is transferred to the reserved storage area M11, it is concatenated at the end of the receive buffer. That is, the start address T11 of the storage area M11 is written as the link information of the storage area M24, and null is written in the link information of the storage area M11. In addition, the start address T11 of the storage area M11 is written in the CID pointer "Tail".

【0063】

Further, the number of cells stored in the ATM cell storage memory 201 is managed by the ATM cell information extraction module 202. That is, the ATM cell information extraction module 202 compares the number of cells stored in the ATM cell storage memory 201 for each CID with the constant "CMAX" held in the CID (S19 in FIG. 5). In this example, 2 is assigned to the constant "CMAX".

【0064】

When the number of cells stored in the ATM cell storage memory 201 exceeds the constant "CMAX", steps S20 and S21 are executed. In step S20, the payload of CMAX ATM cells is DMA-transferred from the ATM cell storage memory 201 to the upper header storage memory 301 using the DMA control circuit 220. When the cell was transferred to the upper header storage memory 301, the CID pointer "Send" was transferred to enable the identification of the transferred cell and the untransferred cell on the ATM cell storage memory 201. Change to indicate the start position of the last cell.

【0065】

For example, in the example shown in FIG. 11, when two ATM cells are transferred from the beginning of the receive buffer, the "Send" of the CID is rewritten so as to indicate the start address T22 of the second storage area M22 of the receive buffer. As shown in FIG. 2, when a plurality of upper header processing units 300 exist, the upper header processing unit 300 of the transfer destination is switched for each VC or each CID. This makes it possible for a plurality of higher-level header processing units 300 to process packets that are different from each other in parallel.

【0066】

In step S21, the CID information corresponding to the cell transferred in step S20 is transferred from the ATM cell information extraction module 202 to the upper header information extraction module 302, for example, in the form of a control command, and the information to be processed is transferred. Notify that.

【0067】

Since the size of each CID is fixed (32 bytes), if the start address of the reception management table is CIDTOP, the start address Ax of the Nth CID can be obtained from the following equation. Ax = (CIDTOP) + (N-1) × 32 When two (CMAX) ATM cells are accumulated in the ATM cell storage memory 201 for each packet by the processing of steps S19 to S21 shown in FIG. 5, two (CMAX) ATM cells are continuously used as ATM cells. It is transferred from the storage memory 201 to the upper header storage memory 301. Immediately after that, the upper header information extraction module 302 can start processing the packet.

【0068】

That is, when adopting the IP and TCP protocols, in most cases the IP and TCP protocol information is contained in the first two ATM cells that make up one AAL5 CPCS-PDU. The upper header processing unit 300 can start processing such as extracting information related to the IP and TCP protocols when the first two ATM cells arrive without waiting for the arrival of all the cells that make up one packet. it can.

【0069】

It is possible to assign a value of 3 or more to the value of the CID constant "CMAX", but it is desirable to set it to 2. In each upper header processing unit 300, the upper header information extraction module 302 performs the operation as shown in FIG. 7. In step S51, it is identified whether or not the information of the cell to be processed (payload only) exists in the upper header storage memory 301. When the ATM cell information extraction module 202 of the ATM cell processing unit 200 notifies the upper header information extraction module 302 of the completion of the transfer, it is sufficient to identify whether or not the upper header information extraction module 302 has received the notification.

【0070】

In step S52, the payload information of a plurality of cells on the upper header storage memory 301 is processed, and the TCP / IP header information and the payload information associated therewith are extracted from the payload. In step S53, the information extracted in step S52 is output to an external device via the information input / output circuit 303. Further, the information of the payload on the upper header storage memory 301 can be rewritten by the information input from the outside via the information input / output circuit 303.

【0071】

When the processing of the upper header information extraction module 302 for one packet is completed, the process proceeds from steps S54 to S55. In step S55, the upper header information extraction module 302 notifies the ATM cell information extraction module 202 of the ATM cell processing unit 200 of an end instruction indicating that the processing of the upper header processing unit 300 has been completed, and the processed packets of the packets have been processed. Notify the ATM cell information extraction module 202 of the CID.

【0072】

In order to send the processed ATM cell to the transmission line again, the ATM cell information extraction module 202 of the ATM cell processing unit 200 executes the processing shown in FIG. Hereinafter, the processing shown in FIG. 8 will be described. In step S30, it is identified whether or not the processing of the upper header processing unit 300, which is the upper unit, has been completed. Actually, since the end instruction is input to the ATM cell information extraction module 202 in step S55 shown in FIG. 7, it is identified whether or not the end instruction is input.

【0073】

In step S31, it is identified whether or not the information extraction process of the ATM cell information extraction module 202 itself regarding the ATM cell on the ATM cell storage memory 201 is completed. If the upper header processing unit 300 has finished processing or the ATM cell information extraction module 202 has finished processing, the process proceeds to step S32. In step S32, the upper header processing unit 300 identifies whether or not the payload has been modified in the processing. If it is corrected, the process proceeds to step S33.

【0074】

In step S33, a storage area for storing CMAX ATM cells is secured from the free list on the ATM cell storage memory 201, and the payload of the CMAX cells existing on the upper header storage memory 301 is stored in the ATM cell. Transfer to the storage area secured on the memory 201. Actually, the DMA control circuit 220 is used to continuously perform DMA transfer.

【0075】

Since only the payload is transferred in step S33, the cell header does not yet exist in the storage area to which it is transferred. Therefore, in the next step S34, the upper header information extraction module 302 acquires the header of the corresponding ATM cell from the receive buffer on the ATM cell storage memory 201 by using the CID notified in step S55 of FIG. 7, and steps S33. Copy to the storage area secured in.

【0076】

In step S35, the storage area secured in step S33 is concatenated to the end of the transmission buffer. That is, CMAX processed ATM cells are added to the storage area to be transmitted. In step S36, the remaining cells of the receive buffer are concatenated to the end of the send buffer. That is, of the Y ATM cells stored in the receive buffer, the storage area of the (Y-CMAX) ATM cells excluding the CMAX ATM cells transferred to the upper header processing unit 30 is concatenated to the transmit buffer. To do.

【0077】

A specific example will be described with reference to FIG. In FIG. 12, fixed-length storage areas M11, M12, M13, and M14 connected to each other exist as a free list, and fixed-length storage areas M21, M22, M23, and M24 connected to each other are allocated as receive buffers. It shows the state in which fixed-length storage areas M31, M32, M33, and M34 connected to each other are allocated as transmission buffers.

【0078】

In the state of FIG. 12, the storage area M11 is located at the beginning of the free list, and its start address T11 is the start address of the free list. Further, the storage area M21 is located at the beginning of the receive buffer, and the storage area M24 is located at the end of the receive buffer. Similarly, the storage area M31 is located at the beginning of the transmission buffer, and the storage area M34 is located at the end of the transmission buffer. Null is held in the link information of each storage area M24, M34, M14 at the end.

【0079】

When executing step S33, for example, the first two storage areas M11 and M12 of the free list of FIG. 12 are secured, and the payload of two cells transferred from the upper header processing unit 300 is written to them. In this case, the value of the pointer indicating the position of the free list is changed so that the storage area M13 is at the top of the free list. In addition, null is written in the link information of the storage area M12 which is the last.

【0080】

When executing step S35, the storage areas M11 and M12 allocated in the free list are concatenated to the last storage area M34 of the transmission buffer. That is, the start address T11 of the storage area M11 is written in the link information of the storage area M34. In step S36, the receive buffers after the third storage area M23 that has not been transferred to the upper header storage memory 301 among the receive buffers are concatenated to the end of the transmit buffer. That is, assuming that the storage area M12 concatenated by the above processing is the last of the transmission buffers, the start address T23 of the storage area M23 is written in the link information of the storage area M12.

【0081】

If the cell received from the upper header processing unit 300 does not exist, in step S36, all the storage areas of the receive buffer of the CID whose processing has been completed are concatenated to the transmission buffer. If the transmission buffer changes due to concatenation, the values of the pointers (Send-Top, Send-Tail) that indicate the start position of each storage area at the beginning and end of the transmission buffer are also corrected. Similarly, when the receive buffer area changes, the CID pointers "Top" and "Tail" are modified accordingly. When the receive buffer becomes empty, the contents of the pointers "Top", "Send", and "Tai1" are all null.

【0082】

In step S37 of FIG. 8, for each CID, the CRC of the packet on the transmission buffer is calculated cell by cell using the CRC recalculation module 204. However, CRC calculation is omitted for CIDs that have not been corrected by the upper header processing unit 300. Since the transmission buffer is VC-multiplexed, the VC may switch before the CRC result of the entire packet is obtained, and the CRC calculation process may be interrupted. Therefore, the intermediate result of the calculation is held in the "OCRC" of the corresponding CID.

【0083】

In step S38, it is determined whether or not the CRC recalculation (S37) of the last cell is completed for each CID. When finished, the process proceeds to step S39. In step S39, the "flag" of the corresponding CID is referred to to identify the presence or absence of a CRC error detected during the CRC calculation at the time of input (see S16 in FIG. 5). If no CRC error is detected during input, proceed to step S40 and change the CRC value in the cell to the CRC value recalculated in step S37. If a CRC error is detected during input, the process proceeds to step S41.

【0084】

In step S41, some bits of the CRC obtained by the recalculation are inverted and an error is inserted into it. Then, the CRC value in which the error is inserted is written as a new CRC value in the cell being processed. In step S42, the processed ATM cell data is sequentially transferred from the start position of the transmission buffer to the ATM framer 110 of the communication signal input / output unit 100.

【0085】

Since this transfer eliminates the storage area on the transmission buffer holding the transmitted cell, in the next step S43, the unnecessary storage area is released and concatenated to the free list. For example, when the ATM cell in the storage area M31 of the transmission buffer shown in FIG. 12 is transferred, the value of the pointer indicating the start address of the transmission buffer is changed to the start address T32 of the storage area M32, and the last storage of the free list is performed. The start address T31 of the storage area M31 is written in the link information of the area M14, and a null is written in the link information of the storage area M31. When the last cell is transferred, a null is written to the pointer indicating the position of the beginning and the end of the transmission buffer.

【0086】

The signal of each ATM cell transferred to the ATM framer 110 is sequentially transmitted to the transmission line. When all the cells on the transmission buffer of the ATM cell storage memory 201 of each VC are transferred to the ATM framer 110, the state of the corresponding VC of the VCI management memory 203 is changed to indicate the end of processing. The ATM cells up to the final cell received after that are output to the return transmission line in the communication signal input / output unit 100.

【0087】

When the transmission to the final cell of one CID is completed in the transmission line, the CID is regarded as an unused CID and used for the next received VC. By such processing, each VC can be separated from the received VC-multiplexed ATM stream and managed in cell units for each packet, and packet information can be easily transmitted to the upper header processing unit 300 as well. Can be transferred.

【0088】

As described above, the data received by the ATM framer 110 from the transmission line via the predetermined receiving port is sequentially stored in the ATM framer 110. The VC separation module 130 determines from the information received by the ATM framer 110 and decides whether to send the cell as it is to the transmission port of the ATM framer 110 or to transfer the cell to the ATM cell processing unit 200 via the DMA control circuit 120. select. At that time, it is determined whether or not there is an error in the input packet based on the CRC value calculated by the input CRC calculation circuit 140.

【0089】

Since the communication signal input / output unit 100 needs to separate cells for each VC, cells C1 (1), C2 (2), C3 (3), and C4 (4) having different VCs have different VCs as shown in FIG. When the signals are received sequentially (the numbers in parentheses represent VC), the transfer is performed from the ATM framer 110 to the ATM cell storage memory 201 in cell units. However, as shown in FIG. 10, when cells of the same VC are consecutive, the cells are separated for each VC, and a plurality of cells are transferred from the ATM framer 110 to the ATM cell storage memory 201 by continuous DMA processing. ..

【0090】

As shown in FIG. 10, when a plurality of cells are continuously transferred, the DMA initialization delay time between the cells can be omitted, so that the transfer is completed in a short time. The number of upper header processing units 300 connected to the ATM cell processing unit 200 may be changed according to the required processing speed, etc., and may be one, but it is desirable to provide two or more.

【0091】

The ATM cell information extraction module 202 may perform the process of allocating the upper header processing unit 300 to be used from a plurality of CIDs. As an allocation method, various methods such as allocation according to the lower bits of the CID can be considered, but it is desirable to allocate so that a plurality of upper header processing units 300 operate at the same time as much as possible.

【0092】

In this example, the number of ATM cell payloads to be transferred from the ATM cell processing unit 200 to the upper header processing unit 300 is fixed by CMAX. However, for example, when the upper header information extraction module 302 of the upper header processing unit 300 determines that the information of the cell of CMAX or higher is necessary, it may be changed to transfer the payload of an additional ATM cell.

【0093】

In addition, when a control command for transferring additional cells is issued from the upper header processing unit 300, the CMAX value in the CID of the ATM cell processing unit 200 is controlled to be automatically changed by the additional amount. Is also good. In this example, the case where the information of each packet is extracted by using the upper header processing unit 300 is shown, but the information is extracted only by the ATM cell processing unit 200 without using the upper header processing unit 300. Control modes may be added or the configuration may be changed.

【0094】

In that case, the ATM cell received by the communication signal input / output unit 100 is transferred to the ATM cell processing unit 200, and the ATM cell that has been processed by the ATM cell processing unit 200 is transferred to the communication signal input / output unit 100. You can change it. In this case as well, it is desirable to recalculate the CRC when the ATM cell processing unit 200 makes a correction.

【0095】

(Second Embodiment) Another embodiment of the protocol processing apparatus of the present invention will be described with reference to FIG. This form corresponds to claim 6. FIG. 13 is a block diagram showing the hardware of this type of protocol processing device. This form is a modification of the first embodiment. In FIG. 13, the elements corresponding to FIG. 2 are shown with the same reference numerals.

【0096】

In this form, the plurality of sets of buses in claim 6 correspond to local buses 190,270. Only the parts different from the first embodiment will be described below. Referring to FIG. 13, a local bus 190 is provided inside the communication signal input / output unit 100, and the ATM framer 110, the DMA control circuit 120, the VC separation module 130, and the input CRC calculation circuit 140 are connected to the local bus 190. ing. Further, the communication signal input / output unit 100 is provided with a bus selection circuit 180. The ATM cell processing unit 200 is provided with a bus selection circuit 290.

【0097】

The bus selection circuit 180 selects either the local bus 190 inside the communication signal input / output unit 100 or the local bus 270 inside the ATM cell processing unit 200, and connects to the input of the ATM framer 110. The selection state of the bus selection circuit 180 is controlled by the signal SEL (1) output from the VC separation module 130.

【0098】

The bus selection circuit 290 selects either the local bus 270 inside the ATM cell processing unit 200 or the local bus 190 inside the communication signal input / output unit 100, and connects to the input of the data memory 210. The selection state of the bus selection circuit 290 is controlled by the signal SEL (2) output from the microprocessor 230.

【0099】

Further, the DMA control circuit 120 and the VC separation module 130 inside the communication signal input / output unit 100 are connected to two sets of local buses 190 and 270, respectively. In addition, the microprocessor 230 inside the ATM cell processing unit 200 is connected to two sets of local buses 190 and 270, respectively. In the device of FIG. 13, both of the two sets of local buses 190 and 270 can be used for data transfer between the ATM framer 110 of the communication signal input / output unit 100 and the data memory 210 of the ATM cell processing unit 200.

【0100】

In the example of FIG. 13, when data is transferred from the ATM framer 110 to the data memory 210, the data is transferred via the local bus 190 and the bus selection circuit 290. When data is transferred from the data memory 210 to the ATM framer 110, the data is transferred via the local bus 270 and the bus selection circuit 180.

【0101】

The local bus 190 is also used for internal processing of the communication signal input / output unit 100, and the local bus 270 is also used for internal processing of the ATM cell processing unit 200. When no data is transferred between the ATM framer 110 and the data memory 210, the bus selection circuit 180 selects the local bus 190 by the signal SEL (1) output from the VC separation module 130. Further, the bus selection circuit 290 selects the local bus 270 by the signal SEL (2) output by the microprocessor 230. In this state, the local bus 190 is used for processing inside the communication signal input / output unit 100, and the local bus 270 is used for processing inside the ATM cell processing unit 200.

【0102】

When data is transferred from the communication signal input / output unit 100 to the ATM cell processing unit 200, the VC separation module 130 inside the communication signal input / output unit 100 issues a transfer instruction to the DMA control circuit 120. In this case, the DMA control circuit 120 transmits an instruction to the microprocessor 230 inside the ATM cell processing unit 200 via the local bus 190.

【0103】

By this instruction, the microprocessor 230 outputs the signal SEL (2), and the bus selection circuit 290 selects the local bus 190. After that, the data transfer is executed so that the data read from the ATM framer 110 is written to the data memory 210 under the control of the DMA control circuit 120. When transferring data from the ATM cell processing unit 200 to the communication signal input / output unit 100, the microprocessor 230 inside the ATM cell processing unit 200 issues a transfer instruction to the DMA control circuit 120 via the local bus 190. give away.

【0104】

In this case, the DMA control circuit 120 controls the bus selection circuit 180 to select the signal of the local bus 270 via the local bus 190. After that, the data transfer is executed so that the data read from the data memory 210 is written to the ATM framer 110 under the control of the DMA control circuit 120. (Third Embodiment) Another embodiment of the protocol processing apparatus of the present invention will be described with reference to FIG. This form corresponds to claim 6.

【0105】

FIG. 14 is a block diagram showing the hardware of this type of protocol processing device. This form is a modification of the first embodiment. In FIG. 14, the elements corresponding to FIG. 2 are shown with the same reference numerals.

【0106】

In this form, the plurality of sets of buses in claim 6 correspond to C-PCI buses 391,392. Only the parts different from the first embodiment will be described below. In the example of FIG. 14, two C-PCI bus interfaces 280 and 285 are provided in the ATM cell processing unit 200 to connect with the two C-PCI buses 391 and 392, respectively. In addition, each upper header processing unit 300 is equipped with two C-PCI bus interfaces 380 and 385 for connecting to the two C-PCI buses 391 and 392, respectively.

【0107】

The data memory 210 and the microprocessor 230 of the ATM cell processing unit 200 are connected to the two C-PCI bus interfaces 280 and 285, respectively. The C-PCI bus interface 280 is connected to the C-PCI bus 391, and the C-PCI bus interface 285 is connected to the C-PCI bus 392.

【0108】

Further, the data memory 310 and the microprocessor 330 of each upper header processing unit 300 are connected to the two C-PCI bus interfaces 380 and 385, respectively. The C-PCI bus interface 380 is connected to the C-PCI bus 392, and the C-PCI bus interface 385 is connected to the C-PCI bus 391.

【0109】

Therefore, data can be transferred between the ATM cell processing unit 200 and each upper header processing unit 300 by using two sets of C-PCI buses 391 and 392 at the same time. In the example of FIG. 14, the C-PCI bus 391 is used for data (cell payload) transfer in the direction from the ATM cell processing unit 200 to the upper header processing unit 300, and the upper header processing unit 300 to the ATM cell processing unit 200 The C-PCI bus 392 is used for data (cell payload) transfer in the direction toward.

【0110】

Therefore, the data transfer in the direction from the ATM cell processing unit 200 to the upper header processing unit 300 and the data transfer in the direction from the upper header processing unit 300 to the ATM cell processing unit 200 can be performed at the same time. When the cell payload is transferred from the ATM cell processing unit 200 toward the upper header processing unit 300, the microprocessor 230 of the ATM cell processing unit 200 gives a transfer instruction to the DMA control circuit 220.

【0111】

In this case, the DMA control circuit 220 outputs the data (cell payload) read from the data memory 210 to the C-PCI bus interface 280. This data is input from the C-PCI bus interface 280 to the C-PCI bus interface 385 of one of the upper header processing units 300 through the C-PCI bus 391, and is written to the data memory 310.

【0112】

When transferring the cell payload from each upper header processing unit 300 toward the ATM cell processing unit 200, first, the microprocessor 330 of the upper header processing unit 300 to transmit gives a transfer instruction to the DMA control circuit 320. In this case, the DMA control circuit 320 outputs the data (cell payload) read from the data memory 310 to the C-PCI bus interface 380. This data is input from the C-PCI bus interface 380 to the C-PCI bus interface 285 of the ATM cell processing unit 200 through the C-PCI bus 392, and is written to the data memory 210.

【0113】

(Fourth Embodiment) Another embodiment of the protocol processing apparatus of the present invention will be described with reference to FIGS. 15 and 16. This form corresponds to claim 6. FIG. 15 is a block diagram showing the hardware of this type of protocol processing device. FIG. 16 is a time chart showing an example of data transfer timing. This form is a modification of the first embodiment. In FIG. 15, the elements corresponding to FIG. 2 are shown with the same reference numerals.

【0114】

In this form, the plurality of sets of buses in claim 6 correspond to buses 501, 502 and 503. Only the parts different from the first embodiment will be described below. Referring to FIG. 15, in this example there are three sets of buses 501,502,503. Further, the communication signal input / output unit 100, the ATM cell processing unit 200, and the upper header processing unit 300 (1), 300 (2), 300 (3) are all connected in common to each of the three sets of buses 501, 502, 503. There is.

【0115】

That is, each of the communication signal input / output unit 100, the ATM cell processing unit 200, and the upper header processing unit 300 (1), 300 (2), and 300 (3) can share three sets of buses 501, 502, 503, and the buses. By separating each of 501, 502, and 503 according to a predetermined schedule or the like, the timing of use by each unit can be smoothly transferred between the units.

【0116】

In the example of FIG. 15, communication between units is [(α) (β)], [(β) (α)], [(β) (γ1)], [(β) (γ2)]. , [(β) (γ3)], [(γ1) (β)], [(γ2) (β)], [(γ3) (β)]. The order of data processing flow is (α) (β) (γ1 or γ2 or γ3) (β) (α).

【0117】

An example of data transfer between actual units will be described with reference to FIG. In the example of FIG. 16, data is transferred from the communication signal input / output unit 100 to the ATM cell processing unit 200 three times, and the three sets of data output from the ATM cell processing unit 200 are transferred to the three upper header processing units 300. It is assumed that processing is performed by (1), 300 (2), and 300 (3), respectively.

【0118】

Further, in FIG. 16A, it is assumed that all three sets of buses 501,502,503 are used, and in FIG. 16B, it is assumed that only two sets of buses 501,502 are used. In (a) of FIG. 16, the bus 501 is used to [(α) (β)], [(β) (γ1)], [(γ1) (β)], [(β) ( Data transfer of [α)] is performed in sequence, and using bus 502, [(α) (β)], [(β) (γ2)], [(γ2) (β)], [(β)] ) (α)] data transfer is performed in sequence, and [(α) (β)], [(β) (γ3)], [(γ3) (β)], using bus 502 Data transfer of [(β) (α)] is performed in sequence.

【0119】

Further, in (b) of FIG. 16, the bus 501 is used to [(α) (β)], [(β) (γ1)], [(β) (γ3)], [(γ1) (β)], [(γ3) (β)], [(β) (α)] data transfer is performed in sequence, and [(α) (β)], [( Data transfer of α) (β)], [(β) (γ2)], [(γ2) (β)], [(β) (α)], [(β) (α)] Are being performed in sequence.

【0120】

As shown in Fig. 16, there are some differences in processing capacity depending on the number of buses that can be used at the same time, but in any case, as shown in Fig. 16, data transfer between units is common in the order predetermined by scheduling. Data can be processed efficiently by performing the data via the bus. Further, by sharing a plurality of buses with all units, it is possible to realize all necessary data transfers with a minimum number of buses. Further, as shown in FIG. 15, when all the buses are connected to all the units (100, 200, 300 (1), 300 (2), 300 (3)) in common, there are no restrictions on the arrangement of each unit.

【0121】

For example, the communication signal input / output unit 100, the ATM cell processing unit 200, and the upper header processing unit 300 (1), 300 (2), 300 (3)) are connected to three sets of buses 301, 302, 303 via a connector having a common shape. When connecting, each unit may be connected to any connector, and the positions where a plurality of units are arranged can be exchanged with each other.

【0122】

If a bus that can be commonly used between units is not used, the protocol processing device of FIG. 15 must determine the connection and arrangement between units in consideration of the data processing procedure as shown in FIG. Also in this form, the communication signal input / output unit 100, the ATM cell processing unit 200, and the upper header processing unit 300 (1), 300 (2), 300 (3)) are each equipped with different programs on the same hardware. It has been realized. Therefore, the connection and arrangement between the units can be freely changed.

【0123】

[Effect of the invention]

As described above, according to the protocol processing apparatus of the present invention, the communication signal input / output means, the ATM cell processing means, and the upper header processing means that operate independently of each other can perform pipeline processing, thus speeding up the processing. it can. Further, according to the ATM cell storage method of the present invention, it is not necessary to allocate a memory area for each VC in advance when receiving a VC multiplex stream, so that there is no wasted area and the memory area can be used efficiently. ..

【0124】

Further, when a plurality of sets of communication paths such as buses that can be used for data transfer between a plurality of units are provided, the data can be transferred more efficiently between the units and the data can be processed efficiently.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the functional structure of the protocol processing apparatus of 1st Embodiment.

[Figure 2]

It is a block diagram which shows the hardware of the protocol processing apparatus of 1st Embodiment.

[Fig. 3]

It is a memory map which shows the structure of the storage area in the ATM cell storage memory.

[Fig. 4]

It is a memory map which shows the structure of the storage area for reception.

[Fig. 5]

It is a flowchart which shows the operation of the communication signal input / output unit and the ATM cell processing unit at the time of cell reception.

[Fig. 6]

It is a flowchart which shows the content of the multi-cell DMA transfer.

[Fig. 7]

It is a flowchart which shows the operation of the upper header processing unit.

[Fig. 8]

It is a flowchart which shows the transmission processing of the ATM cell processing unit.

[Fig. 9]

It is a time chart which shows the operation of the communication signal input / output unit when the VC of each cell is different.

[Fig. 10]

It is a time chart which shows the operation of a communication signal input / output unit when cells of the same VC are continuous.

[Fig. 11]

Configuration of storage area on ATM cell storage memory [Fig. 12]

Configuration of storage area on ATM cell storage memory [Fig. 13]

It is a block diagram which shows the hardware of the protocol processing apparatus of 2nd Embodiment.

[Fig. 14]

It is a block diagram which shows the hardware of the protocol processing apparatus of 3rd Embodiment.

[Fig. 15]

It is a block diagram which shows the hardware of the protocol processing apparatus of 4th Embodiment.

[Fig. 16]

It is a time chart which shows an example of data transfer timing.

[Fig. 17]

It is a block diagram which shows the connection and arrangement example of each unit.

[Explanation of symbols]

100 Communication signal input / output unit 110 ATM framer 120 DMA control circuit 130 VC separation module 140 Input CRC calculation circuit 180,290 Bus selection circuit 190 local bus 200 ATM cell processing unit 201 ATM cell storage memory 202 ATM cell information extraction module 203 VCI management memory 204 CRC recalculation module 205 Information input / output circuit 210 Data memory 220 DMA control circuit 230 microprocessor 240 program memory 250 FPGA 260 Ethernet interface 270 local bus 280,285 C-PCI bus interface 300 Upper header processing unit 301 Upper header storage memory 302 Upper header information extraction module 303 Information input / output circuit 310 Data memory 320 DMA control circuit 330 microprocessor 340 program memory 350 FPGA 360 ethernet interface 370 local bus 380,385 C-PCI bus interface 391,392 C-PCI bus 501,502,503 bus