Receiver and communication system

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a receiving device and a communication system that receives a serial signal and decodes an information signal (information data) from the received signal, and particularly to a receiving device and communication that can decode the information signal (information data) even if noise is mixed. It's about the system.

【0002】

[Conventional technology]

In the serial data transmission method in which a plurality of information bits are transmitted in series, a start bit and an end bit indicating the start and end of a frame are attached before and after the data and transmitted asynchronously, and the receiving side detects the start bit and synchronizes the frames. A method called a pacing synchronization method is used.

【0003】

In the conventional serial data transmission method as described above, if a noise signal (pulse) due to noise exists before the start bit, the noise signal (pulse) may be mistakenly detected as the start bit. If there is a noise signal (pulse) between the data, the noise signal may be mistakenly detected as data.

【0004】

Therefore, when a noise signal (pulse) is generated, a noise signal is removed from the received signal by removing a signal having a predetermined pulse width or less as a noise signal so as not to make an erroneous detection by this noise signal. A method for receiving serial data, which obtains frame-synchronized data based on a signal from which noise has been removed, is disclosed in Japanese Patent Application Laid-Open No. 6-152576.

【0005】

A method for correcting bit loss of a run-in signal is disclosed in Japanese Patent Application Laid-Open No. 58-42336.

【0006】

[Problems to be Solved by the Invention]

In the conventional receiving device, since it is performed as described above, when a noise signal (pulse) having a pulse width similar to that of the data signal is generated, this noise signal (pulse) cannot be removed. Therefore, if a noise signal (pulse) having a pulse width similar to that of the data signal exists in the vicinity of the synchronization signal, there is a problem that the pulse is erroneously detected as a start pulse. Further, if a noise signal (pulse) having a pulse width similar to that of the data signal exists between the data, there is a problem that the pulse is erroneously detected as a data signal.

【0007】

In order to prevent such erroneous detection, the pulse width of the synchronization signal or the data signal may be increased, but in this case, the pulse width of the synchronization signal or the data signal becomes large and the transmission speed (predetermined time). There was a problem that the number of data that can be transmitted within) decreased.

【0008】

The present invention has been made to solve the above problems, and even when there is a noise signal, it is possible to accurately detect a synchronization signal or accurately decode an information signal (data signal), and It is an object of the present invention to provide a communication system and its receiving device in which the transmission speed is not significantly reduced.

【0009】

[Means for solving problems]

The receiving device according to the present invention is a receiving device that receives a serial signal including a synchronization signal and an information signal transmitted via a transmission medium and decodes an information signal from the serial signal, using the synchronization signal or the information signal. There is a predetermined time between a receiving circuit that receives the same first signal and a serial signal including the second signal and the received signal received by the receiving circuit for a predetermined time between the first and second signals. A delay circuit that generates a delay signal by delaying by an interval, a multiplication circuit that multiplies the received signal and the delay signal to generate a multiplication signal, and a decoding circuit that decodes the information signal based on the multiplication signal. It is prepared.

【0010】

Further, even if the first signal and the second signal are used as synchronization signals, the decoding circuit detects the synchronization signal based on the multiplication signal, and decodes the information signal based on the detected synchronization signal. Good.

【0011】

Further, the serial signal includes the same third signal as the first and second signals, and the delay circuit delays the received signal by the time interval between the first and third signals. The delay signal of the above and the second delay signal obtained by delaying the received signal by the time interval between the second and third signals are generated, and the multiplication circuit performs the first and second delay signals and the second delay signal. The received signal may be multiplied to generate a multiplication signal.

【0012】

Further, the first signal, the second signal, and the third signal are used as synchronization signals, the decoding circuit detects the synchronization signal based on the multiplication signal, and the information signal is generated based on the detected synchronization signal. It may be decrypted.

【0013】

Further, the time interval between the first and second signals and the time interval between the second and third signals may be different.

【0014】

Further, the delay circuit sequentially stores the A / D converter, the digital signal converted by the A / D converter, and the digital signal stored in the digital memory is converted into an analog signal. A / A converter and a timing generator that delays the digital signal stored in the digital memory for a predetermined time and outputs the digital signal may be provided.

【0015】

Further, the communication system according to the present invention receives a transmission device that transmits a serial signal including a synchronization signal and an information signal, and the serial signal transmitted from the transmission device via a transmission medium, and information is transmitted from the serial signal. In a communication system including a receiving device for decoding a signal, the receiving device is the synchronization signal or an information signal and receives a serial signal including the same first signal and a second signal set for a predetermined time. The reception circuit, the delay circuit that generates a delay signal by delaying the reception signal received by the reception circuit by a predetermined time interval between the first and second signals, and the reception signal and the delay signal are multiplied. It is provided with a multiplication circuit that generates a multiplication signal and a decoding circuit that decodes the information signal based on the multiplication signal.

【0016】

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. Hereinafter, the embodiment 1 will be described with reference to the drawings. FIG. 1 is a block diagram showing a transmitting station and a receiving station of the communication system of the first embodiment, FIG. 1 (a) is a block diagram showing a configuration of a transmitting device in the transmitting station, and FIG. 1 (b) is a receiving block diagram. It is a block diagram which shows the structure of the receiving device in a station.

【0017】

As shown in FIG. 1A, the transmitting station includes a P / S converter 1 including a flip-flop 1a, a transmitting clock generator 2, a transmitting clock divider 3a, a modulator 4, a power amplifier 5, and a driver 6. Consists of.

【0018】

The parallel-format transmission data 7 to be transmitted is input to the P / S converter 1, and the signal generated by the transmission clock generator 2 is divided by the frequency divider 3a by the P / S converter 1 (the signal is divided by the frequency divider 3a. It is output as bit serial data from the flip-flop 1a at the final stage of the P / S converter 1 in synchronization with the transmission clock). Then, this bit serial data is modulated by the modulator 4, amplified by the power amplifier 5, converted into a signal compatible with the communication medium, and output to the communication medium 8 via the driver 6.

【0019】

Here, the frequency divider 3a operates as a 1/2 frequency divider during the synchronous bit transmission operation, and outputs the signal of the transmission clock generator 2 as it is (does not divide) during the information bit transmission operation. Therefore, during the synchronous bit transmission operation, the transmission clock generator 2 outputs a signal with a period twice that of the normal clock signal, and the P / S converter 1 outputs one clock (in this case, two bits). Since the time of 2 bits elapses in the modulator 4 while the signal of (minutes) is converted, the synchronization bits are output 2 bits in succession. That is, this transmitting station always transmits 2 synchronization bits, and the information bit transmits the data to be transmitted bit by bit.

【0020】

As shown in FIG. 1 (b), the receiving station includes a sensor 10, a preamplifier 11, a detection circuit 12, a band filter 13, a delay circuit 14, a multiplier 15, a comparator 16, a receiving clock generator 17a, and a comparator 18. It consists of an S / P converter 19 including a flip-flop 19a.

【0021】

The signal 20a received via the communication medium is converted into an electric signal by the sensor 10 and amplified by the preamplifier 11. After that, it is detected by the detection circuit 12, and the received signal 20b is demodulated through the band filter 13. Then, this received signal 20b is input to the delay circuit 14 and the multiplier 15.

【0022】

The received signal 20b input to the delay circuit 14 is delayed by 1 bit time in the delay circuit 14 and output as the delay signal 21. Then, the delay signal 21 is input to the multiplier 15 and the comparator 18.

【0023】

Therefore, the delay signal 21 obtained by delaying the received signal 20b by 1 bit time and the received signal 20b as it is without delay are input to the multiplier 15, and the product of the delay signal 21 and the received signal 20b multiplied. The value (multiplication signal 22) is output. Then, the multiplication signal 22 is input to the comparator 16.

【0024】

The comparator 16 determines whether or not the multiplication signal 22 exceeds a certain threshold value 1 (amplitude value of signal 23), and if it exceeds, it is a predetermined value, and if it is not exceeded, it is 0 signal 24. Is generated, and this signal 24 is input to the reception clock generator 17a.

【0025】

Here, the reception clock generator 17a operates so as to regard the rising edge of the signal 24 as synchronous detection, and the reception clock generator 17a has a time interval of 2 bits (the number of synchronous bits) from the time of synchronous detection. A reception clock signal 25 that rises at 1-bit time intervals is generated from a time point after a certain delay time is added. Then, the received clock signal 25 is input to the S / P converter 19.

【0026】

On the other hand, the delay signal 21 output from the delay circuit 14 is also input to the comparator 18. Then, the comparator 18 determines whether or not a certain threshold value 2 (amplitude value of signal 26) is exceeded, and if it is exceeded, a predetermined value is generated, and if it is not exceeded, a signal 27 of 0 is generated. This signal 27 is output to the S / P converter 19.

【0027】

The S / P converter 19 synchronizes the input signal 27 with the reception clock signal 25 output from the reception clock generator 17a and outputs it as an output signal 28 from the first-stage flip-flop 19a, and outputs this output signal 28. Is converted into a parallel signal and output. In this way, the received data 29 in parallel format is obtained as the output of the entire S / P converter 19.

【0028】

Next, the relationship between each signal in the receiving device will be described. FIG. 2 is a timing chart showing the relationship between the received signal 20b, the delay signal 21, the multiplication signal 22, and the like. In the figure, the periods 30a, 30b, 30c, 30d, 30e, 30f, and 30g each indicate a time interval of 1 bit.

【0029】

In the waveform of the received signal 20b (output signal of the band filter 13), the signals 31a and 31b are synchronous signals (synchronous bit signals), and the signals 32a, 32b, 32c, 32d and 32e are information signals (bit signals of information data). Is. An example in which "1" is 2 bits for the synchronization bit signal, and "0", "0", "1", "1", and "0" for the information data bit signal in order from signal 32a to signal 32e. Shown.

【0030】

Here, when the bit data is 1, there is a signal only in the first fixed period of 1 bit time as shown in signals 31a, 31b, 32c, 32d, and conversely, when the bit data is 0. Shows an example of eliminating the signal as shown in signals 32a, 32b, 32e. Note that this is not particularly limited as long as it is a signal that can distinguish at least two values of "1" and "0".

【0031】

Further, the signal 33a is a noise signal, and is the signal 34a in the waveform of the delay signal 21. The noise signals 33a and 34a are signals having the same peak value as the synchronous bit signals 31a and 31b and the bit data 1 signals 32c and 32d.

【0032】

The waveform of the delay signal 21 output from the delay circuit 14 is a waveform translated to the right by 1 bit time (the right is the traveling direction of time) as compared with the waveform of the received signal 20b. Further, the signal 27 is an output signal when the delay signal 21 and the threshold value 2 (amplitude value of the signal 26) are passed through the comparator 18.

【0033】

Here, the noise signal 33a in the received signal 20b exists before the signal 31a of the synchronization bit, but in the multiplier signal 22 (output signal of the multiplier 15) of the received signal 20b and the delay signal 21, noise is generated by multiplying. The influence of the signal has disappeared, and the signal 35, which is the source of the synchronous detection, is generated in the period 30b. Therefore, the output signal 24 of the comparator 16 generates the signal 37 at the time when the signal 35 exceeds the threshold value 1 (amplitude value of the signal 23), and this becomes the synchronous detection signal.

【0034】

Further, the reception clock generator 17a receives the synchronization detection signal 37 and generates the reception clock signal 25. That is, the reception clock generator 17a reliably captures the received data with a fixed delay time (time 39; time 39; time equivalent to 2 bits of synchronization bit) 2 bit time (time 38a: time equivalent to 2 bits of synchronization bit) from the rise of the synchronization detection signal 37 in the signal 24. The reception clock signal 25 that rises every 1 bit time from the time when the delay time for) is added is generated.

【0035】

Then, decoding is performed by sampling the data at the time points 40a, 40b, 40c, 40d of the reception clock signal 25 and the time points 41a, 41b, 41c, 41d of the signal 27. The data decoded at each time point becomes "0", "0", "1", "1" in the order of 42a, 42b, 42c, 42d, which is the received signal 20b of the signals 32a, 32b, 32c, 32d. The data is equal to "0", "0", "1", and "1", and is correctly decoded.

【0036】

The receiving device of this embodiment multiplies the received received signal by a delayed signal obtained by delaying the received signal by the time interval between the two synchronization signals to generate a multiplied signal, and based on this multiplied signal. Since the information signal is decoded based on the detected synchronization signal, the synchronization signal can be accurately detected even when a noise signal (pulse) exists before the synchronization signal. Further, the synchronization signal can be transmitted with a minimum pulse width of 2 bits and the information signal can be transmitted with a minimum pulse width of 1 bit, and the transmission speed does not decrease significantly.

【0037】

Embodiment 2. This embodiment 2 will be described with reference to the figure. FIG. 3 is a block diagram showing a transmitting station and a receiving station of the communication system of the second embodiment, FIG. 3A is a block diagram showing a configuration of a transmitting device in the transmitting station, and FIG. 3B is a receiving block diagram. It is a block diagram which shows the structure of the receiving device in a station.

【0038】

The configuration of the transmitting station, which is different from that of the first embodiment, is that the frequency divider 3b operates as a 1/2 frequency divider in both the synchronization bit and the information bit. That is, in the transmitting station of this embodiment, two synchronization bits are always transmitted, and the same data is transmitted by two bits at a time as the information bits.

【0039】

On the other hand, the configuration different from the first embodiment in the receiving station is that the serial data input of the S / P converter 19 is connected to the output signal 24 of the comparator 16 and the output signal 25 of the receiving clock generator 17a is 1. The difference is that the data is input to the S / P converter 19 via the / 2 divider 43a and that there is no comparator 18 in the first embodiment. That is, the signal 24 used for synchronous detection in the first embodiment is used as the serial data input of the S / P converter 19.

【0040】

Furthermore, by inputting the signal 25 output from the reception clock generator 17a to the 1/2 frequency divider 43a, the 1/2 frequency divider 43a is constant at a time interval of 2 bits from the time of synchronization detection. The point is that the signal 44 that rises at 2-bit time intervals is output from the time point after the time when the delay time is added.

【0041】

Next, the relationship between each signal in the receiving device will be described. FIG. 4 is a timing chart showing the relationship between the received signal 20b, the delay signal 21, the multiplication signal 22, and the like. In the figure, the periods 30a, 30b, 30c, 30d, 30e, 30f, and 30g each indicate a time interval of 1 bit.

【0042】

In the waveform of the received signal 20b, the signals 31a and 31b are synchronous bit signals, the signals 32a, 45a, 32b, 45b and 32c are information data bit signals, respectively, and the signals 32a and 45a and the signals 32b and 45b are the same data, respectively. Is a continuous signal of 2 bits at a time. This is because the transmitting station transmits the synchronization bits by 2 bits in succession, and the information bits also transmit the same data by 2 bits in succession. An example in which "1" is 2 bits in the synchronization bit signal of signals 31a and 31b, and the bit signal of information data is "0", "0", "1", "1" in order from signal 32a to signal 32c. Is shown. In this case, the data bits that the transmitting station wants to convey to the receiving station are 0 and 1. That is, the transmitting station transmits 2 bits of the same information signal to be transmitted to the receiving station.

【0043】

Further, the signal 46a is a noise signal, and is the signal 47a in the waveform of the delay signal 21. The noise signals 46a and 47a are signals having a peak value similar to that of the synchronous bit signals 31a and 31b and the bit data 1 signals 32b and 45b. Further, FIG. 4 shows an example of superimposing on the signal 45a in the period 30d.

【0044】

The waveform of the delay signal 21 output from the delay circuit 14 is a waveform translated to the right by 1 bit time (the right is the traveling direction of time) as compared with the waveform of the received signal 20b. Further, in the multiplication signal 22 which is a product signal of the received signal 20b and the delay signal 21, a signal 35 exceeding the threshold value 1 (amplitude value of the signal 23) is generated at the time point 36 in the period 30b, and this signal With the generation of 35, a signal 37 is generated at the signal 24, and this becomes a synchronous detection signal.

【0045】

Further, the signal 25 output from the reception clock generator 17a is passed through the 1/2 frequency divider 43a, and the output signal 44 is divided by the 1/2 frequency divider 43a. It is a signal that rises every 2 bit time interval from the time after the time when a certain delay time is added to the time interval of 2 bits from the time of synchronization detection. Therefore, the signal 44 has a waveform that rises at time points 48a and 48b.

【0046】

Then, decoding is performed by sampling the data at the time points 49a and 49b of the signal 24 at the time points 48a and 48b of the signal 44. The data decoded at each time point becomes 0 and 1 in the order of 50a and 50b in the signal 44, which is equal to the original data bit string 0 and 1 transmitted.

【0047】

At this time, the noise signal 47a and the signal 32b generate a signal 51 in the multiplication signal 22, and a signal 52 is generated in the signal 24 accordingly, but it is not 48a or 48b at the rising point of the signal 44. Even if it is not sampled as received data and there is a noise signal 46a, it will be decoded correctly.

【0048】

In the description of the second embodiment, the same method as that of the first embodiment is used as the synchronous detection method, but the present invention is not particularly limited, and the transmitting station is the same for each bit as the data bit. Data is transmitted in 2 bits, the receiving station multiplies the received signal by the delayed signal delayed by 1 bit time with a multiplier, and the value of the product is sampled and decoded every 2 bit time. If it is, the synchronous detection means may use another method.

【0049】

The receiving device of this embodiment delays the received received signal by the time interval between the two information signals to generate a delayed signal, and multiplies the delayed signal and the received signal to generate a multiplied signal. Since the information signal is decoded based on this multiplication signal, in addition to the effect of the first embodiment, the information signal can be accurately obtained even when a noise signal (pulse) exists between the data. Can be decrypted.

【0050】

Embodiment 3. The delay circuit having the configuration of Embodiments 1 and 2 can be realized by using a delay line or the like if the 1-bit time is short, but if the 1-bit time is long, some ingenuity is required. Therefore, the delay circuit of this embodiment converts the input signal into digital data with an A / D converter so that the delay signal can be generated even when the 1-bit time is long, and converts this into digital memory. The delay signal of the analog signal for 1 bit time is generated by sequentially storing the digital data stored 1 bit time ago and sequentially taking it out from the digital memory and returning it to the analog signal with the D / A converter. It is a thing.

【0051】

A delay circuit that can handle a long 1-bit time will be described with reference to the figure. FIG. 5 is a diagram showing a configuration of a delay circuit according to this embodiment. In the figure, 14 corresponds to the delay circuit 14 of the first and second embodiments. Further, the input signal 20b and the output signal 21 are signals corresponding to the received signal 20b and the delay signal 21 of FIGS. 1 and 3, respectively.

【0052】

The delay circuit 14 stores the A / D converter 53, the ring-type digital memory 54, the D / A converter 55, and the A / D-converted digital signal 61 at which address of the ring-type digital memory 54. Switch 56 to determine the storage address, storage address pointer 57 to indicate the storage address, switch 58 to determine from which address to read the digital signal 62 to be D / A converted, read address pointer 59 to indicate the read address, and timing generator 60. Consists of.

【0053】

In the timing generator 60, the A / D converter 53 has a timing signal 63 indicating the A / D conversion timing, a timing signal 64 indicating the switching timing of the storage address switch 56, and a timing signal indicating the switching timing of the read address switch 58. 65, a timing signal 66 indicating the D / A conversion timing of the D / A converter 55 is generated.

【0054】

Here, the timing signals 64 and 65 are generated so that the switching cycle T of the switches 56 and 58 is T (T = 1 bit time ÷ the number of samples N within 1 bit time), and the timing signals 64 are generated. Occasionally, the signal 61 is stored at the address indicated by the storage address pointer 55. This stored address pointer 57 points to the next address i + 1 after the signal 61 is stored in the address i, and further points to the address 1 after the address N, so that the addresses 1 and 2 are pointed to. , ... N, 1, 2, ..., Sampled signals 61 are circulated and stored.

【0055】

On the other hand, the read address pointer 59 also points to the next address i + 1 after reading the signal from the address i like the stored address pointer 57, and further points to the address 1 after the address N. However, in reality, the address pointed to by the read address pointer 59 is the address pointed to by the stored address pointer 57 N times before, that is, in this case, the address is circulated and stored, so that the stored address pointer is stored. Make sure that the read address pointer 59 points to the address one after 57. Then, when the timing signal 65 is generated, the signal 62 at the address pointed to by the read address pointer 59 is read, so that the read data becomes the data stored 1 bit time ago and is delayed by 1 bit time. Is generated.

【0056】

Here, the capacity of the ring-type memory 54 is that the digital bit width of the A / D converter 53 and the D / A converter 55 and the 1-bit time are sampled at least 10 times to store and read the data. Considering the above, a capacity of 10 words or more is required. (As in the examples of Embodiments 1 and 2, when demodulating a signal having a modulated signal only in the first fixed period of 1 bit time, demodulation in the first fixed period of 1 bit time is performed at least 10 times. In order to store and read data as a sample, for example, a capacity of 100 words or more is required to sample 100 1-bit times.

【0057】

The conversion time of the A / D converter 53 and the storage time in the digital memory 54, the conversion time of the D / A converter 55 and the read time from the digital memory 54 are calculated from the time obtained by dividing 1 bit time by the number of samples. Need to be configured quickly.

【0058】

The delay circuit of this embodiment converts an A / D converter, a digital memory that sequentially stores the digital signals converted by the A / D converter, and a digital signal stored in the digital memory into an analog signal. Since it is equipped with a D / A converter and a timing generator that delays the digital signal stored in the digital memory for a predetermined time and outputs it, the signals are sequentially stored from the A / D converter to the digital memory and at the same time. At the same time, the signals stored in the digital memory can be sequentially taken out, and a delayed signal can be generated even when the 1-bit time is long.

【0059】

Embodiment 4. Even in the case of the configuration described in Embodiment 1, there may be an effect that synchronous detection cannot be performed accurately depending on how the noise signal is applied. A method for accurately performing synchronous detection even when such a noise signal is applied will be described.

【0060】

Before explaining the above method, FIG. 6 shows a timing chart when synchronous detection cannot be performed accurately by the method of the first embodiment. The signal shown in the figure differs from the signal of FIG. 2 of the first embodiment in that the noise signal 33b is added in addition to the noise signal 33a in FIG. The noise signal 33a and the noise signal 33b are signals that are exactly 1 bit time lag, and the waveforms and the like are the same except for the generation position.

【0061】

Due to the fact that the noise signal 33b is superimposed exactly 1 bit time after the noise signal 33a, the signal 67 is generated in the multiplication signal 22 in FIG. 6, and the signal 68 is generated in the signal 24. Therefore, the rising edge of the signal 68 occurs prior to the signal 37 which should be the original synchronization detection signal, and the rising edge of the signal 68 causes erroneous synchronization detection.

【0062】

Therefore, it is decoded by sampling the data at the rising points 69a, 69b, ..., 69e of the signal 25 and the time points 70a, 70b, ..., 70e at the signal 27, and the data at each time point is 71a, Bit data is decoded as "0" at all points of 71b, ..., 71e. This is a decoding different from the original received data, "0", "0", "1", and "1".

【0063】

FIG. 7 is a block diagram showing a transmitting station and a receiving station of the communication system of the fourth embodiment, FIG. 7A is a block diagram showing a configuration of a transmitting device in the transmitting station, and FIG. 7B is a receiving block diagram. It is a block diagram which shows the structure of the receiving device in a station.

【0064】

The configuration of the transmitting station, which is different from that of the first embodiment, is that the frequency divider 3c operates as a 1/3 frequency divider during the transmission operation of the synchronous bit. The operation of outputting (not dividing) the signal of the transmission clock generator as it is at the time of transmitting the information bit is the same as that of the first embodiment. That is, this transmitting station always transmits 3 synchronization bits, and the information bit transmits the data to be transmitted bit by bit.

【0065】

On the other hand, the receiving station has three configurations different from those of the first embodiment. The first difference is that there are two delay circuits, 14a and 14b, and two multipliers, 15a and 15b, which is different from the signal 21a (1 bit time delay signal) that has passed through the delay circuit only one step. The signal 21b (delayed signal for 2 bits of time) that has passed through the two delay circuits is multiplied by the multiplier 15a, and the multiplied signal 22a and the received signal 20b that does not pass through the delay circuit are multiplied by the multiplier 15b. The point is that the triple product signal 22b (multiplication signal) is input to the comparator 16 (in the first embodiment, the multiplier signal of the delay signal that has passed through the delay circuit and the reception signal that does not pass through the delay circuit is the comparator 16 Is entered in.).

【0066】

The second difference is that the delay signal 21b that has passed through the delay circuit in two stages is input to the comparator 18 (in the first embodiment, the signal that has passed through the delay circuit in one stage is input to the comparator 18). ).

【0067】

The third difference is that in the receive clock generator 17b, the time from synchronization detection to the first rise of the receive clock is a time interval of 3 bits (the number of bits of the synchronization bit) plus a certain delay time. It is a point (in the first embodiment, it is a time obtained by adding a certain delay time to a time interval of 2 bits). It should be noted that the point that the reception clock that rises at every 1-bit time interval from the first rise time of the reception clock is generated is the same as that of the first embodiment.

【0068】

Next, the relationship between each signal in the receiving device will be described. FIG. 8 is a timing chart showing the relationship between the received signal 20b, the delay signals 21a, 21b, the multiplication signal 22b, and the like. In the figure, the periods 30a to 30i each indicate a time interval of 1 bit.

【0069】

In the waveform of the received signal 20b, the signals 31a, 31b, and 31c are synchronous bit signals, and the signals 32a to 32f are information data bit signals, respectively. The synchronization bit signal is "1" for 3 bits, and the information data bit signal is "0", "0", "0", "1", "1", "1" in order from signal 32a to signal 32f. An example is shown.

【0070】

Further, the signals 33a and 33b are noise signals, and are signals 34a and 34b in the waveform of the delay signal 21a and signals 72a and 72b in the waveform of the delay signal 21b. The noise signals 33a and 33b are signals having a peak value similar to that of the synchronous bit and the waveform of the bit data 1, and the noise signal 33a and 33b have a 1-bit time as shown in FIG. It's a distant one.

【0071】

The waveform of the delay signal 21a output from the delay circuit 14a is a waveform translated to the right by 1 bit time (the right is the traveling direction of time) as compared with the waveform of the received signal 20b. Further, the waveform of the delay signal 21b obtained by passing the delay signal 21a through the delay circuit 14b is a waveform translated to the right by 1 bit time as compared with the waveform of the delay signal 21a. That is, the waveform is translated to the right by 2 bit hours compared to the waveform of the received signal 20b.

【0072】

Then, in the multiplied signal 22b, which is a triple product signal of the received signal 20b, the delay signal 21a, and the delay signal 21b, a signal 74 exceeding the threshold value 1 is generated in the period 30c, and the signal 74 is generated as the signal 74 is generated. The signal 75 at 24 is generated, which becomes the synchronous detection signal.

【0073】

Further, the reception clock generator 17b receives the synchronization detection signal 75 and has a fixed delay time (time 39;) 3 bit time (time 38b: time equivalent to 3 bits of synchronization bit) from the rise of the signal 75 in the signal 24. A reception clock signal 25 that rises every 1 bit time is generated from the time when the delay time for reliably capturing the received data) is added. Therefore, the signal 25 has a waveform that rises at time points 76a, 76b, 76c, and 76d.

【0074】

Then, decoding is performed by sampling the data at the time points 77a, 77b, 77c, and 77d of the signal 27 at the time points 76a, 76b, 76c, and 76d of the signal 25. The data at each time point is "0", "0", "0", "1" in the order of 78a, 78b, 78c, 789d, which is the received data bit string "0", "0", "0". ", Equal to" 1 ".

【0075】

In the receiving device of this embodiment, after receiving a signal transmitted by providing 3 bits of a synchronization signal in the receiving circuit, the received received signal is delayed by the time interval between the two synchronization signals, and the first A second delay signal is generated by delaying the delay signal of the above and the interval between the two synchronization signals, and the first delay signal, the second delay signal, and the received signal are multiplied to generate a multiplication signal. .. Then, since the synchronization signal is detected based on this multiplication signal and the information signal is decoded based on the detected synchronization signal, the noise signal (pulse) exists before the synchronization signal, and Even when the noise signal exists at a time interval between the two synchronization signals with respect to this noise signal, the synchronization signal can be detected accurately. Further, the synchronization signal can be transmitted with a minimum pulse width of 3 bits and the information signal can be transmitted with a minimum pulse width of 1 bit, and the transmission speed does not decrease significantly.

【0076】

In this embodiment, the transmitting station transmits 3 synchronization bits, and the receiving station includes a received signal, a delayed signal in which the received signal is delayed by 1 bit time, and a signal in which the received signal is delayed by 2 bit time. Although only the explanation configured to perform synchronous detection based on the triple product signal of is shown, this is not particularly limited, and the transmitting station transmits n bits (n is an integer of n 4). , The receiving station delays the received signal by 1 bit time from the delayed signal that delayed the received signal by 1 bit time to the delayed signal that delays the received signal by n-1 bit time in order. Signals may be generated respectively, and synchronous detection may be performed based on an n-fold signal obtained by multiplying these delay signals and received signals.

【0077】

In this case, three or more noise signals with a time difference of 1 bit time are superimposed in the vicinity of the synchronization bit, and even if the peak value is at the same level as the synchronization signal, there are n-1 noise signals. If it is within the range, synchronous detection can be performed accurately.

【0078】

Embodiment 5. Even in the case of the configuration described in Embodiment 2, there may be an effect that the decoding process cannot be performed accurately depending on how the noise signal is applied. A method for accurately performing decoding processing even when such a noise signal is applied will be described.

【0079】

Before explaining the above method, FIG. 9 shows a timing chart when decoding cannot be performed accurately by the method of the second embodiment. The signal shown in the figure differs from the signal of FIG. 4 of the second embodiment in that the noise signal 46b is added in addition to the noise signal 46a in FIG. The noise signal 46a and the noise signal 46b are signals that are exactly 1 bit time lag, and the waveforms and the like are the same except for this generation position.

【0080】

Due to the fact that the noise signal 46b is superimposed exactly 1 bit time before the noise signal 46a, the signal 79 is generated in the multiplication signal 22 in FIG. 9, which causes the signal 80 to be generated in the signal 24. To do. Therefore, when the data at the rising points 48a and 48b of the signal 44 and the data at the time points 49a and 49b at the signal 24 are sampled and decoded, the data at each time point is "1" and "1" at the time points of 50a and 50b. It decrypts the data. This is a decryption different from the original received data, "0" and "1".

【0081】

FIG. 10 is a block diagram showing a transmitting station and a receiving station of the communication system of the fifth embodiment, FIG. 10A is a block diagram showing a configuration of a transmitting device in the transmitting station, and FIG. 10B is a receiving block diagram. It is a block diagram which shows the structure of the receiving device in a station.

【0082】

The configuration different from the second embodiment in the transmitting station is that the frequency divider 3d operates as a 1/3 divider (in the second embodiment, it is a 1/2 divider). That is, this transmitting station always transmits 3 synchronization bits and transmits 3 bits of the same data as the information bits (in the second embodiment, 2 synchronization bits are always transmitted and 2 bits of the same data as the information bits are transmitted. I'm sending them one by one.)

【0083】

The receiving station has three configurations different from those of the second embodiment. The first difference is that there are two delay circuits, 14a and 14b, and two multipliers, 15a and 15b, which is different from the signal 21a (1 bit time delay signal) that has passed through the delay circuit only one step. The signal 21b (delayed signal for 2 bits of time) that has passed through the two delay circuits is multiplied by the multiplier 15a, and this multiplied signal and the received signal 20b that does not pass through the delay circuit are multiplied by the multiplier 15b. A triple product signal 22b (multiplication signal) is generated, and this multiplication signal 22b is input to the comparator 16 and the S / P converter 19 (in the second embodiment, the signal and the delay that have passed through the delay circuit one step). The multiplied signal of the signal that does not pass through the circuit is input to the comparator 16 and the S / P converter 19).

【0084】

The second difference is that the time from synchronization detection to the first rise of the reception clock in the reception clock generator 17b is the time interval of 3 bits (the number of synchronization bits) plus a certain delay time. (In the second embodiment, it is the time obtained by adding a certain delay time to the time interval of 2 bits).

【0085】

The third difference is that the frequency divider 43b is a 1/3 divider in this embodiment and samples the output signal 25 of the reception clock generator 17b every 3 bit times (Embodiment 2). Then, the 1/2 divider 43a samples the output signal 24 of the reception clock generator 17a every 2 bit times.)

【0086】

Next, the relationship between each signal in the receiving device will be described. FIG. 11 is a timing chart showing the relationship between the received signal 20b, the delay signals 21a, 21b, the multiplication signal 22b, and the like. In the figure, the periods 30a to 30i each indicate a time interval of 1 bit.

【0087】

In the waveform of the received signal 20b, signals 31a, 31b, and 31c are synchronous bit signals, and signals 32a, 45a, 81a, 32b, 45b, and 81b are information data bit signals, respectively, and signals 32a, 45a, 81a, and signal 32b. And 45b and 81b are signals in which the same data is continuous for 3 bits. This is because the transmitting station transmits the synchronization bits three times in succession, and the information bits also transmit the same data three bits in succession. The synchronization bit signals of signals 31a, 31b, and 31c are "1" for 3 bits, and the information data bit signals are "0", "0", "0", "1", and "1" in order from signal 32a to signal 81b. An example of "1" and "1" is shown. In this case, the data bits that the transmitting station wants to convey to the receiving station are 0 and 1. That is, the transmitting station transmits the same data to be transmitted to the receiving station in 3 bits.

【0088】

Further, the signals 46a and 46b are noise signals, and are signals 47a and 47b in the waveform of the delay signal 21a and signals 82a and 82b in the waveform of the delay signal 21b. The noise signals 46a and 46b are signals having peak values similar to those of the synchronization bits 31a to 31c and the signals 32b, 45b and 81b of the bit data "1", and are noise signals similar to those shown in FIG. The distance between 46a and 46b is 1 bit time.

【0089】

The waveform of the delay signal 21a output from the delay circuit 14a is a waveform translated to the right by 1 bit time (the right is the traveling direction of time) as compared with the waveform of the received signal 20b. Further, the waveform of the delay signal 21b obtained by passing the delay signal 21a through the delay circuit 14b is a waveform translated to the right by 1 bit time as compared with the waveform of the delay signal 21a. That is, the waveform is translated to the right by 2 bit hours compared to the waveform of the received signal 20b.

【0090】

Then, in the multiplied signal 22b, which is a triple product signal of the received signal 20b, the delay signal 21a, and the delay signal 21b, a signal 74 exceeding the threshold value 1 is generated in the period 30c, and the signal 74 is generated as the signal 74 is generated. The signal 75 at 24 is generated, which becomes the synchronous detection signal.

【0091】

Further, the reception clock generator 17b receives this synchronization detection signal and generates a signal 25 that rises every 1 bit time from the time when a constant delay time 39 is added 3 bit time 38b after the rise of the signal 75 in the signal 24. .. Then, this signal 25 is input to the 1/3 divider 43b and divided by 1/3, so that the time after the synchronization detection time is the time after a certain delay time is added to the time interval of 3 bits. Outputs a signal 44 that rises every 3 bit time interval. Therefore, the signal 44 has a waveform that rises at the time points 83a and 83b.

【0092】

Then, decoding is performed by sampling the data at the time points 84a and 84b of the signal 24 at the time points 83a and 83b of the signal 44. The data at each time point becomes 0 and 1 in the order of 85a and 85b, which is equal to the original data bit string 0 and 1 received.

【0093】

In this embodiment, synchronous detection is performed in the same manner as in the synchronous detection means of the fourth embodiment, but this is not particularly limited, and the transmitting station transmits the same data bit by bit as data bits. Then, the receiving station samples the triple product signal of the received signal, the delayed signal in which the received signal is delayed by 1 bit time, and the delayed signal in which the received signal is delayed by 2 bit time, every 3 bit time. , The synchronous detection means may be another method as long as it decodes based on the sample value.

【0094】

In this embodiment, the same information signal is continuously provided in 3 bits, the transmitted signal is received by the receiving circuit, and the received received signal is delayed by the time interval between the two information signals in the first method. A delay signal and a second delay signal are generated by delaying by an interval between two information signals, and the first delay signal, the second delay signal, and the received signal are multiplied to generate a multiplication signal. Since the information signal is decoded based on this multiplication signal, there is a noise signal (pulse) at the position where the information signal should be generated, and there are two information signals for this noise signal. Even when noise signals are present at intervals of time between them, the information signal can be accurately decoded.

【0095】

In this embodiment, the transmitting station transmits the same information data bits by 3 bits, and the receiving station delays the received signal, the delayed signal by delaying the received signal by 1 bit time, and the received signal by 2 bits time. Only the explanation is shown in which a triple product signal with a signal is generated and the triple product signal is decoded based on a sample value sampled every 3 bit time, but this is not particularly limited. The transmitting station transmits the same information data bits by n bits (n is an integer of n 4), and the receiving station transmits the received signal for n-1 bit hours in order from the delayed signal in which the received signal is delayed by 1 bit time. Up to the delayed signal, the delayed signal delayed by 1 bit time with respect to the received signal is generated, and the n-fold signal obtained by multiplying these delayed signals and the received signal is generated, and this n The overlap signal may be decoded based on the sample value sampled every n bit time.

【0096】

In this case, three or more noise signals with a time difference of 1 bit time are superimposed on the information bit, and even if the peak value is at the same level as the synchronization signal, the number of noise signals is within n-1. If there is, it can be decrypted accurately.

【0097】

Embodiment 6. The delay circuit of this embodiment is applied to the delay circuits 14a and 14b of Embodiments 4 and 5, and a plurality of delay circuits 14a shown in FIG. 5 of Embodiment 3 are connected in series. It is connected to. FIG. 12 is a diagram showing a configuration of a delay circuit according to the sixth embodiment.

【0098】

In the figure, 14a and 14b correspond to the delay circuits 14a and 14b of FIG. 7 of the fourth embodiment and FIG. 10 of the fifth embodiment. Further, the input signal 20b and the output signal 21a of the delay circuit 14a are signals corresponding to the received signal 20b and the delay signal 21a in FIGS. 7 and 10, respectively, and the input signal 21a and the output signal 21b of the delay circuit 14b are respectively. These are signals corresponding to the delay signals 21a and 21b in FIGS. 7 and 10. Here, the output signal 21a of the delay circuit 14a and the input signal 21a of the delay circuit 14b are connected to form the same signal. The internal configurations of the delay circuits 14a and 14b are the same as those described in the third embodiment, and the functions are also the same. Therefore, the description of the internal configuration and operation will be omitted in order to avoid duplicate explanations.

【0099】

The embodiment of the delay circuit that generates the delay signal delayed by 2 bits time has been described above. However, in order to realize the delay signal delayed by n bits (n is an integer of n 3), it is necessary to realize the delay signal. A configuration may be adopted in which n delay circuits for delaying by 1 bit time of this embodiment are provided and connected in series.

【0100】

Embodiment 7. Even in the case of the configuration described in Embodiment 4, there may be an effect that synchronous detection cannot be performed accurately depending on how the noise signal is applied. A method for accurately performing synchronous detection even when such a noise signal is applied will be described.

【0101】

Before explaining the above method, FIG. 13 shows a timing chart when synchronous detection cannot be performed accurately by the method of the fourth embodiment. The signal shown in the figure differs from the signal shown in FIG. 8 in the fourth embodiment in that the received signal 20b in FIG. 13 does not have the noise signals 33a and 33b shown in FIG. This is the point where the noise signal 33c exists exactly 1 bit time before 31a. The noise signal 33c is a signal having a peak value similar to that of the synchronous bit signals 31a to 31c and the bit data "1" signals 32d to 32f.

【0102】

There is only one noise signal 33c, but due to the fact that it is superimposed exactly 1 bit time before the synchronization signal 31a, signal 86 is generated at time point 85 of the multiplication signal 22b in FIG. As a result, signal 87 is generated at signal 24. Therefore, the rising edge of the signal 87 occurs prior to the signal 75, which should be the original synchronization detection signal, and erroneous synchronization detection is performed.

【0103】

Therefore, it is decoded by sampling the data at the rising points 88a, 88b, ..., 88e of the signal 25 and the time points 89a, 89b, ..., 89e at the signal 27, and the data at each time point is 90a, At 90b, ..., 90e, the bit data is decoded as "1", "0", "0", "0", "1". This is a decoding different from the original received data, "0", "0", "1", "1", and "1".

【0104】

FIG. 14 is a block diagram showing a transmitting station and a receiving station of the communication system of the seventh embodiment, FIG. 14 (a) is a block diagram showing a configuration of a transmitting device in the transmitting station, and FIG. 14 (b) is a receiving block diagram. It is a block diagram which shows the structure of the receiving device in a station.

【0105】

The configuration of the transmitting station that differs from that of the fourth embodiment is that the operation of the transmitting clock generator 2a is different from that of the transmitting clock generator 2 of FIG. 7 of the fourth embodiment. That is, in the synchronization bit transmission operation, the time interval between the first and second synchronization signals (hereinafter referred to as the first synchronization bit interval) and the second and second synchronization signals in three consecutive synchronization signals. The difference is the time interval between the third synchronization signals (hereinafter referred to as the second synchronization bit interval). In this embodiment, the second synchronization bit interval is set to 1 bit time, and the first synchronization bit interval is set to 0.6 bit time.

【0106】

The receiving station has three configurations different from those of the fourth embodiment. The first difference is that the delay time in the delay circuit 14c is 0.6 times as long as the delay time in the delay circuit 14b (in FIG. 7 of the fourth embodiment, the delay time of the delay circuit 14a is the delay circuit 14b). Is the same as.).

【0107】

The second difference is that the input signal of the comparator 18a is the received signal 20b that does not pass through the delay circuit (in FIG. 7 of the fourth embodiment, the signal 21b that passes through the delay circuits 14a and 14b in two stages). Is input to the comparator 18.).

【0108】

The third difference is that the time from synchronization detection to the first rise of the receive clock in the operation of the receive clock generator 17c is the time interval of one bit plus a certain delay time. (In FIG. 7 of the fourth embodiment, the time from the synchronization detection to the first rise of the reception clock in the operation of the reception clock generator 17b is the time obtained by adding a certain delay time to the time interval of 3 bits. It has become.). It should be noted that the point of generating the reception clock that rises at 1-bit time intervals from the first rise time of the reception clock is the same as that of the fourth embodiment.

【0109】

Next, the relationship between each signal in the receiving device will be described. FIG. 15 is a timing chart showing the relationship between the received signal 20b, the delay signals 21c, 21b, the multiplication signal 22b, and the like. In the figure, periods 30, 30a, and 30c to 30i each indicate a 1-bit time interval, and period 30j indicates a time interval that is 0.6 times the 1-bit time interval.

【0110】

In the waveform of the received signal 20b, the signals 31a to 31c are synchronous bit signals, and the signals 32a to 32f are information data bit signals, respectively. The synchronization bit signal is "1" for 3 bits, and the information data bit signal is "0", "0", "0", "1", "1", "1" in order from signal 32a to signal 32f. An example is shown.

【0111】

Further, the signal 33c is a noise signal, which is the signal 34d in the waveform of the delay signal 21c and the signal 72d in the waveform of the delay signal 21b. The noise signal 33c is a signal having a peak value similar to that of the synchronization signals 31a to 31c and the signals 32d to 32f of the bit data 1, and the noise signal 33c is generated at the position shown in FIG.

【0112】

Further, the waveform of the signal 27a is an output waveform when the received signal 20b and the threshold value 2a are input to the comparator 18a, and the waveform of the delay signal 21c output from the delay circuit 14c is compared with the waveform of the received signal 20b. The waveform is moved in parallel to the right by 0.6 bit time, and the waveform of the signal 21b that is passed through the delay signal 21c and further passed through the delay circuit 14b is a waveform that is moved in parallel to the right by 1 bit time compared to the delay signal 21c. .. That is, the waveform is moved to the right by 1.6 bit time compared to the waveform of the received signal 20b.

【0113】

Then, in the multiplication signal 22b, which is a triple product signal of the received signal 20b, the delay signal 21c, and the delay signal 21b, a signal 74 exceeding the threshold value 1 is generated at the time point 73 in the period 30c, and this signal 74 is generated. Along with this, at the signal 24, a signal 75 is generated, which becomes a synchronous detection signal.

【0114】

Further, the reception clock generator 17c receives the synchronization detection signal 75 and rises every 1 bit time from the time when a constant delay time 39 is added after 1 bit time 38c from the rise of the signal 75 in the signal 24. To generate. Therefore, the signal 25 has a waveform that rises at the time points 91a, 91b, 91c, 91d, 91e, and 91f.

【0115】

Then, at the time points 91a, 91b, 91c, 91d, 91e, 91f of the signal 25, the decoding is performed by sampling the data of the time points 92a, 92b, 92c, 92d, 92e, 92f of the signal 27a. The data at each time point was "0", "0", "0", "1", "1", "1" in the order of 93a, 93b, 93c, 93d, 93e, 93f, which was received. Equal to the data bit string 0, 0, 0, 1, 1, 1.

【0116】

Further, in this embodiment, the example in which the first synchronization bit interval is 0.6 times as long as the second synchronization bit interval has been described, but this is not particularly limited, and the second synchronization bit interval is not particularly limited. The first synchronization bit, such as one that is more than one time as long as the first synchronization bit interval, or one in which the first synchronization bit interval is exactly 1 bit time interval and the second synchronization bit interval is shorter or longer than the first synchronization bit interval. The interval may be different from the second synchronization bit interval.

【0117】

In this embodiment, since the first synchronization bit interval and the second synchronization bit interval in the synchronization signal of the fourth embodiment are different, the time interval between the first synchronization bit signal and the synchronization bit is before. Even if there is a noise signal at the position of, it is possible to accurately detect the synchronization signal.

【0118】

In this embodiment, an example in which the synchronization bit is 3 bits is described, but this is not particularly limited, and the synchronization bit is n bits (n is an integer of n 4), and these synchronization bits are used. Of these, the time interval between adjacent synchronization bits may be different from the time interval between other synchronization bits. At this time, the time interval between at least one synchronization bit may be different from the time interval between the other synchronization bits, or a plurality of different time intervals may exist.

【0119】

8. The delay circuit of this embodiment is applied to the delay circuits 14c and 14b of FIG. 14 of the seventh embodiment, and of the delay circuits 14a and 14b shown in FIG. 12 of the sixth embodiment. Among them, the delay circuit 14a is replaced with the delay circuit 14c that delays the delay circuit 14a for a time different from the delay time of the delay circuit 14b.

【0120】

FIG. 16 is a diagram showing a configuration of a delay circuit according to the eighth embodiment. In the figure, the delay circuits 14c and 14b correspond to the delay circuits 14c and 14b in FIG. Further, the input signal 20b and the output signal 21c of the delay circuit 14c are signals corresponding to the received signal 20b and the delay signal 21c of FIG. 14, respectively, and the input signal 21c and the output signal 21b of the delay circuit 14b are respectively shown in FIG. These are signals corresponding to the delay signals 21c and 21b. Here, the output signal 21c of the delay circuit 14c and the input signal 21c of the delay circuit 14b are connected to form the same signal.

【0121】

The internal configurations of the delay circuits 14c and 14b are the same as the configurations described in the third embodiment, and the functions are almost the same. The difference is that the number of samples L stored in the memory 54a and the number M of the samples stored in the memory 54b are different, and the addresses indicated by the storage address pointer 57a of the memory 54a are 1, 2, ..., L, 1, It is switched according to the switching of the switch 56a like 2, ..., while the address indicated by the storage address pointer 55b of the memory 52b is 1, 2, ..., M, 1, 2, ... The point is that it can be switched with the switching of the switch 56b.

【0122】

The address pointed to by the read address pointer 57a is set to the address pointed to by the stored address pointer 57a L times before, and the address pointed to by the read address pointer 57b is pointed to by the stored address pointer 57b M times before. Make it an address. Other basic operations are the same as those in FIG. 12 of the sixth embodiment.

【0123】

The embodiment of the delay circuit when the synchronization bit is 3 bits has been described above, but when the synchronization bit is n bits (n is an integer of n 4), delay circuits having different numbers of samples stored in the memory are used. It is sufficient to provide n-1 delay circuits including them and connect them in series.

【0124】

[Effect of the invention]

The receiving device according to the present invention is a receiving device that receives a serial signal including a synchronization signal and an information signal transmitted via a transmission medium and decodes an information signal from the serial signal, using the synchronization signal or the information signal. There is a predetermined time between a receiving circuit that receives the same first signal and a serial signal including the second signal and the received signal received by the receiving circuit for a predetermined time between the first and second signals. A delay circuit that generates a delay signal by delaying by an interval, a multiplication circuit that multiplies the received signal and the delay signal to generate a multiplication signal, and a decoding circuit that decodes the information signal based on the multiplication signal. Since it is provided, it is possible to accurately decode the information signal even when there is a noise signal, and the transmission speed does not decrease significantly.

【0125】

Further, when the first signal and the second signal are used as synchronization signals, the decoding circuit detects the synchronization signal based on the multiplication signal, and decodes the information signal based on the detected synchronization signal. Can accurately detect the sync signal even when there is a noise signal (pulse) before the sync signal. Further, the synchronization signal can be transmitted with a minimum pulse width of 2 bits and the information signal can be transmitted with a minimum pulse width of 1 bit, and the transmission speed does not decrease significantly.

【0126】

Further, the serial signal includes the same third signal as the first and second signals, and the delay circuit delays the received signal by the time interval between the first and third signals. The delay signal of the above and the second delay signal obtained by delaying the received signal by the time interval between the second and third signals are generated, and the multiplication circuit performs the first and second delay signals and the second delay signal. When the above received signal is multiplied to generate a multiplied signal, a noise signal (pulse) exists before the signal, and noise is separated from this noise signal by the time interval between the two signals. The information signal can be accurately decoded even when the signal is present. Further, the transmission speed does not decrease significantly.

【0127】

Further, the first signal, the second signal, and the third signal are used as synchronization signals, the decoding circuit detects the synchronization signal based on the multiplication signal, and the information signal is output based on the detected synchronization signal. When decoding is performed, even when a noise signal (pulse) exists before the synchronization signal and the noise signal exists at a time interval between the two synchronization signals with respect to this noise signal. , The synchronization signal can be detected accurately. Further, the synchronization signal can be transmitted with a minimum pulse width of 3 bits and the information signal can be transmitted with a minimum pulse width of, for example, 1 bit, and the transmission speed does not decrease significantly.

【0128】

If the time interval between the first and second signals and the time interval between the second and third signals are different, the time interval between the adjacent synchronization signals from the first synchronization signal Even when there is a noise signal in the previous position, it is possible to accurately detect the synchronization signal.

【0129】

Further, the delay circuit sequentially stores the A / D converter, the digital signal converted by the A / D converter, and the digital signal stored in the digital memory is converted into an analog signal. When a / A converter and a timing generator that delays the digital signal stored in the digital memory for a predetermined time and outputs the signal are provided, the signal is sequentially stored in the digital memory from the A / D converter. At the same time, the signals stored in the digital memory can be sequentially taken out, and a delayed signal having a long delay time can be generated.

【0130】

Further, the communication system according to the present invention receives a transmission device that transmits a serial signal including a synchronization signal and an information signal, and the serial signal transmitted from the transmission device via a transmission medium, and information is transmitted from the serial signal. In a communication system including a receiving device for decoding a signal, the receiving device is the synchronization signal or an information signal and receives a serial signal including the same first signal and a second signal set for a predetermined time. The reception circuit, the delay circuit that generates a delay signal by delaying the reception signal received by the reception circuit by a predetermined time interval between the first and second signals, and the reception signal and the delay signal are multiplied. Since it is provided with a multiplication circuit that generates a multiplication signal and a decoding circuit that decodes the information signal based on the multiplication signal, it is possible to accurately decode the information signal even when there is a noise signal. Moreover, the transmission speed does not decrease significantly.

[Simple explanation of drawings]

[Figure 1]

It is a figure which shows the communication system of Embodiment 1 of this invention.

[Figure 2]

It is a timing chart of Embodiment 1 of this invention.

[Fig. 3]

It is a figure which shows the communication system of Embodiment 2 of this invention.

[Fig. 4]

It is a timing chart of Embodiment 2 of this invention.

[Fig. 5]

It is a figure which shows the delay circuit of Embodiment 3 of this invention.

[Fig. 6]

It is a timing chart used for explaining Embodiment 4 of this invention.

[Fig. 7]

It is a figure which shows the communication system of Embodiment 4 of this invention.

[Fig. 8]

It is a timing chart of Embodiment 4 of this invention.

[Fig. 9]

It is a timing chart used for explaining Embodiment 5 of this invention.

[Fig. 10]

It is a figure which shows the communication system of Embodiment 5 of this invention.

[Fig. 11]

It is a timing chart of Embodiment 5 of this invention.

[Fig. 12]

It is a figure which shows the delay circuit of Embodiment 6 of this invention.

[Fig. 13]

It is a timing chart used for explaining Embodiment 7 of this invention.

[Fig. 14]

It is a figure which shows the communication system of Embodiment 7 of this invention.

[Fig. 15]

It is a timing chart of Embodiment 7 of this invention.

[Fig. 16]

It is a figure which shows the delay circuit of Embodiment 8 of this invention.

[Explanation of symbols]

1 P / S converter 1a flip-flop 2, 2a transmit clock generator 3a ~ 3d, 43a, 43b divider 4 modulator 5 power amplifier 6 Driver 7 Send data 10 sensor 11 preamplifier 12 Detection circuit 13 Band filter 14, 14a ~ 14c Delay circuit 15, 15a, 15b Multiplier 16 Comparator 17a ~ 17c Receive clock generator 18 Comparator 19 S / P converter 19a Flip-flop 20a, 20b Received signal 21, 21a ~ 21c Delay signal 22, 22a, 22b, 22c Multiplied signal 31a ~ 31c Sync signal 32a ~ 32f, 45a, 45b, 81a, 81b Information signal 33a ~ 33c, 34a ~ 34d, 46a, 46b, 47a, 47b, 72a ~ 72d, 82a, 82b Noise signal 53 A / D converter 54, 54a, 54b digital memory 55 D / A converter 56, 56a, 56b, 58, 58a, 58b switches 57, 57a, 57b Storage address pointer 59, 59a, 59b Read address pointer 60, 60a, 60b timing generator