Hierarchical address translation system for a network switch

Description: TECHNICAL FIELD [Detailed description of the invention]

Hierarchical address translation system for network switches Background of the invention Technical field to which the invention belongs The present invention routes data transmissions between stations in a network. In particular, the address of each network station Hierarchical address for mapping to switch ports that serve stations Regarding network switches with translation systems. Description of related technology Computer networks are networks between computers or other types of networks. Transfer data between stations. For example, 10 Base-T Ether Net (10BASE-T Ethernet) system is Star Network Each network using a series of twisted pair leads in the topology The station is connected to the central hub. One of the 10BASE-T hubs Receive a data packet from one station and at the same time send it to all other It is a simple repeater that re-broadcasts to the station. Data packet header -Indicates the specified destination station of the packet and each network station Should check the packet header to accept or ignore input packets? To determine. But to networks interconnected via network hubs For example, transmission from any one station is for all other stations. Block transmission from the computer. Therefore, only one network at a given time Only stations can carry packets. In addition, all networks A lot of traffic is directed to other stations Even if you have to look at all the packets sent out on the network Absent. Unlike network hubs, network switches are specific switch ports. Data packets can only be routed to destination stations connected to Yes, each network station can direct packet traffic to itself Can only receive. Appropriate for network switches from input ports Cross contacts for selectively routing each input packet to an egress port It includes a switching mechanism like a switch. Input port is packet head Determine the destination output port from the routing data contained in the data, and then input Request a connection between the port and the destination output port. Input port when connected Sends the packet to the output port via a cross-contact switch. Packets arriving at the switch port are sent to the net of the station to which they are headed. The work address is included and the switch stays before the packet is sent. Associate the address of the station with the switch output port to which the option is connected I have to do it. Destination station network address and switch port The process of associating with G is uncertain. Ruixue dated May 2, 1995 Representative, as shown in U.S. Pat. No. 5412648 patented to Mr. Fan In a typical prior art system, each input port stores an input packet and is packetized. Extract the destination address from the header of the address and translate it into the central address I'm sending it to a knit. Associate a network address with a switch output port The address translation unit holding the reference table identifies the output port (I). Returns D) to the input port. And the input port is the designated output port via the switch. Requests a connection to the port and sends the packet to the output port. Each input port is in the center You must compete for other input ports to access the address translation unit To get an address translation if packet traffic increases Is too late. What is needed is that the input port is due to a conflict with the central address translation service Minimize latency so you can quickly translate network addresses to port IDs Network switch. Outline of the invention The network switch according to the present invention is connected to the input / output port of the switch. Route data transmission between each uniquely addressed network station To ting. The switch has a station network to receive input transmissions. Associate the network address with the switch port to which the station is connected Includes a hierarchical address translation system for The translation system is used for each network. Has memory to store mapping entries for the station Includes a central translation unit, but the entry contains the station's network address Map to that switch port. The system is also in each input port Contains a local translation unit. Each local translation unit is a central translation uni Local for storing a small subset of the mapping entries stored in Includes cache memory. Input where data transmission is directed to a network address When the power port is reached, the input port outputs the network address to the output port. Find the entry that maps to in the cache memory. Cache memory When such an entry is found within, the input port outputs the input data. Transmit to the port. No such entry found in cache memory Sometimes the input port is a copy of the appropriate mapping entry from the central translation unit -Acquired and rated it in cache memory as a new mapping entry In addition, the data is output as identified by the new mapping entry. To transmit to. Network stations are generally the most network stations The next data transmission to the network station that recently transmitted the data So the local translation unit in each input port is the central address translation unit Greatly reduces contention to access, and therefore especially network traffic Improve system throughput while the hook is large. Therefore, an object of the present invention is to minimize the delay of address translation and network. Network switch for expediting the routing of data transmission between stations It is to provide a switch. The final part of this specification specifically points out and explicitly claims the subject matter of the present invention. .. However, those skilled in the art will appreciate the (each) attached drawings in which the same reference code indicates the same element By reading the rest of the specification in succession, you can further understand the structure and operation method of the present invention. Understand the effect and purpose together best. A brief description of the drawing Figure 1 shows serial data packets between up to 24 network stations. The local area network switch of the present invention to route is illustrated. To. Figure 2 shows a typical input port in Figure 1 in a detailed block diagram format. It is shown in the figure. Figure 3 shows the typical output port of Figure 2 in a detailed block diagram format. It is shown in the figure. FIG. 4 is a situation diagram showing the operation of the output port controller of FIG. FIG. 5 illustrates the hierarchical address translation system of the present invention in block diagram format. Shown. Figure 6 shows the local address translation of Figure 1 in a detailed block diagram format. A typical address cache unit of the translation unit is shown in the figure. 7 to 10 are flowcharts showing the operation of the state machine of FIG. FIG. 11 shows an interrupt routine executed by the central translation unit of FIG. It is a flowchart. Figure 12 shows the block of the arbitration system used in the network switch in Figure 1. It is a diagram. Description of the best (each) embodiment Figure 1 shows data transmission between a series of network stations (not shown). The local area network (LAN) switch 10 of the present invention to be used for It is shown in the figure. Each of the network switches 10 has an input bus RX0-RX. Is it a network station of one or more of the corresponding buses out of 23? Includes a set of input ports RP0-RP23 to receive incoming input packets There is. The network switches 10 also have their own output bus TX0-TX2. One or more data packets to the outside on the corresponding bus of 3 Includes a set of output ports TP0-TP23 to send to the network station There is. Each input port RP0-RP23 is on the switch input line V0-V23. Connect to the cross contact switch 12 via the corresponding line, and each output port Switch 1 via the corresponding line of the switch output lines H0-H23 Connect to 2. Switch 12 is via one of the input lines V0-V23 Each data packet arriving from the input port is sent to the switch output line H0-H23. Route to the appropriate output port through one of them. Packet routing One of the input ports RP0 via one of the input buses RX0-RX23 -Data packets arriving at RP23 are sent to the destination network to receive the packet. Contains the network address of the network station. Input port RP0 -When a packet arrives at one of the RP23s, the input port is the packet And read the destination address from the packet. Hierarchical address translation below By using the system, the input port will be the destination address, the destination station Is converted to the identification (ID) of the output port TP0-TP23 that serves. Input port To request a connection to an output port via switch 12, the output port Send the ID to the arbitration controller 22 via the bus (GLOBAL). arbitration Controller 22 also communicates with the output port via the GLOBAL bus. , Each output port is idle, i.e. any other input via switch 12. Determines when no data packet is currently being received from the port. When the requested output port becomes idle, the arbitration controller 22 Establish a connection through the requested switch 12 and connect to the requested input port. Confidence that packets may begin to be transmitted to the output port via switch 12. Send the issue. When the egress port receives a data packet, the egress port accepts it Stored in buffer memory, and then the packet is sent to the output bus TX0-TX23. Send to the destination network station via one of them. Cross contact switch Each of the cross contact switches 12 has input ports RP0-RP23. A set of 24 "vertical" input lines (leads) connected to the corresponding input ports ) V0-V23 and the corresponding output of each output port TP0-TP23 Includes a set of 24 "horizontal" output lines H0-H23 connected to the force port I'm sorry. Each of the arrays of CMOS pass transistors 20 is a horizontal line So connected to one of H0-H23 and one of the vertical lines V0-V23 It has a boot terminal and a drain terminal. Random access memory (R AM) 14 stores 24 24-bit words and separate control signal CO NT is supplied to the gate of each transistor 20. CONT signal is asserted When the pass transistor 20 is turned on, thereby the vertical line V0- The signal transduction path between one of V23 and one of the horizontal lines H0-H23 Establish. Each supplied to transistor 20 in row J of transistor 20 The state of the CONT signal is the pair of the Jth data word stored in RAM14. Determined by the corresponding bit. The arbitration controller 22 is installed in RAM14. Accept connection requests from input port RP0-RP23 by writing data Therefore, the signal of the routing passage through the switch 12 is thereby transmitted. Disconnect. Input port Figure 2 shows the input port RP0 in Figure 2 from the detailed block diagram format. Shown. The same applies to the input ports RP0-RP23. Network station Data packets are processed using the Ethernet 10BASE-T protocol. It is transmitted to the input port RP0 in serial format via the bus RX0. Stan As a Dard Ethernet protocol data unit The formatted data packets are variable length and have the feels listed in Table 1. Contains.<img file="JP2000508136A_D0001.tif" /> Preamble field and START fi A field is a fixed data pattern that is the same for all packets. .. The Destination (DEST) field is for receiving packets or for netting. Shows the network address of the station to show the network address To. The SOURCE field is for the station that transmitted the packet. Indicates the network address. TYPE / LEN The field is the type of packet or data (according to the protocol adopted). DATA) Can indicate the length of the field. DATA field is a package Holds payload data and extends from 46 bytes to 1500 bytes in length can do. Cyclic Redundancy Check (CRC) field is on the receiving station Therefore, a frame check that determines whether or not the packet used is invalid during transmission. Cookfield. A typical 10BASE-T network interface circuit in relation to Figure 2. 30 receives an input packet arriving on the input bus RX0. Transport on the bus The carrier signal is signaled to indicate the start and end of packet transmission. Each of the data packets When the bits arrive, the network interface circuit 30 will be 4 bits. Serial-in-parallel-out Shift register 31 stores bit signals Therefore, the LOAD signal is pulsed. First following the preamble of data packets "Nibble" (half byte) is loaded into register 31 At that time, the interface circuit 30 frustrates the shift-in (SI) signal. Assert to to-in / first-out (FIFO) buffer 32 to make the FIF Store nibbles in the O buffer. Interface circuit 30 continues , Stores each series of data packet nibbles in buffer 32. The longest nibble stored in FIFO buffer 32 is the pre-data packet Network interface times when it is the first nibble following the amble Road 30 sends a START signal to the buffer controller 34. Buffer control The troller 34 is a data packet in random access memory (RAM) 36. Controls the memory of. When the START signal is received, the buffer controller 34 begins to pulse the shift-out signal (SO), and each pulse, The FIFO buffer 32 has a 4-bit data data via the 4-bit data bus 61. Try to shift out the bull to RAM36. Buffer controller 34 Controlled by the address signal and read / write control signal generated by RAM36 stores packet data nibbles at sequential addresses .. The network interface circuit 30 is loaded into the FIFO buffer 32. Count each packet nibble and how much controller 34 Buffer control to determine if the nibble was stored in RAM36 Count the pulses of the SO signal produced by the cooler 34. Interf Ace circuit 30 shifts the last nibble of the packet to FIFO buffer 32. After that, it continues that buffer controller 34 shifts from buffer 32 It counts the number of nibbles you have tossed and it gets the last nibble of the packet It sends an END signal to controller 34 to convey what it has done. buffer The controller 34 also has the input packet data stored in the RAM 36. Count the nibbles of the data when you are. Network interface 3 After receiving the END signal from 0, controller 34 cows in RAM 36 The number of data is stored as the LENGTH field in the header part of the packet. Pa When the packet is subsequently sent to the output buffer, the output buffer will be LENGTH. Determine the packet length from the field. Buffer controller 34 when packet data is loaded into RAM36 From the count of nibbles, the source field and destination fee of the data packet When Ludo (SOURCE, DEST) appears in FIFO buffer 32 judge. At that point, the buffer controller 34 translates the local address. Translated so that unit 44 acquires SOURCE and DEST data (T RANS) Generates a signal pulse. Local translation Yu Knit 44 has a DEST field that identifies the destination station of the packet. Convert to the port ID of the output port to which the destination station is connected. Translation Uni After that, the terminal 44 sets the ID (PORT_ID) of the destination output port to the FIFO back. Output to fa 45. Translation unit 44 uses the input SOURCE field Update the entry and the network identified by the SOURCE field Map the address to output port TP0. The longest stored PORT_ID in FIFO buffer 45 is the arbitration unit. Supplied to 46. The FIFO buffer 45 is empty. In the i-state, the EMPTY signal is supplied to the request transmission state machine 50, Reassert the EMPTY signal when the port ID is stored. Stay Tomachine 50 goes out from input port RP0 on conductor V0 to switch 12 in Figure 1. Control the data flow to the department. State machine 50 is FIFO buffer 45 Detects that is empty and port TP0 is currently through line V0 When not sending packets, the state machine 50 is in arbitration unit 46. The request signal REQ supplied to is pulsed. The arbitration unit 46 is then F Get the longest stored PORT_ID output from IFO buffer 45. After Later, the arbitration controller 22 (Fig. 1) enters the input port R via the GLOBAL bus. Whether P0 is polled and input port TP0 has an ongoing connection request When determining whether, the controller 22 is PORT_ from the arbitration unit 46. Get an ID. Then, when the controller 22 approves the request, the key is adjusted. Notify the stop unit circuit 46 (Fig. 2) and send GRANT to the state machine 50. Supply the issue. And the state machine 50 is the buffer controller 34. The other packets supplied to the controller 34 and stored in the RAM 36 are sent to the controller 34. NEXT_PAC telling you that you can start sending to the outside via the 0 line Pulse the KET signal. To send out packets from RAM36, the buffer controller 34 First, switch the multiplexer 60 and use the hard-wired 5-bit code "J". Receives and outputs the "J" code of the multiplexer 60 to the FIFO buffer 6 Shift to 2. Then, the controller 34 switches the multiplexer 60. Select the hard-wired "K" code and select the "K" code of the multiplexer 60. Shift the output to the FIFO buffer 62. (JK, as explained below The code sequence indicates the start of transmission of a data packet on output line V0. To. ) After that, the controller 34 switches the multiplexer 60 to encode. Select the 5-bit data output of the adapter circuit 58, but the encoder circuit 58 , The 4-bit data that appears on the data input / output bus 61 of RAM36 (described below) ) Convert to 5-bit "4B5B" encoder format. And the control Ra 34 continuously reads 4-bit nibbles of data packets from RAM 36. To start. Encoder 58 nibbles in 5-bit 4B5B encoding format When converted to, the multiplexer 60 passes the 5-bit result into the FIFO buffer. Let me. In the controller 34, the FIFO buffer 62 inputs a 5-bit data value. Strobe the shift to the (SI) signal. FIFO bar The iffa 62 informs the controller 34 when the buffer is full. Generates a FULL signal. The longest nibble stored in FIFO buffer 62 It is sent to the shift register 56. FIFO buffer 62 is not empty When state machine 50 shifts register 56 from buffer 65 to 5 Shift to a bit value and switch it to switch 2 in Figure 1 input line V Inform to shift out in serial format on 0. Switch 12 is day Route the data to the appropriate output port. Buffer controller 34 packs from RAM 36 to FIFO buffer 62 When sending data, it counts the nibbles sent and packs that count. Compare with the known length of the packet stored in the header. Of the packet After the last nibble was sent through encoder 58 to FIFO buffer 62 Controller 34 switches multiplexer 60 to FIFO buffer Select 62 and put a 5-bit hardwired "T" code in FIFO buffer 62 To send. This "T" code indicates the end of the packet, but the "T" code Passes through the FIFO buffer 62, shifts register 56, and packs data. At the end of the line, go out on line V0. The last of the packet nibbles When a bit exits the FIFO buffer 62, the buffer 62 is Notify state machine 50 that it is in an empty state. And state Machine 50 is otherwise available if FIFO buffer 45 is not empty Another GRANTED message that initiates a connection request and indicates that the next connection request has been established Wait for the pulse. And it is the next packet stored in RAM36 By NEXT_PACKET signal pulse indicating that it can be sent Informed by trawler 34. 4B5B encoding The data packet is encoded before it is transmitted to output line V0 and the output port Allows data to determine when a data packet begins and ends To do. ANSI Standard X379 (FDDI) "4B5B" Encoding System According to Mu, the encoder 54 has 5 each 4-bit nibble as shown in Table 2. Convert to the output value of a bit.<img file="JP2000508136A_D0002.tif" /> To represent the 16 possible values of a 4-bit nibble, a 5-bit 4B5B Only 16 of the 32 possible combinations of the card are needed, so The remaining 16 combinations of 4B5B codes are available for other purposes To. Table 3 below shows how the network switches of the present invention are the remaining 16 pieces. It is a chart showing whether you are using the 4B5B code of.<img file="JP2000508136A_D0003.tif" /> Q, H, R, S codes, they are present in a 4B5B encoded data stream If it is, it will be ignored. The T code is the end of the 4B5B encoded data packet It shows the end. I, J, K, V code can be 4B5B enco by the method described below. Used to synchronize the transmission and reception of data streams. Output port Figure 3 shows the output port TP0 of Figure 1 in a more detailed block diagram format. It is shown. The same applies to output ports TP1-TP23. Output port TP 0 is the system for receiving and storing the data bits that have reached the H0 line. 10-bit serial in-paralet clocked by the clock signal CLK It contains a ruout shift register 70. A set of decoders 72 shift The longest stored 5 data bits in register 70 are I or V in Table 2. Or when representing a T code, or 10 bits in shift register 70 Output port controller 7 when all represent J and K codes in succession Send a signal to 3. 4B5B decoder 74 has the longest stored 5 bits Converts the value to the corresponding 4-bit nibble and passes it to the input of FIFO buffer 76 Su. FIG. 4 illustrates the synchronization method performed by the input controller 73 of FIG. It is a situation diagram. Input controller 73 starts from "asynchronous" state 81 To do. In the controller 73, the decoder 72 detects an I (idle) signal. Until then, it remains in state 81. At that point, controller 73 is "pre-synced" Move to state 82. J and K symbols (data package) with consecutive decoders 72 When the detection signal of) is sent, the controller 74 Waits for 10 cycles of CLK signal and then shift register 70 for J and K Clear the umbrella and then make the SI signal the 5th pulse of the system clock signal Assert each time to load each nibble of the input packet into FIFO buffer 76 Switch to SYNC state 84. Decoder 72 marks the end of the packet When the T code is detected, the controller 73 shifts to the state 83 and adjusts. Pulse the IDLE signal supplied to the stop unit 75 and return to state 84 To. When the decoder 72 detects the V code, the controller 73 is not the same It returns to the period state 81. Again in connection with Figure 3, the belief that FIFO buffer 76 is not empty. When sending an issue, controller 73 sends data from FIFO buffer 76. Random access memory (RAM) 78 shifts to 4-bit data I / O bus To do. Then, the controller 73 addresses and controls the RAM 78. A signal is sent so that the RAM 78 stores a 4-bit nibble. Control The ruler 73 can transmit the received data packet to the destination station to the outside. FI for continuously collecting and storing the received data packets until RAM78 is used as the FO buffer. In controller 73, the packet is R When arriving at AM78, the LENGTH field in the packet header Read to determine the length of the packet and the packet received and stored in RAM78 Count bytes to determine when packets are completely collected in RAM78 .. When the packet is fully loaded into RAM 78, controller 73 , Sends a signal to the network interface controller 90. Controller 90 is a data controller on bus TX0 to an external destination station. Controls the transmission of the ket. Controller 90 is stored in RAM78 Switch the multiplexer 92 to the pattern when you are ready to send the packet Select the output of the generator 94 and notify the generator 94 Semi-Ethernet protocol PREAMBLE and STA Generates a series of 4-bit nibbles that form the RT data packet field. Ma Luciplexa 92 is a parallel insulator controlled by controller 90. Pass each nibble to the real-out shift register 96. The shift register 96 Data in serial format on a regular Ethernet interface Passed to the ace circuit 98, which passes the data on the TX0 bus to an external destination network. Send to the station. PREAMBLE and START fields Controller 90 is in control after it has been sent through the multiplexer 92 Signals 73 and sequentials 4-bit data from RAM 78 Start reading and multi-use them for transmission to the destination station It is sent to the interface circuit 98 through the Puexa 92 and the shift register 96. To. When the controller 73 reads the last nibble of the packet, the The controller sends a signal to controller 90. The arbitration unit 75 is the arbitration controller shown in FIG. 1 via the GLOBAL bus. I'm contacting 22. In the arbitration unit 75, the decoder 72 receives the end of the packet. Receives an IDLE signal pulse when it detects a "T" code that indicates that it has been trusted. .. As described in detail below, the arbitration unit 75 is the arbitration controller of FIG. When polled late by -22, it is the arbitration controller. -In addition, output port TP0 is idle and is no longer on line H0. Pa Sends a signal that the ket has not been received. Hierarchical address translation system In connection with Figure 5, the local translation unit 44 for each input port is 6 bytes. The workstation address is the switchpoint to which the station is connected. One of the hierarchical address translation systems 99 for mapping to a 5-bit ID Form a part. Hierarchical address translation system 99 is provided for each network station. Central translation unit with memory for storing mapping entries for Contains 26, and the entry contains the station's network address. Map to a switch port. The system also has a common bus (MAPP). Local translation unit in each input port connected to the central translation unit via ING) Includes knit 44. Only one address in Figure 3 for simplicity The translation unit 44 is illustrated, but in reality each is each input port in Figure 1. 23 other others connected to the MAPPING bus, depending on RP0-RP23 There is such a translation unit. Each local translation unit 44 is stored in the central translation unit 26. Local cache memory for storing a small subset of ping entries ( Contains 101 (consisting of a set of cache units 100) .. When the destination address of the input packet is supplied to the translation unit 44, it Has a cache memory entry that maps the destination address to the output port look for. When such an entry is found in the cache memory, the localr The translation unit 44 is directed to the FIFO buffer 45 in FIG. Place the output port ID on the inn and send a pulse to the output SI line to port Shift the data ID to the FIFO buffer. Translation unit 44 is the input destination ad If you cannot find the entry that maps the reply in the cache memory, Appropriate mapping entry from central translation unit 26 via GLOBAL bus Acquire a copy of, and map the copy into the cache memory 101. Store as an entry. The new mapping entry has not been used most recently Replaces existing entries. And the local translation unit 44 is shown in Figure 2. Place the output port ID on the PORT_ID line towards FIFO buffer 45 At the same time, send a pulse to the output SI line to set the port ID to the FIFO buff. Shift to Network stations generally have the next data transmission, which is the most recent data Is sent to one of the network stations that transmitted the message, so it is local. Translation unit 44 often has the appropriate mat in its local cache unit. Find the ping entry and get the mapping data from the central translation unit There is not much need to gain. Hierarchical address translation unit system of the present invention Significantly reduced contention for accessing central address translation unit 26, Therefore, system through, especially during heavy network traffic Improve put. Create mapping entry The input and output ports that serve the same network station are the same Has an ID. As mentioned above, each input data packet is also said packet. SOURCE field that carries the network address of the station that sends Includes. Translation unit 44 receives the most recently received SOURCE address. Use some cache memory space to store. Cache memo When a current input SOURCE address is received in Lee, translation unit 4 4 replaces the least used entry with the input SOURCE address .. Translation unit 44 also has a new SOURCE address and its own input port. Central address translation unit via the MAPPING bus Send to To 26. The central address translation unit 26 adds the SOURCE address. Create a mapping entry associated with the attached port ID. Then the switch A new mapping en of all input packets destined for the network address Route to the output port identified by the bird. For example, a new net The workstation connects to the network and changes its network address When it does, it sends the packet to establish its own mapping entry. Send to yourself. Input SOURCE add currently stored in cache memory Re When the translation unit 44 receives the message, the translation unit 44 sends a SOUR to the central translation unit 26. Do not send CE address. Because SOU in local cache memory Central translation unit 26 already maps that the RCE address exists This is because it indicates that the entry has been created. One or more network stays It should be noted that an option can be served by a given pair of I / O ports. I'm sorry. Therefore, the local cache memory in each local translation unit 44 -Can contain one or more SOURCE address entries. Local address translation unit The cache memory 101 of the local address translation unit 44 in FIG. 2 is 6 Contains a set of four cache units 100 (0) -100 (63). each The cache unit 100 is one machine containing the data listed in Table 4 below. Has a ping entry.<img file="JP2000508136A_D0004.tif" /> The ADDRESS field is a 6-byte SOU for network stations. RCE address or DEST address. Entry is valid for V bit Indicates whether or not. At system startup, the V bit of each entry is logically " Set to "0" to indicate that the entry is invalid. Valid data cache When loaded into the unit, its V bit is set to "1". S / D Bit creates a source address or destination network address for the entry Indicates whether or not it was done. The cache unit is in the ADDRESS field When including a dress, the 5-bit port field is ADDRESS The ID of the output port to which the station identified by the field is connected Includes. In the PORT field, the cache unit is ADDRESS Not used when the source is stored in the field. First, all cache units 100 are input SOURCE or DEST Does not contain a valid source or destination ADDRESS entry to match the address Imagine that. TRANS signal from controller 34 in Figure 2. Ruth sets the SOURCE and DEST addresses of the input packet in unit 44. Load into FIFO buffer 102. FIFO buffer 102 is a statema Signals scene 104 to contain SOURCE and DEST addresses .. The state machine 104 sends a signal to the multiplexer 106 by In response, output the SOURCE address to each cache unit 100. Ste The machine 104 also sends a T1 signal pulse to each cache unit 100. send. Each cache unit with a valid source entry when responding to a T1 signal pulse Knit 100 has the input SOURCE address in its stored ADDRESS Compare with the field. Cache unit 100 storing the source address Allows matching between the input SOURCE address and its stored source address If so, the cache unit immediately responds to the state machine 104. Assert (pull down) the HIT line input. HIT line pulse Central translation unit 26 already on port machine 104 source address on port ID Inform that you have mapped. In this case, all cache units 100 stores a valid source address that matches the input SOURCE address Unit 100 does not send a pulse to the HIT line because it is not. Stays that did not detect HIT line pulses when responding to output T1 signal pulses The tomachine 104 FIs the SOURCE address output of the multiplexer 106. Pulse the INT signal loaded into FO buffer 108. FIFO buffer 108 also has the ID of the input port (PORT) and the FIFO buffer 108. State machine 10 indicating that the addressed address is the source address Stores S / D bits from 4. FIFO back when not empty The fa 108 sends a signal to the bus interface circuit 110 to map the interrupt. Send to central translation unit 26 via PING bus. Then the central translation unit 26 reads data from FIFO buffer 108 and shifts out S Create a mapping entry for the OURCE address and port ID. FIFO buffer for SOURCE data to be sent to central translation unit 26 After loading on 108, the state machine 104 says "Token passing service". Start "Icle" and input S in the least used cache unit 100 Create a new entry for the OURCE field. Each gash unit To 100 counts the number of received T1 signal pulses, which is applied to the HIT line. Resets its own count whenever it sends a ruth. Therefore, the most The cache unit 100, which has a high count, is "most recently used. Not a "cache unit". Cache unit 100 and state machine The 104 are connected to form a token passing ring, where they are stationed. The machine 104 uses the TOKEN signal pulse as the first cache unit 100. TOKE sent to (0) and received by the Nth cache unit 100 (N) Pass the N signal pulse through the cache unit N + 1 (pass the token), and finally Cache unit 100 (63) passes the token and is a state machine Return to 104. Each cache unit 100 (N) also has the following cache unit: The next cash unit via a set of CNT lines that carry counts to the knit It is connected to (N + 1). Each cache unit 100 (N) has a unique I Has D and transports the cache unit ID to the next cache unit Connected to the next cache unit (N + 1) by another set of CID lines There is. After storing the SOURCE address in FIFO buffer 108, the statema Scene 104 is a first capture of the token (pulsed the output TOKEN signal). Pass it through the wash unit 100 (0). First cache unit 100 ( When 0) receives a token from state machine 104, it is its coun. The number and ID number are transmitted to the second cache unit 100 (1), and then Pass the token through the second cache unit 100 (1). Second ca Shu unit 100 (1) toe from first cache unit 100 (0) When it receives a kun, it counts itself as the first cache uni Compare with the number of input counts from t100 (0). Second cache unit If the count of is less than the count of the first cache unit, then the second Cache unit talks about the count number and ID of the first cache unit And send it to the third cache unit 100 (3). On the other hand, the second cashier The count of units is greater than the count of the first cache unit Or if they are the same, the second cache unit is with its own count Send the ID along with the token to the third cache unit 100 (3). Subsequent cache unit 100 (N) behaves in the same way, but precedes it. The number of counts received from the unit 100 (N-1) is the number of its own counts. When greater than, along with the count and ID received from the preceding unit Pass the token to the next unit (N + 1), and then the preceding unit 100 The count received from (N-1) is less than its own count When they are the same, the token is next united with its own count and ID. Pass through (N + 1). The last cache unit 100 (63) is the most Large counts (ie, most recently unused mapping entries Output the ID of the cache unit with (including) to the decoder 112 and talk And return to the state machine 104. The decoder 112 has 64 outputs L0-L63, each of which is a bird. Cache unit 1 via state buffer 114 It is linked to the corresponding one of 00 (0) -100 (63). decoder -112 is the cache ID (CID) output of cache unit 100 (63) Of the outputs L0-L63 corresponding to the cache unit identified by force Assert one of. The state machine 104 immediately occupies buffer 114. Responds to the return of the token by setting it to, but one of the buffers , Thereby cache unit 10 containing the least used entries Outputs the pulse of the L0-L63 signal to 0. L0-L63 pulse is received Inform the hash unit 100 and let the current ADDRESS field be known. Ru Replaced with the current SOURCE address output of Chiplexa 106 and its V fee Set the led to indicate that the entry is valid, and its S / D fee Set the led to indicate that the entry is the source address. The new SOURCE entry is thus out of cache unit 100 If you replace one of the most recently unused entries, sequence The sir 106 switches the multiplexer 106 to the FIFO buffer 102. Pass the delivered DEST field through cache unit 100, and Pulse the T2 signal supplied to all cache units to the destination address Start the translation cycle. Destination address field that matches the DEST address The cache unit 100 that stores the pulse sends a pulse to the HIT line. This place In any case, a valid destination address that matches the input DEST address Since the unit 100 is not included, the cache unit 100 is a HIT lie. Do not send a pulse to the computer. The state machine 104 responds to its T2 signal pulse. Then, the HIT line is detected, but in the machine, the cache unit 100 is D. Know that you can't translate the EST field. At that point, state machine 1 04 again pulsed the INT line signal, this time the FIFO buffer 108 However, the input port ID and the sequence indicating that the destination address translation is requested. Multiplexer 10 in FIFO buffer with S / D bits from sir 104 Store the DEST address output of 6. State machine 104 , Also, counter 1 that constantly records the number of ongoing DEST address translations Send a pulse to 17. The pulse increments its count by 1 on counter 117 Tell them to do it. State machine 104 DES to central translation unit 26 I sent the T address, but this time I sent the shift out pulse to the FIFO buffer 102 To signal the FIFO buffer 102 to the next stored SOURCE / DE The ST address pair, if any, is supplied to the multiplexer 60. afterwards, The state machine 104 starts a new address translation unit cycle. State machine 10 when FIFO buffer 102 is empty 4 new to FIFO buffer 102 before the start of other address translation cycles We are waiting for the data to arrive. The central translation unit 26 then reads the data from the FIFO buffer 108. When you do, translate the DEST field to the corresponding output port ID, and , DEST field and S / D bit and output port via MAPPING bus The ID is sent back to the bus interface circuit 110. Interface circuit 11 0 stores the returned data in another FIFO buffer 116. FIFO bar The iffa 116 then went to the state machine 104 and it was empty. Send a signal of cousin. The state machine 104 is the first cache unit 10 Respond by passing the token through 0 (0) again. After that, Cash Uni The T100 works as described above and is the most recently unused mappin. A cache unit that identifies the cache unit 100 that contains the entry Output the ID to the decoder 112. Token returns to state machine 104 The state machine 104 then temporarily turns on buffer 114 again. Send a pulse to one of the lines L0-L63. This is most recently used The cache unit 100 contains unused mapping entries. Replace it with the mapping data stored in FIFO buffer 116 Will be. This cache unit also uses the newly stored output port ID. Pull down the HIT line through the PORT_ID line. After that, The machine 104 sends a pulse to the SI line and the FIFO buffer 4 in FIG. Shift PORT_ID to 5 and send SO signal to FIFO buffer 116 to F Shifts traditional mapping data from IFO buffer 116 and further counters -Sends a signal to 117 to decrement the ongoing DEST address translation count by one .. Here, one cache unit 100 is already the SOU of the input packet. Contains an entry to store the ADDRESS field that matches the RCE address And the other cache unit 100 has a DEST address on the output port It is assumed that it already contains a valid entry to map the space. TR In response to the ANS pulse, the state machine 104 sends each T1 pulse. Send to Shunit 100. Input SOUR when responding to T1 signal pulses The specific key that currently stores the ADDRESS field that matches the CE address The hash unit 100 immediately sends a pulse to the HIT line. HIT line The pulse is already cached in the state machine 104 with the SOURCE address By one of the 100 units (and by the central translation unit 26) ) Mapped and no further action on the input SOURCE address Notify that it is not required. Then, the state machine 104 switches the multiplexer 106 to D. Send EST address input to all cache units 100 and T2 communication Send the No. pulse to all cache units 100. Enter the DEST address Cache unit 1 containing valid ADDRESS fields to match 00 places its stored PORT field on the PORT_ID line , And send a pulse to the HIT line. State machine 104 is ongoing Of counter 117 asserted when the number of address translations is greater than 0 Respond to HIT line pulses by checking the output signal. Translation unit 44 is PO in the same order in which the corresponding DEST address appears. An output port ID must be generated on the RT_ID line. Therefore, The machine 104 responds to the current input DEST field with all One of 100 cache units until the ongoing DEST translation is processed Port ID provided by and the result sent to FIFO buffer 45 in Figure 2. Delay the sending of the port ID that occurs as. The output signal of counter 117 , Statema, if it indicates that there is no ongoing DEST address translation Scene 104 sends a pulse to the SI line to see the current status on the PORT_ID line. HIT signal by shifting the port ID to FIFO buffer 45 in Figure 2. Respond to. Then it's a traditional SOURC from FIFO buffer 102 Shift E / DEST data and other SOURCEs in FIFO buffer 102 / Wait for the DEST address to arrive. However, the output signal of counter 117 has ongoing DEST address translation. If it indicates that, the state machine 104 is a cache unit. 100 places the destination port ID on the PORT_ID line and pals the HIT signal Do not send a pulse to SI even after conversion. Instead, state machine 10 4 stops the T2 signal output and the ongoing DEST address translation is FIFO A mapping entry is placed in cache memory when the iffer 116 is reached. To store and send the arriving destination port ID to the outside on the PORT_ID line Therefore, the translation process is continued. The output signal of counter 117 is D Multiplexer if it indicates that all EST address translations have been processed By letting the cache unit 100 pass the DEST address , The state machine 104 again pulses the T2 signal. Cache unit When 100 is still mapping the DEST address to the port ID, It places the port ID on the PORT_ID line and asserts the HIT signal. The state machine 104 sends a pulse to the SI line on the PORT_ID line. Shift the port ID of to FIFO buffer 45 in Figure 2 to FIFO buffer 10. Shift the last processed SOURCE and DEST addresses from 6 and then If the FIFO buffer 106 is not in the empty state, a new translation process is started. Respond by doing. Cache unit 100 is no longer input DEST If the dress is not mapped to a port ID, the HIT line asserts Instead, the state machine 104 has a DEST address similar to the one above. Send to Central Translation Unit 26 by law. locking A system that accesses the central translation unit 26 via I / O port 129. Neger orders central translation unit 26 to match each cache unit 100 You may write the ping entry directly. System manager Also, request the central translation unit to write the data to lock register 120 You can also do it. The decoder 122 captures the data in the lock register 120. Decode to generate a separate LOCK signal for each cache unit 100 To do. The LOCK signal is sent to the cache unit 100 that receives the cache unit. Even if it can store entries that haven't been used most recently Inform that the translated data that has been made should not be replaced. Therefore, LOCK signal input to swoosh unit 100 asserts during token pass cycle When the cache unit is counted, the cache unit itself has a large count. Even if there is, the count and ID of the preceding cache unit rather than itself To pass through. Therefore, the system manager should have one or more cashiers. Translation data can be written into the unit, and their caches Lock the data to the unit and then it has been used most recently Even if there is no translated data, it will not be replaced. Central translation unit The central translation unit 26 is a random access device that stores mapping entries. To execute the program instructions stored in Molly 124 and ROM 128 Input for data from microprocessor 126 and system manager A regular microcomputer with 129 I / O ports to provide the path -Adopts texture. Run by microprocessor 126 The main program routine is simply data from the system manager To lock register 120 or by the system manager The register in the cache unit 100 at the register address supplied by Write to the ter. The microprocessor 126 has the interrupts described below. Use tin to manage address translations and mapping entry updates. Cache unit Figure 6 shows a more detailed block diagram of the cache unit 100 (1) in Figure 5. It is illustrated in gram format. The same is true for the other cache units 100 .. Cache unit 100 (1) is for storing mapping entries. Contains register 130. The normal interface circuit 132 is It is in contact with the interface circuit 110 (Fig. 5) and is a bus interface circuit. Allows you to write directly to access register 130. Register in The surface circuit 132 also returns DES from the FIFO buffer 116. Receives the T address and port ID, and the S / D bit is the destination address mapping en Buffer 11 when sent to indicate that the bird should be saved Store them in register 130 in response to the LOAD_1 signal from 4 (Figure 5) Su To. The register interface circuit 132 also includes a multiplexer 106 ( Is it the state machine 104 (Fig. 5) that receives the SOURCE address from Fig. 5)? These S / D signals indicate that the SOURCE address should be saved In response to the pulse of the LOAD_1 signal when Store. At system startup, the interface circuit is in register 130. Set the valid bit V of to the logic "0" to indicate that the entry is not valid. Then, when valid data is loaded into register 130, the interface The circuit 132 sets the V bit to logic "1". Also, interface times Road 132 writes SOURCE or DEST entry to register field When it is, it sets the S / D bit to "0" or "1" and the register is SOU Indicates whether it contains an RCE or DEST address. In the comparator 134, the ADDRESS field in the register 130 is the circle shown in FIG. To the input SOURCE address or input DEST address from Chiplexa 106 Assert the output signal M whenever it matches. M signal and statema T1 and T2 signal pulses from scene 104 (Fig. 5) and V-bi in register 130 All the bits and S / D bits are supplied to the logic circuit 136. Logic circuit 136 , Truth Table 5 generates the output signal IM_HIT.<img file="JP2000508136A_D0005.tif" /> In the above table, "1" indicates that the signal is asserted, and "0" indicates that the signal is asserted. The number indicates that it has not been asserted, and an "X" may indicate that the signal has been asserted. It shows that it does not have to be slaughtered. Signal IM_HIT is logic "1" When you turn on the pair of tristate buffers 138 and 140. Buffer 13 8 places the PORT ID in register 130 on the PORT_ID line. Buffer 140 pulls down (asserts) the HIT line. The cache unit 100 also increments for each pulse of the T1 signal. Includes counter 142 that is and is reset for each pulse of the IM_HIT signal I'm out. Counter 142 is the ADDRESS stored in register 130. Is set to either the input SOURCE field or the DEST field Record the number of times it did not match and generate the output count MY_COUNT. MY_ When COUNT reaches the upper limit of the counter, the counter is also reset. Until then, it remains the upper limit. The comparator 144 precedes MY_COUNT. CNT is MY_COUNT compared to the input count CNT from the shock unit Generates an output signal LRU when it is less than or equal to it. Input TO The KEN signal, the LRU signal, and the LOCK signal (from the decorator 122 in Figure 5) are It becomes an input to another logic circuit 146. The logic circuit 146 is a pair of multiplexers. Generates an output signal PASS that controls 148 and 150. Multiplexer 148 Is the count data from the preceding cache unit on the CNT line, or By selecting one of MY_COUNT from Unter 142, The unto data is supplied to the next cache unit on the CNT line. Multip Is the Lexa 150 an ID from the preceding cache unit on the CID line? By choosing one of its own hardware IDs (MY_ID) And pass the cache unit ID to the next cache unit on the CID line Let me. When logic circuit 146 asserts PASS, multiplexer 1 48 and 150 pass MY_COUNT and MY_ID. Table 6 shows the logical times The logic implemented by road 146 is shown.<img file="JP2000508136A_D0006.tif" /> The LRU logic circuit 146 appropriately delays the pulsing of its output TOKEN signal. And the multiplexers 148 and 150 switch according to the change in the state of the PASS signal. You will not pass the token before you have time to spare. Local translation unit state machine logic Figure 7 shows the main routine performed by the state machine 104 in Figure 5. It is a flowchart which showed. In relation to Figures 5 and 7, first, step 160 In, the state machine 104 checks the FIFO buffer 116 and Contains the DEST address mapping data that it returned from central translation unit 26 Check if it is. Destination mapping returned by FIFO buffer 116 If it contains data, the state machine 104 has FIFO buffer 1. Write the destination data from 16 to one of the cache units 100, P Address translation by sending a return port ID on the ORT_ID line Update the cache (step 162). (Step 162 is detailed below ing. ) State machine 104 has a FIFO back in step 160. Steps 160 and 162 until Fa 116 is found to be empty repeat. Then check the FIFO buffer 102 and it's a new translation Determine if it contains translation data (step 164). When not included The state machine 104 returns to step 160. FIFO buffer 10 If 2 is not in the empty state, the state machine 104 will be in the FIFO buffer. Process the new SOURCE address within 102 (step 166) and then Process the new DEST address in FIFO buffer 102 (step 16) 8). (Steps 166 and 168 are detailed below.) New SOURC State machine 102 after processing the E-address and the new DEST address Transmits the NEXT signal to the FIFO buffer 102 and the last processed SOUR Shift out the CE and DEST addresses (step 170) and then Return to step 160. Figure 8 shows the FIFO buffer 116 fed back by the central address translation unit. State machine 104 detects that it stores the destination mapping data When you do, the return destination (RETURN DE) performed in step 162 of Figure 7. ST) Subroutine is illustrated. State machine in relation to Figures 5 and 8 104 first passes the token through cache unit 100 (0) Set (step 172), and cache unit 100 (63) is a token Wait until it returns (step 174). Then buffer a new signal pulse The destination address translation data in the FIFO buffer 116 is transmitted to 114 most. Write to cache unit 100 that has not been used recently (step 17) 6). The cache unit 100 that receives the data is on the PORT_ID line. Place the port ID in. The state machine 104 pulses the SI signal. , Write the port ID to buffer 45 in Figure 2 (step 178). And Tate Machine 104 should decrement its counts one by one. Along with sending a signal pulse to the counter 117 that informs (step 180), Notify that the last processed destination address translation data will be shifted out Sends a signal pulse to the FIFO buffer 116. And the subroutine is called Return to the original routine. Figure 9 shows the new call in step 166 of the main subsystem in Figure 7. The NEW SOURCE subsystem is illustrated. In Figure 5 and Figure 9 Relatedly, the state machine 104 first sets the S / D bit to "0". The multiplexer 106 determines the current SOURCE of the FIFO buffer 102. Make sure to select the dress output (step 182) and assert the T1 signal (Step 184). One of the cache units 100 is the input SO When it contains an entry that matches the URCE address, it is a HIT lie. Is asserted. State machine 104 detects HIT line assertion At (step 186), the subsystem ends. But the cache If the unit does not contain an entry that matches the SOURCE address The state machine pulses the INT signal (step 188) and the central translation unit FIFO address mapping data to be sent to Knit 26 Send to Puffa 108. And the state machine 190 caches the token. Pass through unit 100 (0) (step 190) and the token is returned Wait until (step 192). At that point, a new (NEW) signal pulse To buffer 114 to store the most recently unused entries Make the cache unit 100 store the new SOURCE address (Step 194). And the routine returns to the main routine. Figure 10 shows the new call in step 168 of the main subsystem in Figure 7. Nana (NEW) DEST Sabrutin is illustrated. Related to Figures 5 and 10 The state machine 104 first sets the S / D bit to "1" and then Multiplexer 106 captures DEST address output of FIFO buffer 102 Make sure to pass through the swoosh unit 100 (step 200). And Ste The machine 104 pulses the T2 signal (step 202) and hits the lie. Check (step 204). All cache units are HIT If the in is not asserted, the state machine 104 will be counter 11 Signal 7 and increment its count one by one (step 206), INT signal The number should be pulsed and sent to FIFO buffer 108 to central translation unit 26. Load the DEST address translation data. And the subroutine is the main Return to the routine. However, one of the cache units is step 204 If the HIT line is asserted in, the state machine 104 counts. Check the output of Tar 117 (step 210). And state machine FI confirms that the central translation unit has returned the destination address translation data. Wait for FO buffer 116 to indicate (step 212). At that point The machine 104 performs the RETURN DEST subbrutin in Figure 8. And the translation data output of FIFO buffer 116 has not been used most recently Write to cache unit 100 (step 214). State machine 1 04 writes all ongoing destination address translations to cache unit 100 The count maintained by counter 117, which indicates that it has been entered, becomes zero. Repeat steps 210, 212 and 214 until you reach the end. At that point, Statema Scene 104 pulses the T2 signal (step 216) and reactivates the HIT line. Check (step 218). One of the cache units is multi It still contains an entry that matches the input DEST address from Plexa 106 If so, the cache unit places the port ID on the PORT_ID line. And assert the HIT line. Asserting the HIT line is a stay The SI signal is pulsed to the tomachine 104 and the port ID is set to the buffer 45 in Fig. 2. Inform them to shift (step 220). Pre-filled DEST address The cache unit 100 mapping the cache is no longer like that The HIT line is not asserted in step 218. Instead, Tate machine 104 performs DEST feel by performing steps 206 and 208 Is sent to the central translation unit 26. And the subroutine is the main rooty Return to Figure 11 shows one of the local translation units 44 via the GLOBAL bus. Executed by the central address translation unit 26 in FIG. 5 in response to these interrupt signals. It is a flowchart which shows the interrupt routine to be performed. Related to Figures 5 and 11 The central translation unit 26 polls the local translation unit first. (Step 230) and has a FIFO buffer 108 that is not empty The translation unit 44 is placed. Data found in FIFO buffer 108 If not, the central translation unit reads the translation data from the FIFO buffer. Take out and shift (step 232) and check the S / D bits in the data (step 232) Step 234). When the S / D bit is logical "0", then the data is S Carry the OURCE address and the corresponding port ID. In this case, Central Translation Uni T26 adds a mapping entry to its address translation table. 236) Map the source address to the associated port ID. S / D If the bit is logical "1" (step 234), is it the FIFO buffer 108? The data obtained from the above will carry the destination address, and the central translation unit 26 will carry the appropriate data. Find the corresponding output port ID in the pping entry (step 238), and then , Destination address, S / D bit and port ID, from which destination address is obtained Shift to FIFO buffer 116 of local translation unit 44 (step) 240). After that, or, the mapping entry in step 236 is changed. After the new, the interrupt routine returns to step 230 and again the local translation unit Polling for more data on any of the local translation units 44 Determines whether or not it is stored in the FIFO buffer 108. Interrupt Lou Tin continues to read and all FIFO buffers 108 are empty Process such data until it is in a tee state. At that point (step 231) Then, the interrupt routine ends. Mediation system FIG. 12 shows the arbitration controller 22 (FIG. 1) and the input port arbitration unit 46. Detailed block diagram format of (Fig. 2) and output port arbitration unit (Fig. 3) They are all interconnected by the GLOBAL bus. Only one input port arbitration unit 46 and one output port translation unit 75 Although illustrated, in reality, each connected in parallel to the GLOBAL bus There are 24 types. Sequencer 22 is under the control of the firmware stored in ROM252. Microphone that works with and uses RAM254 for temporary data storage Includes Roprocessor 250. Microprocessor 250 and ROM 25 0, RAM254, I / O interface circuit 256 and all I / O ports Are connected by the GLOBAL bus. Sequencer 22 is in RAM254 Holds two tables. One table is the I / O port to be connected Contains ongoing requests from input ports RP0-RP23. other The table shows which output ports TP0-TP23 are currently idle. Shown. The sequencer 22 periodically pours the input port arbitration unit 44. Ring to determine which input port is making a new connection request , Output port arbitration unit 110 is polled and which output port is currently idle Judge whether it is in the state of The input port arbitration unit 46 includes a bus interface circuit 270 and a register. Includes ter 272 and flip-flop 274. State machine 50 (Fig. 2) transmits a REQ signal pulse to the arbitration unit 46 to request a new connection. When signaling that there is, the REQ signal is the ID (POR) of the requested port. Load T_ID) into register 272 to set flip-flop 274 .. After that, when the arbitration controller 22 polls the arbitration unit 46 , It checks the Q output of flip-flop 274 and new demands are ongoing And reset the flip-flop. New point If the request is ongoing, the microprocessor 250 will register 272. Obtain the ID of the output port (PORT_ID) requested from. Microprocess The Sasser 250 then reconfigures the idle output port in RAM254. Check the strike to determine if the requested output port is idle To do. Microprocessor if the requested port is not idle 250 adds that request to the ongoing request table. The requested output port is When idle, the microprocessor 250 has an idle table. Update the file to indicate that the requested output port is no longer idle Both have the requested output to register 28 via interface circuit 256. Send the port ID and the requested input port ID to register 260. The decoder 262 in controller 22 has an output port in register 258. Decode the ID and one of the W0-W23 lines for RAM14 in Figure 1. Assert one. Decoder 264 is the input port ID in register 260 Decodes, asserts one of the bitlines B0-B23, and the rest of the bits Deassert the line. Then the microprocessor 250 is in Sends a signal to the surface circuit 250 and writes light energy to RAM 14 in FIG. Send a pulse to Lurain. RAM14 is asserted W0-W23 bits Storing the B0-B23 dataword in the memory location indicated by, in Figure 1. Cross-contact switch 12 between the requested input port and the requested output port Make a connection or disconnect from the previous connection to the output port. Then my The cross processor 250 is a bus interface on the request input port where the request is allowed. Sends a signal to the ace circuit 270. And the interface circuit 270 is GR Pulse the ANTED signal and send it to the input port state machine 90 (Figure 2) To. Output port arbitration unit 75 flips with bus interface circuit 280 -Includes flop 282. Controller 73 in Figure 3 sends IDLE signal It was ruthened and signaled the end of the unicast packet that reached the H0 line. The IDLE signal pulse sets the flip-flop 282. afterwards, When the arbitration controller 22 polls the output port, it flips- Check the Q output of flop 282 to see if the port is newly idle Then, the flip-flop is reset. Microprocessor -250 receives an indicator that the output port TPO-TP23 is idle When it does, it checks the ongoing request list and the input port is new Determine if you have an ongoing request for an idle output port Determine. If so, register the input port ID and the requested output port ID -By sending to 258 and 260, further input to interface circuit 256 Allow the request by notifying that the WE is pulsed. Yes. The microprocessor 250 then sends a GRANTED message. Send to the requested input port via the global bus. Newly idle Microprocessor in the absence of ongoing requests for output ports that have become 250 samples update idle port list, output port is currently idle Indicates that it is in a state of In this way, all network addresses are switched to switch output ports. Central translation unit for wrapping and relatively when switching each input port A local translation unit that maintains a cache of the few most recently used address translations Local area networks with hierarchical address translation units including knits Itch was listed. Network stations generally carry out the following data transmissions: One of the relatively few network stations that sent the most recent data Since it is sent to, the local address cache of each input port is the central address. Greatly reduces contention for access to translation units. Therefore, the net of the present invention Workswitch is a network station with minimal delay in address translation Route data transmissions between them immediately. The above specification describes the most preferred embodiments of the present invention. The vendor does not depart from the present invention at various angles of the present invention. Many changes can be made. Therefore, the scope of the attached claims is the invention. Intended to protect all such changes within the true and spiritual scope of It is a thing.