Shift register and image display using the same

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a shift register that is suitably used for, for example, a drive circuit of an image display device and can shift an input pulse even when the amplitude of a clock signal is lower than the drive voltage, and an image display device using the shift register. It is a thing.

【0002】

[Conventional technology]

For example, in a data signal line drive circuit or a scanning signal line drive circuit of an image display device, in order to take timing when sampling each data signal from a video signal or to create a scanning signal to be given to each scanning signal line. , Shift registers are widely used.

【0003】

On the other hand, the power consumption of an electronic circuit increases in proportion to the frequency, the load capacity, and the square of the voltage. Therefore, for example, in a circuit connected to an image display device such as a circuit for generating a video signal to an image display device, or in an image display device, the drive voltage tends to be set lower and lower in order to reduce power consumption. is there.

【0004】

For example, in a circuit in which a polycrystalline silicon thin film is used to secure a large display area, such as a pixel, a data signal line drive circuit, or a scanning signal line drive circuit, even between the substrates or within the same substrate. Since the difference in the threshold voltage may reach, for example, several [V], it cannot be said that the reduction of the drive voltage has progressed sufficiently, but for example, as in the video signal generation circuit described above, it is simple. In circuits using crystalline silicon transistors, the drive voltage is often set to a value of, for example, 5 [V], 3.3 [V], or less. Therefore, when a clock signal lower than the drive voltage of the shift register is applied, the shift register is provided with a level shifter for boosting the clock signal.

【0005】

Specifically, for example, as shown in FIG. 39, when a clock signal CK having an amplitude of, for example, about 5 [V] is given to the conventional shift register 101, the level shifter 103 sets the drive voltage of the shift register 101. Boosts the clock signal CK up to (15 [V]). The clock signal CK after boosting is each flip-flop F.₁~ F_nThe shift register unit 102 shifts the start signal SP in synchronization with the clock signal CK.

【0006】

[Problems to be Solved by the Invention]

However, in the conventional shift register 101, after level-shifting the clock signal CK, each flip-flop F₁~ F_nFlip-flop F because it is transmitted to₁~ F_nAs the distance between both ends of the above increases, the transmission distance becomes longer and the power consumption increases.

【0007】

Specifically, as the transmission distance increases, the capacity of the signal line for transmission increases, so that the level shifter 103 needs a larger drive capacity, and the power consumption increases. Further, when the drive capacity of the level shifter 103 is not sufficient, as in the case where the drive circuit including the level shifter 103 is formed by using the polycrystalline silicon thin film transistor, a distortion-free waveform is transmitted. , Level shifter 103 and each flip-flop F, as shown by the dashed line₁~ F_nSince it is necessary to provide a buffer 104 between and, more power consumption is required.

【0008】

In recent years, since an image display device having a wider display screen and higher resolution has been demanded, the number of stages of the shift register unit 102 tends to increase more and more. Therefore, flip-flop F₁~ F_nThere is a strong demand for shift registers and image display devices that consume less power even if the distance between both ends increases.

【0009】

The present invention has been made in view of the above problems, and an object of the present invention is a shift register that operates normally even when the amplitude of the clock signal is lower than the drive voltage and consumes less power. The purpose is to realize an image display device using the above.

【0010】

[Means for solving problems]

In order to solve the above problems, the shift register according to the present invention boosts a plurality of stages of flip-flops that operate in synchronization with a clock signal and a clock signal having an amplitude smaller than the drive voltage of the flip-flops to boost each of the above. It has a level shifter applied to a flip-flop, and is characterized by taking the following measures in a shift register that transmits an input pulse in synchronization with the clock signal.

【0011】

That is, each of the flip-flops is divided into a plurality of blocks composed of at least one flip-flop, the level shifter is provided for each block, and the input pulse of the plurality of level shifters at that time. At least one of the level shifters corresponding to the block that does not require the input of the clock signal for transmission of is stopped.

【0012】

Whether or not each block requires a clock signal for transmission of the input pulse is determined by the flip-flops constituting the shift register. For example, when a set reset flip-flop set according to a clock signal is used as the flip-flop, the block is used from the time a pulse is input to the block until the final flip-flop is set. If the flip-flop is a D flip-flop, the clock signal is required from the time the pulse is input to the block until the final flip-flop finishes the pulse output. .. In any case, one flip-flop is included in each block, and a level shifter may be provided for each flip-flop, or a level shifter may be provided for each of a plurality of flip-flops. Good.

【0013】

In the above configuration, the clock signal is boosted by one of the plurality of level shifters, then applied to the flip-flop in the block corresponding to the level shifter, and the input pulse is sequentially transmitted in synchronization with the boosted clock signal. Will be done. Further, of each level shifter, at least one of the level shifters that does not need to output a clock signal stops operation.

【0014】

Here, examples of the block that does not require a clock signal include a block that does not transmit an input pulse. Further, even in the case of a block transmitting an input pulse, for example, in the case of a set reset flip-flop in which the flip-flop is set according to the clock signal and reset according to the output of the flip-flop in a later stage. Does not require a clock signal for the period after the final flip-flop is set.

【0015】

In the above configuration, since a plurality of level shifters are provided in the shift register, the distance from the level shifter to the flip-flop can be shortened as compared with the case where only one level shifter applies the clock signal after the level shift to all the flip-flops. .. As a result, the transmission distance of the clock signal after the level shift can be shortened, so that the load capacity of the level shifter can be reduced and the drive capacity required for the level shifter can be suppressed. As a result, for example, even when the drive capacity of the level shifter is small and the distance between both ends of the flip-flop is long, it is not necessary to provide a buffer between the level shifter and the flip-flop, and the power consumption of the shift register can be reduced. Can be reduced. In addition, since at least one of the plurality of level shifters is stopped, the power consumption of the shift register can be reduced as compared with the case where all the level shifters are operated at the same time. As a result, it is possible to realize a shift register that can operate with a low-voltage clock signal input and has low power consumption.

【0016】

Further, in the shift register having the above configuration, it is preferable that each of the level shifters operates only during the period in which the flip-flop that requires the input of the clock signal at that time is included in the corresponding block.

【0017】

According to this configuration, since only the level shifter required for the transmission of the input pulse operates, the power consumption of the shift register can be significantly reduced as compared with the case where other level shifters operate.

【0018】

Further, in the shift register of each of the above configurations, the specific block of the above blocks includes the set reset flip-flop set according to the clock signal as the flip-flop, and corresponds to the specific block. The specific level shifter may start the operation when the pulse input to the specific block is started, and may stop the operation after the flip-flop of the final stage of the specific block is set.

【0019】

According to this configuration, the specific level shifter supplies the clock signal after the level shift during the period required for the set reset flip-flop of the specific block to operate, and the clock signal to the set reset flip-flop is transmitted. If no input is required, the operation is stopped. As a result, the power consumption can be reduced in the level shifter which includes the set reset flip-flop as the flip-flop and can operate at a higher speed than the case of the D flip-flop.

【0020】

Further, in the shift register having the above configuration, when there is one flip-flop (set / reset / flip-flop) in the specific block, the specific level shifter starts the pulse input to the specific block when the pulse input to the specific block is started. The operation may be started and stopped when the pulse input is completed.

【0021】

According to this configuration, the operation / stop of the specific level shifter can be controlled by using the input pulse when the specific block is in the front stage and the output of the flip-flop in the previous stage in other cases. As a result, it is not necessary to provide another circuit for determining the period during which the specific level shifter operates, and the shift register configuration can be simplified.

【0022】

On the other hand, in the shift register having the above configuration, when there are a plurality of the flip-flops in the specific block, the specific level shifter is flip-flops while the pulse is input to the specific block and except for the final stage in the specific block. Can operate while any of the pulses are being output.

【0023】

According to this configuration, the operation / stop of the specific level shifter can be controlled based on the input to the specific block and the output of the flip-flop in the specific block. The operation period can be calculated by, for example, ORing each of the above pulse signals. For example, when the operation period is calculated without using the input / output of the flip-flop by using a counter for counting the number of clocks. The operating period can be calculated with a simple circuit. As a result, a shift register that is simple and has a high operating speed can be realized.

【0024】

Further, in the shift register having the above configuration, when there are a plurality of the flip-flops in the specific block, the specific level shifter includes a signal input to the specific block and an output signal of the flip-flop in the final stage of the specific block. A latch circuit that changes the output may be included depending on the situation.

【0025】

In this configuration, when a signal is input to the specific block, the latch circuit changes the output, and the specific level shifter starts operation based on the output of the latch circuit. The latch circuit then holds the output until the final flip-flop outputs the signal. As a result, the specific level shifter continues to operate while the signal is transmitted through the specific block. Further, when the final stage flip-flop outputs a signal, the latch circuit changes the output, and the specific level shifter stops operating. Since the shift register transmits a signal, if the signal that triggers the operation / stop of the specific level shifter, that is, the input signal to the specific block and the output signal of the final stage flip-flop is monitored, The operating period of a specific level shifter can be correctly identified.

【0026】

According to the above configuration, the output of the latch circuit is changed based on the two signals that trigger the operation / stop of the specific level shifter, and the operation / stop of the specific level shifter is controlled. Therefore, unlike the case where the operation / stop is controlled based on the output signal of each flip-flop, the circuit configuration of the circuit for determining the operation period is not complicated even if the number of flip-flops in the specific block increases. As a result, a shift register having a simple circuit configuration can be realized even when the number of flip-flops is large.

【0027】

On the other hand, the present invention is applicable not only to the case where the flip-flop includes a set / reset / flip-flop, but also to the case where a specific block among the above blocks includes a D flip-flop as the flip-flop. In this case, the specific level shifter corresponding to the specific block starts the operation when the pulse input to the specific block is started, and operates after the flip-flop in the final stage of the specific block finishes the pulse output. It is preferable to stop.

【0028】

According to this configuration, since the specific block includes a D flip-flop as a flip-flop, the pulse width (clock number) of the input pulse changes, unlike the case of the set-reset flip-flop. However, the input pulse can be transmitted without any trouble. Further, according to the above configuration, the specific level shifter supplies the clock signal after the level shift during the period required for the D flip-flop of the specific block to operate, and it is not necessary to input the clock signal to the D flip-flop. In that case, the operation is stopped. As a result, it is possible to realize a shift register that can transmit input pulses having different pulse widths and consumes less power.

【0029】

In addition, the period from the pulse input to the specific block to the pulse output of the flip-flop in the final stage is, for example, the logical sum of the pulse signal input to the specific block and the output signal of the flip-flop in each stage. Can be calculated by calculating or latching the trigger signal. Therefore, in this case, the circuit configuration of the shift register can be simplified as compared with the case where the operation period is calculated separately from the input / output of the flip-flop.

【0030】

Further, in the shift register having the above configuration, when there are a plurality of the flip-flops in the specific block, the specific level shifter includes a signal input to the specific block and an output signal of the flip-flop in the final stage of the specific block. A latch circuit that changes the output may be included depending on the situation.

【0031】

According to the above configuration, as in the case of the set reset flip-flop described above, the output of the latch circuit is changed based on the two signals that trigger the operation / stop of the specific level shifter, and the operation / stop of the specific level shifter is changed. Stop is controlled. Therefore, unlike the case where the operation / stop is controlled based on the output signal of each flip-flop, the circuit configuration of the circuit for determining the operation period is not complicated even if the number of flip-flops in the specific block increases. As a result, the circuit configuration of the shift register can be simplified even when the number of flip-flops is large.

【0032】

Further, in the shift register having the above configuration, the level shifter may include a current-driven level shift unit in which the input switching element to which the clock signal is applied is always conductive during operation.

【0033】

According to this configuration, the input switching element of the level shifter is always conducting while the level shifter is operating. Therefore, unlike the voltage-driven level shifter that conducts / cuts off the input switching element depending on the level of the clock signal, even if the amplitude of the clock signal is lower than the threshold voltage of the input switching element, there is no problem. The clock signal can be level-shifted.

【0034】

Further, the current-driven level shifter consumes more power than the voltage-driven level shifter because the input switching element is conducting during operation, but at least one of the plurality of level shifters is stopped. .. As a result, it is possible to realize a shift register that can shift the level even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element and consumes less power than when all the level shifters operate at the same time.

【0035】

Further, in the shift register having the above configuration, an input signal control unit may be provided to stop the level shifter by giving a signal at a level blocked by the input switching element as an input signal to the level shift unit. ..

【0036】

According to this configuration, as an example, the case where the input switching element is a MOS transistor will be described. For example, when an input signal is applied to a gate, an input signal at a level that cuts off between the drain and the source is used. When applied to the gate, the input switching element is shut off. When the input signal is applied to the source, the input switching element is cut off by, for example, applying an input signal substantially the same as the drain.

【0037】

In any configuration, if the input signal control unit controls the level of the input signal and shuts off the input switching element, the current-driven level shifter stops operating. As a result, the input signal control unit can stop the level shifter, and during the stop, the power consumption can be reduced by the amount of the current flowing to the input switching element during operation.

【0038】

On the other hand, the shift register having each of the above configurations may include a power supply control unit that stops the power supply to the level shift unit and stops the level shifter.

【0039】

According to the configuration, the power supply control unit stops the power supply to each level shift unit and stops the level shifter. As a result, the power supply control unit can stop the level shifter, and during the operation stop, the power consumption can be reduced by the amount of the power consumed by the level shifter during the operation.

【0040】

By the way, if the output voltage of the level shifter becomes indefinite while the level shifter is stopped, the operation of the flip-flop connected to the level shifter may become unstable.

【0041】

Therefore, in the shift register having each of the above configurations, it is preferable that the level shifter is provided with an output stabilizing means for maintaining the output voltage at a predetermined value when stopped.

【0042】

According to this configuration, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means while the level shifter is stopped. As a result, malfunction of the flip-flop due to an indefinite output voltage can be prevented, and a more stable shift register can be realized.

【0043】

Further, the shift register having each of the above configurations is provided with a switch that is arranged between the clock signal line through which the clock signal is transmitted and the level shift unit and is opened while the level shifter is stopped. Is preferable. The switch can also be realized as a part of the input signal control unit.

【0044】

In the above configuration, unlike the case where all level shifters are always connected to the clock signal line and the input switching elements of all level shift sections serve as loads on the clock signal line, the input switching elements connected to the clock signal line operate. Limited to medium level shifters. Further, even if the switch is opened and the input of the level shifter becomes undefined during the stop, the output of the level shifter is maintained at a predetermined value by the output stabilizing means, so that the flip-flop does not malfunction. As a result, the load capacity of the clock signal line can be reduced, and the power consumption of the circuit that drives the clock signal line can be reduced.

【0045】

On the other hand, in order to solve the above problems, the image display device according to the present invention has a plurality of pixels arranged in a matrix, a plurality of data signal lines arranged in each row of each pixel, and each of the pixels. A plurality of scanning signal lines arranged in each row, a scanning signal line drive circuit that sequentially supplies scanning signals having different timings to the scanning signal lines in synchronization with a first clock signal having a predetermined period, and A data signal from a video signal that is sequentially given in synchronization with a second clock signal having a predetermined period and that indicates the display state of each pixel to each pixel of the scanning signal line to which the scanning signal is given is transmitted. In an image display device having a data signal line drive circuit that extracts and outputs to each of the data signal lines, at least one of the data signal line drive circuit and the scanning signal line drive circuit is the first or second clock signal. It is characterized in that it includes a shift register having any of the above configurations, which is the clock signal of the above.

【0046】

Here, in the image display device, as the number of data signal lines or the number of scanning signal lines increases, the number of flip-flops for generating timing for each signal line increases, and between both ends of the flip-flops. The distance becomes longer. However, the shift register having each of the above configurations can reduce the buffer and reduce the power consumption even when the drive capacity of the level shifter is small and the distance between both ends of the flip-flop is long.

【0047】

Therefore, by providing a shift register having each of the above configurations in at least one of the data signal line drive circuit and the scanning signal line drive circuit, it is possible to realize an image display device with low power consumption.

【0048】

Further, in the image display device having the above configuration, it is desirable that the data signal line drive circuit, the scanning signal line drive circuit, and each pixel are formed on the same substrate.

【0049】

According to this configuration, the data signal line drive circuit, the scanning signal line drive circuit, and each pixel are formed on the same substrate, and the wiring between the data signal line drive circuit and each pixel, and scanning are performed. The wiring between the signal line drive circuit and each pixel is arranged on the substrate and does not need to be taken out of the substrate. As a result, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines to be taken out of the substrate does not change, and the labor during assembly can be reduced. Further, since it is not necessary to provide a terminal for connecting each signal line to the outside of the substrate, it is possible to prevent an undesired increase in the capacitance of each signal line and prevent a decrease in the degree of integration.

【0050】

By the way, the polycrystalline silicon thin film is easier to expand the substrate area than the single crystal silicon, while the polycrystalline silicon transistor has transistor characteristics such as mobility and threshold value as compared with the single crystal silicon transistor. Is inferior. Therefore, if each circuit is manufactured using a single crystal silicon transistor, it is difficult to expand the display area, and if each circuit is manufactured using a polycrystalline silicon thin film transistor, the driving ability of each circuit is lowered. If both drive circuits and pixels are formed on different boards, it is necessary to connect both boards with each signal line, which takes time and effort during manufacturing and increases the capacity of each signal line. ..

【0051】

Therefore, in the image display device having each of the above configurations, it is preferable that the data signal line driving circuit, the scanning signal line driving circuit, and each pixel include a switching element made of a polycrystalline silicon thin film transistor.

【0052】

In this configuration, since the data signal line drive circuit, the scanning signal line drive circuit, and each pixel all include a switching element made of a polycrystalline silicon thin film transistor, the display area can be easily expanded. Further, since it can be easily formed on the same substrate, it is possible to reduce the labor during manufacturing and the capacity of each signal line. In addition, since the shift registers having the above configurations are used, the clock signal after the level shift can be applied to each flip-flop without any problem even when the drive capability of the level shifter is low. As a result, it is possible to realize an image display device having low power consumption and a wide display area.

【0053】

In addition, in the image display device having each of the above configurations, it is desirable that the data signal line drive circuit, the scanning signal line drive circuit, and each pixel include a switching element manufactured at a process temperature of 600 degrees or less.

【0054】

According to this configuration, the process temperature of the switching element is set to 600 degrees or less, so even if a normal glass substrate (a glass substrate with a distortion point of 600 degrees or less) is used as the substrate of each switching element, distortion is caused. No warping or bending caused by the process above the point. As a result, it is possible to realize an image display device that is easier to mount and has a wider display area.

【0055】

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 7. The present invention can be widely applied to a shift register in which the amplitude of the input clock signal is smaller than the drive voltage, but the case where it is applied to an image display device will be described below as a preferable example.

【0056】

That is, as shown in FIG. 2, the image display device 1 according to the present embodiment includes a display unit 2 having pixel PIX arranged in a matrix, a data signal line drive circuit 3 for driving each pixel PIX, and a scanning signal. A line drive circuit 4 is provided, and when the control circuit 5 generates a video signal DAT indicating the display state of each pixel PIX, an image can be displayed based on the video signal DAT.

【0057】

The display unit 2 and both drive circuits 3 and 4 are provided on the same substrate in order to reduce labor and wiring capacity during manufacturing. Further, in order to integrate more pixel PIXs and expand the display area, each of the above circuits 2 to 4 is composed of a polycrystalline silicon thin film transistor formed on a glass substrate. Furthermore, even if a normal glass substrate (a glass substrate with a strain point of 600 degrees or less) is used, the polycrystalline thin film silicon transistor is 600 degrees or less so that warpage and deflection due to the process above the strain point do not occur. Manufactured at the process temperature of.

【0058】

Here, the display unit 2 is the data signal line SL of l (L: in the following, uppercase L is used for reference).₁~ SL_LAnd each data signal line SL₁~ SL_LM scanning signal lines intersecting each other GL₁~ GL_mAnd have. If any positive integer less than or equal to L is i and any positive integer less than or equal to m is j, then the data signal line SL_iAnd scanning signal line GL_jPixel PIX for each combination with_{(i, j)}Is provided, and each pixel PIX_{(i, j)}Is two adjacent data signal lines SL_i SL_{i + 1}, And two adjacent scanning signal lines GL_j GL_{j + 1}It is placed in the area surrounded by.

【0059】

On the other hand, the above pixel PIX_{(i, j)}For example, as shown in FIG. 3, the gate is the scanning signal line GL._jTo, the drain is the data signal line SL_iA pixel capacitance C in which one electrode is connected to the field effect transistor (switching element) SW connected to and the source of the field effect transistor SW._PAnd have. Also, the pixel capacity C_PThe other end of is connected to a common electrode wire common to all pixel PIX. Pixel capacity C_PIs the liquid crystal capacity C_LAnd the auxiliary capacity C added as needed_SIt is composed of and.

【0060】

Above pixel PIX_{(i, j)}In the scanning signal line GL_jWhen is selected, the field effect transistor SW becomes conductive and the data signal line SL_iThe voltage applied to is the pixel capacitance C_PIs applied to. On the other hand, the scanning signal line GL_jPixel capacitance C while the field effect transistor SW is cut off after the selection period of_PContinues to hold the voltage at the time of interruption. Here, the transmittance or reflectance of the liquid crystal is the liquid crystal capacity C._LIt changes depending on the voltage applied to. Therefore, the scanning signal line GL_jSelect and data signal line SL_iIf a voltage corresponding to the video data is applied to, the pixel PIX_{(i, j)}The display state of can be changed according to the video data.

【0061】

In the image display device 1 shown in FIG. 2, the scanning signal line drive circuit 4 selects the scanning signal line GL, and the video data to the pixel PIX corresponding to the combination of the selected scanning signal line GL and the data signal line SL is transmitted. , The data signal line drive circuit 3 outputs to each data signal line SL. As a result, each video data is written to the pixel PIX ... Connected to the scanning signal line GL. Further, the scanning signal line driving circuit 4 sequentially selects the scanning signal line GL, and the data signal line driving circuit 3 outputs video data to each data signal line SL. As a result, each video data is written to all the pixels PIX of the display unit 2.

【0062】

Here, between the control circuit 5 and the data signal line drive circuit 3, the video data to each pixel PIX is transmitted as a video signal DAT in a time-divided manner, and the data signal line drive circuit 3 is a timing signal. Each video data is extracted from the video signal DAT at a timing based on the clock signal CKS and the start signal SPS having a predetermined period.

【0063】

Specifically, the data signal line drive circuit 3 sequentially shifts the start signal SPS in synchronization with the clock signal CKS, so that the output signal S has different timings at predetermined intervals.₁~ S_LShift register 3a to generate, and each output signal S₁~ S_LThe video signal DAT is sampled at the timing indicated by, and each data signal line SL₁~ SL_LIt is equipped with a sampling unit 3b that extracts the video data to be output to the video signal DAT from the video signal DAT. Similarly, the scanning signal line drive circuit 4 sequentially shifts the start signal SPG in synchronization with the clock signal CKG, thereby transmitting scanning signals having different timings at predetermined intervals to each scanning signal line GL.₁~ GL_mIt has a shift register 4a that outputs to.

【0064】

Here, in the image display device 1 according to the present embodiment, the display unit 2 and both drive circuits 3 and 4 are formed of polycrystalline silicon thin film transistors, and the drive voltages V of these circuits 2 to 4 are formed._CCIs set to, for example, about 15 [V]. On the other hand, the control circuit 5 is formed of a single crystal silicon transistor on a substrate different from each of the circuits 2 to 4, and the drive voltage is, for example, 5 [V] or less. Voltage V_CCIt is set to a lower value than. Although the circuits 2 to 4 and the control circuit 5 are formed on different substrates, the number of signals transmitted between the circuits 2 to 4 is larger than the number of signals transmitted between the circuits 2 to 4. It is significantly less, for example, a video signal DAT, each start signal SPS (SPG), or a clock signal CKS (CKG). Further, since the control circuit 5 is formed of a single crystal silicon transistor, it is easy to secure a sufficient driving ability. Therefore, even if they are formed on different substrates, the labor during manufacturing and the increase in wiring capacity or power consumption are suppressed to the extent that they do not cause a problem.

【0065】

Here, in the present embodiment, the shift register 11 shown in FIG. 1 is used for at least one of the shift registers 3a and 4a. In the following, each start signal SPS (SPG) will be referred to as SP, the number of stages L (m) of shift register 1 will be referred to by n, and the output signal will be referred to as S so that it may be used as any shift register.₁~ S_nIt is called.

【0066】

Specifically, the shift register 11 has an n-stage set reset flip-flop (SR flip-flop) F1.₍₁₎Including ..., the above drive voltage V_CCThe flip-flop unit 12 that operates in the above and the drive voltage V supplied from the control circuit 5 above._CCEach SR flip-flop F1 boosts the clock signal CK, which has a smaller amplitude than₍₁₎Level shifter 13 applied to ...₍₁₎... is included.

【0067】

In this embodiment, each level shifter 13₍₁₎... is each SR flip-flop F1₍₁₎It is provided so that there is a one-to-one correspondence with ..., and as will be described later, the amplitude of the clock signal CK is the above-mentioned drive voltage V._CCEven if it is smaller than that, it is configured as a current-driven level shifter so that the voltage can be boosted without any trouble. Also, assuming that an integer less than or equal to n and greater than or equal to 1 is i, each level shifter 13_(i)Is the control signal ENA_iCorresponding SR flip-flop F1 based on the clock signal CK and its inverting signal CK bar while instructing operation_(i)Clock signal CK after boosting to_iCan be applied. In addition, while the control signal ENA is instructing to stop, the operation is stopped and the corresponding SR flip-flop F1_(i)Clock signal to CK_iThe level shifter 13 caused by the through current by shutting off the input switching element described later while the operation is stopped._(i)Power consumption can be reduced.

【0068】

On the other hand, the flip-flop unit 12 is configured so that the start signal SP having a period width of one clock can be transmitted to the next stage at each edge (rising and falling) of the clock signal CK. Specifically, each level shifter 13_(i)Output is inverter I1_(i)SR flip-flop F1 as a negative logic set signal S bar via_(i)Is applied to. Also, each SR flip-flop F1_(i)Output Q is the output S of shift register 11._iIs output as, and the next level shifter 13_{(i + 1)}Control signal ENA_{i + 1}Is applied as. The first level shifter 13₍₁₎The control signal ENA₁As a result, the start signal SP from the control circuit 5 shown in FIG. 1 is applied after being boosted. In addition, each SR flip-flop F1_(i)Of the set signals to the SR flip-flop F1 in the subsequent stage, a signal delayed by the pulse width of the pulse to be transmitted is applied as the reset signal R. In the present embodiment, since a pulse having a width of one clock cycle is transmitted, a signal delayed by one clock cycle, that is, SR flip-flop F1 after two stages_{(i + 2)}Clock signal to CK_{(i + 2)}Is applied as a positive logic reset signal.

【0069】

Also, odd-numbered SR flip-flops F1₍₁₎, F1₍₃₎Odd-numbered level shifter 13 so that ... is set at the rising edge of the clock signal CK₍₁₎In ..., the clock signal CK is applied to the non-inverting input terminal, and the inverted signal CK bar of the clock signal is applied to the inverting input terminal. On the contrary, even-numbered level shifters 13₍₂₎、13₍₄₎... is an even-numbered SR flip-flop F1₍₂₎The clock signal CK is applied to the inverting input terminal and the inverting signal CK bar is applied to the non-inverting input terminal so that ... is set at the falling edge of the clock signal CK.

【0070】

According to the above configuration, as shown in FIG. 4, the level shifter 13 in the front stage while the start signal SP is pulse-input.₍₁₎Clock signal CK after operating and boosting₁SR flip flop F1₍₁₎Apply to. As a result, SR flip-flop F1₍₁₎Is set when the clock signal CK first rises after the start of the pulse input, and the output S₁To a high level.

【0071】

Output S above₁Is the control signal ENA₂As, the second level shifter 13₍₂₎Is applied to. As a result, level shifter 13₍₂₎Is an SR flip-flop F1₍₁₎While the pulse is being output (control signal ENA)₂= S₁During high level), clock signal CK₂Is output. However, level shifter 13₍₂₎Since the clock signal CK is applied to the inverting input terminal, the level shifter 13₍₂₎Is the opposite of the polarity of the clock signal CK, and the boosted signal is the clock signal CK.₂Output as. As a result, SR flip-flop F1₍₂₎Is the output S of the previous stage₁Is set when the clock signal CK first falls after it reaches a high level, and the output S₂To a high level.

【0072】

Each output signal S_iIs the next level shifter 13_{(i + 1)}To, control signal ENA_{i + 1}Since it is applied as, SR flip-flop F1 of the second and subsequent stages₍₂₎... is the output S of the previous stage₁The output S is delayed by 1/2 cycle of the clock signal CK.₂Output ...

【0073】

On the other hand, the level shifter 13 of each stage_(i)Level shifter 13 after 2 steps_{(i + 2)}Output CK_{i + 2}Is applied as the reset signal R. Therefore, each output S_iChanges to a low level after becoming a high level for one clock cycle. As a result, the flip-flop unit 12 can transmit the start signal SP having a period width of one clock to the next stage at each edge (rising and falling) of the clock signal CK.

【0074】

Here, each level shifter 13_(i)Is an SR flip-flop F1_(i)SR flip-flop F1 because it is provided for each_(i)Even when the number of stages is large, the distance between the corresponding level shifters and the flip-flops can be shortened as compared with the case where the clock signal CK is boosted by a single level shifter and then applied to all flip-flops. Therefore, the clock signal CK after boosting_iTransmission distance can be shortened, and each level shifter 13_(i)Load capacity can be reduced. Also, since the load capacity is small, for example, the level shifter 13_(i)Level shifter 13 as if is composed of polycrystalline silicon thin film transistors_(i)It is not necessary to provide a buffer even when it is difficult to secure a sufficient driving capacity of the above. As a result, the power consumption of the shift register 11 can be reduced.

【0075】

In addition, the start signal SP and the output S of the previous stage_i-1Each SR flip-flop F1_(i)Is the clock signal CK_iLevel shifter 13 if no input is required_(i)Has stopped working. In this state, the clock signal CK_iIs not driven, so the power consumption required for driving is not generated. Furthermore, as will be described later, each level shifter 13_(i)The power supply itself to the level shift unit 13a provided in the above is stopped, the input switching element is cut off, and a through current does not flow. Therefore, despite the fact that many (n) current-driven level shifters are provided, the operating level shifter 13_(i)Power is consumed only in. As a result, the power consumption of the shift register 11 can be significantly reduced.

【0076】

In addition, the level shifter 13 according to the present embodiment_(i)Is an SR flip-flop F1_(i)Clock signal CK_iThe required period, that is, the start signal SP or the output S of the previous stage_i-1SR flip-flop F1 from the time when the pulse output started_(i)The period until is set is the start signal SP or the output S of the previous stage._i-1Judgment is based only on. As a result, the start signal SP or the output S of the previous stage_i-1Each level shifter 13 simply by applying directly_(i)The operation / stop of the shift register 11 can be controlled, and the circuit configuration of the shift register 11 can be simplified as compared with the case where a circuit for creating a new control signal is provided.

【0077】

Further, in the present embodiment, each level shifter 13_(i)Each SR flip-flop F1 while_(i)Clock input to is blocked. Therefore, level shifter 13_(i)Apart from that, the start signal SP can be transmitted correctly without providing a switch that conducts depending on the necessity of clock input.

【0078】

Here, in each of the SR flip-flops F1, for example, as shown in FIG. 5, the drive voltage V_CCA P-type MOS transistor P1 and an N-type MOS transistor N2 and N3 are connected in series between the transistor P1 and the ground level, and a negative logic set signal S bar is applied to the gates of the transistors P1 and N3. Will be done. Further, a positive logic reset signal R is applied to the gate of the transistor N2. Further, the drain potentials of the two transistors P1 and N2 connected to each other are inverted by the inverters INV1 and INV2, respectively, and output as an output signal Q. On the other hand, the drive voltage V_CCFurther, P-type MOS transistors P4 / P5 and N-type MOS transistors N6 / N7 connected in series are provided between the ground level and the ground level. The drains of both transistors P5 and N6 are connected to the input of the inverter INV1, and the gates of both transistors P5 and N6 are connected to the output of the inverter INV1. Further, a reset signal R is applied to the transistor P4, and a set signal S bar is applied to the gate of the transistor N7.

【0079】

In the SR flip-flop F1, as shown in FIG. 6, when the set signal S bar changes to active (low level) while the reset signal R is inactive (low level), the transistor P1 becomes conductive and conducts. Change the input of inverter INV1 to a high level. As a result, the output signal Q of the SR flip-flop F1 changes to a high level.

【0080】

In this state, the transistors P4 and P5 are conducted by the reset signal R and the output of the inverter INV1. In addition, the reset signal R and the output of the inverter INV1 cut off the transistors N2 and N6. As a result, even if the set signal S bar changes inactive, the input of the inverter INV1 is maintained at a high level, and the output signal Q is maintained at a high level.

【0081】

After that, when the reset signal R becomes active, the transistor P4 is cut off and the transistor N2 becomes conductive. Here, since the set signal S bar remains inactive, the transistor P1 is cut off and the transistor N3 becomes conductive. Therefore, the input of the inverter INV1 is driven to the low level, and the output signal Q changes to the low level.

【0082】

On the other hand, the level shifter 13 according to the present embodiment is, for example, as shown in FIG. 7, to the level shift unit 13a for level-shifting the clock signal CK and to the level shift unit 13a during the stop period when the supply of the clock signal CK is unnecessary. The power supply control unit 13b that cuts off the power supply of the above, the input control unit (switch) 13c that cuts off the level shift unit 13a and the signal line through which the clock signal CK is transmitted during the stop period, and the above level during the stop period. The input switching element cutoff control unit (input signal control unit) 13d that shuts off the input switching element of the shift unit 13a, and the output stabilization unit (output stabilization means) that maintains the output of the level shift unit 13a at a predetermined value during the stop period. It is equipped with 13e.

【0083】

The level shift unit 13a is a constant current source Ic that supplies a predetermined current to the P-type MOS transistors P11 / P12 in which the sources are connected to each other and the sources of both transistors P11 / P12 as differential input pairs in the input stage. It is equipped with N-type MOS transistors N13 / N14, which form a current mirror circuit and serve as active loads for both transistors P11 / P12, and transistors P15 / N16 with a CMOS structure that amplifies the output of the differential input pair. ..

【0084】

The clock signal CK is input to the gate of the transistor P11 via the transistor N31 described later, and the inverted signal CK bar of the clock signal is input to the gate of the transistor P12 via the transistor N33 described later. Further, the gates of the transistors N13 and N14 are connected to each other, and further connected to the drain of the transistors P11 and N13. On the other hand, the drains of the transistors P12 and N14 connected to each other are connected to the gates of the transistors P15 and N16. The sources of the transistors N13 and N14 are grounded via the N-type MOS transistor N21 as the power supply control unit 13b.

【0085】

On the other hand, in the input control unit 13c on the transistor P11 side, an N-type MOS transistor N31 is provided between the clock signal CK and the gate of the transistor P11. Further, in the input switching element cutoff control unit 13d on the transistor P11 side, the gate of the transistor P11 and the drive voltage V_CCA P-type MOS transistor P32 is provided between the two. Similarly, the inverted signal CK bar of the clock signal is applied to the gate of the transistor P12 via the transistor N33 as the input control unit 13c, and the drive voltage is applied via the transistor P34 as the input switching element cutoff control unit 13d. V_CCIs given.

【0086】

Further, the output stabilization unit 13e has a configuration in which the output voltage OUT of the level shifter 13 during the stop period is stabilized at the ground level, and the drive voltage V_CCA P-type MOS transistor P41 is provided between the transistor and the gates of both transistors P15 and N16.

【0087】

In this embodiment, the control signal ENA is set to indicate the operation of the level shifter 13 at a high level. Therefore, the control signal ENA is applied to the gates of the transistors N21 to P41.

【0088】

In the level shifter 13 having the above configuration, when the control signal ENA indicates operation (in the case of high level), the transistors N21, N31, and N33 are conducted, and the transistors P32, P34, and P41 are cut off. In this state, the current of the constant current source Ic flows through the transistors P11 and N13, or the transistors P12 and N14, and then through the transistors N21. Further, a clock signal CK or a clock signal inversion signal CK bar is applied to the gates of both transistors P11 and P12. As a result, a voltage corresponding to the ratio of the gate-source voltage flows through both transistors P11 and P12. On the other hand, since the transistors N13 and N14 act as an active load, the voltage at the connection point of the transistors P12 and N14 becomes a voltage corresponding to the difference in the voltage levels of both CK and CK bars. The voltage becomes the gate voltage of the CMOS transistors P15 and N16, and after the power is amplified by both transistors P15 and N16, it is output as the output voltage OUT.

【0089】

The level shifter 13 has a configuration in which the conduction / interruption of the transistor P11 / P12 of the input stage is switched by the clock signal CK, that is, unlike the voltage drive type, the level shifter 13 is a current drive in which the transistors P11 / P12 of the input stage are always conductive during operation. It is a type, and the clock signal CK is level-shifted by dividing the current of the constant current source Ic according to the ratio of the gate-source voltage of both transistors P11 and P12. As a result, even when the amplitude of the clock signal CK is lower than the threshold values of the transistors P11 and P12 in the input stage, the clock signal CK can be level-shifted without any problem.

【0090】

As a result, each level shifter 13_(i)Is the corresponding control signal ENA, as shown in Figure 4._iClock signal CK during high level_iAs the peak value is the drive voltage V_CCIt has the same shape as the clock signal CK with a lower value (for example, about 5 [V]), and the peak value is the drive voltage V._CCIt can output an output voltage OUT boosted to (for example, about 15 [V]).

【0091】

On the contrary, the control signal ENA_iIndicates an outage (at low level), the current flowing from the constant current source Ic through the transistors P11 and N13, or the transistors P12 and N14, is cut off by the transistor N21. In this state, the current supply from the constant current source Ic is blocked by the transistor N21, so that the power consumption caused by the current can be reduced. Further, in this state, since no current is supplied to both transistors P11 and P12, both transistors P11 and P12 cannot operate as a differential input pair, and the output end, that is, the connection point of both transistors P12 and N14. The potential of the transistor cannot be determined.

【0092】

Further, in this state, the transistors N31 and N33 of each input control unit 13c are cut off. As a result, the signal line that transmits the clock signal CK (CK bar) and the gates of both transistors P11 and P12 in the input stage are separated, and the gate capacitance that is the load capacitance of the signal line is the level shifter 13 during operation. Limited to things only. As a result, a plurality of level shifters 13 are attached to the signal line._(i)The load capacitance of the signal line can be reduced even though the clock signal CK (CK bar) is connected, and the power consumption of the circuit that drives the clock signal CK (CK bar) can be reduced as shown in the control circuit 5 shown in FIG.

【0093】

Further, since the transistors P32 and P34 of each input switching element cutoff control unit 13d are conductive during the stop, the gate voltages of both transistors P11 and P12 are the drive voltage V._CCThen, both transistors P11 and P12 are cut off. As a result, the current consumption can be reduced by the amount of the current output by the constant current source Ic, as in the case of interrupting the transistor N21. In this state, both transistors P11 and P12 cannot operate as a differential input pair, so that the potential at the output end cannot be determined.

【0094】

In addition, when the control signal ENA indicates that the operation has stopped, the transistor P41 of the output stabilizer 13e is further conducted. As a result, the output end, that is, the gate potential of the CMOS transistors P15 and N16 is the drive voltage V._CCAnd the output voltage OUT becomes low level. As a result, as shown in FIG. 4, the control signal ENA_iIf indicates an outage, level shifter 13_(i)Output voltage OUT (CK_i) Is kept at a low level regardless of the clock signal CK. As a result, level shifter 13_(i)SR flip-flop F1 unlike the case where the output voltage OUT is indefinite while the_(i)It is possible to prevent the malfunction of the shift register 11 and realize a shift register 11 that can operate stably.

【0095】

[Second Embodiment] In the present embodiment, unlike the first embodiment, a case where the shift register is composed of a plurality of stages of D flip-flops will be described with reference to FIGS. 8 to 14. In each of the following embodiments, for convenience of explanation, members having the same functions as those in the previous embodiment are designated by the same reference numerals and the description thereof will be omitted.

【0096】

That is, as shown in FIG. 8, the shift register 21 according to the present embodiment has a plurality of stages of D flip-flops F2.₍₁₎Flip-flop part 22 consisting of ... and each D flip-flop F2₍₁₎Level shifter 13 provided for each and shown in Fig. 1.₍₁₎Level shifter 23 with the same configuration as ...₍₁₎... and has.

【0097】

Each of the above D flip-flops F2_(i)Is the clock signal CK_iIs a D flip-flop that changes the output Q according to the input D during the high level period and maintains the output Q during the low level, and each D flip-flop F2_(i)Output Q is output S_iIs output as, and the next stage D flip-flop F2_{(i + 1)}Is entered in. The first D flip-flop F2₍₁₎The start signal SP is input to.

【0098】

Also, as in FIG. 1, the odd-numbered level shifter 23₍₁₎... is the clock signal CK that boosts the boosted clock signal CK during operation.₁Output as ... and even-numbered level shifter 23₍₂₎... is the signal CK that is boosted with the opposite polarity to the clock signal CK during operation.₂Output ... In addition, regardless of even number, D flip-flop F2_(i)The corresponding clock signal CK_iAnd inverter I2_(i)Clock signal generated by CK_iInverted signals of are applied respectively.

【0099】

Here, D flip-flop F2_(i)Output S_iIs the clock signal CK_iSR flip-flop F1 shown in Fig. 1 because it does not change until_(i)Unlike the output S_iClock signal CK not only at the rising point of_iNeed. Therefore, in the present embodiment, each level shifter 23_(i)OR circuit G1 that calculates the logical sum of the input and output of_(i)Is provided, and the level shifter 23 corresponding to the calculation result_(i)Control signal to ENA_iIs output as.

【0100】

In the above configuration, as shown in FIG. 9, when the start signal SP is pulse-input, the control signal ENA₁Changes to a high level, D flip-flop F2₍₁₎Clock signal CK after boosting₁Is entered. As a result, after the start signal SP is pulse-input, the next clock signal CK₁D flip-flop F2 at the start of₍₁₎Output S₁Changes to a high level and the clock signal CK₁During the low level, even if the start signal SP changes to the low level, it remains at the high level.

【0101】

After the start signal SP changes to low level, the clock signal CK first₁D flip-flop F2 when₍₁₎Output S₁Changes to low level. Furthermore, in this state, the start signal SP and the output S₁Are both low level, so OR circuit G1₍₁₎Is the control signal ENA₁To low level, level shifter 23₍₁₎To stop.

【0102】

Here, each D flip-flop F2_(i)Output S_iIs the next D flip-flop F2_{(i + 1)}Input to the adjacent D flip-flop F2_(i) F2_{(i + 1)}Clock signals CK that are out of phase with each other_i CK₊₁Is entered. As a result, the flip-flop unit 22 can transmit the start signal SP to the next stage at each edge (rising and falling) of the clock signal CK.

【0103】

In the above configuration, each level shifter 23_(i)Is the corresponding D flip-flop F2_(i)Is the clock signal CK_iWhile requiring input of, i.e. D flip-flop F2_(i)After the pulse input is started, D flip-flop F2_(i)Can operate until the end of the pulse output, and can be stopped for the remaining period. As a result, as in the first embodiment, the drive voltage V_CCA shift register 21 that can operate with a clock signal CK having a smaller amplitude and consumes less power can be realized.

【0104】

Further, unlike the first embodiment, the flip-flop unit 22 according to the present embodiment is composed of a D flip-flop that changes the output Q based on the input D and the clock signal CK, and thus is a start signal. Even if the pulse width (clock number) of the SP changes, the start signal SP can be transmitted without any problem.

【0105】

For example, in the sampling unit 3b shown in FIG. 2, when the driving capability of the sampling transistor for sampling the video signal DAT is low, a longer sampling period is required, and the output S with a longer pulse width (time) is required.₁... S_nNeed. On the other hand, even if the pulse width is the same time, the number of clocks increases as the frequency of the clock signal CK increases. Therefore, the optimum value of the pulse width of the start signal SP changes depending on the driving capability of the sampling transistor and the frequency of the clock signal CK. Therefore, as shown in the shift register 11 shown in FIG. 1, the output S₁In the case of a configuration in which the connection destination of the reset signal R is set according to the pulse width (clock number) of ..., it is necessary to design a different circuit for each desired pulse width (clock number). Further, when the same data signal line drive circuit 3 is driven by clock signals CK of different frequencies, or when it is diverted to drive different display units 2, the optimum pulse width cannot be secured and the display quality may be deteriorated. There is.

【0106】

On the other hand, the shift register 21 according to the present embodiment simply changes the pulse width of the start signal SP, and outputs S with a desired pulse width.₁... can be output. Therefore, it is possible to reduce the design effort and realize the image display device 1 in which the display quality does not deteriorate even in the above case.

【0107】

However, as shown in FIG. 5, the SR flip-flop F1 can be realized with fewer elements than the D flip-flop F2 shown in FIG. 10 described later, and can operate at a higher speed when the operating speeds of the elements are the same. Furthermore, the output S of the previous stage_i-1Then, the next level shifter 13_(i)Since the operation / stop of the above can be directly controlled, the above OR circuit G1_(i)Is unnecessary. As a result, when the optimum pulse width (number of clocks) can be determined in advance and a high-speed shift register with a small circuit scale is required, it is preferable to use the SR flip-flop F1.

【0108】

Here, in each of the above D flip-flops F2, for example, as shown in FIG. 10, the drive voltage V_CCThe P-type MOS transistors P51 and P52 and the N-type MOS transistors N53 and N54 are connected in series with each other between the ground level and the ground level. An input signal D is applied to the gates of the transistors P52 and N53, and the drain potentials of both transistors P52 and N53 connected to each other are inverted by the inverter INV51 and then output as an output Q. On the other hand, the drive voltage V_CCFurther, P-type MOS transistors P55 and P56 and N-type MOS transistors N57 and N58 connected in series are provided between the ground level and the ground level. The drains of both transistors P56 and N57 are connected to the input of the inverter INV51, and the respective gates are connected to the output of the inverter INV51. Further, an inverted clock signal CK bar is applied to the gates of the transistors P51 and N58, and a clock signal CK is applied to the gates of the transistors N54 and P55.

【0109】

In the D flip-flop F2 having the above configuration, the transistors P51 and N54 are conducted while the clock signal CK is at a high level, and the transistors P55 and N58 are cut off. As a result, the input D is inverted by the transistors P52 and N53 and then inverted by the inverter INV51. As a result, the output Q changes to the same value as the input D. On the contrary, since the transistors P51 and N54 are cut off while the clock signal CK is at a low level, the transistors P52 and N53 cannot invert the input D. Further, in this state, the transistors P55 and N58 are conducted, and the output of the inverter INV51 is fed back to the input. As a result, while the clock signal CK is at a low level, the output Q is maintained at the same value as when the clock signal CK falls, even if the input D is at a high level. Therefore, as shown in FIG. 11, the output Q of the D flip-flop F2 changes following the input D when the clock signal CK rises for the first time after the input D changes.

【0110】

On the other hand, in each of the OR circuits G1, for example, as shown in FIG. 12, each input IN₍₁₎P-type MOS transistor P61 corresponding to ...₍₁₎A series circuit consisting of ... and each input IN₍₁₎N-type MOS transistor N62 corresponding to ...₍₁₎A parallel circuit consisting of ... and a CMOS inverter consisting of a P-type MOS transistor P63 and an N-type MOS transistor N64 are provided. Here, since the OR circuit G1 is a 2-input OR circuit, two transistors P61 and two are provided for each of the transistors P61 and N62, and the transistor P61 is provided.₍₁₎ N62₍₁₎At the gate of the input IN₍₁₎Is applied and transistor P62₍₂₎ N62₍₂₎At the gate of the input IN₍₂₎Is applied. Further, the series circuit and the parallel circuit are connected in series with each other, and the drive voltage V_CCIt is placed between the ground level and the ground level. Further, the connection point between the series circuit and the parallel circuit is connected to the input end of the CMOS inverter, that is, the gate of both transistors P63 and N64. As a result, the OR circuit G1 is input IN from the drain of the transistors P63 and N64, which are the output ends of the CMOS inverter.₍₁₎ IN₍₂₎Can output the logical sum of.

【0111】

By the way, in Fig. 8, each D flip-flop F2_(i)Level shifter 23 by ORing the input and output of_(i)OR circuit G1 that instructs operation / stop to_(i)Is provided, but each level shifter itself is a D flip-flop F2._(i)If the operation / stop can be determined by ORing the input and output of, OR circuit G1_(i)Can be omitted.

【0112】

Specifically, as shown in FIG. 13, in the shift register 21a according to this modification, the level shifter 23_(i)Instead of the control signal ENA₁ ENA₂Level shifter 24 that works when one of the is active (true)_(i)Is provided. Along with this, the OR circuit G1 shown in Fig. 8_(i)Is omitted, D flip-flop F2_(i)Input / output is the control signal ENA₁ ENA₂As a level shifter 24 corresponding to each other_(i)Is entered directly in.

【0113】

As shown in FIG. 14, the level shifter 24 has substantially the same configuration as the level shifter 13 shown in FIG. 7, but unlike the level shifter 13, the power supply control unit 24b to the output stabilization unit 24e control signals. ENA₁ ENA₂Correspondingly, the same number (two in this case) of each transistor N21 to P41 is provided. Specifically, in the power supply control unit 24b, the transistor N21₍₁₎ N21₍₂₎Are connected in parallel with each other. Similarly, in the input control unit 24c corresponding to the transistor P11, the transistor N31₍₁₎ N31₍₂₎However, in the input control unit 24c corresponding to the transistor P12, the transistor N33₍₁₎ N33₍₂₎Are connected in parallel to each other. On the other hand, in the output stabilizer 24e, the transistor P41₍₁₎ P41₍₂₎Are connected in series with each other, and each input switching element cutoff control unit 24d is a transistor P32 connected in series with each other.₍₁₎ P32₍₂₎Or, transistors P34 connected in series with each other₍₁₎ P34₍₂₎Consists of. Further, in the present embodiment, since the shift register 21a transmits a high-level pulse signal, each of the above transistors N21₍₁₎~ P41₍₂₎Of which, the control signal ENA₁Those who correspond to (subscript is₍₁₎The control signal ENA at the gate₁Is applied and the control signal ENA₂Those who correspond to (subscript is₍₂₎The gate of the corresponding control signal ENA₂Is applied.

【0114】

According to the above configuration, the control signal ENA₁Or ENA₂Transistor N21 if at least one of them is high level₍₁₎ N21₍₂₎And one of the transistors N31₍₁₎ N31₍₂₎And one of the transistors N33₍₁₎ N33₍₂₎One of them conducts. Also, transistor P32₍₁₎ P32₍₂₎And one of the transistors P34₍₁₎ P34₍₂₎And one of the transistors P41₍₁₎ P41₍₂₎One of them is blocked. As a result, the level shifter 24 operates in the same manner as the level shifter 13 described above. On the contrary, the control signal ENA₁And ENA₂When all of the are low level, N type transistor N21₍₁₎~ N34₍₂₎Everything is cut off, P-type transistor P31₍₁₎~ P41₍₂₎Since everything is conductive, the level shifter 24 stops operating in the same manner as the level shifter 13 described above. As a result, the level shifter 23 shown in FIG._(i)Similar to Level Shifter 24_(i)Is the corresponding D flip-flop F2_(i)It can be started / stopped according to the input / output of, and the same effect can be obtained.

【0115】

[Third Embodiment] By the way, in the first and second embodiments, a level shifter is provided for each flip-flop, but when reduction of the circuit scale is strongly required, each of the following embodiments can be used. As shown, a level shifter may be provided for each of a plurality of flip-flops. In the present embodiment, a case where a level shifter is provided for each of the plurality of SR flip-flops will be described with reference to FIGS. 15 to 19.

【0116】

That is, in the shift register 11a according to the present embodiment, as shown in FIG. 15, N SR flip-flops F1 are divided into K SR flip-flops F1 and a plurality of blocks B₁~ B_PIt is divided into. Further, a level shifter 13 is provided for each block B. In the following, for convenience of explanation, if an integer of 1 or more is i for P or less and an integer of 1 or more is j for K or less, the i-th block B_iIn the jth SR flip-flop F1, F1_{(i, j)}Refer to as.

【0117】

Further, in the present embodiment, each block B_iEvery time, level shifter 13_(i)Control signal ENA_iOR circuit G2_(i)Is provided. The OR circuit G2_(i)Is the block B_iInput signal to the block B_iSR flip-flop F1 excluding the last stage_{(i, 1)}... F1_{i, (K-1)}Calculate the logical sum with each output signal of the above level shifter 13_(i)It is an OR circuit of K input that outputs to. Where block B_iThe input signal to is the block B in the front stage.₁Then, it is the start signal SP, and the block B from the second stage onward_iThen, block B in the previous stage_i-1Is the output signal of. In the OR circuit G2, for example, as shown in FIG. 16, in the OR circuit G1 shown in FIG. 12, the number of transistors P61 and the number of transistors N62 are increased to the number of inputs (K in this case). It can be realized by a circuit.

【0118】

As a result, as shown in FIG. 17, the block B_iSR flip-flop F1 one before the final stage from the time when the pulse input to_{(i, (K-1))}Output S_{i, (K-1)}Level shifter 13 until the end of the pulse output of_(i)Control signal to ENA_iBecomes a high level. As a result, level shifter 13_(i)Is at least the block B_iSR flip-flops in F1_{(i, 1)}... F1_{(i, K)}One of the clock signals CK_iSR flip-flop F1 in the final stage from the time when the input of the above is required, that is, from the time when the pulse input is started._{(i, K)}Clock signal CK until when is set_iCan be output, and the above SR flip-flop F1_(iK)After set, SR flip-flop F1_{(i, (K-1))}Output S_{i, (K-1)}The operation can be stopped when the pulse output of is completed.

【0119】

Here, in the present embodiment, the level shifter 13_(i)Is the block B_iSR flip flop F1_{(i, j)}If any of them require a clock input, the clock signal CK_iEach SR flip-flop F1 to keep outputting_{(i, j)}Clock signal CK_iIs supplied as it is, SR flip-flop F1 as shown by the broken line in FIG._{(i, j)}SR flip-flop F1 again after reset_{(i, j)}Is set, a plurality of pulses are generated from one pulse of the start signal SP. Therefore, as shown in FIG. 15, the level shifter 13 is stored in the shift register 11a._(i)And each SR flip-flop F1_{(i, j)}Between and the switch SW_{i, j}Is provided, and the SR flip-flop F1 in the previous stage_{(i, (j-1))}Clock signal CK only while is pulse output_iSR flip flop F1_{(i, j)}Is applied to. In addition, the above switch SW_{i, j}Each SR flip-flop F1 while_{(i, j)}Each SR flip-flop F1 to prevent set input to_{(i, j)}Negative logic set terminal S bar has P-type MOS transistor P_{i, j}Drive voltage V via_CCHas been applied. In the front stage of the shift register 11a, the transistor P_1,1The start signal SP is applied to the gate of, and the transistor P of the remaining stage_{i, j}At the gate of the previous stage SR flip-flop F1_{(i, j-1)}Output S_{i, j-1}Is applied. As a result, the switch SW_{i, j}Transistor P while_{i, j}Is conducting, and the above set terminal S bar has a predetermined potential (in this case, the drive voltage V)._CC) Is fixed and set input is blocked. As a result, the start signal SP is transmitted without any trouble. For example, the final stage SR flip-flop F1_{(i, K)}After being reset, the clock signal CK_iIn the SR flip-flop F1 to which is not supplied, the clock signal CK is directly applied without going through the above switch SW._iMay be entered.

【0120】

In the above configuration, as shown in the first embodiment, the distance between the level shifter 13 and the SR flip-flop F1 is longer than that in the case where the level shifter 13 is provided for each SR flip-flop F1, but from a single level shifter. Compared with the conventional technique of supplying the clock signal CK to all SR flip-flops, the distance between the two can be shortened and the buffer can be reduced. Therefore, as in the first embodiment, the shift register 11a with low power consumption is used. realizable.

【0121】

Here, if the number of SR flip-flops F1 included in the block B is increased, the number of level shifters 13 included in the shift register 11a can be reduced, so that the circuit configuration can be simplified. On the other hand, if the number of SR flip-flops F1 is increased too much, the drive capacity of the level shifter 13 becomes insufficient and a buffer is required, so that the power consumption increases. Therefore, if the circuit scale is required to be reduced without increasing the power consumption too much, the level shifter 13 is not provided with a buffer._(i)Is the clock signal CK_(i)It is desirable to set the number of SR flip-flops F1 in each block B within the range that can supply.

【0122】

In the above embodiment, the case where the operation / stop of the level shifter 13 is controlled by the OR circuit G2 has been described as an example. However, as shown in FIG. 18, the level shifter 14 itself is OR as shown in FIG. The operation / stop may be determined based on each input signal to the circuit G2. For example, as shown in FIG. 19, the level shifter 14 can be realized by a circuit provided with each transistor N21 to P41 in the level shifter 24 shown in FIG. 14 in the same number as the inputs (K in this case).

【0123】

[Fourth Embodiment] Hereinafter, a case where a level shifter is provided for each of the plurality of D flip-flops will be described with reference to FIGS. 20 to 24. That is, as shown in FIG. 20, the shift register 21b according to the present embodiment is similar to the shift register 21 shown in FIG. 8, but N D flip-flops F2 are every K D flip-flops F2. Divided into multiple blocks B₁~ B_PIt is divided into. Further, a level shifter 23 is provided for each block B.

【0124】

Further, in the present embodiment, each block B_iEvery time, level shifter 23_(i)Control signal ENA_iOR circuit G3_(i)Is provided. The OR circuit G3_iIs an OR circuit with (K + 1) input, and block B_iD flip flop in F2_{(i, 1)}... F2_{(i, K)}Calculate the logical sum of each input / output of the above level shifter 23_(i)Output to. Here, the first stage D flip-flop F2_{(i, 1)}The input signal to is the block B in the front stage.₁Then, it is the start signal SP, and the block B from the second stage onward_iThen, block B in the previous stage_i-1Is the output signal of. In the OR circuit G3, for example, as shown in FIG. 21, in the OR circuit G1 shown in FIG. 12, the number of transistors P61 and the number of transistors N62 are increased to the number of inputs (K + 1 in this case). It can be realized by the circuit.

【0125】

As a result, as shown in FIG. 22, the block B_iD flip flop in F2_{(i, 1)}... F2_{(i, K)}One of the clock signals CK_iWhile requiring input of, i.e., block B_iD flip-flop F2 of the final stage from the time when the pulse input to_{(i, K)}Level shifter 23 until the end of pulse output_(i)Control signal to ENA_iBecomes a high level, level shifter 23_(i)Is the clock signal CK_iCan be output. In addition, the remaining period is the control signal ENA._iWill be low level, so level shifter 23_(i)Can stop operation.

【0126】

In the above configuration, the distance between the level shifter 23 and the D flip-flop F2 is longer than that in the case where the level shifter 23 is provided for each D flip-flop F2 as in the shift register 21 shown in the second embodiment, but it is simple. Compared with the conventional technique of supplying the clock signal CK from one level shifter to all D flip-flops, the distance between the two can be shortened and the buffer can be reduced, so that the power consumption is low as in the second embodiment. The shift register 21b can be realized.

【0127】

Further, as in the third embodiment, in the present embodiment, the number of level shifters 23 can be reduced as compared with the shift register 21. Furthermore, if the circuit scale is required to be reduced without increasing the power consumption too much, the level shifter 23 without providing a buffer._(i)Is the clock signal CK_iEach block B within the range that can be supplied_iIt is preferable to set the number of D flip-flops F2 in.

【0128】

Further, in FIG. 20, the case where the operation / stop of the level shifter 23 is controlled by the OR circuit G3 has been described as an example. However, as in the shift register 11b shown in FIG. 18, the level shifter is shown in the shift register 21c shown in FIG. The 25 itself may control operation / stop based on each input signal to the OR circuit G3. For example, as shown in FIG. 24, the level shifter 25 can be realized by a circuit provided with each transistor N21 to P41 in the level shifter 14 shown in FIG. 19 in the same number as the inputs (in this case, K + 1).

【0129】

[Fifth Embodiment] By the way, in the third (fourth) embodiment, the level shifter or the OR circuit logically ORs K, (K + 1) signals to control the operation / stop of the level shifter. The case was explained. On the other hand, in the present embodiment, a case where the operation / stop of the level shifter is controlled by using the latch circuit will be described with reference to FIGS. 25 to 29.

【0130】

Specifically, as shown in FIG. 25, in the shift register 11c according to the present embodiment, the OR circuit G2 of the shift register 11a shown in FIG. 15_(i)Instead of, latch circuit 31_(i)Is provided. The latch circuit 31 is the block B._iSR flip-flop F1 in the front stage of_{(i, 1)}Pulse input to, and SR flip-flop F1 in the final stage_{(i, K)}The level shifter 13 is configured to change the output by using the pulse output of the above as a trigger, and from the time when the pulse input is started to the time when the pulse output is started._(i)You can instruct the operation to.

【0131】

The latch circuit 31 is, for example, the first block B.₁As shown in FIG. 26, the start signal SP inverted by the inverter 31a is applied as the negative logic set signal S bar, and the final stage SR flip-flop F1 is used as the positive logic reset signal R._{(1, K)}Output S_1,KThe SR flip-flop 31b to which is applied is provided. In addition, block B from the next stage onward_iThen, instead of the start signal SP, block B in the previous stage_i-1Output is applied.

【0132】

In the above configuration, as shown in FIG. 27, the latch circuit 31_(i)Is the first SR flip-flop F1_{(i, 1)}From the time the input to is changed to a high level, the output S_{i, K}Control signal ENA until_iIs set to a high level. As a result, level shifter 13_(i)Is the clock signal CK during the period_iCan continue to be supplied. Also, output S_{i, K}When changes to a high level, the control signal ENA_iBecomes low level, level shifter 13_(i)Stops working. As a result, the shift register 11c with less power consumption than the conventional one can be realized as in the third embodiment.

【0133】

Further, the latch circuit 31 according to the present embodiment_(i)Is the OR circuit G2 of the third embodiment_(i)(Level shifter 14_(i)Level shifter 13 based on K signals as in)_(i)(14_(i)) Is different from the case of judging the operation / stop of block B_iRegardless of the number of stages K of the SR flip-flop F1 inside, the control signal ENA is triggered by two signals._iIs being generated. Therefore, the number of signal lines for transmitting the signal required for determination can be reduced to two. Here, when the number of signal lines for judgment increases, the output S_{i, j}And clock signals CK / CK_iThere is a risk that the number of intersections with the signal lines that transmit the signal will increase, and the capacity of each signal line will increase. However, in the present embodiment, since the number of signal lines for determination is reduced to two, it is possible to suppress an increase in wiring capacity due to the signal line for determination as compared with the third embodiment, and further, the power consumption is reduced. A small shift register 11c can be realized.

【0134】

In FIG. 26, the latch circuit 31_(i)Has been described as an example in which is composed of SR flip-flops, but the present invention is not limited to this. Level shifter 13 triggered by two signals_(i)If the operation / stop of the above latch circuit 31 can be controlled,_(i)Alternatively, for example, the latch circuit 32 shown in FIG. 28 can be used to obtain the same effect.

【0135】

The latch circuit 32 includes two D flip-flops 32a and 32b that form a two-divider, a start signal SP, and an output S._1,KA NOR circuit 32c that calculates the negation of the logical sum of, and an inverter 32d that inverts the output of the NOR circuit 32c are provided. The output Q of the D flip-flop 32a is input to the D flip-flop 32a via the D flip-flop 32b. In addition, the output L of the inverter 32d is attached to the D flip-flop 32a._SETIs applied as a clock, and the output of the NOR circuit 32c is applied as a clock to the D flip-flop 32b. Furthermore, the output L of the D flip-flop 32a_OUTIs the control signal ENA₁Is output as. As a result, as shown in FIG. 29, the latch circuit 32_(i)Is the above latch circuit 31_(i)Similar to the SR flip-flop F1 in the front stage_{(i, 1)}After the pulse input is started, the output S_{i, K}High-level control signal ENA until the rising point of_iOutput, level shifter 13_(i)You can instruct the operation.

【0136】

In this embodiment, the SR flip-flop F1 in the front stage is used as a trigger for the latch circuit (31/32)._{(i, 1)}Start of pulse input to and final stage SR flip-flop F1_{(i, K)}The start of the pulse output of is used, but the present invention is not limited to this. Block B_iSR flip-flop F1 in the clock signal CK_iControl signal ENA at a timing before the required period_iThe signal that can be actively set and the control signal ENA at the timing after the period_iThe same effect can be obtained by using a signal that can be set to be inactive as a trigger.

【0137】

[Sixth Embodiment] In the present embodiment, a configuration in which the operation / stop of the level shifter is controlled by the latch circuit in the shift register using the D flip-flop will be described with reference to FIGS. 30 to 34.

【0138】

That is, in the shift register 21d according to the present embodiment, the OR circuit G3 of the shift register 21b shown in FIG. 20_(i)Instead of, the latch circuit 31 shown in FIG._(i)D flip-flop F2 in the front stage_{(i, 1)}Pulse input to and the final stage D flip-flop F2_{(i, K)}Latch circuit 33 triggered by the pulse output of_(i)Is provided. However, as described above, in the case of the D flip-flop, the final stage D flip-flop F2_{(i, K)}Clock signal CK until_iIs required, so the above latch circuit 33_(i)Is the level shifter 23 from the time when the pulse input is started to the time when the pulse output is stopped._(i)It is configured to instruct the operation to.

【0139】

Specifically, the latch circuit 33 is the first block B.₁For example, as shown in FIG. 31, in addition to the latch circuit 31 shown in FIG. 26, the output signal L_OUTAnd the output S of the final stage_1,KIt is equipped with a NOR circuit 33c that calculates the negation of the logical sum with and an inverter 33d that inverts the calculation result. In addition, block B from the next stage onward_iThen, instead of the start signal SP, block B in the previous stage_i-1Output is applied.

【0140】

In the above configuration, as shown in FIG. 32, the latch circuit 33₍₁₎Is the first D flip-flop F2_(1,1)From the time the input to is changed to a high level, the output S_1,KControl signal ENA until₁Is set to a high level. As a result, level shifter 23₍₁₎Is the clock signal CK during the period₁Can continue to be supplied. Also, output S_1,KWhen changes to low level, the control signal ENA₁Becomes low level, level shifter 23₍₁₎Stops working. As a result, the shift register 21d with less power consumption than the conventional one can be realized as in the fourth embodiment.

【0141】

Further, in the present embodiment, as in the fifth embodiment, the number of signal lines required for determining the operation / stop of the level shifter 23 can be reduced, so that the signal line for determination is more important than in the fourth embodiment. An increase in wiring capacity can be suppressed, and a shift register 21d with low power consumption can be realized.

【0142】

In FIG. 31, the case where the latch circuit 33 is composed of SR flip-flops has been described as an example, but the present invention is not limited to this. If the operation / stop of the level shifter 13 can be controlled by using two signals as triggers, the above latch circuit 31_(i)Alternatively, for example, the latch circuit 34 shown in FIG. 33 can be used to obtain the same effect.

【0143】

In the latch circuit 34, the NOR circuit 33c and the inverter 33d shown in FIG. 31 are added to the latch circuit 32 shown in FIG. 28. As a result, as shown in FIG. 34, the latch circuit 34 has the same block B as the latch circuit 33._iD flip-flop F2 in the front stage of_{(i, 1)}From the time when the pulse input to is started, the final stage D flip-flop F2_{(i, K)}High level control signal ENA until the end of pulse output_iOutput, level shifter 23_(i)You can instruct the operation.

【0144】

In this embodiment, the frontmost D flip-flop F2 is used as a trigger for the latch circuit (33 to 34)._{(i, 1)}Start of pulse input to and final stage D flip-flop F2_{(i, K)}The end of the pulse output of is used, but it is not limited to this. Block B_iD flip-flop F2 in the clock signal CK_iControl signal ENA at a timing before the required period_iThe signal that can be actively set and the control signal ENA at the timing after the period_iThe same effect can be obtained by using a signal that can be set to be inactive as a trigger.

【0145】

[7th Embodiment] In the following, referring to FIG. 35, the level shifters 23 (24, 25) supply the clock signal CK to the plurality of D flip-flops F2 as in the fourth and sixth embodiments. The configuration in which the power consumption can be further reduced in the shift registers 21b to 21d will be described.

【0146】

Specifically, the shift register according to the present embodiment has the same configuration as the shift registers 21b to 21d, but each D flip-flop F2._{(i, j)}Clock signal control circuit 26 for each_{(i, j)}Is provided, level shifter 23_(i)(24_(i)、25_(i): Below, 23_(i)(Represented by) is the clock signal CK after boosting only to the D flip-flop F2 that requires clock input._(i)Is supplying.

【0147】

The above clock signal control circuit 26_{(i, j)}Is the clock signal CK, as shown in Figure 35._iSwitch SW1 provided on the signal line to which_{(i, j)}And the clock signal CK_iInversion signal CK_iSwitch SW2 provided on the transmission line of the bar_{(i, j)}And have. Both switches SW1_{(i, j)} SW2_{(i, j)}Is the level shifter 23 shown in Figure 8._{(i, j)}Similar to D flip-flop F2_{(i, j)}OR circuit G1 that calculates the logical sum of input and output of_{(i, j)}Controlled by D flip-flop F2_{(i, j)}Is the clock signal CK_i(CK_iIt conducts when bar) is needed and is cut off when clock input is not needed. In addition, the clock signal control circuit 26_{(i, j)}D flip-flop F2_{(i, j)}N-type MOS transistor N71 provided between the clock input terminal and the ground potential of_{(i, j)}And D flip-flop F2_{(i, j)}Inverted clock input terminal and drive voltage V_CCP-type MOS transistor P72 provided between_{(i, j)}And are provided. Transistor N71_{(i, j)}At the gate of, OR circuit G1_{(i, j)}Output is inverter INV71_{(i, j)}It is applied after being inverted by, and the above transistor P72_{(i, j)}At the gate of, OR circuit G1_{(i, j)}Output is applied.

【0148】

In the above configuration, the corresponding D flip-flop F2_{(i, j)}Is the clock signal CK after boosting_i(CK_iBar) for the required period, switch SW1 above_{(i, j)}(SW2_{(i, j)}) Conducts and the D flip-flop F2_{(i, j)}Clock signal CK_i(CK_iBar) is applied. On the other hand, during the period when clock input is unnecessary, the above switch SW1_{(i, j)} SW2_{(i, j)}Is blocked, for example, D flip-flop F2_{(i, j)}Etc., both switches SW1_{(i, j)} SW2_{(i, j)}Subsequent circuits and level shifter 23_(i)Separate from. Furthermore, during the period when clock input is unnecessary, both transistors N71 described above_{(i, j)} P72_{(i, j)}Conducted, D flip-flop F2_{(i, j)}Since the clock input terminal and the inverting input terminal of are maintained at predetermined values (low level and high level), respectively, unlike the case where both input terminals are indefinite, the D flip-flop F2_{(i, j)}It is possible to suppress the malfunction of.

【0149】

According to the above configuration, both switches SW1 during the period when clock input is not required._{(i, j)} SW2_{(i, j)}Subsequent circuits and level shifter 23_(i)Level shifter 23_(i)Is the clock signal CK at the moment_(i)D flip flops that require F2_{(i, j)}You only have to drive. Therefore, block B_iAll D flip flops in F2_{(i, 1)}~ F2_{(i, K)}Level shifter 23 compared to driving_(i)The load capacity of the device can be significantly reduced, and the power consumption can be reduced. As a result, a shift register with low power consumption can be realized.

【0150】

In the above, D flip-flop F2_{(i, j)}Clock signal control circuit 26 for each_{(i, j)}Although the case where is provided is described as an example, the description is not limited to this, and for example, a clock signal control circuit 26 may be provided for each of a plurality of D flip-flops F2. In this case, both switches SW1 and SW2 are used while the D flip-flop F2 connected to both switches SW1 and SW2 requires a clock input, that is, after the pulse input to the frontmost D flip-flop F2 is started. , The same as the OR circuit G3 shown in FIG. 20 and the latch circuit 33 (34) shown in FIG. 30 (FIG. 33) so that the D flip-flop F2 in the final stage can conduct air until the pulse output is completed. It is controlled by the circuit. In this case, the load capacitance of the level shifters 23 (24, 25) is larger than that of the configuration in which the clock signal control circuit 26 is provided for each D flip-flop F2, but the number of clock signal control circuits 26 can be reduced. The circuit configuration can be simplified.

【0151】

[Eighth Embodiment] By the way, for example, in the data signal line drive circuit 3 and the scanning signal line drive circuit 4 shown in FIG. 2, the shift registers (11 11a to 11c 21 21a to 21d) according to each of the above embodiments are used. The output of each stage of) may be used directly as a signal indicating the timing, but a signal obtained by logically operating the output of a plurality of stages may be used as a timing signal.

【0152】

In the following, FIGS. 36 and 37 are shown for configurations suitable for logically operating the outputs of a plurality of stages in a shift register using the SR flip-flop F1, as in the first, third, and fifth embodiments. It will be explained with reference to it. The configuration using the SR flip-flop F1 can be applied to other embodiments, but the case of the first embodiment will be described below as an example.

【0153】

That is, the shift register 11d according to the present embodiment has two outputs S adjacent to each other in addition to the configuration of the shift register 11 shown in FIG._i S_{i + 1}The logical product of is calculated, and the calculation result is the timing signal SMP._iAND circuit G4 to output as_(i)It has. Furthermore, the SR flip-flop F1 in the front stage₍₁₎SR flip-flop F1 in front of₍₀₎Is provided, and the SR flip-flop F1₍₀₎Output S₀And output S₁AND circuit G4 that calculates and outputs the logical product of₍₀₎Is provided. Also, SR flip-flop F1₍₀₎As a set signal of negative logic, the inverted signal SP bar of the start signal SP is applied to the SR flip-flop F1.₍₀₎The output of is the next level shifter 13₍₁₎Control signal ENA₁Is entered as. SR flip-flop F1₍₀₎Is the SR flip-flop F1 of the other stage_(i)Similarly, the level shifter 13 after the number of stages (in this case, 2 stages) according to the pulse width of the pulse signal to be transmitted.₍₂₎Output CK₂Is applied.

【0154】

Here, each SR flip-flop F1₍₀₎, F1₍₁₎... output S₀, S₁Of the ..., output S₀Only single AND circuit G4₍₀₎Is connected to the other output S_iIs two AND circuits G4_(i-1) G4_(i)Is connected to. As a result, SR flip-flop F1₍₀₎And the remaining SR flip-flop F1_(i)The output load is different, and even if it is driven at the same timing, the output S₀And the residual output S₁...The delay times for the clock signal CK are different from each other. Therefore, when the frequency of the clock signal CK is high, the AND circuit G4 described above is used to suppress timing variation due to a delay time shift.₍₀₎The output signal of is a dummy signal DUMMY that is not used in the subsequent circuit, and the remaining AND circuit G4₍₁₎... output SMP₁Only ... is used for video signal extraction.

【0155】

In the above configuration, SR flip-flop F1₍₀₎Unlike the other stages, the inverted signal SP bar that is not synchronized with the clock signal CK is applied as a negative logic set signal, so the output S₀Timing (rise, pulse width, etc.) of other SR flip-flops F1₍₁₎... output S₁... is different. However, as mentioned above, the output S₀Is not used as a dummy signal DUMMY in the subsequent circuit. Therefore, the output S₀Even if the timing of is different, the shift register 11d does not cause any problem, and the timing signal SMP with different timing is used for each predetermined time.₁... can be output.

【0156】

Further, in the above configuration, SR flip-flop F1₍₀₎The inversion signal SP bar is applied to, and the level shifter 13 is omitted. Therefore, SR flip-flop F1₍₀₎The number of level shifters 13 can be reduced as compared with the case where the level shifters 13 are also provided.

【0157】

In the first to eighth embodiments described above, the case where the level shifters (13, 14, 23 to 25) are of the current drive type has been described as an example, but as shown in FIG. 38, the voltage drive type level shifter 41 is used. You may use it. As an input switching element, the level shift unit 41a of the level shifter 41 is conducted / cut off according to the N-type MOS transistor N81 which is conducted / cut off according to the clock signal CK and the inverted signal CK bar of the clock signal CK. It is equipped with an N-type MOS transistor N82. The drive voltage V is connected to the drain of each transistor N81 (N82) via a P-type MOS transistor P83 (P84) that serves as a load._CCIs applied, and the sources of both transistors N81 and N82 are grounded. Further, the potential at the connection point of the transistors N82 and P84 is output as the output OUT of the level shifter 41 and is applied to the gate of the transistor P83. Similarly, the potential at the connection point of the transistors N81 and P83 is output as the inverted output OUT bar of the level shifter 41 and is applied to the gate of the transistor P84.

【0158】

On the other hand, the level shifter 41 is provided with N-type MOS transistors N91 and N92 as input release switch portions (switches) 41b, and while the level shifter 41 is operating, the gate of the transistor N81 is passed through the transistor N91. The clock signal CK is applied, and the inverted signal CK bar of the clock signal CK is applied to the gate of the transistor N82 via the transistor N92.

【0159】

Further, the level shifter 41 is provided with an N-type MOS transistor N93 and a P-type MOS transistor P94 as an input stabilizer 41c. As a result, while the level shifter 41 is stopped, the gate of the transistor N81 is grounded via the transistor N93, and the drive voltage V is connected to the gate of the transistor N82 via the transistor P94._CCIs applied. The input stabilizing unit 41c corresponds to the output stabilizing means described in the claims, and controls the input voltage to both transistors N81 and N82 to stabilize the output. Here, since the level shifter 41 is a voltage-driven type and consumes power only when the output OUT is changed, power consumption does not occur even if the output voltage is controlled by the input voltage when the level shifter 41 is stopped.

【0160】

In the present embodiment, when the control signal ENA is at a high level, the operation of the level shifter 41 is shown. Therefore, the control signal ENA is applied to the gates of the transistors N91, N92, and P94, and the control signal is applied to the transistor N93. ENA is applied after being inverted by the inverter INV91.

【0161】

In the above configuration, when the control signal ENA is at a high level, the transistors N91 and N92 conduct, and the transistors N81 and N82 conduct / cut off according to the clock signal CK and its inverting signal CK bar. As a result, the output OUT has a drive voltage V when the clock signal CK is at a high level._CCIt is boosted to the level of, and in the case of low level, it becomes the ground level.

【0162】

On the contrary, when the control signal ENA is at a low level, the transistors N93 and P94 are conducted, so that the transistor N81 is interrupted and the transistor N82 is conducted. As a result, the output OUT is kept at the ground level, and the inverting output OUT bar has a drive voltage of V._CCIs maintained at. Further, in this state, since both transistors N91 and N92 are cut off, the gate of the transistor N81 (N82) as an input switching element is separated from the transmission line of the clock signal CK (CK bar). Thereby, for example, the load capacity and power consumption of the drive circuit of the clock signal CK (CK bar) such as the control circuit 5 shown in FIG. 2 can be reduced.

【0163】

In FIG. 38, as in the case of the level shifters 13 and 23, the case where the operation / stop is controlled by one control signal ENA has been described as an example. However, as in the above level shifters 14 and 24 and 25, the transistors N91 to P94 and so on have been described. If the number of inverters INV91 is increased according to the number of control signals ENA, operation / stop can be controlled by a plurality of control signals ENA.

【0164】

Even when the level shifter 41 having the above configuration is used, since a plurality of level shifters 41 are provided and at least one of the level shifters 41 that do not require clock output is stopped, a single level shifter goes to all flip-flops of the shift register. Compared with the case of supplying a clock signal, the load capacity of each level shifter can be reduced, and the power consumption of the shift register can be reduced.

【0165】

However, the current-driven level shifter 13 (14, 23 to 25: hereinafter, represented by the level shifter 13) shown in the first to eighth embodiments is always sent to the input switching element (P11, P12) during operation. Since the current is flowing, even if the amplitude of the clock signal CK is lower than the threshold value of the input switching elements (transistors N81 / N82) and the level shifter 41 cannot operate, the clock signal CK is boosted without any problem. it can. Further, since the level shifter 13 is stopped according to the necessity of clock output, the power consumption is increased even though there are a plurality of level shifters 13 that consume power even when the output is not changed. Can be suppressed. Therefore, it is preferable to use the current-driven level shifter 13.

【0166】

In the third to seventh embodiments, the case where the level shifters (13, 14, 23 to 25) are provided for each of K flip-flops (F1 and F2) has been described as an example, but there are a plurality of shift registers. If the blocks are divided into blocks and a level shifter is provided for each block, substantially the same effect can be obtained even if the number of flip-flops contained in each block is not the same.

【0167】

Further, in each of the above embodiments, an image display device has been described as an example of application of the shift register, but the present invention provides an application in which a clock signal CK having an amplitude lower than the drive voltage of the shift register is given. The shift register can be widely applied. However, since there is a strong demand for improving the resolution and expanding the display area in the image display device, it is often the case that the number of stages of the shift register is large and the driving capacity of the level shifter cannot be sufficiently secured. Therefore, it is particularly effective when applied to the drive circuit of an image display device. [0168]

[Effect of the invention]

As described above, the shift register according to the present invention is divided into a plurality of blocks in which the flip-flop is composed of at least one flip-flop, and the level shifter for boosting the clock signal having an amplitude smaller than the drive voltage is provided for each block. At least one of the plurality of level shifters corresponding to the block corresponding to the block that does not require the input of the clock signal for the transmission of the input pulse at that time is stopped.

【0169】

In this configuration, since the shift register is provided with a plurality of level shifters, the distance from each level shifter to the flip-flop can be shortened. Also, at least one of the plurality of level shifters has stopped operating. As a result, it is possible to realize a shift register that can operate with a low-voltage clock signal input and has low power consumption.

【0170】

In the above configuration, the shift register according to the present invention has a configuration in which each of the above level shifters operates only during a period in which a flip-flop that requires input of a clock signal at that time is included in the corresponding block.

【0171】

According to this configuration, since only the level shifter required for the transmission of the input pulse operates, the power consumption of the shift register can be significantly reduced as compared with the case where other level shifters operate.

【0172】

In the shift register according to the present invention, in the above configuration, the specific level shifter corresponding to the specific block among the above blocks starts operating when the pulse input to the specific block is started, and the final stage of the specific block. The operation is stopped after the set / reset / flip-flop of is set.

【0173】

According to this configuration, the specific level shifter stops operating when it is not necessary to input the clock signal to the set reset flip-flop of the specific block. As a result, the power consumption can be reduced in the level shifter that can operate at a higher speed than the case where the flip-flop is a D flip-flop.

【0174】

In the above configuration, when the shift register according to the present invention has one set / reset / flip-flop in the specific block, the specific level shifter operates when the pulse input to the specific block is started. The configuration is such that the operation is stopped when the pulse input is completed.

【0175】

According to this configuration, the operation / stop of the specific level shifter can be controlled by using the output itself of the flip-flop in the previous stage, which has the effect of simplifying the configuration of the shift register.

【0176】

In the shift register according to the present invention, when there are a plurality of flip-flops in the specific block in the above configuration, the specific level shifter excludes the final stage in the specific block while the pulse is input to the specific block. It is a configuration that operates while one of the flip-flops outputs a pulse.

【0177】

According to this configuration, the operation / stop of the specific level shifter can be controlled based on the input to the specific block and the output of the flip-flop in the specific block, so that a simple and fast shift register can be realized. ..

【0178】

In the shift register according to the present invention, when there are a plurality of flip-flops in the specific block in the above configuration, the specific level shifter has a signal input to the specific block and an output signal of the flip-flop in the final stage of the specific block. The configuration includes a latch circuit that changes the output according to the above.

【0179】

According to this configuration, the output of the latch circuit is changed based on the two signals that trigger the operation / stop of the specific level shifter, and the operation / stop of the specific level shifter is controlled, so that even if the number of flip-flops is large. It has the effect of realizing a shift register with a simple circuit configuration.

【0180】

In the shift register according to the present invention, in the above configuration, the specific block includes a D flip-flop, and the specific level shifter starts operation when the pulse input to the specific block is started, and the final stage of the specific block. The operation is stopped after the flip-flop finishes the pulse output.

【0181】

According to this configuration, the specific level shifter supplies the clock signal after the level shift during the period required for the D flip-flop of the specific block to operate, and when the input of the clock signal to the D flip-flop is unnecessary. Since the operation is stopped, there is an effect that input pulses having different pulse widths can be transmitted and a shift register with low power consumption can be realized.

【0182】

In the above configuration, the shift register according to the present invention includes a plurality of D flip-flops in the specific block, and the specific level shifter includes a signal input to the specific block and an output signal of the flip-flop in the final stage of the specific block. The configuration includes a latch circuit that changes the output according to the above.

【0183】

According to this configuration, the output of the latch circuit changes based on the two signals, and the operation / stop of the specific level shifter is controlled. Therefore, even if the number of flip-flops in the specific block is large, the circuit configuration of the shift register can be changed. It has the effect of being simplified.

【0184】

In the shift register according to the present invention, in the above configuration, the level shifter includes a current-driven level shift unit in which the input switching element to which the clock signal is applied is always conductive during operation.

【0185】

According to this configuration, at least one of the current-driven level shifters stops operating, so that level shift is possible even when the amplitude of the clock signal is lower than the threshold voltage of the input switching element, and power consumption is consumed. It has the effect of realizing a shift register with a small number of.

【0186】

The shift register according to the present invention has a shift register having the above configuration, in which an input signal control unit is provided to give a signal at a level cut off by the input switching element to the level shift unit to stop the level shifter. Is.

【0187】

According to this configuration, the input signal control unit controls the level of the input signal to shut off the input switching element, so that the power consumption can be reduced by the amount of the current flowing to the input switching element during operation during stop. It plays the effect.

【0188】

In the above configuration, the shift register according to the present invention includes a power supply control unit that stops the power supply to the level shift unit and stops the level shifter.

【0189】

According to this configuration, since the power supply to each level shift unit is stopped and the level shifter is stopped, the power consumption can be reduced by the amount of power consumed by the level shifter during stoppage and operation. ..

【0190】

In each of the above configurations, the shift register according to the present invention has a configuration in which the level shifter is provided with an output stabilizing means for maintaining an output voltage at a predetermined value when stopped.

【0191】

According to this configuration, the output voltage of the level shifter is maintained at a predetermined value by the output stabilizing means while the level shifter is stopped, so that malfunction of the flip-flop due to an indefinite output voltage can be prevented, and more. It has the effect of realizing a stable shift register.

【0192】

The shift register according to the present invention has a configuration in which a switch is provided between the level shift unit and the transmission line of the clock signal in each of the above configurations while the level shifter is stopped.

【0193】

In this configuration, the input switching element connected to the clock signal line is limited to that of the operating level shifter, so that the load capacitance of the clock signal line can be reduced and the power consumption of the circuit that drives the clock signal line can be reduced. It has the effect of being able to do it.

【0194】

As described above, the image display device according to the present invention has a configuration in which at least one of the data signal line drive circuit and the scanning signal line drive circuit includes a shift register having any of the above configurations.

【0195】

According to this configuration, since at least one of the data signal line drive circuit and the scanning signal line drive circuit is provided with the shift registers having the above configurations, it is possible to realize an image display device with low power consumption.

【0196】

In the image display device according to the present invention, in the above configuration, the data signal line drive circuit, the scanning signal line drive circuit, and each pixel are formed on the same substrate.

【0197】

According to this configuration, even if the number of data signal lines and the number of scanning signal lines increase, the number of signal lines to be taken out of the substrate does not change, so that an undesired increase in the capacitance of each signal line can be prevented. , It has the effect of preventing a decrease in the degree of integration.

【0198】

In the above configuration, the image display device according to the present invention includes the data signal line drive circuit, the scanning signal line drive circuit, and each pixel including a switching element made of a polycrystalline silicon thin film transistor.

【0199】

In this configuration, the data signal line drive circuit, the scanning signal line drive circuit, and each pixel all include a switching element made of a polycrystalline silicon thin film transistor, so that the image consumes less power and has a large display area. It has the effect of realizing a display device.

【0200】

In the above configuration, the image display device according to the present invention includes the data signal line drive circuit, the scanning signal line drive circuit, and each pixel including a switching element manufactured at a process temperature of 600 degrees or less.

【0201】

According to this configuration, even if a normal glass substrate (glass substrate with a distortion point of 600 degrees or less) is used, warpage and deflection due to the process above the distortion point do not occur, so that mounting is easier and more. It has the effect of realizing an image display device with a wide display area.

[Simple explanation of drawings]

[Figure 1]

An embodiment of the present invention is shown, and it is a block diagram which shows the main part structure of the shift register which is configured including the set reset flip-flop.

[Figure 2]

It is a block diagram which shows the main part structure of the image display apparatus using the shift register.

[Fig. 3]

It is a circuit diagram which shows the structural example of a pixel in the said image display device.

[Fig. 4]

It is a timing chart which shows the operation of the shift register.

[Fig. 5]

It is a circuit diagram which shows the structural example of the set reset flip-flop used in the said shift register.

[Fig. 6]

It is a timing chart which shows the operation of the said set reset flip-flop.

[Fig. 7]

It is a circuit diagram which shows the structural example of the level shifter in the said shift register.

[Fig. 8]

It shows another embodiment of this invention, and is the block diagram which shows the main part structure of the shift register which is configured including D flip-flop.

[Fig. 9]

It is a timing chart which shows the operation of the shift register.

[Fig. 10]

It is a circuit diagram which shows the structural example of the said D flip-flop.

[Fig. 11]

It is a timing chart which shows the operation of the said D flip-flop.

[Fig. 12]

It is a circuit diagram which shows the structural example of the OR circuit used in the said shift register.

[Fig. 13]

It is a block diagram which shows the modification of the shift register.

[Fig. 14]

It is a circuit diagram which shows the structural example of the level shifter in the said shift register.

[Fig. 15]

It shows still another embodiment of this invention, and is the block diagram which shows the shift register which provided the level shifter for each of a plurality of set reset flip-flops.

[Fig. 16]

It is a circuit diagram which shows the structural example of the OR circuit used in the said shift register.

[Fig. 17]

It is a timing chart which shows the operation of the shift register.

[Fig. 18]

It is a block diagram which shows the modification of the shift register.

[Fig. 19]

It is a circuit diagram which shows the structural example of the level shifter in the said shift register.

[Fig. 20]

Another embodiment of the present invention is shown, and is a block diagram showing a shift register in which a level shifter is provided for each of a plurality of D flip-flops.

[Fig. 21]

It is a circuit diagram which shows the structural example of the OR circuit used in the said shift register.

[Fig. 22]

It is a timing chart which shows the operation of the shift register.

[Fig. 23]

It is a block diagram which shows the modification of the shift register.

[Fig. 24]

It is a circuit diagram which shows the structural example of the level shifter in the said shift register.

[Fig. 25]

It shows still another embodiment of the present invention, and is a block diagram showing a shift register including a latch circuit for controlling the operation of a level shifter, and a set reset flip-flop.

[Fig. 26]

It is a block diagram which shows the structural example of the said latch circuit.

[Fig. 27]

It is a timing chart which shows the operation of the shift register.

[Fig. 28]

It is a block diagram which shows the other structural example of the said latch circuit.

[Fig. 29]

It is a timing chart which shows the operation of the said latch circuit.

[Fig. 30]

Another embodiment of the present invention is shown, and is a block diagram showing a shift register including the latch circuit and a D flip-flop.

[Fig. 31]

It is a block diagram which shows the structural example of the said latch circuit.

[Fig. 32]

It is a timing chart which shows the operation of the shift register.

[Fig. 33]

It is a block diagram which shows the other structural example of the said latch circuit.

[Fig. 34]

It is a timing chart which shows the operation of the said latch circuit.

[Fig. 35]

It shows still another embodiment of this invention, and is the circuit diagram which shows the clock signal control circuit provided when the level shifter of each block selectively supplies a clock signal to the D flip-flop in the block.

[Fig. 36]

Another embodiment of the present invention is shown, and it is a block diagram which shows the main part structure of the shift register.

[Fig. 37]

It is a timing chart which shows the operation of the shift register.

[Fig. 38]

A modification of the present invention is shown, and is a circuit diagram showing a voltage-driven level shifter.

[Fig. 39]

A conventional example is shown, and it is a block diagram which shows a shift register including a level shifter.

[Explanation of symbols]

1 Image display device 3 Data signal line drive circuit 4 Scanning signal line drive circuit 11 11a ~ 11d 21 21a ~ 21c Shift register 13 14 23 ~ 25 41 Level shifter 13a 14a 23a ~ 25a 41a Level shift section 13b 14b 23b ~ 25b Power supply control unit 13c / 14c / 23c ~ 25c Input control unit (switch) 13d / 14d Input switching element cutoff control unit (input signal control unit) 13e 14e 23e ~ 25e Output stabilizer (output stabilizer) 23d ~ 25d Input switching element cutoff control unit (input signal control unit) 31 ~ 34 Latch circuit 41b Input release switch (switch) 41c Input stabilizer (output stabilizer) B₁... block (specific block) F1₍₁₎... SR flip-flops (flip-flops) F2₍₁₎... D Flip-Flop (Flip-Flop) P11 / P12 transistor (input switching element) PIX pixels