Semiconductor device and its configuration

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a semiconductor device having a replica circuit for monitoring the critical path delay of the semiconductor circuit and a method thereof.

【0002】

[Conventional technology]

In recent years, in semiconductor circuits, the power supply voltage is V in order to reduce power consumption._DDThe method of lowering is generally taken. This is because the AC component of the power consumption of a semiconductor circuit (LSI) is proportional to the square of the power supply voltage, so lowering the power supply voltage is the most effective way to reduce the power consumption of the LSI.

【0003】

From this point of view, in recent years, a method of dynamically controlling the power supply voltage with respect to the operating frequency of the LSI, process variation, etc., and always supplying the minimum voltage has been reported.

【0004】

In the control circuit that adopts such a method, design a replica circuit that has the same power supply voltage-delay characteristics as the critical path of the LSI, and set the power supply voltage so that the delay of the replica circuit does not exceed one cycle of the operating frequency. Control.

【0005】

Then, as shown in FIG. 23, usually, some delay element 2 from the critical path of the chip is added as a margin to the replica circuit 1, and in order to guarantee the operation, a delay larger than the delay of the critical path is obtained.

【0006】

[Problems to be Solved by the Invention]

However, since the conventional device described above creates a fixed delay margin, it is necessary to set a larger margin value in order to guarantee the deviation between the design and the actual device and the required margin. It disappears. In addition, the margin is smaller than expected and there is a possibility of malfunction.

【0007】

Further, when the replica or the margin delay part is simply configured by the transistor gate according to the delay value, as shown in FIG. 24, like the RC delay based on the wiring resistance R and the wiring capacitance C included in the actual device. Due to the effect of delay characteristics different from transistors, there is a possibility that the critical path and tracking of the chip cannot be obtained due to changes in delay due to voltage or temperature. If the delay element is built as in the conventional case, it cannot be adjusted after the chip is manufactured, and if there is a problem with the delay value, it is necessary to remake it by changing the design. In addition, RC delay and memory delay are generally custom-designed, and there is a problem that efficiency is deteriorated because a design method such as normal automatic placement and wiring cannot be used for replica unit design.

【0008】

Therefore, there has been a need for a replica circuit configuration that is more reliable and can be designed flexibly and efficiently.

【0009】

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device and a method thereof capable of constructing a replica circuit with high reliability, flexibility and efficiency.

【0010】

[Means for solving problems]

In order to achieve the above object, the present invention is a semiconductor device having a semiconductor circuit having a transmission path and a replica circuit for monitoring the delay time of the critical path of the semiconductor circuit, and the input side and the output of the replica circuit. It has a delay element that is located at least one of the sides and whose delay value is adjustable.

【0011】

Further, the semiconductor device of the present invention is composed of a semiconductor circuit having a transmission path and a circuit having a power supply voltage-delay characteristic equivalent to the transmission path adopted as the critical path of the semiconductor circuit, and propagates a reference signal. A replica circuit that monitors the critical path of the semiconductor circuit, a delay element that is arranged at least between the input side and the output side of the replica circuit and whose delay amount can be adjusted, and a monitor of the replica circuit. It has a voltage control circuit that generates a power supply voltage having a value based on the result and supplies the power supply voltage to the semiconductor circuit and the replica circuit.

【0012】

Further, the present invention is a semiconductor device having a semiconductor circuit having a transmission path and a replica circuit for monitoring the delay time of the critical path of the semiconductor circuit, wherein the replica circuit is a delay element whose delay value can be adjusted. Has.

【0013】

Further, the present invention is a semiconductor device having a semiconductor circuit having a transmission path and a replica circuit that propagates a reference signal and monitors the delay time of the critical path of the semiconductor circuit. The replica circuit is a delay element. A plurality of replica units including the above, a connection selection means for connecting the plurality of replica units in parallel or in series with respect to the input of the reference signal in response to the selection signal, and a delay amount from the outputs of the plurality of replica units. It has a selection means for selecting the output signal of the delay element having a large value as a monitor signal.

【0014】

Further, the semiconductor device of the present invention has a semiconductor circuit having a transmission path and a delay element having a power supply voltage-delay characteristic equivalent to the transmission path adopted as the critical path of the semiconductor circuit, and the delay value can be adjusted. A replica circuit that propagates a reference signal to monitor the critical path of the semiconductor circuit and a power supply voltage having a value based on the monitoring result of the replica circuit are generated and supplied to the semiconductor circuit and the replica circuit. It has a voltage control circuit.

【0015】

Further, the semiconductor device of the present invention has a semiconductor circuit having a transmission path and a power supply voltage-delay characteristic equivalent to the transmission path adopted as the critical path of the semiconductor circuit, and a plurality of replica units including a delay element. A connection selection means that receives the selection signal and connects the plurality of replica units in parallel or in series with respect to the input of the reference signal, and an output of a delay element having a larger delay amount from the outputs of the plurality of replica units. It has a selection means for selecting a signal as a monitoring signal, and generates a replica circuit that propagates a reference signal to monitor the critical path of the semiconductor circuit and a power supply voltage having a value based on the monitoring result of the replica circuit. The semiconductor circuit and the voltage control circuit supplied to the replica circuit are provided.

【0016】

Further, in the present invention, the delay element includes delay elements having different delay characteristics, and the delay value can be adjusted by setting. Further, the different delay characteristics of the delay elements are the delay characteristic of the transistor gate, the RC delay characteristic based on the wiring resistance R and the wiring capacitance C, and the delay characteristic of the memory.

【0017】

Further, the present invention has a register and means for adjusting the delay value of the adjustable delay element based on the setting data in the register.

【0018】

Further, in the present invention, the connection selection means connects the plurality of replica units in parallel or in series based on the setting data in the register.

【0019】

Further, the present invention has an input terminal for an external signal and means for adjusting the delay value of the adjustable delay element based on the external signal input to the input terminal.

【0020】

Further, in the present invention, the connection selection means connects the plurality of replica units in parallel or in series based on an external signal input to the input terminal.

【0021】

Further, in the present invention, the delay elements having different delay characteristics are standardized, and the adjustable delay element, the replica circuit, or both of them are arranged in the standard cells of the delay elements. ..

【0022】

Further, the present invention is a method for configuring a semiconductor device having a semiconductor circuit having a transmission path and a replica circuit for monitoring the delay time of the critical path of the semiconductor circuit, wherein a delay element having an adjustable delay value is provided. A value that is arranged in at least one of the input side and the output side of the replica circuit including the inside of the replica circuit, and the delay value of the delay element is set to a value that operates with a margin in the critical path delay of the semiconductor circuit after manufacturing. Adjust to.

【0023】

Further, the present invention is a method for configuring a semiconductor device having a semiconductor circuit having a transmission path and a replica circuit for monitoring the delay time of the critical path of the semiconductor circuit, and the delay value of the replica circuit can be adjusted. After manufacturing, the delay value of the delay element is adjusted to a value that operates with a margin for the critical path delay of the semiconductor circuit.

【0024】

Further, the present invention is a method for configuring a semiconductor device having a semiconductor circuit having a transmission path and a replica circuit for monitoring the delay time of the critical path of the semiconductor circuit, wherein the replica circuit is made of a plurality of delay elements. The connection form can be changed, and after manufacturing, the plurality of delay elements are connected in parallel or in series, and the delay value of the replica circuit is adjusted to a value that operates with a margin for the critical path delay of the semiconductor circuit. ..

【0025】

Further, in the present invention, the delay element is formed so that the delay value can be adjusted, and the delay value of the delay element is set after manufacturing.

【0026】

According to the present invention, the replica circuit is configured as a circuit having a delay characteristic equivalent to the path selected as the critical path in the semiconductor circuit, and the delay can be adjusted to either the input side or the output side of the replica circuit. The element is provided. Then, for example, after manufacturing the chip, the delay value of the delay element based on the register or the external signal ensures that the replica system including the replica circuit operates with a margin in the critical path delay of the semiconductor circuit (LSI). Adjusted to value.

【0027】

Further, according to the present invention, the replica circuit has a delay characteristic equivalent to that of a path selected as a critical path in a semiconductor circuit, for example, and is composed of at least one adjustable delay element. Then, for example, after manufacturing the chip, the delay value of the delay element based on the register or the external signal ensures that the replica system including the replica circuit operates with a margin in the critical path delay of the semiconductor circuit (LSI). Adjusted to value.

【0028】

Further, according to the present invention, the reference signal is propagated through the replica circuit, the phase of the original reference signal and the output signal of the replica circuit including the delay element are compared in the voltage control circuit, and the output signal of the replica circuit is the source. If the reference signal is delayed by one cycle or more, the voltage value is increased, and if it is advanced by one cycle or more, the voltage value is controlled to be small, and the power supply voltage is supplied to the semiconductor circuit and the replica circuit. To.

【0029】

BEST MODE FOR CARRYING OUT THE INVENTION

1st Embodiment FIG. 1 is a block diagram showing a first embodiment of a semiconductor device using the replica circuit according to the present invention. This semiconductor device uses a replica circuit as the power supply voltage V of the semiconductor circuit._DDIt is a figure which shows the example which applied to the power supply voltage control system circuit which dynamically changes and controls so that the minimum operating voltage is always supplied.

【0030】

The semiconductor device 10 includes a semiconductor circuit (LSI) 11, a replica circuit 12, an adjustable delay element 12A, a phase comparator 13, a charge pump 14, and a DC-DC converter 15. A voltage control circuit is configured by the phase comparator 13, the charge pump 14, and the DC-DC converter 15.

【0031】

The semiconductor circuit 11 has a power supply voltage V due to the DC-DC converter 15._DDIs supplied, for example, as shown in FIG. 2, in a synchronous circuit having a plurality of transmission paths, the flip-flops (FF) 111-1,111-2,111-3 on the signal transmitting side and the flip-flops 112-1,112 on the receiving side. -2,112-3, main transmission path (transmission path) 113,114,115 connecting the transmitting side and receiving side flip-flops, branch path 113-1, 115-1, gate element 116 as a transmission element having a predetermined threshold voltage It is composed of -1 to 116-11.

【0032】

The main transmission path 113 is connected between the output of the signal transmitting side flip-flop 111-1 and the input of the receiving side flip-flop 112-1. Then, the branch path 113-1 is branched from the branch point 113a of the main transmission path 113, and this branch path 113-1 is connected to one input terminal of the gate element 116-6. Then, the gate elements 116-1 and 116-2 are arranged in the main transmission path 113 between the output of the flip-flop 111-1 and the branch point 113a, and are located between the branch point 113a and the input of the receiving flip-flop 112-1. The gate element 116-3 is arranged in the main transmission path 113.

【0033】

The main transmission path 114 is connected between the output of the signal transmitting side flip-flop 111-2 and the input of the receiving side flip-flop 112-2. The gate elements 116-4 to 116-9 are arranged in the main transmission path 114 between the output of the flip-flop 111-2 and the input of the receiving flip-flop 112-2. Specifically, one input of the gate element 116-5 is connected to the output of the gate element 116-4, the output of the gate element 116-5 is connected to the other input of the gate element 116-6, and the gate element 116 Gate elements 116-7 to 116-9 are connected to the output side of -6.

【0034】

The main transmission path 115 is connected between the output of the signal transmitting side flip-flop 111-3 and the input of the receiving side flip-flop 112-3. Then, the branch path 115-1 is branched from the branch point 115a of the main transmission path 115, and this branch path 115-1 is connected to the other input terminal of the gate element 116-5. Then, the gate elements 116-10 and 116-11 are arranged in the main transmission path 115 between the output of the flip-flop 111-3 and the branch point 115a.

【0035】

The gate elements 116-1 to 116-11 are configured by using, for example, an insulated gate type field effect transistor, that is, a MIS (Metal Insulator Semiconductor) system circuit.

【0036】

In the synchronous semiconductor circuit 11 of FIG. 1, the delay path (critical path) having the maximum delay value is the flip-flop 111-3 main transmission path 115 gate element 116-10,116-11 branch path 115-1 gate element. 116-5 Main transmission path 114 Gate elements 116-6 to 116-9 Flip-flop 112-2 transmission path. Therefore, in principle, the replica circuit 12 is configured based on the elements and paths that make up this path.

【0037】

The replica circuit 12 is a semiconductor circuit 11 and is configured as a circuit having a power supply voltage-delay characteristic equivalent to the path configuration selected as the critical path as described above, and the power supply voltage V by the DC-DC converter 15._DDIt operates by receiving the supply of the above, inputs the reference signal SIN of a predetermined cycle, gates it, and propagates it. Taking the case of FIG. 2 as an example, the replica circuit 12 has flip-flop 111-3 main transmission path 115 gate element 116-10,116-11 branch path 115-1 gate element 116-5, as described above. Main transmission path 114 Gate elements 116-6 to 116-9 Flip-flop 112-2 and equivalent circuit.

【0038】

Then, in the first embodiment, the delay element 12A whose delay amount can be adjusted is connected to the output side of the replica circuit 12. The delay value of this adjustable delay element 12A is set to a value at which the replica system including the replica circuit 12 receives the adjustment signal SADJ and operates reliably with a margin in the critical path delay of the semiconductor circuit (LSI) 11. The output signal of the replica circuit 12 is propagated with this delay value, and the propagated signal is output to the phase comparator 13 as a delay signal S12A.

【0039】

In the example of FIG. 1, the adjustable delay element 12A is arranged on the output side of the replica circuit 12, but the positional relationship between the replica circuit 12 and the delay element 12A is limited to this. Of course, it may be located on the input side of the replica circuit 12 or in the replica circuit 12, for example.

【0040】

FIG. 3 is a circuit diagram showing a configuration example of an adjustable delay element. As shown in FIG. 3, the delay element 12A is composed of delay gates GT1 to GT4 and a selector 121. The output terminals of the delay gates GT1 to GT4 are connected to the selector 121, and the output signals of the gates having different delay amounts are selected by the supplied adjustment signal SADJ. As a result, the required margin delay value can be adjusted. Then, the selector 121 outputs the selected delay gate output as the delay signal S12A.

【0041】

Further, the adjustable delay element 12A is set to a desired value by supplying an adjustment signal SADJ by a predetermined method, for example, after manufacturing the chip. This adjustment signal SADJ can be supplied by configuration as shown in FIG. 4 or FIG. 5, for example.

【0042】

The configuration shown in FIG. 4 is an example using the register 122. That is, it is a configuration example in which the register 122 is directly accessed by DMA from the outside, or the delay value (gate output) data to be selected from some internal control circuit is set and given as the adjustment signal SADJ.

【0043】

Further, the configuration shown in FIG. 5 is an example in which the selector 121 is controlled via the decoder 123 by setting signals to external pins (external signal input terminals) 124, 125, 126. It is clear that the present invention also includes the case where the decoder 123 is not provided. Needless to say, the present invention is not limited to these configuration examples.

【0044】

The phase comparator 13 compares the phases of the reference signal SIN and the output delay signal S12A of the delay element 12A, and if the delay signal S12A is delayed by one cycle or more from the reference signal SIN, generates an up signal UP, and 1 If it has advanced more than a cycle, a down signal DN is generated and output to the charge pump 14.

【0045】

When the charge pump 14 receives the up signal UP by the phase comparator 13, the power supply voltage V by the DC-DC converter 15_DDWhen the down signal DN is received, the power supply voltage V by the DC-DC converter 15 is increased._DDThe signal S14 instructing to reduce the value is output to the DC-DC converter 15.

【0046】

The DC-DC converter 15 receives the output signal S14 of the charge pump 14 and receives the power supply voltage V as indicated by this signal S14._DDThe value of is adjusted and supplied to the semiconductor circuit 11 and the replica circuit 12.

【0047】

Next, the operation according to the above configuration will be described. The replica circuit 12 is configured as a circuit having a delay characteristic equivalent to the path configuration selected as the critical path in the semiconductor circuit 11, and is a delay element 12A that can be adjusted between, for example, the output side of the replica circuit 12 and the phase comparator 13. Is provided. Then, for example, after manufacturing the chip, the adjustment signal SADJ is given to the selector 121 constituting the delay element 12A through the register 122 or the decoder 123. As a result, the delay value of the delay element 12A is adjusted to a value at which the replica system including the replica circuit 12 receives the adjustment signal SADJ and operates reliably with a margin in the critical path delay of the semiconductor circuit (LSI) 11. ..

【0048】

In the semiconductor device in which the delay value is adjusted in this way, the reference signal SIN having a predetermined cycle is input to the replica circuit 12. Then, the reference signal SIN is delayed by a predetermined time in the replica circuit 12 due to gate processing or the like, and is further delayed by a set amount by the delay element 12A whose delay value is adjusted, and is output to the phase comparator 13 as the delay signal S12A. To.

【0049】

In the phase comparator 13, the reference signal SIN and the output delay signal S12A of the delay element 12A are input, and the phases of both signals are compared. As a result of comparison, when the delay signal S12A is delayed by one cycle or more from the reference signal SIN, an up signal UP is generated and output to the charge pump circuit 14. On the other hand, when the delay signal S12A is ahead of the reference signal SIN by one cycle or more, a down signal DN is generated and output to the charge pump 14.

【0050】

In the charge pump 14, when the up signal is UP by the phase comparator 13, the power supply voltage V by the DC-DC converter 15 is V._DDIs increased to generate a signal S14 instructing the processing speed to be faster (to reduce the delay) and output to the DC-DC converter 15. On the other hand, when the down signal DN is received by the phase comparator 13, the power supply voltage V by the DC-DC converter 15_DDA signal S14 is generated instructing the processing speed to be slower (the delay is to be increased), and is output to the DC-DC converter 15.

【0051】

Then, in the DC-DC converter 15, the power supply voltage V is received by the output signal S14 of the charge pump 14 as indicated by this signal S14._DDThe value of is adjusted and supplied to the semiconductor circuit 11 and the replica circuit 12.

【0052】

As described above, according to the first embodiment, the replica circuit 12 is configured as a circuit having a delay characteristic equivalent to the path configuration selected as the critical path in the semiconductor circuit 11, and the replica circuit 12 is configured, for example, on the output side. An adjustable delay element 12A is provided between the and the phase comparator 13, for example, after manufacturing a chip, the delay value of the delay element 12A is determined by the replica system including the replica circuit 12 to be critical of the semiconductor circuit (LSI) 11. Since the path delay is configured to be adjustable to a value that operates reliably with a margin, it is possible to prevent excessive margin setting, and it is also possible to prevent malfunction by increasing this when the margin is smaller than expected. Become.

【0053】

Further, by making it possible to change the delay value of the adjustable delay element 12A by setting a register or an external pin, there is an advantage that the delay value and the margin can be adjusted after the chip is manufactured.

【0054】

In the above description, as shown in FIG. 3, the adjustable delay element 12A is configured by the delay gates GT1 to GT4 and the selector 121, but the configuration of the delay element is limited to this. However, various aspects are possible.

【0055】

For example, as shown in FIG. 6, the adjustable delay element 12A can be composed of delay elements having different delay characteristics such as transistor gate delay, RC delay, and memory delay. In FIG. 6, 12B shows an adjustable delay element with the same delay characteristics as the transistor gate delay, 12C shows an adjustable delay element with the same RC delay characteristics, and 12D has a memory delay characteristic. Shows an adjustable delay factor.

【0056】

FIG. 7 is a circuit diagram showing a specific configuration example of a delay element composed of delay elements having different delay characteristics.

【0057】

As shown in FIG. 7, the adjustable delay element 12B having the same delay characteristic as the transistor gate delay is composed of delay gates GTB1 to GTB3 and selector 121B connected in series. The output terminals of the delay gates GTB1 to GTB3 and the output terminals of the replica circuit 12 are connected to the selector 121B, and the output signals of the gates having different delay amounts are selected by the supplied adjustment signal SADJB. The delay gates GTB1 to GTB3 having transistor gate delay characteristics are composed of a buffer formed by connecting two inverters INV1 and INV2 in series, for example, as shown in FIG.

【0058】

The adjustable delay element 12C having RC delay characteristics is composed of delay gates GTC1 to GTC3 and selector 121C connected in series. The output terminals of the delay gates GTC1 to GTC3, the output terminals of the delay gate GTB3 of the delay element 12B, and the output terminals of the replica circuit 12 are connected to the selector 121C via the selector 121B, and the adjustment signal SADJC is supplied. Select the output signals of the gates with different delay amounts. The delay gates GTC1 to GTC3 having RC delay characteristics are composed of so-called RC units, for example, as shown in FIG.

【0059】

The adjustable delay element 12D having a memory delay characteristic is composed of delay gates GTD1 to GTD3 and selector 121D connected in parallel. The output terminals of the delay gates GTD1 to GTD3 and the output terminals of the selector 121C of the delay element 12C are connected to the selector 121D, and the output signals of the gates having different delay amounts are selected according to the supplied adjustment signal SADJD. ..

【0060】

Note that the delay gates GTD1 to GTD3, which have memory delay characteristics, are configured so that they can be selected by changing the load value using a unit that emulates the so-called bit line discharge characteristics, for example, as shown in FIG. Will be done. Basically, the delay gate GTD1 has a power supply voltage V, as shown in FIG. 10 (A)._DDIt is composed of a p-channel MOS (PMOS) transistor PT1 and an n-channel MOS (NMOS) transistor NT1 connected between the and ground line, an inverter INV3, and a load capacitance LC1 formed by connecting the source and drain of the NMOS transistor. .. Then, as shown in FIG. 10 (B), the delay gate GTD2 is configured by increasing the load capacitance by one, and as shown in FIG. 10 (C), the delay gate GTD3 is configured by further increasing the load capacitance by one. To.

【0061】

In the delay element having such a configuration, the delay amount is selectively combined by the adjustment signals SADJB, SADJC, SADJD to the selectors 121B, 121C, 121D, and the delay adjustment and the margin adjustment for the critical path of the actual device are performed. It is said.

【0062】

In this way, there is an advantage that the delay element is composed of delay elements having different delay characteristics, and by adjusting the delay value and characteristics by these, it is possible to prevent tracking from being lost due to changes in voltage and temperature and becoming defective. ..

【0063】

The configuration of each delay element is not limited to the above-described configuration, and the delay element is not limited to the three types of transistor gate delay, RC delay, and memory delay, and the transistor delay is also various. The circuit configuration can be applied.

【0064】

Further, as shown in FIG. 11, it is also possible to convert the delay elements having different delay characteristics described above into standard cells. In FIG. 11, SCB shows the standard cell block. Further, for example, the RC delay unit RCU is configured by a predetermined pattern, and a desired RC delay can be obtained by configuring using a plurality of these patterns. In this way, by using delay units with different critical paths and delay characteristics as standard cells, it is possible to design delay units using automatic placement and wiring using ordinary CAD, which in turn improves design efficiency. There are advantages.

【0065】

Second Embodiment FIG. 12 is a block diagram showing a second embodiment of the semiconductor device adopting the replica circuit according to the present invention. Similar to the semiconductor device according to the first embodiment, the semiconductor device according to the second embodiment has a replica circuit and a power supply voltage V of the semiconductor circuit._DDIt is a figure which shows the example which applied to the power supply voltage control system circuit which dynamically changes and controls so that the minimum operating voltage is always supplied.

【0066】

The second embodiment differs from the first embodiment described above, in that the adjustable delay element is placed separately outside the replica circuit (in the first embodiment, on the output side of the replica circuit). The replica circuit 16 is configured by an adjustable delay element 160, the combination of delay elements can be arbitrarily changed by setting, and a desired delay characteristic can be realized by the combination.

【0067】

Specifically, as shown in FIG. 12, the replica circuit 16 according to the second embodiment has a plurality of gate delay elements 161-1 to 161-n as delay elements connected in series, and a selector 162. It is composed of an adjustable delay element 160 including the above, and is configured to select the number of gate delay element stages having a desired delay value with the selector 162.

【0068】

As shown in FIG. 8, the gate delay elements 161-1 to 161-n shall be composed of a buffer formed by connecting two inverters INV1 and INV2 in series, a NAND gate, a NOR gate, a composite gate, or the like. Is possible. Further, the input line of the reference signal SIN and the output nodes of the gate delay elements 161-1 to 161-n are connected to the selector 162.

【0069】

Further, the replica circuit 16 composed of the adjustable delay element 160 is supplied with the adjustment signal SADJE by a predetermined method, for example, after manufacturing the chip, and is set to a desired value. This adjustment signal SADJE can be supplied by configuration as shown in FIG. 13 or FIG. 14, for example.

【0070】

The configuration shown in FIG. 13 is an example using the register 163. That is, it is a configuration example in which the register 163 is directly accessed by DMA from the outside, or the delay value (gate output) data to be selected from some internal control circuit is set and given as the adjustment signal SADJE.

【0071】

Further, the configuration shown in FIG. 14 is an example in which the selector 161 is controlled via the decoder 167 by setting signals to external pins (external signal input terminals) 164, 165, 166. It is clear that the present invention also includes the case where the decoder 167 is not provided. Needless to say, the present invention is not limited to these configuration examples.

【0072】

In the semiconductor device 10A, the replica circuit 16 is composed of an adjustable delay element. Then, for example, after manufacturing the chip, the adjustment signal SADJE is supplied to the selector 162 constituting the replica circuit 16 through the register 163 or the decoder 167. As a result, the replica system including the replica circuit 16 is adjusted to a value that reliably operates with a margin in the critical path delay of the semiconductor circuit (LSI) 11.

【0073】

In the semiconductor device 10A in which the delay value is adjusted in this way, the reference signal SIN having a predetermined cycle is input to the replica circuit 16. Then, the reference signal SIN is delayed by a predetermined time in the replica circuit 16 due to gate processing or the like, and is further delayed by a set amount for which the delay value has been adjusted, and is output to the phase comparator 13 as a delay signal S16.

【0074】

In the phase comparator 13, the reference signal SIN and the output delay signal S16 of the replica circuit 16 are input, and the phases of both signals are compared. As a result of comparison, when the delay signal S16 is delayed by one cycle or more from the reference signal SIN, an up signal UP is generated and output to the charge pump circuit 14. On the other hand, when the delay signal S16 is ahead of the reference signal SIN by one cycle or more, a down signal DN is generated and output to the charge pump 14.

【0075】

In the charge pump 14, when the up signal is UP by the phase comparator 13, the power supply voltage V by the DC-DC converter 15 is V._DDIs increased to generate a signal S14 instructing the processing speed to be faster (to reduce the delay) and output to the DC-DC converter 15. On the other hand, when the down signal DN is received by the phase comparator 13, the power supply voltage V by the DC-DC converter 15_DDA signal S14 is generated instructing the processing speed to be slower (the delay is to be increased), and is output to the DC-DC converter 15.

【0076】

Then, in the DC-DC converter 15, the power supply voltage V is received by the output signal S14 of the charge pump 14 as indicated by this signal S14._DDThe value of is adjusted and supplied to the semiconductor circuit 11 and the replica circuit 16.

【0077】

As described above, according to the second embodiment, the replica circuit 16 is composed of adjustable delay elements, and for example, after manufacturing a chip, the delay value of the delay elements constituting the replica circuit 16 is determined. Since the replica system including the replica circuit 16 is configured to be adjustable to a value that operates reliably with a margin in the critical path delay of the semiconductor circuit (LSI) 11, it is possible to prevent an excessive margin setting and more than expected. When the margin is small, it is possible to prevent malfunction by increasing it. Further, a replica circuit that can be used for general purposes can be configured, and the operating voltage margin of the semiconductor circuit 11 can be flexibly set.

【0078】

Further, by making it possible to change the delay value of the adjustable delay element constituting the replica circuit 16 by setting a register or an external pin, it is possible to adjust the delay value and the margin after manufacturing the chip. There are advantages.

【0079】

Third Embodiment FIG. 15 is a diagram for explaining a third embodiment of the semiconductor device according to the present invention, and is a circuit diagram showing another configuration example of a replica circuit constituting the semiconductor device.

【0080】

The difference between the replica circuit according to the third embodiment and the replica circuit according to the second embodiment described above is that the adjustable delay element 170 is longitudinally connected to the subsequent stage of the adjustable delay element 160. is there.

【0081】

The delay element 170 has a plurality of RC delay elements 171-1 to 171-n as element elements connected in series, and a selector 172, and the selector 172 selects the number of RC delay element stages to be a desired delay value. It is configured as follows.

【0082】

The RC delay elements 171-1 to 171-n are composed of, for example, aluminum wiring or the like. Further, the output of the selector 162 of the delay element 160 in the previous stage and the connection node of each RC delay element 171-1 to 171-n are connected to the selector 172.

【0083】

FIG. 16 is a diagram showing the relationship between the ratio of gate delay and RC delay and the voltage delay characteristic. In FIG. 16, the curve shown by shows the voltage delay characteristic when the RC component is small, and the curve shown by shows the voltage delay characteristic when the RC component is larger (when the RC component is medium) and is shown by. The curve shows the voltage delay characteristics when the RC component is larger than the case of. As shown in FIG. 16, desired voltage-delay characteristics can be obtained by varying the ratio of gate delay to RC delay. Therefore, in the replica circuit 16A according to the third embodiment, the number of gate delay element stages and the number of RC delay element stages having a desired delay value and a desired gate delay / RC delay ratio are controlled via, for example, a register or a decoder. Is selected by selectors 162 and 172, respectively.

【0084】

According to the third embodiment, the same effect as that of the second embodiment described above can be obtained.

【0085】

Although the third embodiment shows a configuration example in which the RC delay element chain is connected to the subsequent stage of the gate delay element chain, the present invention is not limited to this positional relationship, and the RC delay element chain is not limited to this positional relationship. Needless to say, even if a gate delay element chain is connected to the subsequent stage, it is within the scope of the present invention.

【0086】

Fourth Embodiment FIG. 17 is a diagram for explaining a fourth embodiment of the semiconductor device according to the present invention, and is a circuit diagram showing another configuration example of a replica circuit constituting the semiconductor device.

【0087】

The difference between the replica circuit according to the fourth embodiment and the replica circuit according to the third embodiment described above is that the adjustable delay element 180 is longitudinally connected to the subsequent stage of the adjustable delay element 17. is there.

【0088】

The delay element 180 has memory delay elements 181-1 to 181-1 and selector 182 having different load values as element elements connected in parallel, and selects a memory delay element having a desired delay value. It is configured to be selected in 182.

【0089】

As shown in FIG. 10, for example, the memory delay elements 181-1 to 181-n are configured so that a unit that emulates the discharge characteristics of a bit line can be used and the load value can be changed. Further, the output of the selector 172 of the delay element 170 in the previous stage and the output node of each memory delay element 181-1 to 181-n are connected to the selector 182.

【0090】

According to the fourth embodiment, the same effect as that of the third embodiment described above can be obtained.

【0091】

Also in the fourth embodiment, the positional relationship between the gate delay element chain, the RC delay element chain, and the memory delay element is not limited thereto.

【0092】

Fifth Embodiment FIG. 18 is a diagram for explaining a fifth embodiment of the semiconductor device according to the present invention, and is a circuit diagram showing another configuration example of a replica circuit constituting the semiconductor device.

【0093】

The difference between the replica circuit according to the fifth embodiment and the replica circuit according to the third embodiment described above is that the replica circuit 16A- consists of a gate delay element and an RC delay element as longitudinally connected delay elements. 1,16A-2 are connected in parallel or longitudinally to the input of the reference signal SIN via the selector 191 as the connection selection means, and the outputs of the two replica parts 16A-1 and 16A-2 are ANDed as the selection means. It is configured to obtain replica output S16C via gate 192. The AND gate 192 as a selection means selects and outputs the output signal of the delay element having a larger delay amount as the delay signal S16C which is a monitor signal from the outputs of the plurality of replica units.

【0094】

Further, the replica units 16A-1 and 16A-2 can independently set the number of gate delay element stages and the number of RC total element stages.

【0095】

In such a configuration, when the reference signal SIN, which is a replica input, is selected by the selector 191, the two replica units 16A-1 and 16A-2 operate in parallel. In order to operate in parallel in this way, it is suitable in the following cases. That is, when the critical paths of the semiconductor circuit (LSI) 11 main body are replaced by the operating voltage, a discontinuity occurs in the voltage-delay characteristics of the LSI. In such a case, it becomes difficult to obtain optimum tracking for the voltage-delay characteristics of the LSI with one replica. Therefore, by matching the two replica units 16A-1 and 16A-2 to their respective critical paths, it is possible to optimally match the voltage-delay characteristics of the replica with the characteristics of the LSI itself.

【0096】

When the output signal S16A-1 of the replica unit 16A-1 is selected by the selector 191, the two replica units 16A-1 and 16A-2 are connected in series (longitudinal) and operate as one replica. In order to connect in series in this way and operate as one replica, it is suitable in the following cases. That is, if the critical path of the LSI body is a configuration such as gate + long wiring + gate + long wiring (for example, when a repeater buffer is inserted for a long wiring), two replicas are connected in series. By setting the number of gate delay element stages and the number of RC delay element stages independently for each replica, it is possible to make the replica closer to the configuration of the critical path of the LSI main body. It is also possible to double the setting range of the gate delay component and RC delay component.

【0097】

As described above, according to the fifth embodiment, in addition to the effect of the third embodiment described above, it is possible to obtain the effect that the configuration of the critical path of the LSI main body can be made closer.

【0098】

In FIG. 18, the case where two replica circuits shown in FIG. 15 according to the third embodiment are used as an example has been described, but the same applies even if the replica shown in FIG. 17 according to the fourth embodiment is applied. Needless to say, the effect of is obtained.

【0099】

6th Embodiment FIG. 19 is a diagram for explaining a sixth embodiment of the semiconductor device according to the present invention, and is a circuit diagram showing another configuration example of a replica circuit constituting the semiconductor device.

【0100】

The difference between the replica circuit according to the sixth embodiment and the replica circuit according to the fifth embodiment described above is that the replica portion including the gate delay element and the RC delay element as the delay elements connected in cascade is m ( Using m 3), these replica units 16A-1 to 16A-m are connected in parallel or in series (longitudinal) to the input of the reference signal SIN via the selectors 191-1 to 191-m-1. It is configured to operate in parallel and / or in series, and to obtain the delay signal S16D which is a replica output via the m input AND gate 193 as the output of m replica units 16A-1 and 16A-2 as a selection means. There is.

【0101】

According to the sixth embodiment, not only the same effect as that of the fifth embodiment described above can be obtained, but also a plurality of replicas such as gate + long wiring + gate + long wiring + ... are configured. , It is possible to operate them in parallel to deal with characteristics with discontinuities.

【0102】

In FIG. 19, the case where m replica circuits shown in FIG. 15 according to the third embodiment are used as an example has been described, but the same applies even if the replica shown in FIG. 17 according to the fourth embodiment is applied. Needless to say, the effect of is obtained.

【0103】

Seventh Embodiment FIG. 20 is a diagram for explaining a seventh embodiment of the semiconductor device according to the present invention, and is a circuit diagram showing another configuration example of a replica circuit constituting the semiconductor device.

【0104】

In the seventh embodiment, the adjustable replica circuit group shows a specific configuration example in which the adjustable replica circuit group can be set to a desired value after the chip is manufactured. FIG. 20 is a circuit diagram showing a configuration example in which the delay value of the replica circuit group that can be adjusted can be changed by using a register. In this circuit, as shown in the second to sixth embodiments described above, the number of stages of delay elements and the connection method are selected by the selector, and these are set by the register 194. The information set in the register 194 is decoded by the decoders 195-1 to 195-m provided corresponding to each replica unit 16A-1 to 16A-m and supplied to the selector. Register 194 may be directly accessed by DMA from the outside, or may be set from some internal control circuit.

【0105】

The delay value of the replica circuit can be set by not using a register as shown in FIG. 20, but by setting the signal of an external pin as shown in FIGS. 5 and 15, for example.

【0106】

8th Embodiment FIG. 21 is a block diagram showing an eighth embodiment of a semiconductor device using the replica circuit according to the present invention.

【0107】

The eighth embodiment differs from the second to seventh embodiments described above in that it is a phase comparator that outputs an up signal and a down signal and a charge pump that outputs a signal corresponding to these up signals and down signals. Instead of using, the phase difference detection circuit 20 and the phase difference information signal S20 that compare the phases of the reference signal SIN and the output delay signal S12A of the delay element 12A and output the digital phase difference information signal S20 corresponding to the difference. In addition to receiving and accumulating, the power supply voltage V_DDThe accumulator 21 that outputs the N-bit signal S21 that instructs the adjustment of, and the N-bit DA (digital-analog) that converts the N-bit signal S21 from a digital signal to an analog signal S22 and supplies it to the DC-DC converter 15. The converter 22 is provided.

【0108】

As the configuration of the replica circuit 16, for example, those shown in FIGS. 12, 15, 17, 17, 18, 19, and 20 can be applied. Further, in the configuration using the phase difference detection circuit 20, the accumulator 21, and the DA converter 22 as shown in FIG. 21, the delay element 12A is outside the replica circuit 12 as in the first embodiment shown in FIG. It is also applicable to the configuration in which.

【0109】

According to the eighth embodiment, the same effect as that of each of the above-described embodiments can be obtained.

【0110】

9th Embodiment FIG. 22 is a block diagram showing a ninth embodiment of a semiconductor device using the replica circuit according to the present invention.

【0111】

The difference between the ninth embodiment and the eighth embodiment described above is that the processor 23 is used instead of the accumulator 21. In this case, for example, the difference between the set value set to an arbitrary value by the program and the phase difference information signal S20 is the power supply voltage V._DDIt is output as an N-bit signal S23 instructing the adjustment of.

【0112】

According to the ninth embodiment, the same effect as that of each of the above-described embodiments can be obtained.

【0113】

[Effect of the invention]

As described above, according to the present invention, it is possible to prevent an excessive margin setting by providing an adjustable delay element, and it is also possible to prevent malfunction by increasing the margin when the margin is smaller than expected. become.

【0114】

Further, according to the present invention, by providing a replica circuit in which a delay value can be arbitrarily set by combining delay elements, a replica circuit that can be used for general purposes can be configured, and at the same time, the operating voltage of the semiconductor circuit can be configured. It is possible to flexibly set the margin.

【0115】

Further, since the delay adjusting element is composed of delay elements having different delay characteristics, it is possible to prevent the delay value and the characteristics from being adjusted by these delay elements so that tracking cannot be performed due to changes in voltage and temperature, resulting in a defect.

【0116】

Further, by making it possible to change the adjustable delay element by inputting an external signal to a register or an input terminal, it becomes possible to adjust the delay value and the margin after manufacturing the chip.

【0117】

Further, by preparing delay elements having different delay characteristics as standard cells and arranging and configuring replicas and delay adjustment units in the standard cells, there is an advantage that design efficiency can be improved.

【0118】

In addition, by preparing a plurality of replica units and selecting parallel operation, series operation, or parallel / series combined operation, it is possible to make them closer to the configuration of the critical path of the semiconductor circuit body.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows 1st Embodiment of the semiconductor device which adopted the replica circuit which concerns on this invention.

[Figure 2]

It is a circuit diagram which shows the structural example of the semiconductor circuit which concerns on this invention.

[Fig. 3]

It is a circuit diagram which shows the structural example of the adjustable delay element which concerns on this invention.

[Fig. 4]

It is a circuit diagram which shows the configuration example which supplies the adjustment signal to the selector which comprises the adjustable delay element which concerns on 1st Embodiment.

[Fig. 5]

It is a circuit diagram which shows the other configuration example which supplies the adjustment signal to the selector which comprises the adjustable delay element which concerns on 1st Embodiment.

[Fig. 6]

FIG. 5 is a conceptual diagram in the case where the adjustable delay element according to the present invention is composed of delay elements having different delay characteristics such as transistor gate delay, RC delay, and memory delay.

[Fig. 7]

It is a circuit diagram which shows the structural example of the delay gate which has a transistor gate delay characteristic.

[Fig. 8]

It is a circuit diagram which shows the structural example of the delay gate which has the delay characteristic of a memory.

[Fig. 9]

It is a circuit diagram which shows the structural example of the delay gate which has RC delay characteristic.

[Fig. 10]

It is a circuit diagram which shows the specific structural example of the delay element composed of delay elements of different delay characteristics.

[Fig. 11]

It is a figure for demonstrating the example which made the delay element of a different delay characteristic into a standard cell.

[Fig. 12]

It is a block diagram which shows the 2nd Embodiment of the semiconductor device which adopted the replica circuit which concerns on this invention.

[Fig. 13]

It is a circuit diagram which shows the configuration example which supplies the adjustment signal to the selector which comprises the adjustable delay element which concerns on 2nd Embodiment.

[Fig. 14]

It is a circuit diagram which shows the other configuration example which supplies the adjustment signal to the selector which constitutes the adjustable delay element which concerns on 2nd Embodiment.

[Fig. 15]

It is a figure for demonstrating the 3rd Embodiment of the semiconductor device which concerns on this invention, and is the circuit diagram which shows the other structural example of the replica circuit which constitutes the semiconductor device.

[Fig. 16]

It is a figure which shows the relationship between the ratio of a gate delay and RC delay, and a voltage delay characteristic.

[Fig. 17]

It is a figure for demonstrating the 4th Embodiment of the semiconductor device which concerns on this invention, and is the circuit diagram which shows the other structural example of the replica circuit which constitutes the semiconductor device.

[Fig. 18]

It is a figure for demonstrating the 5th Embodiment of the semiconductor device which concerns on this invention, and is the circuit diagram which shows the other structural example of the replica circuit which constitutes the semiconductor device.

[Fig. 19]

It is a figure for demonstrating the sixth embodiment of the semiconductor device which concerns on this invention, and is the circuit diagram which shows the other structural example of the replica circuit which constitutes the semiconductor device.

[Fig. 20]

It is a figure for demonstrating the 7th Embodiment of the semiconductor device which concerns on this invention, and is the circuit diagram which shows the structural example which made it possible to change the delay value of the replica circuit group which can be adjusted by using a register.

[Fig. 21]

It is a block diagram which shows the 8th Embodiment of the semiconductor device which adopted the replica circuit which concerns on this invention.

[Fig. 22]

It is a block diagram which shows the 9th Embodiment of the semiconductor device which adopted the replica circuit which concerns on this invention.

[Fig. 23]

It is a figure which shows the replica system circuit which connected the delay element for a fixed delay margin.

[Fig. 24]

It is a figure which shows the voltage dependence of a transistor delay and RC delay.

[Explanation of symbols]

10,10A, 10B, 10C ... semiconductor device, 11 ... semiconductor circuit, 12,16,16A ~ 16E ... replica circuit, 12A ... adjustable delay element, 12B ... transistor gate delay Adjustable delay element with characteristics, 12C ... RC Adjustable delay element with delay characteristics, 12D ... Adjustable delay element with memory delay characteristics, 13 ... Phase comparator , 14 ... charge pump, 15 ... DC-DC converter, 16A-1 ~ 16A-m ... replica part, 20 ... phase difference detection detection circuit, 21 ... accumulator, 22. .. N-bit DA converter, 23 ... processor, 111-1 to 111-3 ... signal transmitting side flip flop, 112-2 to 112-3 ... receiving side flip flop, 113,114,115 ... main transmission Path, 113-1,115-1 ... Branch path, 16-1 ~ 16-11 ... Gate element, 121,121B, 121C, 121D ... Selector, 160,170,180 ... Adjustable delay element, 191-1 ~ 191-m ... Selector (connection selection means), 192,193 ... AND gate (selection means), GT1 ~ GT4 ... Delay gate, GTB1 ~ GTB3 ... Transistor gate Delay gate with delay characteristics, GTC1 ~ GTC3 ... Delay gate with RC delay characteristics, GTD1 ~ GTD3 ... Delay gate with memory delay characteristics.