Wiring board

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a wiring board having multi-layer wiring portions on both main surfaces of the core substrate, and more particularly to a wiring board in which a chip capacitor is built in the core substrate.

【0002】

[Conventional technology]

In recent years, the operation of IC chips has become faster and faster due to advances in integrated circuit technology. Along with this, noise may be superimposed on the power supply wiring or the like, causing a malfunction. Therefore, in order to remove such noise, for example, a chip capacitor is separately mounted on the upper surface or the lower surface of the wiring board, and the chip capacitor wiring is connected to the two terminal electrodes (first and second terminal electrodes) of this chip capacitor, respectively. Is provided inside the wiring board. As a result, the chip capacitor can be connected to the IC chip via the chip capacitor wiring and the IC connection terminal.

【0003】

However, in the wiring board having the above structure, it is necessary to mount a chip capacitor separately after the completion of the wiring board, which requires man-hours and increases the cost. Further, the reliability of the wiring board may be lowered depending on the connection reliability of the chip capacitor, for example, the quality of the connection of the chip capacitor affects the quality of the entire wiring board. Furthermore, it is necessary to secure the area for mounting the chip capacitor on the upper and lower surfaces in advance, which reduces the degree of freedom of mounting other electronic components and fixing the reinforcing member (stiffener) for reinforcing the wiring board. There is also. In addition, the chip capacitor connection wiring that connects the IC chip and the chip capacitor tends to be long and thin due to restrictions on other wiring and the like. For this reason, there is a problem that the resistance and inductance of the chip capacitor connection wiring itself tend to be excessive, and the demand for low resistance and low inductance cannot be sufficiently met.

【0004】

PROBLEM TO BE SOLVED: To solve a problem

The present invention solves the above-mentioned problems, reduces noise, reduces the resistance and inductance of the wiring connected to the chip capacitor, and even if the chip capacitor malfunctions, the loss cost is low. An object of the present invention is to provide a wiring board which can be manufactured at low cost and has a built-in chip capacitor having a large capacitance.

【0005】

[Means for solving problems]

The present invention was conceived in order to solve the above-mentioned problems by incorporating a chip capacitor having a large capacitance in a core substrate and connecting the two terminal electrodes to the upper and lower surfaces of the substrate, respectively. Is. That is, the wiring board of the present invention includes a core board having a first main surface and a second main surface, a recess formed on the first main surface of the core board, and a chip capacitor housed in the recess. A first multilayer wiring section formed by alternately stacking conductor layers and insulating layers on the first main surface of a core substrate accommodating this chip capacitor, and an IC formed on the upper surface of the first multilayer wiring section. An IC connection terminal for connecting to a chip, an IC connection wiring provided in the first multilayer wiring portion and connected to the IC connection terminal, and a conductor on the second main surface of a core substrate containing the chip capacitor. A second multi-layer wiring portion formed by alternately laminating layers and insulating layers, an external connection terminal formed on the upper surface of the second multi-layer wiring portion, and a bottom surface portion of the second multi-layer wiring portion and the recess. A wiring board provided with an external connection wiring provided in the above and connected to the external connection terminal, wherein the chip capacitor is connected to the first IC connection wiring on the first main surface side and The first terminal electrode connected to the first external connection wiring on the second main surface side and the second IC connection wiring connected to the first main surface side and on the second main surface side. It is characterized by including a second terminal electrode connected to a second external connection wiring.

【0006】

In the above wiring board, a recess for accommodating a chip capacitor is formed in the core substrate, the chip capacitor is built in the recess, and the first multilayer wiring portion and the second layer wiring portion are formed on both sides of the core substrate in the chip capacitor. The first terminal electrode, the second terminal electrode, and the IC connection terminal are connected to the IC connection on the first main surface side, respectively. Further, the first terminal electrode and the second terminal electrode of the chip capacitor are each connected to the external connection wiring on the second main surface side. Therefore, both terminal electrodes of the chip capacitor can be taken out to the first main surface side (upper side) and the second main surface side (lower side), respectively.

【0007】

That is, the chip capacitor can be arranged at a very short distance from the IC connection terminal or the like connected to the IC chip. This makes it possible to form the first IC connection wiring and the second IC connection wiring as extremely short. Therefore, noise can be reduced and the resistance and inductance of the wiring connected to the chip capacitor can be lowered. Moreover, since the chip capacitor itself is built in the wiring board, it is not necessary to separately install the chip capacitor after the completion of the wiring board, or the number of chip capacitors to be installed can be reduced.

【0008】

In particular, it is desirable to use a wiring board characterized in that at least a part of the plurality of IC connection terminals is located above the chip capacitor and at a position overlapping the chip capacitor. For example, when the IC connection terminal of the flip chip pad is located above the chip capacitor, the first IC connection wiring and the second IC connection wiring connecting the IC connection terminal and the first terminal electrode and the second terminal electrode of the chip capacitor are connected. The length of the IC connection wiring can be particularly shortened. Therefore, the resistance and inductance of the first IC connection wiring and the second IC connection wiring can be further suppressed, so that the noise reduction ability (effect) can be further improved.

【0009】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, suitable embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a cross section of a main part of the wiring board 1 according to the present invention. The wiring board 1 has a core board 2 made of a glass-epoxy resin composite material and having a first main surface 2a and a second main surface 2b in the substantially center in the thickness direction, and the first main surface 2a of the core board 2 is provided. A substantially rectangular recess 4 is formed in the plan view. A plurality of chip capacitors 10 are housed in the recess 4, and each chip capacitor 10 has a first terminal electrode 12 and a second terminal electrode 14 at both left and right ends in the drawing. For the chip capacitor 10, for example, a laminated ceramic chip capacitor (capacitor) having a capacitance of about 1000 to 10000 pF (picofarat) and using barium titanate or the like as a dielectric is used, and the size example is 1.0. It is about × 0.5 × 0.5 mm. The vacant space in the recess 4 is filled with an insulating material (layer) 4b.

【0010】

The terminal electrodes 12 and 14 are connected to the upper ends of the through-hole conductors 6 and 6 penetrating the bottom surface portion 4a in the recess 4 of the core substrate 2 by solders 16 and 18, respectively. A plurality of through-hole conductors 8 penetrating the core substrate 2 are formed in the thick portion of the core substrate 2 without the recess 4, and the first and second main surfaces 2a and 2b of the core substrate 2 are formed at the upper and lower ends thereof. A land 9 extending upward is formed. Further, the hollow portions in the through-hole conductor 6 and the through-hole conductor 8 are filled with resin 5 or resin 7, respectively. Further, the upper end portion 8a of the through-hole conductor 8 and the upper land 9 form a part of the first conductor layer 20a described below, and the lower end portions 6a, 8a and the lower land of the through-hole conductors 6, 8 are formed. 9 forms a part of the first conductor layer 30a described later.

【0011】

Further, on the first main surface 2a on which the recess 4 of the core substrate 2 is formed, the first to third conductor layers 20a, 22, 24, the first and second insulating layers 21, 23, and the solder resist (insulation) are formed. ) A first multilayer wiring portion 20 in which layers 25 and layers 25 are alternately laminated is formed. In the second and third conductor layers 22 and 24, via conductors 22a and 24b that penetrate the insulating layers 21 and 23 and establish continuity between the conductor layers are formed. A plurality of IC connection terminals 28 that penetrate the solder resist layer 25 and project from the surface thereof are formed at appropriate positions of the third conductor layer 24. The IC connection terminal 28 is brazed to an external connection terminal (not shown) on the bottom surface of the IC chip 29 mounted on the upper surface of the wiring board 1. The conductor layers 20a, 22, 24 that connect the IC chip 29 and the first and second terminal electrodes 12, 14 of the chip capacitor 10 form the first and second IC connection wirings 26, 27. ..

【0012】

Further, on the second main surface 2b of the core substrate 2, the first to third conductor layers 30a, 32, 34, the first and second insulating layers 31, 33, and the solder resist (insulating) layer 35 are formed. A second multilayer wiring portion 30 that is alternately laminated is formed. Via conductors 32a and 34a are formed in the conductor layers 32 and 34 so as to penetrate the insulating layers 31 and 33 and establish continuity between the conductor layers. External connection terminals 38 that are exposed in the plurality of openings 39 formed in the solder resist layer 35 are formed at appropriate positions in the third conductor layer 34. The conductor layers 30a, 32, 34 portion connecting the external connection terminal 38 and the first and second terminal electrodes 12, 14 of the chip capacitor 10 form the first and second external connection wirings 36, 37. ing. The surface of the external connection terminal 38 is plated with thin Au and Ni. Further, the conductor portion connected to the external connection terminal 38 via the conductor layers 24,22,20a,30a,32,34 in the wiring board 1 without passing through the IC chip 29 and the chip capacitor 10 has a signal connection wiring. Form.

【0013】

As described above, the wiring board 1 has a plurality of chip capacitors 10 built in the recesses 4 of the core board 2, and the first and second terminal electrodes 12 and 14 and the IC connection terminals 28 are housed in the first multilayer wiring section 20. Connect with the 1st and 2nd IC connection wirings 26 and 27 of. Further, the first and second terminal electrodes 12 and 14 of the chip capacitor 10 and the external connection terminals 38 are connected by the first and second external connection wirings 36 and 37 in the second multilayer wiring portion 30. Therefore, the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are connected to and conductive on the upper surface (first main surface 2a side) and lower surface (second main surface 2b side) of the substrate 1, respectively. .. That is, the chip capacitor 10 can be arranged at a close distance from the IC connection terminal 28 connected to the IC chip 29, and the first and second IC connection wirings 26 and 27 can also be arranged extremely short.

【0014】

Therefore, according to the wiring board 1, noise can be reduced, the resistance and inductance of the IC connection wires 26 and 27 connected to the chip capacitor 10 can be lowered, and the conduction between the IC chip 29 and the chip capacitor 10 can be obtained at high speed and accurately. Moreover, the conduction between the IC chip 29 and the first and second multilayer wiring portions 20 and 30 can be surely taken. Further, it is possible to reliably establish the continuity between the circuit element in the motherboard (not shown) to which the wiring board 1 is connected via the external connection terminal 38 and the chip capacitor 10 or the like. Moreover, since the chip capacitor 10 is built in the recess 4 of the core substrate 2, it is not necessary to mount the chip capacitor separately on the upper surface of the substrate 1, and the overall thickness can be suppressed, or the number of chip capacitors to be mounted separately. Can be reduced. Further, in the wiring board 1, since each IC connection terminal 28 is located above the chip capacitor 10, the first and second IC connection wirings 26 and 27 can be made the shortest, and these inductances and resistors can be further reduced. Since it is kept low, the noise reduction characteristics are remarkably improved.

【0015】

The manufacturing method of the wiring board 1 described above will be described below. In the following FIGS. 2 and 2 described below, the chip capacitor 10 on the left side in FIG. 1 will be mainly described. FIG. 2 (A) shows a cross section of a core substrate base plate 2c made of glass-epoxy resin with copper foil c attached on both sides, and as shown in FIG. 2 (B), a through hole is drilled at a predetermined position. Drill 3 Then, copper plating is applied to both sides of the base plate 2c and the inside of the through hole 3, and the hollow portion near the center of the through hole 3 is filled with resin and cured. After that, both sides of the base plate 2c are further plated with copper, and masking is performed to remove the copper plating layer and the copper foil c at unnecessary positions by etching. As a result, as shown in FIG. 2C, a through-hole conductor 6 and a resin 5 embedded near the center thereof are formed in each through-hole 3, and the upper and lower ends of the through-hole conductor 6 are substantially circular. Flange 6a is formed. By the above masking, the land 6b extends from a part of the flange 6a. The lower end flange 6a and the land 6b form a part of the first conductor layer 30a.

【0016】

Next, as shown in FIG. 2D, a thick core substrate base plate 2d is laminated on the upper surface of the core substrate base plate 2c via a film-shaped adhesive sheet 2e and thermocompression bonded. A substantially rectangular opening 2f is formed in advance in the base plate 2d, a core substrate 2 is formed by joining the base plates 2c and 2d, and a recess 4 is formed on the first main surface 2a side thereof. The lower surface of the core substrate 2 is the second main surface 2b. Further, as shown in FIG. 3A, the chip capacitor 10 is charged in the recess 4, and the chip capacitor 10 is placed on the upper end flange 6a of each through-hole conductor 6 penetrating the bottom surface 4a of the recess 4. 1. Place the 2nd terminal electrodes 12 and 14 close to each other. As shown in FIG. 3 (B), solders 16 and 18 are applied in this state to join the first and second terminal electrodes 12 and 14 and the through-hole conductors 6 and 6. As a result, the terminal electrodes 12 and 14 having a substantially U-shaped cross section provided on the left and right ends of the chip capacitor 10 conduct with the through-hole conductors 6 and 6 via the solders 16 and 18, respectively.

【0017】

Next, after applying an epoxy resin on the core substrate 2 and the chip capacitor 10, the surface thereof is ground and flattened. As a result, as shown in FIG. 3C, the upper end surfaces of the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are exposed, and the chip capacitor 10 is embedded in the recess 4. A resin (insulating) layer 4b is formed. In the following, the upper surface of the resin layer 4b will be referred to as the first main surface 2a of the core substrate 2 for convenience of explanation.

【0018】

Subsequently, as shown in FIG. 4A, a through hole 3 is drilled at a predetermined position in a thick portion of the core substrate 2 without the recess 4. Next, copper plating is applied to both sides of the core substrate 2 and the inside of the through hole 3, and the hollow portion near the center of the through hole 3 is filled with resin and cured. Further, masking is applied to remove the copper plating layer at unnecessary positions by etching. As a result, as shown in the figure, a through-hole conductor 8 and a resin 7 embedded near the center thereof are formed in each through-hole 3, and a substantially circular flange 8a is formed at the upper and lower ends of the through-hole conductor 8. Will be done. Land 9 extends from a part of the flange 8a by the above masking. The upper and lower flanges 8a and lands 9 form a part of the first conductor layers 20a and 30a, respectively.

【0019】

During this period, the upper ends of the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are also thickened to the same level as the flange 8a. Next, after applying an epoxy resin on the core substrate 2 and the chip capacitor 10, the surface thereof is ground and flattened. As a result, as shown in FIG. 4B, a resin (insulating) layer 19 is formed in which the upper end surfaces of the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are exposed. Further, an epoxy resin is also applied on the second main surface 2b of the core substrate 2, and the surface thereof is ground to form a flattened resin layer 19. Flange 6a, 8a and lands 6b, 9 forming the conductor layer 30a are exposed on the surface of the resin layer 19 on the second main surface 2b.

【0020】

Then, as shown in FIG. 5 (A), a film-like photosensitive epoxy resin sheet is attached above the first main surface 2a and the second main surface 2b of the core substrate 2 to form a first insulating layer. Form 21,31. Via holes 21a and 31a are formed at predetermined positions on the insulating layers 21 and 31 by a known photolithography technique. Copper plating is formed in the via holes 21a and 31a and on the first insulating layers 21 and 31, respectively, and then etching (patterning) is performed on a predetermined pattern. As a result, via conductors 22a, 32a and second conductor layers 22,32 are formed, as shown in FIG. 5 (B).

【0021】

Similarly, an epoxy resin sheet is attached above the first insulating layers 21, 31 and the second conductor layers 22, 32 to form the second insulating layers 23, 33, and via holes are formed at predetermined positions. After the formation, the via conductors 24a, 34a and the third conductor layers 24,34 are formed. Finally, solder resist layers 25 and 35 are formed on both sides, and the solder resist layers 25 and 35 are formed so as to penetrate the IC connection terminal 28 from a predetermined position of the resist layer 25 and are externally connected into a plurality of openings 39 provided in the resist layer 35. By exposing each of the terminals 38, the wiring board 1 shown in FIG. 1 can be obtained. The IC connection terminal 28 is generally located above the chip capacitor 10.

【0022】

Then, as shown in FIG. 1, the IC chip 29 is mounted on the wiring board 1 by connecting the external connection terminals provided on the bottom surface of the IC chip 29 to each IC connection terminal 28 via a brazing material. To. The conductor layers 20a, 22, 24 portions connecting the IC chip 29 and the first and second terminal electrodes 12, 14 of the chip capacitor 10 form the first and second IC connection wirings 26, 27. Further, the conductor layers 30a, 32, 34 portion connecting the external connection terminal 38 and the first and second terminal electrodes 12, 14 of the chip capacitor 10 are provided with the first and second external connection wirings 36, 37. Form. As a result, the first and second terminal electrodes 12 and 14 of the chip capacitor 10 are connected to and conduct with the first main surface 2a side and the second main surface 2b side of the substrate 1, respectively, and are connected to the IC chip 29. Since the chip capacitor 10 can be arranged at a close distance from the IC connection terminal 28, the first and second IC connection wirings 26 and 27 can also be made extremely short.

【0023】

Therefore, according to the wiring board 1, as described above, noise can be reduced, the resistance and inductance of the IC connection wires 26 and 27 connected to the chip capacitor 10 can be reduced, and the continuity between the IC chip 29 and the chip capacitor 10 can be reduced. Can be taken quickly and accurately. Further, the circuit element in the motherboard to which the wiring board 1 is connected via the external connection terminal 38 and the chip capacitor 10 can be surely connected to each other. Moreover, since the chip capacitor 10 is built in the recess 4 of the core substrate 2, it is not necessary to separately mount the chip capacitor on the upper surface of the substrate 1, and the thickness of the entire wiring board 1 can be suppressed or mounted on the upper surface. The quantity can be reduced.

【0024】

The present invention is not limited to the forms described above. For example, a plurality of recesses may be formed on the first main surface of the core substrate, and chip capacitors may be individually incorporated in each recess. Alternatively, the recess can be formed by partially removing the first main surface side of a single core substrate by cutting or the like. Further, as the chip capacitor, in addition to the above-described form, various types such as a semiconductor type ceramic chip capacitor can be applied. Further, as the IC chip to be mounted, in addition to a monocyclic IC (bipolar type, MOS type, Bi-CMOS) chip in which a semiconductor is integrated, a hybrid IC chip in which a capacitor and a resistor are integrated together with a semiconductor can be applied.

【0025】

In addition to the glass-epoxy composite material used in the above form, the core substrate 2 includes a BT resin-glass material, a glass-PPE material, a composite resin material such as paper-epoxy, or an epoxy, BT resin, or polyimide. , PPE, PTFE and other resins can also be used. The conductor layers 22, 24 and the like are not limited to copper, but Ni and its alloys (Ni-P, Ni-B, Ni-Cu-P), Co and its alloys (Co-P, Co-B, Co-). Ni-P), Sn and alloys thereof (Sn-Pb, Sn-Pb-Pd), Au, Ag, Pd, Pt, Rh, Ru and the like, and alloys based on these can also be used.

【0026】

[Effect of the invention]

The wiring board of the present invention described above has a chip capacitor built in a recess of the core board, and the first and second terminal electrodes and the IC connection terminal of the chip capacitor are connected to the first and second ICs of the first multilayer wiring section. It is connected by the connection wiring, and the first and second terminal electrodes of the chip capacitor and the external connection terminal are connected by the first and second external connection wiring of the second multilayer wiring part. As a result, the first and second terminal electrodes of the chip capacitor are connected to and conductive on the upper surface (first main surface side) and lower surface (second main surface side) of the wiring board, respectively, and thus connected to the IC chip. The chip capacitor can be arranged at a close distance from the IC connection terminal to be connected, and the first and second IC connection wirings can be arranged as extremely short.

【0027】

Therefore, according to the wiring board, noise can be reduced, resistance and inductance of the IC connection wiring connected to the chip capacitor can be lowered, conduction between the IC chip and the chip capacitor can be obtained quickly and accurately, and the IC chip and the first It is possible to reliably establish continuity with the 1st and 2nd multilayer wiring sections 2. Further, the circuit element in the motherboard to which the wiring board is connected via the external connection terminal and the chip capacitor can be surely connected to each other. Moreover, since the chip capacitor is built in the recess of the core substrate, it is not necessary to separately mount the chip capacitor on the upper surface of the wiring board, and the overall thickness can be suppressed, or the number of chip capacitors separately mounted on the upper surface can be reduced. can do.

【0028】

Furthermore, in the form in which the IC connection terminal is located above the chip capacitor on the wiring board, the first and second IC connection wiring can be made the shortest, and these inductances and resistances can be further suppressed, resulting in noise reduction characteristics. Is further improved. In addition, even if a defect occurs in the chip capacitor, the loss cost is low, the product can be manufactured at low cost, and a wiring board containing a chip capacitor having a large capacitance can be provided.

[Simple explanation of drawings]

[Figure 1]

The cross-sectional view which shows the main part in the wiring board of this invention.

[Figure 2]

(A) to (D) are partial cross-sectional views showing an outline of each manufacturing process for obtaining the wiring board of the present invention.

[Fig. 3]

(A) to (C) are partial cross-sectional views showing an outline of each manufacturing process following FIG.

[Fig. 4]

(A) and (B) are partial cross-sectional views showing an outline of each manufacturing process following FIG.

[Fig. 5]

(A) and (B) are partial cross-sectional views showing an outline of each manufacturing process following FIG.

[Explanation of symbols]

1....................... Wiring board 2 ........................ Core board 2a ..................... 1st main surface 2b ..................... 2nd main surface 4 ....................... Recessed 4a ..................... Bottom part 10 ..................... Chip Capacitor 12. .................... 1st terminal electrode 14. .................... 2nd terminal electrode 20 ..................... 1st multi-layer wiring section 20a, 22,24 ... Conductor layer 21,23,25 ...... Insulation layer 26 ..................... 1st IC connection wiring 27 ..................... 2nd IC connection wiring 28 ..................... IC connection terminal 29 ..................... IC chip 30 ..................... 2nd multi-layer wiring section 30a, 32, 34 ... Conductor layer 31,33,35 ...... Insulation layer 36 ..................... 1st external connection wiring 37 ..................... 2nd external connection wiring 38 ..................... External connection terminal