Liquid crystal display device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a liquid crystal display device, and particularly relates to a liquid crystal display device having a built-in peripheral circuit in which a drive unit is formed on the same substrate as the display unit.

【0002】

[Conventional technology]

As a driving method for a small, high-definition liquid crystal display panel, a method of forming a matrix peripheral circuit on a glass substrate using a thin film transistor has been conventionally used. For example, it is reported on pages 879 to 881 of the 1998 SID International Symposium Digest of Technical Papers. The details of the active matrix drive system and the liquid crystal display module are described in detail in the liquid crystal display technology (industrial books) edited by Shoichi Matsumoto.

【0003】

Hereinafter, in order to clarify the difference from the present invention, the conventional display device configuration shown in FIG. 2 and the schematic configuration of the liquid crystal display device according to the present invention shown in FIG. 1 will be described.

【0004】

In FIG. 1, the display data and the synchronization signal are supplied from the input terminal 214 of the liquid crystal display module 105 to the digital data driver unit 106 via the high-speed data bus 203 and the high-speed control bus 216. A low-speed data bus 102 and a low-speed control bus 107 separated for each of a plurality of blocks 103 are arranged in the digital data driver section, and data on the high-speed data bus is deployed in parallel at a lower rate than the high-speed data bus. Transferred to the data latch. Parallel expansion is performed by the high-speed data alignment circuit 101 arranged for each block. Further, the shift register and the synchronization signal required for data transfer are individually generated for each block by the high-speed data control circuit 104 arranged for each block, and the operation of allocating the display data to the data latch is performed at an independent timing for each block. Will be done.

【0005】

The configuration of the conventional TFT liquid crystal display module shown in FIG. 2 does not include a low-speed data bus that transfers display data at low speed, and a set of high-speed data bus 203 input from the input terminal 214 to the liquid crystal display module 215. Then, the shift register 202 is driven by the high-speed control bus 216 to transfer the display data to each data latch 204. After that, the data for one line on the data latch is latched in the line memory 205, the voltage is amplified by the level shifter 206, and then the digital display data is converted to the liquid crystal drive voltage by the D / A conversion circuit 207 provided for each signal wiring. It is converted and the pixel unit 209 is driven by the signal wiring 208. The scanning side drive circuit 213 is composed of a shift register 211 and a level shifter 212 connected in series, and displays an active matrix by outputting a selection pulse of a pixel portion to the scanning wiring 210. In this system, as the panel becomes larger and has higher definition, the wiring width must be increased in order to suppress the signal delay in the data bus, which causes an increase in the area of the wiring portion.

【0006】

In addition, since all data latches and line memories of the data driver circuit must be driven in synchronization, if the time difference between the synchronization signals to each part of the circuit increases, each part of the circuit cannot be synchronized and the TFT with a relatively low operating frequency. It was difficult to realize the peripheral circuit of the large panel.

【0007】

In addition, since a large number of data latches are connected to one set of data buses, the capacity value of the data bus wiring becomes large, so that the time constant determined by the wiring resistance and the wiring capacity increases, and the wiring delay time becomes long. This also made it difficult to realize peripheral circuits for large panels.

【0008】

The feature of this configuration is that an independent low-speed data bus is provided for each block, and synchronization control is made independent for each block.

【0009】

First, for the display data on the high-speed data bus, the display data corresponding to the blocks is sorted in parallel by the high-speed data control circuit into a larger number of low-speed data buses than the high-speed data bus by the data alignment circuit. Since the latch circuit connected to the high-speed data bus becomes a capacitive load, if this increases, the wiring delay increases, which makes it difficult to speed up the data transfer. In the past, a large number of data latch circuits for the number of signal wirings were connected to this bus, but in the configuration of the present invention, the circuit connected to the high-speed data bus is one circuit for each block, and data that does not correspond to the blocks. Since the low-speed data bus can be separated from the high-speed data bus when the data is being transferred, the capacitive load of the data wiring can be significantly reduced. Similarly, in the conventional example, a large number of shift registers are connected to the control bus, but in the present invention, only one high-speed data control circuit is connected to each block, so that the capacitive load can be reduced. Since the high-speed bus can be driven with a low-capacity load in this way, the high-speed data bus wiring can be transmitted with thin wiring, which has the advantage of reducing the circuit area.

【0010】

Next, the present invention is characterized in that data is latched from the low-speed data bus to the data latch by an individual synchronization signal for each block. In the conventional technology, all shift registers and data latches are driven by a high-speed synchronization signal such as a dot clock on a common wiring. Therefore, if the waveform is distorted due to wiring delay or the like, or if the phase of the data and the synchronization signal is significantly deviated, the data latch operation of the entire data driver circuit cannot be performed. Therefore, the panel has become a bottleneck for increasing the size and definition. According to the present invention, since the synchronization signal required for the data latch operation is independently generated for each block, even if a delay occurs in the high-speed data bus, the synchronization is maintained in each block, resulting in higher definition and larger size. However, reliable data latching is possible. Further, the data bus in the block is slow, and the time for the data latch operation can be longer than that of the conventional example, so that there is an advantage that the data latch can be performed more reliably. Therefore, data latch operation is possible even if some transmission delay occurs on the high-speed control bus and high-speed data bus. Therefore, a waveform shaping circuit should be provided in the middle of the high-speed data bus wiring to correct the waveform distortion during wiring transmission. This also has the advantage that a large panel can be easily realized because transfer is possible even if the wiring length is long.

【0011】

In addition, since the data driver circuit is divided into blocks and the data latch operation and D / A conversion operation can be performed individually, the power consumption of these circuits is averaged, so that the power supply wiring width can be reduced and the data driver circuit. There are advantages that the area can be reduced, the peak output of the power supply capacity for driving this circuit can be reduced, the load on the power supply circuit can be reduced, and a large panel can be easily driven.

【0012】

[Problems to be Solved by the Invention]

In the conventional technique, the pixel display data for one scanning line must be transferred to each data latch corresponding to the signal wiring of the pixel portion via the data bus inside the panel for each horizontal scanning period for the liquid crystal display module. Must be. The transfer rate at this time increases as the number of pixels increases. For example, in a configuration of 1024 x 768 pixels, high-speed transfer of 18-bit data for each pixel is required at about 50 MHz.

【0013】

In order to transfer such high-speed data, data is sequentially arranged in series for each pixel, supplied via a data bus connected to all data latches, and a start pulse, transfer clock signal, and shift register circuit are used. A specific data latch was operated by a data latch signal that shifts sequentially, and data was transferred. However, the data bus requires a horizontal length of the display area, the wiring length is long, and many data latches with a capacitive load are connected to one wiring, and the load capacity of the wiring is the panel. It increases with the number of pixels of, and the wiring delay increases. In order to increase the number of pixels, the wiring resistance increases, the wiring load capacitance increases, and the signal delay also increases, although faster data transmission is required. Therefore, the above structure is a high-definition panel. It was difficult to increase the size of the.

【0014】

The present invention provides a liquid crystal display device having a small load capacitance on a display panel and capable of transmitting display data input to a high-speed data bus to the end of the bus with less waveform distortion even in a large high-definition panel. The purpose.

【0015】

[Means for solving problems]

In order to achieve the above object, in the present invention, a TFT active matrix type display area and a TFT peripheral circuit using a thin film TFT are formed on a substrate of a liquid crystal display panel of a liquid crystal display device, and a high-speed data bus and high-speed control are performed. A high-speed bus consisting of buses, a blocked low-speed data bus, and a signal wiring drive circuit are provided. The high-speed bus supplies high-speed display data from the outside, corrects waveform distortion due to signal delay in the bus wiring with a waveform shaping circuit provided in the wiring, and high-speed display data up to the end and high-speed such as dot clock and synchronization signal. Transfer the control signal.

【0016】

The display data is expanded in parallel on a large number of low-speed buses for each block, the display data is sequentially transferred to the data latch, and the digital display data is converted to the liquid crystal drive voltage by the line memory and D / A conversion circuit to display the active matrix display. Try to drive.

【0017】

Further, by blocking the low-speed data bus and operating it by individual timing signals, it is possible to sequentially capture the display data developed in parallel on a large number of buses into a large number of data latches at a low speed. Furthermore, even if a large signal delay occurs between blocks on the high-speed data transfer bus, the sampling operation to the latch is independent for each block, so that the display data can be correctly transferred to the latch. Due to the above effects, in a large panel with high definition, the display data can be transferred to each data latch even if the transfer rate of the display data increases, and the data transfer speed can be increased even in the large panel as a whole.

【0018】

BEST MODE FOR CARRYING OUT THE INVENTION

The liquid crystal display device of the present invention will be described in detail with reference to the drawings.

【0019】

FIG. 3 shows the circuit configuration of the liquid crystal display device according to the first embodiment. This circuit consists of a high-speed data bus 203 on the glass substrate 305 of the display device, a data driver circuit 307 including a divided low-speed data bus 102, a scanning side drive circuit 210, and a pixel portion of active matrix type pixels composed of a thin film transistor. Consists of 209. These circuits are formed by a CMOS TFT forming processor.

【0020】

As a method for forming a TFT substrate, non-alkali glass is used as a TFT substrate as a Si film, low-temperature polysilicon by a laser annealing growth method is used as a method for forming a Si crystal film, and high-temperature polysilicon by a solid-state growth method is used as a quartz glass substrate. Polycrystalline Si film such as, etc. can be used. A TFT substrate can be formed by combining this with a doping method and simultaneously forming pch and nch TFTs on the same substrate.

【0021】

Next, the details of the configuration of FIG. 3 will be described.

【0022】

The display data and synchronization signal required for display from the input terminal 214 are connected to the high-speed bus drive circuit 306. The high-speed bus drive circuit is connected to the high-speed data bus 203 and the high-speed control bus 216. The high-speed data bus 203 and the high-speed control bus 216 are sequentially connected to the high-speed data control circuit 104 and the data alignment circuit 101 arranged for each block 103 via the waveform shaping circuit 303 on the way. The display data is developed in parallel on the low-speed data bus 102 divided into a large number of blocks by the data alignment circuit 101 by the synchronization signal from the high-speed data control circuit 104, and is connected to the latch circuit 302 of each block. The synchronization signal in the block is generated from the synchronization signal on the high-speed control bus 216 by the high-speed data control circuit 104, and is supplied to the block by the low-speed control bus 107 divided into blocks. A plurality of shift registers 301, data latch 302, line memory 205, level shifter 206, and D / A conversion circuit 207 corresponding to the signal wiring 208 of the pixel unit 209 are provided in the block. Further, in the scanning side drive circuit 210, the scanning pulse required for the line sequential scanning of the pixel unit 209 is generated by the synchronization signal supplied by the panel scanning control bus 304 as in the conventional example, and is supplied to the scanning wiring 213 of the pixel unit. ..

【0023】

With the above configuration, the circuit performs the display operation as follows.

【0024】

Dot clock and horizontal synchronization and vertical synchronization signals and display data are converted to low impedance by input terminal 214 high-speed bus drive circuit 306, and level shift processing that adjusts the amplitude of the logic signal to match the logic circuit composed of CMOS TFT. After that, it is connected to the high-speed data bus 203 and the high-speed control bus 216, and is supplied to each block. Further, the waveform shaping circuit 303 intervening in the middle corrects the waveform distortion and the timing deviation between the data and the synchronization signal that occur during bus transmission.

【0025】

In each block, the high-speed data control circuit 104 detects the period during which the data required for processing in the block has arrived from the dot clock and the horizontal synchronization signal on the high-speed control bus, and turns the data alignment circuit 101 into the high-speed data bus. Connecting. In the data alignment circuit 101, the data on the high-speed data bus is rearranged in parallel to the low-speed data bus 102 composed of at least a larger number of wires than the high-speed data bus by the control signal from the high-speed data control circuit 104. The shift register 301, which operates in synchronization with this, sequentially generates a data latch signal in the latch circuit 302, and the latch circuit 302 latches the display data corresponding to the block 103 by latching the display data on the low-speed data bus 102. Transfer to circuit 302. When each block sequentially performs the above operation and the display data for one line is transferred to all the latch circuits, the latch circuit transfers the data to the line memory 205 and is converted into the liquid crystal drive voltage by the D / A circuit. Later, the signal wiring 208 is driven and the pixel unit 209 is driven.

【0026】

Further, the frame start signal input from the input terminal 214 can be displayed by driving the scanning wiring 213 of the pixel unit 209 by the scanning side drive circuit 210 by the panel scanning control bus 304 in the same operation as in the prior art.

【0027】

In this configuration, the larger the number of low-speed data buses, the smaller the number of blocks, the load on the high-speed data bus can be reduced, and the wiring can be lengthened. On the other hand, when the number of data buses increases, wiring can be performed. It is necessary to optimize the number of wirings because the occupied area of the circuit increases and the circuit area increases.

【0028】

The case of an actual panel will be described. In a 640 x 480 pixel panel, when transferring a gradation signal of 640 pixels for one line and 6 bits for each RGB color, it is necessary to transfer 640 x 3 x 6 = 11520 bits. In the conventional example, a shift register circuit Driven at 12.5MHz, and the data wiring was connected to 320 latch circuits per high-speed data wiring inside the 4.7-inch diagonal panel.

【0029】

On the other hand, in the present invention, only a high-speed data alignment circuit having a number of blocks is connected to the high-speed data bus. For example, if the number of blocks is 8 blocks, the number of load circuits connected to the high-speed data bus is 1/40. Can be reduced to. Therefore, when the wiring time constants are compared under the same conditions, the wiring width is only 1/40, and the area of the wiring portion can be reduced.

【0030】

The detailed configuration of each block circuit portion will be described below with the case of 1024 × 768 pixels and the case of 8 blocks. Needless to say, this method can be realized with other pixel configurations.

【0031】

The contents of the high-speed data alignment circuit and the high-speed data control circuit, which are the main parts of the present invention, are shown in FIGS. 4 and 5, respectively. The high-speed control bus 216 is composed of a dot clock bus 401 and a horizontal start signal bus 402. It is composed of a dot counter 403 consisting of a 9-bit binary counter that operates with a dot clock as a clock, a count start signal for the rising edge of the horizontal start signal, and a reset signal for the falling edge, and a decoder circuit 404. The combination of b8 to b0 of each bit output 410 of the dot counter indicates the pixel position on the line of display data appearing on the high-speed data bus (not shown). The output of the dot counter is output as the following necessary control signals by a decoder circuit configured by using a logic circuit.

【0032】

The block selection signal 405 outputs logic "1" during the period when the pixel data included in each block is output to the display data bus. In this case, the upper 3 bits b8 to b6 of the counter output may be decoded. The state of the upper 3 bits of the first block may be (000), the second block may be (001), the third block may be (011), and the eighth block may be (111). For this signal, the pixels handled by one block are n = 1 to 127 pixels in the first block on the left edge of the screen, 128 to 255 pixels in the second block, and 896 to 1024 pixels in the eighth block. .. In Fig. 4, since it is the second block, only b7 is decoded when the logic is 1. A switch 409 is provided for the output of b5 to b0, the switch is controlled so that the following signal is output only when the block selection signal is "1", the operation of unnecessary logic circuits is stopped, and the decoder circuit 404 is consumed. Reduce power.

【0033】

The low-speed start signal 406 is output for a period of 4 clocks from the period when the leftmost pixel in the block is output. This is obtained by taking the NAND when all b5 to b2 are 0.

【0034】

The 4-phase low-speed shift clock 407 from # 1 to # 4 is generated using b1 and b0. # 1 is obtained by b1 and # 3 is the inverted signal of B1, and # 2 is obtained by the EX-OR operation of b1 and b0. # 4 uses the inverted signal of # 2.

【0035】

The four low-speed bus switching signals 408 can be generated by decoding b0 and b1. The dot counter 403 is reset every horizontal cycle by the falling edge of the horizontal start pulse, and the above operation is repeated for each line.

【0036】

The detailed configuration of the data alignment circuit 101 shown in FIG. 5, which is driven by using the synchronization control signal for each block generated in this way, will be described. The function of the high-speed data alignment circuit is to expand the signals on the high-speed data bus in n parallels on the low-speed data bus provided by n times the number of high-speed data buses, and one pixel from the data latch to the D / A conversion process. There is an advantage that the display data processing time per hit can be extended and the display data input at a high speed can be handled even if the wiring response is slow. Here, it is described as n = 4.

【0037】

Each wiring constituting the high-speed data bus 203 is connected to the bus drive circuit 502 via a block selection switch 501 whose continuity is commonly controlled in block units by the block selection signal 405. By doing so, only when the block selection switch is in a conductive state by the block selection signal, the bus drive circuit is connected to the high-speed data bus wiring as a load, so that the capacity load of the high-speed data bus wiring can be reduced and the bus can be made thinner. it can. The output of the bus drive circuit has a function to switch the connection from one signal to four high-speed data buses, and a selector circuit consisting of four CMOS analog switches is configured, and the low-speed bus is controlled by the low-speed bus switching signal. Connected to changeover switch 503. In this case, since the number of low-speed data buses is 4 for each high-speed data bus, 6 × 4 = 24 low-speed buses are used to support the gradation display of 6 bits for each pixel. A large number of data latch circuits and a parasitic capacitance 504 formed by wiring intersections are formed on the low-speed bus, and the voltage of the low-speed data bus wiring is maintained even if the bus changeover switch is disconnected. .. The block selection switch 501, The low speed bus changeover switch 503 can be realized by a combination of other appropriate logic circuits having equivalent functions. Next, the circuit operation will be described below using waveforms. FIG. 6 shows the operation waveforms of each part of the high-speed data control circuit 104 and the data alignment circuit 101 that perform signal conversion processing from the high-speed data bus to the low-speed data bus. Here, the case where n blocks consisting of m pixels per block and the number of low-speed buses inside the block is 4 per bit is shown. Display data from 1 pixel to m × n pixels, which are pixels for one line, are sequentially displayed on the high-speed data bus in synchronization with the positive horizontal synchronization signal. The block selection signal of each block becomes positive logic only during the period when the data corresponding to each block appears, the block selection switch 405 is in a conductive state, and the high-speed data bus 203 is connected to the bus drive circuit 502. The operation of the high-speed data alignment circuit will be described below for the second block containing m + 1 pixels to 2 m pixels. During the period when the data corresponding to the pixels in the second block is supplied, the high-speed data control circuit 104 synchronizes with the high-speed dot clock, and the four low-speeds are phase-delayed by each clock with a period of 4 clocks. Bus switching signals # 1 to # 4 are generated. The low-speed bus changeover switch 503 connects each bit on four low-speed buses by a low-speed bus changeover signal, and m + 1 pixel, m + 5 pixels on the low-speed data bus of # 1 and m + on the # 2 pixel. Data of 2 pixels, m + 6 pixels, and every 4 pixels are imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus. Data of m + 6 pixels and every 4 pixels is imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus. Data of m + 6 pixels and every 4 pixels is imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus. Data of m + 6 pixels and every 4 pixels is imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus. Data of m + 6 pixels and every 4 pixels is imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus. Data of m + 6 pixels and every 4 pixels is imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus. Data of m + 6 pixels and every 4 pixels is imported. Therefore, the data on the low-speed data bus is updated in the following order. The data of the m + 1th pixel is # 1, the data of the m + 2nd pixel is # 2, the data of the m + 3rd pixel is # 3, the data of the m + 4th pixel is # 4, and the data of the m + 5th pixel is # 4. The data on the low-speed data bus is updated every 4 pixels in the order of # 1 for the data and # 2 for the m + 6th pixel. In this way, the serial data in sequence of one pixel transferred by one high-speed data bus is developed in a parallel format of every four pixels on the low-speed data bus.

【0038】

On the low-speed data bus, the data parallelized every 4 pixels with a phase shift of 1/4 cycle from each other is taken into the data latch 302 shown in FIG. 3, so that the high-speed data control circuit uses the shift register 301 inside the block. A 4-phase shift register is used as. A 4-phase clock for driving the 4-phase shift register is generated as a low-speed shift clock. Like the low-speed bus switching signal, the period is four high-speed dot clock cycles, and each phase is phase-delayed by 1/4 cycle. Output of each stage of shift register force becomes a latch signal for driving the data latch 302 of FIG. 3, a high-speed dot clock 4 cycle of the pulse width, has a pulse whose phase is delayed by one clock from one another.

【0039】

The operation of the line memory will be described with reference to FIG. 7. A data latch is connected to the input of the line memory, and the data for one scanning line is updated every horizontal period. The line memory takes in the input of this data input after the update by the line memory control signal and updates the data. The updated data is connected to the D / A conversion circuit 207 of FIG. 3, is instantly converted into a liquid crystal drive voltage, and is supplied to the signal wiring 208 that drives the pixel unit 209. Since the operation waveform of the pixel portion is the same as that of the conventional example, a schematic description will be given. The circuit of the configuration shown in FIG. 8 is connected to the scanning wiring 213 for each line. The shift register 701 is driven by a shift clock having a period of one horizontal period and a pulse of a frame start signal every frame time, and is horizontal. A scanning pulse sequentially shifted for each period period is applied to the scanning wiring 213 of FIG. 3 via the level shifter and the driver circuit 702. Further, in the data driver circuit 307, the display is performed by pixels by applying the liquid crystal drive voltage of each dot to each signal wiring for one line by the D / A conversion circuit in synchronization with the scanning pulse.

【0040】

Next, the second embodiment will be described with reference to FIG. This figure shows the circuit configuration of each block. The feature of this method is that the latch from the data latch to the memory is transferred at different timing for each block. Another feature is that the data is transferred from the line memory to the D / A conversion circuit at different timings for each block. Therefore, as a configuration, a memory selection switch 901 is provided between the latch circuit and the memory circuit, and a D / A conversion circuit selection switch 902 is provided between the line memory and the D / A conversion circuit, and the memory transfer signal 903 and the D / A are provided, respectively. The point is that it is controlled by the conversion transfer signal 904. The memory selection switch and the D / A selection switch use the CMOS analog switch 905 for each line, and use the inverter 906 to obtain the control signals of both polarities for driving the analog switch. The control signals of each analog switch are connected in common, and one block is collectively controlled by the transfer signals 903 and 904. By doing so, the operation of the line memory circuit can be distributed for each block, and there is an advantage that the power consumption can be distributed and the capacity of the power supply circuit can be reduced. Further, by driving the D / A conversion circuit by dividing it into blocks, the power supply current of the D / A circuit can be dispersed in time, so that the current consumption can be reduced and the voltage drop in the power supply wiring can be reduced. There is an advantage that a liquid crystal drive voltage with a small error can be obtained stably even if the wiring resistance is high.

【0041】

According to the present invention, the high-speed data bus and the high-speed control bus formed on the display TFT substrate each transmit high-speed display data and synchronization signals such as a dot clock supplied from the outside via a waveform shaping circuit. Supply to the end of.

【0042】

The display data is expanded in parallel on a large number of low-speed data buses separated for each block, and is taken into the data latch in the block at low speed. After that, it is transferred to the line memory and holds the data for one line. This data is used to convert the digital gradation data of each dot into a gradation voltage applied to the liquid crystal of the pixel.

【0043】

By transferring the display data to a large number of data latches in this way, it is possible to transfer the display data to the circuit around the large panel at high speed as a whole, and a large high-definition panel can be easily configured.

【0044】

[Effect of the invention]

With the liquid crystal display device of the present invention, the load capacitance on the display panel is small, and the display data input to the high-speed data bus can be transmitted to the end of the bus with less waveform distortion even in a large high-definition panel.

[Simple explanation of drawings]

[Figure 1]

It is a schematic block diagram of this invention.

[Figure 2]

It is a schematic block diagram of the prior art.

[Fig. 3]

It is a block diagram of the liquid crystal display circuit block of this invention.

[Fig. 4]

It is a detailed block diagram of a high-speed data control circuit.

[Fig. 5]

It is a detailed block diagram of a high-speed data alignment circuit.

[Fig. 6]

It is explanatory drawing of the operation waveform of each part of a high-speed data alignment circuit.

[Fig. 7]

It is a line memory operation explanatory diagram.

[Fig. 8]

It is a detailed block diagram of a scanning circuit.

[Fig. 9]

It is a block diagram of the 2nd Example of this invention.

[Explanation of symbols]

101 ... data alignment circuit, 102 ... low speed data bus, 103 ... block, 104 ... high speed data control circuit, 105 ... liquid crystal display module, 106 ... digital data driver section, 107. .. Low speed control bus, 203 ... High speed data bus, 209 ... Pixel part, 210 ... Scan side drive circuit, 211 ... Shift register, 212 ... Level shifter, 214 ... Input terminal, 215 ... LCD display module, 216 ... High speed control bus.