Digital signal processing circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a digital data processing circuit, and more particularly to a digital data processing circuit in which error correction processing is performed after digital data is temporarily stored in a memory.

【0002】

[Conventional technology]

An example of a digital data processing circuit for data read from a recording medium is described in Kenji Hayashi, "CD-From Audio to Personal Computer-", Corona, pp.56-71 (1990). This describes the processing contents of the CD playback device and the digital data processing unit included in the device, and the circuit configuration thereof.

【0003】

Further, in Japanese Patent Application Laid-Open No. 10-107648, the number of access to the memory required for CIRC error correction processing is leveled by parallel processing of C1 code and C2 code syndrome operations including read data, and error correction is performed. There is a description of a method and a circuit for realizing high-speed processing. Further, Japanese Patent Application Laid-Open No. 8-167857 describes a method for shortening the time required for the syndrome calculation by simultaneously processing a plurality of words for the syndrome calculation of the RS code, and a circuit for realizing the method.

【0004】

[Problems to be Solved by the Invention]

However, the conventional method is to reduce the number of access to the memory from the error correction circuit or to process multiple words of RS code syndrome at the same time in a system that corrects errors by changing the data reading direction for each code. Although there is a description on how to shorten the processing time required for syndrome calculation, error correction codes are formed in multiple directions like product codes, and it is possible to perform multiple error correction processing collectively in one direction. In some cases, there is a method to reduce the number of accesses from the error correction circuit to the memory, and a method that can speed up the syndrome calculation even when the number of words that need to be processed at one time changes according to the direction of the error correction code. There is no description about the circuit.

【0005】

An object of the present invention is to reduce the number of memory accesses of an error correction circuit, speed up error correction processing, and digital data processing having this circuit even when the number of words required for syndrome calculation processing changes at the same time. It is to speed up the data processing of the circuit.

【0006】

[Means for solving problems]

In order to achieve the above-mentioned problems, in the present invention, data in which at least the first inspection symbol and the second inspection symbol are added to a data field consisting of a plurality of data strings is input, and the input digital data is demolished. In addition to the error correction circuit, demodulation circuit, and error correction circuit, which reads data from the memory and memory that temporarily stores the demodified digital data and corrects or detects the error data, writes or reads data to the memory. In a digital data processing circuit including another circuit, the error correction circuit switches an input to a plurality of error correction codes or a plurality of data on one error correction code, and performs the next operation from several obtained syndromes. By selecting the syndrome used in the above and outputting it from the syndrome calculation circuit, the number of accesses from the error correction circuit to the RAM is reduced, and the speed of the error correction circuit and the digital data processing circuit including this circuit is realized.

【0007】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0008】

FIG. 1 is a block diagram showing a configuration of a digital data processing circuit according to the first embodiment of the present invention.

【0009】

In this figure, 101 is a 2-series simultaneous processing syndrome arithmetic circuit, 102 is a syndrome arithmetic circuit, 103 is a Sn arithmetic circuit, 104 is a Sn-1 arithmetic circuit, 105 is an S0 arithmetic circuit, 106 is an 8-bit data input terminal, and 107 is an 8-bit data input terminal. Addition circuit on GF (2 ^ 8), 108 is reset, 8-bit register with enable, 109 is α ^ n multiplication circuit, 110 is α ^ n-1 multiplication circuit, 111 is α ^ 0 multiplication circuit, 112 is an 8-bit register with enable, 113 is an enable signal input terminal, 114 is a reset signal input terminal, 115 is a select signal input terminal, 116 is an AND circuit, 117 is a select circuit, 118 is an 8 × (n + 1) bit output. It is a terminal.

【0010】

However, the 8-bit digital data input from the 8-bit data input terminal 106 is generated polynomial: G (x) = (x-α ^ n) (x-α ^ n-1) ... (x-α) ^ 0) (Here, α ^ n represents the nth power of α, and α ^ n, α ^ n-1, ..., α ^ 0 are the elements of GF (2 ^ 8), respectively) RS code (code length l, n + 1).

【0011】

The digital data input from the two 8-bit data input terminals 106 is a different RS code, and within each syndrome arithmetic circuit 102, Sn arithmetic circuit 103, Sn-1 arithmetic circuit 104, ..., S0 arithmetic circuit 105 It is input to n + 1 circuits of. This data is input from the enable signal input terminal 113 after being added to the data obtained by multiplying the output of the reset and enable 8-bit register 108 included in the circuit by α ^ i in each Si arithmetic circuit 103, 104, 105. When the enable signal is H, it is reset at the rising timing of the clock and is taken into the enabled 8-bit register 108.

【0012】

Further, the data output from the 8-bit register 108 becomes the input of the select circuit 117 together with the output of the other Sj arithmetic circuits, or becomes the input to the enabled 8-bit register 112. The output data from the reset and enable 8-bit register 108 input to the 8-bit register 112 is when both the reset signal input from the reset signal input terminal 114 and the select signal input from the select signal input terminal 115 are H. When the clock rises, it is taken into the enabled 8-bit register 108 and input to the select circuit 117.

【0013】

One of the two types of data input to the select circuit 117 is selected according to the H and L values of the select signal input from the select signal input terminal 115, and the 8 × (n + 1) bit output terminal. From 118, it is output as output data (symdrome (Sn, Sn-1, ..., S0)) of the two-series simultaneous processing syndrome arithmetic circuit 101.

【0014】

FIG. 2 is an example of a block diagram showing a configuration of an error correction circuit including the two-series simultaneous processing syndrome calculation circuit 101 of FIG.

【0015】

In this figure, 201 is an error correction circuit, 101 is a 2-series simultaneous processing syndrome arithmetic circuit, 113 is an enable signal input terminal, 106 is an 8-bit data input terminal, 202 is a second arithmetic circuit, 203 is a third arithmetic circuit, and 204. Is an error correction circuit, 206 is an error correction reception signal input terminal, 207 is an error position output terminal, 208 is an error value output terminal, 114 is a reset signal input terminal, and 115 is a select signal input terminal.

【0016】

The two-series simultaneous processing syndrome arithmetic circuit 101 using the select signal described above is reset once every two reset signals input to all blocks from the reset signal input terminal 114, and then reset. Two digital data input from the 8-bit data input terminal 106 are taken in by two enable signals synchronized with each of them, and the syndrome for each data string is calculated before the next reset occurs. Further, the syndrome value thus obtained is output from the two-series simultaneous syndrome calculation circuit 101 according to the value of the select signal input from the select signal input terminal 115.

【0017】

The second arithmetic circuit takes in the syndrome output from the two-series simultaneous syndrome arithmetic circuit 101 at the timing of the reset signal input from the reset signal input terminal 114, and generates an error position polynomial and an error evaluation polynomial based on this value. To do. The error position polynomial and error evaluation polynomial generated by the second arithmetic circuit 202 are input to the third arithmetic circuit 203 at the timing of the next processing start signal, and are based on the error position polynomial and error evaluation polynomial in this circuit. After the error position and the error value are obtained, they are taken into the error correction circuit 204 by the next reset signal.

【0018】

Finally, some error positions and error values input to the error correction circuit 204 are controlled by the error correction reception signal input from the error correction reception signal input terminal 206, and the error position output terminal 207, error. The value output terminal 208 of is output one after another to the outside of the error correction circuit 201.

【0019】

Next, it will be described with reference to FIGS. 3 and 4 that the present invention is effective in shortening the error correction processing time.

【0020】

FIG. 3 is a diagram showing the relationship between the time and the frame number in which the calculation is performed in each circuit of the error correction circuit having the syndrome calculation circuit that calculates only one series of syndromes at the same time.

【0021】

In FIG. 3, the vertical axis is the frame number, the horizontal axis is the time, 301 is the syndrome operation, 302 is the second operation (error position polynomial, error evaluation polynomial generation), and 303 is. The third operation (error position, error value operation) is performed, and 304 indicates that the error has been corrected.

【0022】

Further, this figure shows that the error correction processing operation for each frame is shifted to the next frame at the time T + i · Δt. That is, the processing in the error correction circuit having the syndrome calculation circuit that calculates only one series of syndromes at the same time is performed by the four-stage pipeline processing in which the processing time of one pipeline is Δt of the fixed time. There is. Furthermore, from FIG. 3, it can be seen that the processing time Δt of one pipeline of the error correction circuit is determined from the syndrome calculation processing time.

【0023】

Therefore, in a system that requires a long time to input digital data to the error correction circuit, such as when the code length l of the input error correction code is long, this is used when speeding up the error correction processing. The phenomenon becomes a problem.

【0024】

That is, in such a system, speeding up the syndrome calculation and speeding up the data input are indispensable for shortening the error correction processing time.

【0025】

FIG. 4 is a diagram showing the relationship between the time and the frame number in which the calculation is performed in each circuit of the error correction circuit 201 of FIG.

【0026】

In FIG. 4, as in FIG. 3, the vertical axis is the frame number to be error-corrected, the horizontal axis is time, 301 is the syndrome operation, and 302 is the second operation (error position polynomial, error evaluation). Polynomial generation) is performed, 303 indicates that the third operation (error position, error value operation) is performed, and 304 indicates that error correction is performed.

【0027】

In this figure, error correction is performed by 4-stage pipeline processing in the same way as the error correction circuit explained in Fig. 3, only the syndrome calculation is time T + i · Δt, and the other calculations are time T + 1/2 · i. Although it is performed with Δt, in the error correction circuit 201 of Fig. 2, the syndrome calculation can be performed for two series at the same time. Therefore, by outputting the obtained syndrome while switching the time 1/2 i Δt, 1 It shows that the processing time of the pipeline can be set to 1/2 · Δt.

【0028】

As a result, compared to the system shown in Fig. 3, this system substantially performs syndrome operations without changing the code length of the RS code to be input or the time required to input digital data to the error correction circuit. It can be seen that the same effect as the double speeding can be obtained, and the error correction processing time for two series can be shortened by 2.Δt.

【0029】

Further, in this process, in the error correction circuit 201 of FIG. 2, two types of control signals (reset signal and select signal) are input at the timing of FIG. 4, and are output from the syndrome calculation circuit 101 to the second calculation circuit 202. When the reset signal of (T + i · Δt) = H, the value of the 8 × (n + 1) bit syndrome is set as the output from the reset and enabled 8-bit register 108 in Fig. 1, and (T + (1/2). When the reset signal of + i) · Δt) = H, it is realized by outputting the value of the syndrome held for (1/2 · Δt) by the 8-bit register 108 with reset and enable once.

【0030】

Further, in the error correction circuit 201 of FIG. 2, in the syndrome calculation circuit 101 of FIG. 1, the select signal input from the select signal input terminal 115 is fixed to H, and the 8-bit data can be obtained only from the 8-bit data input terminal 106. Of course, it is also possible to perform the same operation as the error correction circuit that performs the syndrome calculation of only one series as shown in Fig. 3 by inputting.

【0031】

The two-series simultaneous syndrome calculation circuit has been described above, but the same effect can be obtained by using a circuit capable of simultaneously performing three-series, four-series, ... and multiple-series syndrome operations. it can.

【0032】

FIG. 5 is a block diagram showing a configuration of a digital signal processing circuit according to a second embodiment of the present invention.

【0033】

In this figure, 501 is a 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit, 508 is a syndrome arithmetic circuit with × α ^ i output, 509 is a syndrome arithmetic circuit, 103 is a Sn arithmetic circuit, and 502 is × α ^. Sm arithmetic circuit with m or × α ^ 2m selector, 105 is S0 arithmetic circuit, 506 is 8-bit data input terminal for high-order byte data, 507 is 8-bit data input terminal for low-order byte data, 107 is GF (2 ^ 8) Above addition circuit, 108 is reset, 8-bit register with enable, 109 is α ^ n multiplication circuit, 503 is α ^ m multiplication circuit, 111 is α ^ 0 multiplication circuit, 112 is enable 8-bit register, 113 is the enable signal input terminal, 114 is the reset signal input terminal, 115 is the select signal input terminal, 505 is the mode signal input terminal, 116 is the AND circuit, 504 is the OR circuit, 117 is the select circuit, and 118 is 8 × (n +). 1) It is a bit output terminal.

【0034】

However, the 8-bit data input from the 8-bit data input terminal 506 for the upper byte and the 8-bit data input terminal 507 for the lower byte handled here are Generation polynomial: Two sets of RS codes (l, n + 1) consisting of G1 (x) = (x-α ^ n) (x-α ^ n-1) ... (x-α ^ 0). Or Generation polynomial: A 2-byte set of RS code (k, m + 1) consisting of G2 (x) = (x-α ^ m) (x-α ^ m-1) ... (x-α ^ 0) Data (D2i + 1, D2i). (The data string with RS (k, m + 1) code is (Dk-1, Dk-2, ..., Dm + 1, Dm, ..., D0).) In this 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501, the value of the mode signal input from the mode communication input terminal 505 is L, and two RS codes having the same code length at the same timing are higher. When input is performed from the 8-bit data input terminal 506 for bytes and the 8-bit data input terminal 507 for lower bytes, the operation is the same as that of the 2-series simultaneous syndrome calculation circuit 101 shown in FIG. Also, when the value of the mode signal is H, from the 8-bit data input terminal 506 for the upper byte and the 8-bit data input terminal 507 for the lower byte (Dk-1, Dk-2, ..., Dm + 1, Dm ,. Input 2-byte set data of RS code represented by .., D0) in the order of (Dk-1, Dk-2), (Dk-3, Dk-4), ..., (D1, D0). Then, the syndrome calculation circuit 508 with × α ^ i output and the syndrome calculation circuit 509 have different data sequences, respectively (Dk-1, Dk-3, ..., D1), (Dk-2, Dk-4,, ..., D0) is entered.

【0035】

× α ^ i Syndrome calculation circuit with output D2i + 1 is input to n + 1 circuits of the calculation circuit 103, ..., Sm calculation circuit 502, ..., S0 calculation circuit 105 in the calculation circuit 508 at the same time. In the Si (i = n, ..., m + 1) arithmetic circuit, the data output from the reset and enable 8-bit register 108 included in the circuit is added to the data obtained by multiplying the data by α ^ i. In the Sj (j = m, ..., 0) arithmetic circuit, the data output from the reset and enable 8-bit register 108 included in the circuit is added to the data obtained by multiplying α ^ j twice. After that, when the enable signal input from the enable signal input terminal 113 is H, it is reset at the rising timing of the clock and is taken into the enable 8-bit register 108.

【0036】

Similarly, D2i is input to n + 1 circuits of Sn arithmetic circuit 103, ..., Sm arithmetic circuit 502, ..., S0 arithmetic circuit 105 in the syndrome arithmetic circuit 509 at the same time, and Si (i = In the n, ..., m + 1) arithmetic circuit, add the data output from the reset and enable 8-bit register 108 included in the circuit by α ^ i, and add Sj (j = m, ..., 0) In the arithmetic circuit, the enable signal is added after adding the data output from the reset and enable 8-bit register 108 included in the circuit to the data obtained by multiplying α ^ j twice. When the enable signal input from the input terminal 113 is H, it is reset at the rising timing of the clock and is taken into the enabled 8-bit register 108.

【0037】

The signal captured in the 8-bit register 108 with reset and enable becomes the output from the Si (i = n, ..., 0) arithmetic circuit, and from the syndrome arithmetic circuit 508 with × α ^ i output, j For (m), the value obtained by xα ^ j of the value of the 8-bit register 108 with reset and enable is also output.

【0038】

The output after xα ^ j of the syndrome arithmetic circuit 508 with × α ^ i output after all one RS code is input, that is, after k / 2 data are input to each syndrome arithmetic circuit. The output values for j (m) of the syndrome arithmetic circuit 509 are, respectively. Sj_508 = Dk-1 α ^ (j (k-1)) + Dk-3 α ^ (j (k-3)) + ... + D1 α ^ j, Sj_509 = Dk-2 α ^ (j (k-2)) + Dk-4 α ^ (j (k-4)) + ... + D0.

【0039】

From this, when the mode signal input from the mode signal input terminal 505 is H, (Sm_1, Sm-1_1, ..., S0_1) and (Sm_2,) are transmitted from the 8 × (n + 1) bit output terminal 118. The syndrome (Sm, Sm-1, ..., S0) obtained by adding each of Sm-1_2, ..., S0_2) is output.

【0040】

From the above, the 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501 simultaneously processes 1-series RS code for 2 bytes when the mode signal input from the mode signal input terminal 505 is H, and the mode signal is generated. It can be seen that when L, two series of RS codes are processed at the same time.

【0041】

FIG. 10 is a block diagram showing a configuration of a digital disk player having an error correction circuit 1005 including a 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501 of FIG.

【0042】

First, the format of the digital data written on the disk 1001 of FIG. 10 will be described. The signal recorded on the disk 1001 is created by constructing "data sector 601", "ECC block 701", "recording sector 802", and "physical sector 901" in this order from the main data.

【0043】

FIG. 6 is a diagram showing the configuration of one data sector 601.

【0044】

Using this figure, the flow from the main data to the creation of one data sector 601 will be described.

【0045】

First of all, 2048 bytes of main data 602 divided in time series, 4 bytes of identification data (ID) 603, 2 bytes of ID error detection code (IED) 604, 6 bytes of copyright management information (CPR_MAI) 605 Is added to the beginning of the main data. Furthermore, one data sector 601 is generated by adding a 4-byte error detection code (EDC) 606 to the 2060-byte data at the end of the data 203.

【0046】

FIG. 7 is a diagram showing the configuration of 1 ECC block 701.

【0047】

Using this figure, the flow from 16 data sectors 601 to 1 ECC block 701 being created will be described.

【0048】

First, a 16-byte external code (PO702) is added to each 172-byte column of the 16-data sector 601. Next, a 10-byte internal code (PI703) is added to each of the generated 208 lines. The data field consisting of 208 rows x 182 bytes generated in this way is called 1 ECC block 701.

【0049】

However, the PI sign is Generation polynomial GPI (x) = (x-α ^ 9) (x-α ^ 8) ... (x-α ^ 0) It is an RS (182,172,11) code consisting of, and the PO code is Generation polynomial GPO (x) = (x-α ^ 15) (x-α ^ 14) ... (x-α ^ 0), It is an RS (208,192,17) code consisting of.

【0050】

FIG. 8 is a diagram showing the configuration of the recording sector 802.

【0051】

One recording sector 801 is a data field of 182 bytes × 13 lines in which one line of PO702 added when 1ECC block 701 is generated is combined under one data sector of 12 lines including PI703.

【0052】

FIG. 9 is a diagram showing the configuration of one physical sector 901.

【0053】

The flow from one recording sector 801 to the creation of one physical sector will be described with reference to this figure.

【0054】

One recording sector 801 is vertically divided into two at the beginning (one divided block is 91 bytes x 13 lines), and as shown in Fig. 9, 32-bit SYNC code 902 (SY0 to SY7) at the beginning of each line. Is added. Then, the data divided into two is resynthesized, and the data of 182 x 13 bytes excluding the SYNC code 902 is 8/16 modulated to suppress the DC component (based on a data table with data composed of 8 bits). A system that converts to 16 channel bits). The 2976 × 13-bit data created in this way is one physical sector 901, and this signal becomes a disk recording signal and is written to the disk 1001 in FIG.

【0055】

A digital disk player having an error correction circuit 1005 including a 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501 shown in FIG. 10 will be described.

【0056】

In Fig. 10, 1001 is a disk, 1002 is a pick, 1003 is a demodulator circuit, 1004 is RAM, 105 is an error correction circuit with 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome calculation circuit, 1006 is an output circuit, and 1007 is a control. The circuit, 1008 is the data request signal input terminal, and 1009 is the main data output terminal.

【0057】

The RAM 1004 included in this digital disc playback device is read and written in 2-byte units.

【0058】

In this figure, the digital signal read from the disk 1001 by the pick 1002 is first input to the demodulation circuit 1003. The demodulation circuit 1003 detects the SYNC code 902, performs 8/16 demodulation, sends a data write request signal to the RAM 1004 to the control circuit 1007, sends the SYNC code 902, and then PIs to the address sent from the control circuit 1007 to the RAM 1004. Write 2-byte data in the direction at once. When the demodulation circuit 1003 writes the data of the 1ECC block 701 to the RAM 1004, the control circuit 1007 causes the error correction circuit 1005 to perform error correction processing in the order of PI correction for 208 series and PO correction for 172 series.

【0059】

The control circuit 1007 sets the mode signal of the error correction circuit 1005 to H during the period when the error correction for the 208 series PI code is performed, and when the data is not written from the demodulator circuit 1003 to the RAM 1004, the error correction is performed from the RAM 1004. By making the circuit 1005 output 2 bytes of data and at the same time setting the enable signal input to the error correction circuit 1005 to H, the syndrome calculation circuit can take in the 2 bytes of data included in the PI code at a time, and the PI code. Syndrome arithmetic processing for.

【0060】

During PO correction, the control circuit 1007 sets the mode signal value of the error correction circuit 1005 to L, and the RAM 1004 inputs 2 bytes of data in the PI direction to the error correction circuit 1005 in the same way as when the PI is corrected. By setting the enable signal to H at the same time, the syndrome arithmetic circuit is made to perform two series of PO corrections at the same time. In the control circuit 1007 in this figure, the error correction circuit 1005 corrects the error on the RAM 1004 based on the reset signal that teaches the error correction circuit 1005 the switching timing of the pipeline processing and the position of the error obtained by the error correction circuit 1005. The demodulation circuit 1003 error correction circuit prepares for the external data request input from the data request signal input terminal 1008 by generating the control signal of RAM1004 and the data of 1 ECC block that has undergone error correction processing. Controls such as output to the output circuit 1006 when access from 1005 to RAM1004 is not performed.

【0061】

Even in a device where data temporary storage circuits such as RAM1004 are accessed from multiple circuits as shown in this figure, if the 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit 501 shown in Fig. 5 is used, an error correction circuit will be used. Since the 1005 can halve the number of accesses required to read data from the RAM 1004, the error correction processing time can be shortened as shown with reference to FIGS. 3 and 4.

【0062】

Further, when speeding up the reading of data from the disk 1001 and increasing the data processing speed in the apparatus, there are problems such as a method of speeding up each processing circuit and an increase in the number of RAM accesses from each processing circuit. Since the number of accesses from the error correction circuit 1005 to the RAM 1004 can be reduced by using the circuit of, the error correction processing can be speeded up as explained with reference to FIG. 4, and from other processing circuits. It can be seen that the present invention is very effective for speeding up the system having the circuit configuration as shown in FIG. 10 because it can cope with the increase in the number of RAM accesses.

【0063】

In this embodiment, a digital signal circuit having a syndrome calculation circuit capable of simultaneous calculation of 2 series and 2 bytes of 1 series has been mainly taken up, but all multiple series such as 3, 4, 5, ... The same effect can be obtained by having a syndrome calculation circuit capable of simultaneous calculation and simultaneous calculation of multiple series and multiple bytes.

【0064】

Further, the effect of the syndrome circuit described can be obtained by a circuit configuration other than the digital data reproduction device shown in FIG.

【0065】

[Effect of the invention]

As described above, according to the present invention, in a data reproduction processing device that inputs data in which error correction is performed in a plurality of directions, a plurality of data strings or a plurality of inputs of a syndrome calculation circuit included in the error correction circuit are input to the same data string. By switching to data, selecting the syndrome to be used in the next calculation from the obtained multiple syndromes, and outputting from the syndrome calculation circuit, the memory access of the error correction circuit even when the number of data required to be processed changes at the same time. It is possible to reduce the number of times, speed up the error correction processing, and speed up the processing of the digital signal processing circuit having this circuit.

[Simple explanation of drawings]

[Figure 1]

Diagram of two-series simultaneous syndrome arithmetic circuit.

[Figure 2]

The figure of the error correction circuit which has 2 series simultaneous syndrome arithmetic circuit.

[Fig. 3]

The figure which showed the relationship between the series number and time in the error correction circuit which has an existing syndrome calculation circuit.

[Fig. 4]

The figure which showed the relationship between the series number and time in the error correction circuit which has 2 series simultaneous syndrome calculation circuit.

[Fig. 5]

Diagram of 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit.

[Fig. 6]

Diagram of one data sector.

[Fig. 7]

Diagram of 1 ECC block.

[Fig. 8]

Diagram of recording sectors.

[Fig. 9]

Diagram of one physical sector.

[Fig. 10]

Diagram of a disc player.

[Explanation of symbols]

101 ... 2 series simultaneous syndrome arithmetic circuit, 102 ... syndrome arithmetic circuit, 103 ... Sn arithmetic circuit, 104 ... Sn-1 arithmetic circuit, 105 ... S0 arithmetic circuit, 106 ... 8 Bit data input terminal, addition circuit on 107 ... GF (2 ^ 8), 108 ... reset, 8-bit register with enable, multiplication circuit of 109 ... α ^ n, 110 ... α ^ n -1 multiplication circuit, 111 ... α ^ 0 multiplication circuit, 112 ... 8-bit register with enable, 113 ... enable signal input terminal, 114 ... reset signal input terminal, 115 ... select Signal input terminal, 116 ... AND circuit, 117 ... select circuit, 118 ... 8 × (n + 1) bit output terminal, 201 ... error correction circuit, 202 ... second arithmetic circuit, 203 ... 3rd arithmetic circuit, 204 ... error correction circuit, 206 ... error correction reception signal input terminal, 207 ... error position output terminal, 208 ... error value output terminal, 501. .. 1-series 2-byte simultaneous processing or 2-series simultaneous processing syndrome arithmetic circuit, 502 ... × α ^ m or × α ^ 2m Sm arithmetic circuit with selector, 503 ... α ^ m multiplication circuit, 504 .. .OR circuit, 505 ... mode signal input terminal, 506 ... 8-bit data input terminal for upper byte data, 507 ... 8-bit data input terminal for lower byte data, 508 ... × α ^ i output Syndrome arithmetic circuit with, 509 ... Syndrome arithmetic circuit.