Memory management unit and its control method for ethernet controller

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a memory management device of an Ethernet controller and a management method thereof, and more particularly to a memory management device of an Ethernet controller for storing data received from the Ethernet controller and a management method thereof.

【0002】

[Conventional technology]

In order for many computers to operate independently and exchange information with each other, management technology using a unified protocol is indispensable. Recently, users have made it the biggest task to transmit a large amount of information within a short time, which indicates an increase in the amount of information per unit time. Therefore, it is necessary to connect a large number of computers with one network and smoothly exchange information between terminals within the range of the network.

【0003】

Therefore, it is necessary to distinguish whether the terminal sends / receives data within the range of one network or sends / receives data in another network. Therefore, a repeater called a hub or repeater is set up to manage data exchange in the network. The greater the number of terminals in the network connected to these repeaters, that is, the number of channels, the more difficult the technology for managing them. Therefore, the better the performance of the repeater, the more it is necessary to investigate the content of the data transmitted and received by each terminal and control it accordingly so that the bottleneck phenomenon does not occur in the network.

【0004】

Hereinafter, Ethernet communication will be described with reference to the drawings.

【0005】

Figure 1 is a configuration diagram of an Ethernet frame according to the IEEE 802.3 standard. In the Ethernet communication method, the IEEE (Institute of Elec-trical and Electronic Engineers) 802.3 convention is called CSMA / CD (carrier sense multiple acc-ess with collision detection).

【0006】

A terminal operating in the CSMA / CD system checks the carrier in the transmission line before transmission and performs frame transmission if the channel is available. However, if there is transmission on another terminal at the time of transmission, a collision inevitably occurs between frames. As soon as a collision is detected, the transmission of the rest of the frame being transmitted is interrupted and prepared for re-transmission after a certain period of time.

【0007】

Therefore, in the CSMA / CD system, when the frames transmitted by the terminal collide with each other by sharing the transmission medium, the physical layer and the data link layer are provided with a function of detecting the collision with the carrier and a function of retransmitting.

【0008】

As shown in Fig. 1, the frames used in the IEEE802.3 system are preamble, starting frame delimiter (hereinafter referred to as SFD), destination address, source address, and so on. It consists of length or ethertype, information data and frame-check sequence (hereinafter referred to as FCS).

【0009】

The preamble matches the bit synchronization for matching the transmission / reception speed between the transmitting side and the receiving side. SFD is a frame synchronization bit string that signals the start of a valid frame. The destination address and the source address indicate the address of the destination Ethernet card and the address of the transmitting Ethernet controller, respectively. The length or ether type indicates the length of the information data area of the frame or determines the Ethernet type. The information data area is actually loaded with valid data, and there is padding that is supplemented with 0 when it is smaller than the minimum length of the frame. FCS is used to detect the occurrence of errors in the bit string of the valid frame excluding the preamble and SFD.

【0010】

Fig. 2 (a) and Fig. 2 (b) are block diagrams showing frame transmission and reception by the Ethernet controller, respectively.

【0011】

Direct memory access (hereinafter referred to as DMA) 2 existing in the Ethernet controller at the time of data transmission interprets the data to be transmitted in memory 1 and MAC (medium access control) which is a sub-layer of the data link hierarchy. ) Communicate to 3. At this time, MAC3 adds the preamble, SFD, padding and FCS described above to the transmitted data and transmits it to the physical hierarchy. At this time, the central processing unit (hereinafter referred to as CPU) organizes the address of the terminal to be transmitted and the address of the receiving terminal at the time of data transmission in the memory in advance and informs the DMA in advance.

【0012】

On the contrary, when data is received, the received data transmitted from the physical hierarchy is transmitted to DMA2 ́ by removing the preamble and SFD by MAC3 ́. DMA2 ́ saves this in memory 1 ́ without the help of the CPU.

【0013】

On the other hand, the CPU informs the DMA of the address of the data to be transmitted and the storage address of the received data when transmitting and receiving data through the frame descriptor. Here, the frame instructor is allocated to the memory area by the CPU, and the frame instructor is read by the pointer (frame descriptor pointer).

【0014】

FIG. 3 is a configuration diagram of a frame instructor used in the Ethernet controller.

【0015】

One frame instructor 5 is mapped 1: 1 with one frame at the time of transmission / reception. As shown in FIG. 3, one frame pointer is a data pointer 5a, a status field 5b, a length field 5c, a control field 5d and an indicator pointer ( descriptor pointer) Consists of 5e. Here, the data pointer 5a is a 32-bit pointer indicating the initial address of the data to be transmitted and the data received and stored in the memory. The status field 5b contains bits indicating the resulting status after transmission and reception and the type of error when an error occurs. The length field 5c indicates the length of the data in the frame to be sent and received, and the control field 5d specifies the method when sending and receiving the frame. The indicator pointer 5e currently has the address of the frame indicator concatenated next to the frame indicator 5. In this way, many frame directives have a linked list structure.

【0016】

FIG. 4 is a drawing showing a method of transmitting and receiving data using a frame instructor with an Ethernet controller.

【0017】

In FIG. 4, the frame descriptor pointer 10 is provided separately from the frame indicator 20 to 22 and manages the frame indicator having a large number of linked list structures. That is, the frame instructor pointer 10 has the address of the currently executed frame instructor 20, and when all the current frame instructors 20 are executed, the value of the instructor pointer 20e, that is, the current frame instructor It is updated to the address of the frame instructor connected next to.

【0018】

A large number of frame instructors 20 to 22 are allocated by the CPU to specific areas of memory in a linked list structure. At this time, the frame instructor pointer 10 will indicate the first frame instructor among the many frame instructors 20 to 22 created.

【0019】

Data to be transmitted is configured in the memory 30 at the time of transmission, and 1518 bytes, which is the length of the maximum frame information data, is sequentially secured at regular intervals in advance in order to store the received data at the time of reception.

【0020】

Next, the data transmission / reception process using the Ethernet controller will be described with reference to FIG.

【0021】

When transmitting data, first, the data to be transmitted is configured in the memory 30. The data pointer 20a of the frame instructor 20 is set to the initial address of the transmission data, and the length field 20c is set to the length of the transmission data. The address of the frame instructor 21 concatenated next to the currently executed frame instructor 20 is set in the instructor pointer 20e. Finally, the transmission data is transmitted through the Ethernet controller by setting the transmission control bit in control field 20d. When the transmission is completed, the status field 20b is set with a bit indicating the result, and the frame indicator pointer 10 is updated to the value of the indicator pointer 20e.

【0022】

On the other hand, in the case of data reception, the data input from the MAC is received by the frame instructor 20 indicated by the frame instructor pointer 10. That is, the received data is stored in the memory 30 area specified by the data pointer 20a. At this time, the length field 20c is set by the length of the received data, and the state field 20b indicates the result of reception. Again, when reception is complete, the frame instructor pointer 10 is updated to the value of the instructor pointer 20e. Here, since the length of the data to be received cannot be known in advance, the maximum reception length must be secured in advance in the memory 30. The maximum length that can be received by IEEE802.3 is 1518 bytes. Therefore, the memory 30 is sequentially allocated in advance at intervals of 1518 bytes, and the reserved memory start addresses are set in the data pointers 20a, 21a, and 22a of the frame instructors 20 to 22, respectively. For example, if the data pointer 20a of the first frame instructor 20 is set to the address 1000, the data pointer 21a of the second frame instructor 21 is set to the address 2518 separated by 1518 bytes.

【0023】

[Problems to be Solved by the Invention]

For example, if the length of the first received frame data is short, that is, 64 bytes, the data is saved from the address 1000, which is the first memory area, and the remaining memory area excluding 64 bytes is free. It will remain in the state. Then, since the frame data received next is stored from the address 2518, which is the second memory area, the data is not used for the memory, and an area remaining in a free state is generated. When the received data is generally short, such an unused memory area becomes much larger than the used memory area, resulting in a great waste of memory.

【0024】

Therefore, an object of the present invention is to solve the conventional problem by adding the length field value of the currently received frame and the previously available memory address when receiving a frame from the Ethernet controller. The purpose is to provide a variable and compact memory space for frames received in Ethernet.

【0025】

[Means for solving problems]

To achieve the above object, the present invention detects the length of a frame while receiving an Ethernet frame in the memory management device of the Ethernet controller. The length of the detected frame is added to the memory address currently used by the database pointer. After all, the added values are linked in a linked list structure and then used as a memory address.

【0026】

A memory management device for an Ethernet controller according to an embodiment of the present invention includes a monitoring unit, a counter, and a detection unit. Here, the monitoring unit monitors the start and end of the Ethernet frame, the counter is initialized by the monitoring unit, and the counter is increased by receiving the Ethernet frame in a fixed unit. In addition, the detection unit detects the length field value when the Ethernet frame is received, adds the length field value to the current memory address, and outputs the new memory address for the next frame.

【0027】

The present invention further includes a frame buffer that temporarily stores when an Ethernet frame is received. It further contains a first buffer that temporarily stores the current memory address, and further contains a second buffer in which a new memory address is calculated and temporarily stored. Further, the update controller can be further included in connection with the detection unit. The update controller receives the input of the first control signal from the detection unit and outputs the bus request signal to the control bus. Further, after receiving the input of the bus permission signal from the central processing unit through the control bus, the second control signal is output so as to set a new memory address in the memory.

【0028】

The present invention has information for receiving Ethernet frames and storing them in a memory for each Ethernet frame, and such information is linked by a linked list structure and stored in a database that is accessed sequentially. Here, the database consists of a memory address, a state field, a length field, a control field, and an address pointer.

【0029】

The memory management device of the Ethernet controller according to another embodiment of the present invention includes a large number of frame instructors, a monitoring unit, a counter, a detection unit, and a control unit.

【0030】

A large number of frame instructors include memory addresses for receiving Ethernet frames and storing them in memory, which are linked in a linked list structure and accessed sequentially. The monitoring unit monitors the start and end of the Ethernet frame, the counter is initialized by the monitoring unit, and the counter is incremented by receiving the Ethernet frame in a fixed unit.

【0031】

When the Ethernet frame is received, the detector outputs an interrupt signal after detecting the length field value. Upon receiving the interrupt signal, the control unit updates the length field value to the memory address of the frame instructor currently used and the memory address of the next concatenated frame instructor .

【0032】

On the other hand, the control method according to one embodiment of the present invention monitors the start and end of the Ethernet frame, thereby initializing the frame counter and setting the position of the Ethernet frame length field in the frame length detector. While receiving an Ethernet frame, increment the frame counter to determine if the frame counter value is the position of the Ethernet frame length field. If the frame counter value is the length field position, the length field value is detected to determine if the detection was successful.

【0033】

If the length field value is successfully detected, it is updated to the memory address for the next Ethernet frame in addition to the currently used memory address. If the length field value is not detected successfully, the memory address already set is used.

【0034】

On the other hand, in the management method according to another aspect of the present invention, when the detection of the length field value is successful, an interrupt signal is generated and the central processing unit adds the length field value and the memory address where the current data is stored. , Calculates a new memory address for the next frame and updates the existing memory address.

【0035】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the Ethernet controller according to the embodiment of the present invention will be described with reference to the drawings.

【0036】

FIG. 5 is a drawing showing an operation related to a frame instructor in the memory management device of the Ethernet controller according to the embodiment of the present invention.

【0037】

As shown in FIG. 5, the memory management device according to the embodiment of the present invention includes a frame indicator pointer 100, a large number of frame indicator 200 to 220 linked by a linked list structure, a memory 300, and a frame length detector 550. Works in relation.

【0038】

Next, the operation of the memory management device of FIG. 5 will be described. The frame indicator pointer 100 initially points to the first frame indicator 200 of the linked list structure. Then, the data pointer 200a of the first frame instructor 200 indicates the address of the memory 300, that is, the address 1000. On the other hand, the frame length detector 550 detects the currently received frame length field. Therefore, the data pointer 210a of the second frame instructor 210 is added to the previous data point value of 1000 and the current frame length detected by the frame length detector 550, for example, 1064, which is the sum of 64. It is set.

【0039】

FIG. 6 is a block diagram showing a memory management device of the Ethernet controller according to the embodiment of the present invention.

【0040】

As shown in FIG. 6, the memory management device 500 according to the embodiment of the present invention includes a frame start monitoring unit 510, a frame end monitoring unit 520, a frame counter 530, a frame buffer 540, a frame length detector 550, and a current data pointer buffer 560. It consists of the next data pointer buffer 570, the update control 580, and the next frame indicator buffer 590.

【0041】

In FIG. 6, the frame start monitoring unit 510 and the frame end monitoring unit 520 sense the start and end of the frame. The frame counter 530 counts the received frames in bytes, and the frame buffer 540 temporarily stores the received frames. The frame length detector 550 detects the value in the length field at the frame.

【0042】

The current data pointer buffer 560 stores the data pointer 200a value of the current frame indicator 200, and the next data pointer buffer 570 stores the calculated data pointer 210a value of the next concatenated frame indicator 210. The update controller 580 outputs a control signal such as a bus request signal to the CPU in order to save the updated data pointer value to the next frame instructor, and receives a bus permission signal from the CPU, and the memory management device receives the bus permission signal. It will occupy the address bus and the data bus. The next frame instructor buffer 590 has the address of the next frame instructor 210.

【0043】

FIG. 7 is a flow chart showing a memory management method of the Ethernet controller according to the embodiment of the present invention.

【0044】

In the memory management device 500 of the present invention, the frame start monitoring unit 510 monitors the SFD with the received frame to detect the start of the frame. The frame end monitoring unit 520 monitors the FCS and detects the end of the frame (S400). When receiving a frame, the frame start monitoring unit 510 initializes the frame counter 530. At this time, the values of 13 and 14 are set in the frame length detector 550. This value indicates the position of the frame length field in the IEEE 802.3 frame format (S410).

【0045】

Frames are received in bytes and temporarily stored in framebuffer 540 (S420), which increments the frame counter 530 (S430). Determines if the value of frame counter 530 is 13 which is the length field position (S440). When the frame counter 530 reaches 13, the frame length detector 550 detects a length field value of 2 bytes (S450) and determines if the detection was successful (S460).

【0046】

If the detection is successful, the frame length detector 550 adds the value currently stored in the data pointer buffer 560 to the length field value and stores it in the next data pointer buffer 570. Further, the frame length detector 550 sends a first control signal to the update controller 580. Upon receiving the first control signal, the update controller 580 outputs a bus request signal to the control bus (CTRL BUS).

【0047】

The CPU that receives the bus request signal from the update controller 580 through the control bus (CTRL BUS) outputs the bus permission signal. Upon receiving the bus permission signal, the update controller 580 outputs a second control signal to the next frame instructor buffer 590 and the next data pointer buffer 570, respectively. The next frame instructor buffer 590 receives the second control signal and outputs the address of the next frame instructor stored in the address bus (ADD BUS). In addition, the next data pointer buffer 570 receives the second control signal and outputs a new stored data pointer value to the data bus (DATA BUS). This updates the data pointer value for the next frame instructor (S470).

【0048】

If the detection fails, the value initially set by the CPU will be used as it is (S480).

【0049】

In the above-described embodiment, the frame length detector detects the frame length, and after the received frame is saved using the detection result, the data pointer of the frame instructor is updated by the memory address, but other than this. The method is also possible. For example, after successful frame length detection, an interrupt signal is generated, the CPU directly calculates the memory address of the next received frame, and stores this in the data pointer of the next frame instructor.

【0050】

In the embodiment of the present invention, the present invention has been described by taking an IEEE802.3 frame as an example, but the present invention is not limited to the above-mentioned IEEE802.3 frame, and various Ethernet protocols such as IEEE802.4 and IEEE802.5 are used. It goes without saying that it can be applied to an Ethernet controller using.

【0051】

[Effect of the invention]

As described above, according to the present invention, when a variable length frame is received by the Ethernet controller, after detecting the frame length, it is used as a memory address for saving the next frame in addition to the current memory address. As a result, memory waste can be reduced and memory management can be performed efficiently.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of an Ethernet frame according to the IEEE802.3 standard.

[Figure 2]

It is a block diagram which shows the frame transmission and frame reception in an Ethernet controller.

[Fig. 3]

It is a block diagram of a frame instructor used in an Ethernet controller.

[Fig. 4]

It is a figure which showed the method of sending and receiving data by using a frame instructor in an Ethernet controller.

[Fig. 5]

It is a figure which shows the operation about the frame instructor in the memory management apparatus of the Ethernet controller by embodiment of this invention.

[Fig. 6]

It is a block diagram which shows the memory management apparatus of the Ethernet controller by embodiment of this invention.

[Fig. 7]

It is a flow chart which shows the memory management method of the Ethernet controller by embodiment of this invention.

[Explanation of symbols]

100 frame indicator pointer 200 ~ 220 frame instructor 200a ~ 220a Data pointer 300 memory 500 memory management device 510 frame start monitoring unit 520 Frame end monitoring unit 530 frame counter 540 frame buffer 550 frame length detector 560 Data pointer buffer 570 data pointer buffer 580 Update controller 590 frame indicator buffer