Ecc function verification circuit and ecc function verifying method

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to ECC function verification, and more particularly to an ECC function verification circuit and an ECC function verification method for a computer device and other electronic devices.

【0002】

[Conventional technology]

As is well known, an error check and correct circuit (hereinafter abbreviated as ECC circuit) is used when reading data from a storage device such as a random access memory (hereinafter abbreviated as RAM) or a buffer. It is a circuit that detects bit errors in data and corrects error bits.

【0003】

FIG. 9 is a block diagram showing a main part of a storage device equipped with a conventional ECC function verification circuit of this type described in Jitsukaihei No. 5-83847.

【0004】

In FIG. 9, the memory 11 and the memory 12 each use RAM, the memory 11 stores the write data, and the memory 12 stores the check bits generated by the check bit generation circuit 13.

【0005】

The check bit generation circuit 13 generates check bits from the written data based on a 1-bit error correction / 2-bit error detection code (Single-bit Error Correct Double-bit Error Detect code; hereinafter abbreviated as SECDED code).

【0006】

In the verification mode, the write data inverting signal generation circuit 14 generates an inverting control signal for inverting any one bit of the write data at the time of data writing, and the bit inverting circuit 15 generates a write data inverting signal generation circuit 14. The specified write data bit is inverted by the inversion control signal output from.

【0007】

The 1-bit error detection circuit 16 inspects the presence or absence of a 1-bit error by the data read from the memory 11 and the check bit read from the memory 12. Further, the 1-bit error correction circuit 17 corrects the error bit indicated by the 1-bit error detection circuit 16 when a 1-bit error is detected in the data.

【0008】

In FIG. 9, the 1-bit error detection circuit 16 and the 1-bit error correction circuit 17 surrounded by the dotted line constitute the ECC circuit 18.

【0009】

Next, the operation of this conventional ECC function verification circuit will be described with reference to the flowchart of FIG. In this circuit, as a method of verifying the function of the ECC circuit, only one bit of the data to be written to the memory 11 is inverted and written to the memory 11, and when the data is read, the inverted bit is detected as a 1-bit error. Furthermore, the function of the ECC circuit 18 is verified by confirming the operation of correcting the bit.

【0010】

Now, the width of the data to be written to the memory 11 is 64 bits, and the width of the check bits generated from the write data is 8 bits. When the data WD00 to WD63 are written to the memory 11 (step S31 in FIG. 10), the check bit generation circuit 13 generates 8-bit check bits WC00 to WC07 from the 64-bit write data based on the SECDED code (step). S32), write this to memory 12 (step S34 in Figure 10).

【0011】

The write data inversion signal generation circuit 14 outputs an inversion control signal indicating the bit position to be inverted to the bit inversion circuit 15. When inverting the write data bit WD63, the write data inverting signal generation circuit 14 outputs "1" to the exclusive OR circuit XD63 in the bit inverting circuit 15, and "0" to the other exclusive OR circuits. Is output. When "1" is input, the exclusive OR circuit XD63 in the bit inverting circuit 15 inverts the value of the write data bit WD63 (step S33) and outputs it to the memory 11 (step S34).

【0012】

Next, the data WD00 to WD62 and WD63'written in the memory and the check bits WC00 to WC07 are read, and the read data RD00 to RD63 and the read check bits RC00 to RC07 are input to the 1-bit error detection circuit 16.

【0013】

The 1-bit error detection circuit 16 detects the data bit RD63 inverted at the time of writing from the read data RD00 to RD63 and the read check bits RC00 to RC07 as a 1-bit error, and causes a 1-bit error in the 1-bit error correction circuit 17. Notify the bit position that is being used (step S35).

【0014】

The 1-bit error correction circuit 17 inverts the bit in which the 1-bit error indicated by the 1-bit error detection circuit 16 has occurred again to perform error correction (step S36), and sets the read data as MD00 to MD63 (step S37). ..

【0015】

Then, the write data WD00 to WD63 and the read data MD00 to MD63 whose 1-bit error detection / correction by the 1-bit error detection circuit 16 and the 1-bit error correction circuit 17 match, and the write data inversion signal is generated. By confirming that the bit inverted by the circuit 14 and the bit inversion circuit 15 and the bit in which the 1-bit error occurred detected by the 1-bit error detection circuit 16 match, the function of the ECC circuit 18 is normal. Verify that it is working.

【0016】

Next, as another conventional example, a storage device provided with the ECC function verification circuit described in Japanese Patent Application Laid-Open No. 61-226853 will be described. FIG. 11 is a block diagram showing the main part thereof.

【0017】

In FIG. 11, the memory 21 and the memory 22 each use RAM, the memory 21 stores data, and the memory 22 stores the check bits generated by the check bit generation circuit 23.

【0018】

In the verification mode, the read data inversion signal generation circuit 23 generates a control signal that inverts an arbitrary 1 bit of the read data at the time of data reading. The bit inversion circuit 24 inverts one bit of the designated read data by the inversion control signal output from the read data inversion signal generation circuit 23.

【0019】

The 1-bit error detection circuit 25 inspects the presence or absence of a 1-bit error by the data read from the memory 21 and the check bit read from the memory 22. Further, the 1-bit error correction circuit 26 corrects the error bit indicated by the 1-bit error detection circuit 25 when a 1-bit error is detected in the data. In FIG. 11, the 1-bit error detection circuit 25 and the 1-bit error correction circuit 26 surrounded by the dotted line constitute the ECC circuit 27 that is the target of the functional verification of the present invention.

【0020】

Next, the operation of this conventional ECC function verification circuit will be described with reference to the flowchart of FIG. In this circuit, as a method of verifying the function of the ECC circuit, when the data stored in the memory 21 in advance is read, only one bit is inverted, the inverted bit is detected as a one-bit error, and that bit is further corrected. The function of ECC circuit 27 is verified by confirming the operation.

【0021】

Now, let the width of the data for reading and writing the memories 21 and 22 be 64 bits, and the width of the check bits be 8 bits. First, the check bits generated from the data D00 to D63 are written to the memory 21 and the memory 22 from the data D00 to D63 (steps S41, S42, S43 in FIG. 12).

【0022】

The read data inversion signal generation circuit 23 outputs an inversion control signal indicating a bit position to be inverted to the bit inversion circuit 24. When the read data bit RD63 is inverted, the read data inversion signal generation circuit 23 outputs "1" to the exclusive OR circuit XD63 in the bit inversion circuit 24, and outputs "0" to the other exclusive OR circuits. Output. The exclusive OR circuit XD63 in the bit inverting circuit 24 inverts the value of the read data bit RD63 when "1" is input, and reads read data RD00 to RD62, RD63'and check bits RC00 to RC07. Output to the 1-bit error detection circuit 25 (step S44).

【0023】

The 1-bit error detection circuit 25 detects the inverted data bit RD63'as a 1-bit error from the read data RD00 to RD62, RD63'and the read check bits RC00 to RC07, and causes a 1-bit error in the 1-bit error correction circuit 26. Notify the bit position where is occurring (step S45).

【0024】

The 1-bit error correction circuit 26 reverses the bit in which the 1-bit error indicated by the 1-bit error detection time 25 occurs again to perform error correction (step S46), and sets the read data as MD00 to MD63 (step S47). ..

【0025】

Then, by confirming that the bits inverted by the read data inversion signal generation circuit 23 and the bit inversion circuit 24 and the bits in which the 1-bit error has occurred detected by the 1-bit error detection circuit 25 match, ECC Verify that the function of circuit 27 is operating normally.

【0026】

As shown in the flowcharts of FIGS. 10 and 12, what is common to the above two conventional techniques is that, as shown by the double frame in the figure, the data is inverted by 1 bit by the bit inversion circuit to pseudo-bit error. The ECC function is verified by detecting and correcting error bits using the check bits generated from the data before they are generated and inverted, and confirming this series of operations.

【0027】

Note that FIG. 13 shows a time chart in the verification mode in the above-mentioned prior art.

【0028】

[Problems to be Solved by the Invention]

However, the first problem with this conventional ECC verification circuit or detection method is that the equipment configuration required to verify the ECC function becomes large, and the function verification is performed only with the LSI that has the ECC circuit. It means that it cannot be done. The reason is that in order to verify the ECC function, the necessary data is stored in the memory and the ECC function is verified by reading the data, so it cannot be verified unless the memory is mounted in addition to the ECC circuit. As a result, the verification device configuration also becomes large-scale.

【0029】

The second problem is that it takes a long time to verify the function. The reason is that it takes time to perform a series of verifications because the work of writing the data to the memory and reading the data again is performed.

【0030】

Furthermore, the third problem is that it is necessary to set the bit to be verified every time. The reason is that if the data width is 64 bits, in order to verify all the bits, as is clear from Fig. 13, the bits that are inverted and generate a pseudo 1-bit error are set 64 times. There is a need to do. Also, when verifying the case where the circuit fails to "1" ("1" failure) and the case where it fails to "0" ("0" failure), the bit setting becomes 128 times, and before inverting further. This is because it is necessary to consider the value of the data of and the value of the data after inversion.

【0031】

Therefore, an object of the present invention is to provide an ECC function verification circuit and an ECC function verification method having a small device scale.

【0032】

Another object of the present invention is to provide a high-speed ECC function verification circuit and an ECC function detection method.

【0033】

Furthermore, another object of the present invention is to provide an ECC function verification circuit and an ECC function verification method that do not require setting of an error bit.

【0034】

[Means for solving problems]

The first ECC function verification circuit of the present invention includes an ECC function verification data generation circuit that automatically generates verification data in which a pseudo 1-bit error is generated, a bit position in which the 1-bit error is generated, and the verification. Compare the data with the bit position where the ECC circuit detected the 1-bit error, and compare the data value before the 1-bit error is generated with the data value after the ECC circuit corrects the 1-bit error. As a result, an ECC function verification control circuit for verifying the function of the ECC circuit is provided.

【0035】

Further, the second ECC function verification circuit of the present invention is an ECC function verification data generation circuit that automatically generates verification data in which a 1-bit error of "1" failure and "0" failure is generated in a pseudo manner for each clock. In the verification mode, the normal data / verification data selector that selects the verification data instead of the memory write data, and in the verification mode, the verification data is displayed instead of the check bit for the memory write data. Compare the normal check bit / verification check bit selector that selects the verification check bit with the bit position that caused the 1-bit error and the bit position where the ECC circuit detected a 1-bit error from the outputs of the two selectors. In addition, an ECC function verification control circuit is provided to verify the function of the ECC circuit by comparing the data value before the 1-bit error is generated and the data value after the ECC circuit corrects the 1-bit error. It is characterized by that.

【0036】

Further, in a preferred embodiment of the ECC function verification circuit of the present invention, in the verification data, only one bit out of all 0 (1) corresponding to the memory read / write data bit width is 1 (0). "), And this" 1 "(" 0 ") is sequentially shifted for each clock to generate the data.

【0037】

Further, the ECC function verification method of the present invention includes a procedure for automatically generating verification data in which a 1-bit error of a pseudo "1" failure and a "0" failure is generated for each clock, and the verification data and the verification data. A procedure for detecting a 1-bit error in the verification data, a procedure for correcting the 1-bit error, a bit position where the 1-bit error was generated, and a bit position for the detected 1-bit error. The procedure for verifying the function of the ECC circuit by comparing the data value before the 1-bit error is generated and the data value after the 1-bit error is corrected is described in the memory read / write data bit. It is characterized by performing pipeline processing for the width.

【0038】

In the present invention, instead of storing the data necessary for verifying the ECC function in the memory, a circuit that automatically generates the verification data is inserted, and the characteristics of the SECDED code are considered and applied to obtain the data for ECC function verification. It is automatically generated at high speed and accurately, and the data is directly input to the ECC circuit without being stored in the memory.

BEST MODE FOR CARRYING OUT THE INVENTION

【0039】

Next, an embodiment of the present invention will be described with reference to the drawings.

【0040】

FIG. 1 shows a block diagram of a main part of a storage device having the ECC function verification circuit of the present invention. In the present embodiment, instead of storing the data for verifying the ECC function in the memory as in the conventional case, the ECC function verification data generation circuit 5 that automatically generates the verification data and the ECC function verification control circuit 4 that controls the verification. Is used.

【0041】

That is, the ECC function verification data generation circuit 5 automatically generates data in which only one bit is inverted with respect to the normal data based on the SECDED code. The function of the ECC circuit is verified by detecting the error bit with the 1-bit error detection circuit 8 and confirming whether the data is corrected to normal data with the 1-bit error correction circuit 9.

【0042】

As shown in FIG. 1, this storage device includes a memory (data storage unit) 1, a memory (check bit storage unit) 2, a check bit generation circuit 3, an ECC function verification control circuit 4, and an ECC function verification data generation. It is composed of a circuit 5, a normal data / verification data selector 6, a normal check bit / verification check bit selector 7, a 1-bit error detection circuit 8, and a 1-bit error correction circuit 9.

【0043】

Memory 1 and memory 2 each use RAM, memory 1 stores write data, and memory 2 stores check bits generated by the check bit generation circuit 3. The check bit generation circuit 3 generates check bits from the written data based on the SECDED code. The memory 1, the memory 2, and the check bit generation circuit 3 are used at the time of normal memory access, and are not used at the time of verification of the ECC function to which the present invention is applied.

【0044】

The ECC function verification control circuit 4 switches between the normal mode and the verification mode, checks the verification result, and notifies the verification result.

【0045】

The ECC function verification data generation circuit 5 automatically generates data used for function verification of the ECC circuit.

【0046】

The normal data / verification data selector 6 selects data during normal access and verification mode, and the normal check bit / verification check bit selector 7 selects check bits during normal access and verification mode.

【0047】

The 1-bit error detection circuit 8 inspects the data for 1-bit error, and the 1-bit error correction circuit 9 corrects the error bit indicated by the 1-bit error detection circuit 8 when a 1-bit error is detected in the data. Do.

【0048】

ECC function verification control circuit 4, ECC function verification data generation circuit 5, normal data / verification data selector 6 and normal check bit / verification check bit selector 7 constitute the ECC function verification circuit of the present invention, and are surrounded by dotted lines. A certain 1-bit error detection circuit 8 and 1-bit error correction circuit 9 constitute an ECC circuit 10 whose function is to be verified.

【0049】

Before explaining the operation of this embodiment, the characteristics of the general SECDED code and check bit used in the present invention will be described.

【0050】

Figure 7 shows the SECDED code table, and Figure 8 shows the correspondence table between syndromes and error bits. As shown in FIG. 7, the check bit generation circuit 3 generates 8-bit check bits from 64-bit data.

【0051】

The check bit can be generated by exclusive-ORing the bit with "1" among the horizontal elements of the write data part of the SECDED code table. As an example, Fig. 2 shows a circuit that generates check bit C00. With reference to FIG. 2, it can be seen that the adjacent bits in which "1" of the write data stands are exclusively ORed one after another, and finally the check bit C00 is obtained. The method of generating check bits C01 to C07 is the same.

【0052】

What is important in the characteristics of check bits is that the number of "1" s in the horizontal element of the write data is an even number of 26 for all check bits. That is, when the values of the data bits D00 to D63 are all "0" or all are "1", the values of the check bits C00 to C07 are all "0". Using this characteristic, the ECC function verification data generation circuit 5 is created.

【0053】

Next, the syndrome used when detecting a 1-bit error will be described. The syndrome can be generated by exclusive-ORing the bits with "1" among the horizontal elements of the read data part and check bit part of the SECDED code table. As an example, Fig. 3 shows a circuit that generates syndrome S00. Referring to FIG. 3, similar to FIG. 2, the check bit C00 is added to the data bits D58 and D60 as the input of the lowermost exclusive OR circuit in the first stage exclusive OR circuit group of FIG. The only difference is that they are. The method for generating the syndromes S01 to S07 is the same. From the values of the generated syndromes S00 to 07, as shown in FIG. 8, it is possible to identify the bit in which the 1-bit error occurs.

【0054】

FIG. 8 shows the hexadecimal value SYN of the values of the syndromes S00 to S07 when an error occurs in any one of the data bits D00 to D63 and the check bits C00 to C07. For example, if a bit 1-bit error occurs in the data bit D00 of the read data, the values of syndromes S00 to S07, that is, SYN becomes C8 [H].

【0055】

Next, the operation of this embodiment will be described using the flowcharts shown in FIGS. 4 (steps S1 to S11) and FIG. 5 (steps S12 to S).

【0056】

First, error detection and error correction in normal operation in which write data WD00 to WD63 are written to memory 1 and read data MD00 to MD63 are read from memory 1 will be described.

【0057】

The write data WD00 to WD63 are written to the memory 1. At the same time, the check bit generation circuit 3 generates write check bits WC00 to WC07 from the write data WD00 to WD63 according to the SECDED code table shown in FIG. 7, and writes them to the memory 2.

【0058】

When reading the memory 1, the normal data / validation data selector 6 selects the read data D00 to D63 from the memory 1, and the normal check bit / validation check bit selector 7 is the read check bit from the memory 2. Select C00 to C07.

【0059】

The 1-bit error detection circuit 8 is shown in FIG. 8 from the read data RD00 to RD63 selected by the normal data / verification data selector 6 and the read check bits RC00 to RC07 selected by the normal check bit / verification check bit selector 7. Based on the corresponding table of syndrome and error bits shown, a syndrome SYN is generated and the read data RD00 to RD63 are checked for 1-bit error or 2-bit error.

【0060】

As a result, when a 1-bit error is detected, the bit position and read data RD00 to RD63 are output to the 1-bit error correction circuit 9. The 1-bit error correction circuit 9 corrects by inverting the 1-bit error bit in the read data RD00 to RD63, and outputs the corrected read data MD00 to MD63.

【0061】

Now, in order to verify the ECC circuit 10, first, the ECC function verification control circuit 4 is set to the verification mode (step S1). Then, the ECC function verification control circuit 4 notifies the ECC function verification data generation circuit 5 of the start of verification, and outputs a verification mode signal to the normal data / verification data selector 6 and the normal check bit / verification check bit selector 7. (Step S2).

【0062】

The normal data / verification data selector 6 selects the verification data output from the ECC function verification data generation circuit 5 with the selector on the verification data side (step S3). In addition, the normal check bit / verification check bit selector 7 selects the value of 00 [H] with the selector on the verification check bit side (step S4).

【0063】

The ECC function verification data generation circuit 5 automatically generates 64-bit verification data TD00 to TD63 and outputs them to the 1-bit error detection circuit 8 via the normal data / verification data selector 6.

【0064】

The ECC function verification data generation circuit 5 first uses 80000000 [H] as verification data TD00 to TD63 for inspecting "1" failures from bit 00 to bit 63, that is, failures in which "0" is garbled as "1". Generates 64 values in which "1" is shifted to the right by 1 bit in 64-bit data such as 40000000 [H], 20000000 [H], and so on. That is, the value obtained by inverting bit 00 of the normal data value 00000000 [H] corresponding to the value 00 [H] of the normal check bit / verification check bit selector 7 selected by the normal check bit / verification check bit selector 7, and the value obtained by inverting bit 01. The inverted value of bit 02 ... is sequentially generated and output for each clock (step S5). In this case, the value 00 [H] of the verification check bit is correct for the normal data value 00000000 [H] where the number of "1" s is even.

【0065】

After generating 64 verification data TD00 to TD63, the ECC function verification data generation circuit 5 enters the standby state (step S6), notifies the ECC function verification control circuit 4 of the standby state, and then again the ECC function verification control circuit 4 Continue to output the data as a value of 00000000 [H] until the start notification is given from. (Step S5).

【0066】

The 1-bit error detection circuit 8 generates a syndrome from the verification data TD00 to TD63 and the verification check bit, detects a 1-bit error from the value of the syndrome, and performs it in the ECC function verification control circuit 4 and the 1-bit error correction circuit 9. Output the bit position where the 1-bit error occurred (step S7).

【0067】

The 1-bit error correction circuit 9 inverts the bit in which the error occurs, which is indicated by the 1-bit error detection circuit 8, corrects the error, and outputs the corrected data to the ECC function verification control circuit 4 (step S8). ).

【0068】

The ECC function verification control circuit 4 confirms the position of the error bit output by the 1-bit error detection circuit 8, and the value of the corrected data output by the 1-bit error correction circuit 9 is 00000000 [H]. If the error bit position is incorrect or the corrected data value is not 00000000 [H], the verification result is notified as an ECC function defect (steps S9 and S10).

【0069】

The above operation is continuously performed for 64 data from the verification data 80000000 [H] to 00000001 [H] (step S11).

【0070】

Next, a "0" failure from bit 00 to bit 63, that is, a failure in which "1" is garbled as "0" is inspected. When the ECC function verification data generation circuit 5, which has output 64 "1" failure data and has been in the standby state, is again notified of the start by the ECC function verification control circuit 4 (step S12 in FIG. 5). , As verification data TD00 to TD63 to inspect "0" failure from bit 00 to bit 63, 7FFFFFFF [H], BFFFFFFF [H], DFFFFFFF [H] ... Generates 64 values that are right-shifted bit by bit. That is, the value obtained by inverting bit 00 of the normal data value FFFFFFFF [H] corresponding to the value 00 [H] of the verification check bit selected by the normal check bit / verification check bit selector 7, and the value obtained by inverting bit 01. The inverted value of bit 02 ... is sequentially generated and output for each clock (step S13). Again, the validation check bit value 00 [H] is correct for the normal data value FFFFFFFF [H] where the number of "1" s is even.

【0071】

After generating 64 verification data TD00 to TD63, the ECC function verification data generation circuit 5 is in the end state (step S14), the ECC function verification control circuit 4 is notified of the end state, and the data is sent to the value of FFFFFFFF [H]. And continue to output (step S13).

【0072】

The 1-bit error detection circuit 8 generates a syndrome from the verification data TD00 to TD63 and the verification check bit, detects a 1-bit error from the value of the syndrome, and performs it in the ECC function verification control circuit 4 and the 1-bit error correction circuit 9. Output the bit position where the 1-bit error occurred (step S15).

【0073】

The 1-bit error correction circuit 9 inverts the bit in which the error occurs, which is indicated by the 1-bit error detection circuit 8, corrects the error, and outputs the corrected data to the ECC function verification control circuit 104 (step S16). ).

【0074】

The ECC function verification control circuit 4 confirms the position of the error bit output by the 1-bit error detection circuit 8, and the value of the corrected data output by the 1-bit error correction circuit 9 is FFFFFFFF [H]. If the error bit position is incorrect or the corrected data value is not FFFFFFFF [H], the verification result is notified as an ECC functional defect (steps S17 and S18).

【0075】

The above operation is continuously performed for 64 data from the verification data 7FFFFFFF [H] to FFFFFFFE [H], and when the verification is completed, the ECC function verification control circuit 4 becomes the ECC function verification data generation circuit 5. The verification completion notification is given, and the normal mode signal is output to the normal data / verification data selector 6 and the normal check bit / verification check bit selector 7 (step S19).

【0076】

The ECC function verification data generation circuit 5 returns the data to the initial value of 00000000 [H] (step S20). Normal data / validation data selector 6 sets the selector to the normal data side, reads from memory 1 and selects data (step S21), and normal check bit / validation check bit selector 7 sets the selector to the normal check bit side. Then, select the read check bit from memory 2 (step S22).

【0077】

This completes the verification of the ECC function. FIG. 6 shows an operation time chart in the verification mode of the present invention described above. As is clear from this time chart, a series of processes such as verification data generation, 1-bit error detection, 1-bit error correction, and verification result report are pipelined. Therefore, it is possible to perform verification with one verification data in one clock.

【0078】

Comparing FIG. 6 with FIG. 13 showing an operation time chart of the prior art, it is clear that according to the present invention, the verification time is shortened as compared with the prior art.

【0079】

[Effect of the invention]

The first effect of the present invention is that the scale of the device configuration for verifying the ECC function can be reduced, and the function can be verified only by the LSI having the ECC circuit. That is. The reason is that the ECC function is verified by storing the data necessary for verifying the ECC function in the memory and reading the data in the prior art, whereas in the present invention, the memory is not used. This is because the scale of the device configuration is small because the circuit that automatically generates the verification data is used, and the function verification can be performed only by the LSI alone because no memory is required.

【0080】

The second effect is that the time for functional verification can be shortened. The reason is that the ECC function can be verified faster than the operation of writing to the memory and the operation of reading because the circuit that automatically generates the data is also used without using the memory.

【0081】

Furthermore, the third effect is that it is not necessary to set the bit to be verified every time. The reason is that when the verification mode is set, "1" failure verification data (64 pieces) and "0" failure verification data (64 pieces) of each data bit are automatically generated, so consider the bits to be verified. This is because it is not necessary to set it every time.

[Simple explanation of drawings]

[Figure 1]

Block diagram of an embodiment of the storage device of the present invention [Figure 2]

Circuit diagram of the check bit generation circuit in Fig. 1. [Fig. 3]

Circuit diagram of the syndrome generation circuit in Fig. 1 [Fig. 4]

Flowchart of ECC function verification circuit in Fig. 1 (first half) [Fig. 5]

Flowchart of ECC function verification circuit in Fig. 1 (second half) [Fig. 6]

Time chart of ECC function verification circuit in Fig. 1 [Fig. 7]

Diagram showing the SECDED code table [Fig. 8]

Diagram showing syndrome and error bit correspondence table [Fig. 9]

Block diagram of the first conventional ECC function detection circuit [Fig. 10]

Flowchart of ECC function detection circuit in FIG. [Fig. 11]

Block diagram of the second conventional ECC function detection circuit [Fig. 12]

Flowchart of ECC function detection circuit in FIG. [Fig. 13]

Time chart of ECC function detection circuit in FIGS. 9 and 11 [Explanation of symbols]

1,2 memory 11,12 memory 21,22 Memory 3,13 Check bit generation circuit 4 ECC function verification control circuit 5 ECC function verification data generation circuit 6 Normal data / validation data selector 7 Normal check bit / validation check bit selector 8,16,25 1-bit error detection circuit 9,17,26 1-bit error correction circuit 10,18,27 ECC circuit 14 Write data inversion signal generation circuit 15,24 bit inverting circuit 23 Read data inversion signal generation circuit