Increment redundant transmission and communication device and method for increment redundant transmission of communication system

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to incremental redundant transmission in a communication system, and more particularly to a time slot communication system.

【0002】

[Conventional technology]

Link-layer restoration protocols are used in data communication systems for error and loss restoration. Link-layer restoration is extremely important for wireless communications due to the particularly bad loss and error characteristics of links.

【0003】

When a lost data frame is retransmitted, the receiver can combine multiple copies of the received frame to increase the chances of correct decoding. Alternatively, the transmitter can transmit additional parity information instead of retransmitting another copy of the lost frame. Incrementally redundant transmission and soft coupling methods are well known in the art.

【0004】

Despite their potential performance, these methods have not been applied in real systems. To allow efficient transmission (ie, high rate coding), the protocol needs to allow the transmission of a proportionally small amount of incremental parity information.

【0005】

Issues related to efficient transmission are addressed in the article "A Proposal for IS-136 + Data Services" by Robert Van Nobelen and Nambirajan Seshadri of AT & T Labs and Krishna Balachandran, Richard Ejzak and Sanjiv Nanda of Lucent Technologies Inc. It is shown in. This paper proposes that this issue is addressed by decomposing an unencoded data frame into D blocks and introducing P parity blocks.

【0006】

First, all the data blocks that make up the frame are transmitted. If the receiver is unable to reconstruct, the transmitted frame parity block is transmitted until the receiver is able to restore the frame. If all P parity frames are transmitted, the corresponding coding rate is D / (D + P).

【0007】

The practical implementation of the proposed procedure requires the transmission of a block sequence number for the frame and each block. Also, variable size blocks are used in different modulation formats (eg, QPSK, 8PSK and 16PSK).

【0008】

[Problems to be Solved by the Invention]

An object of the present invention is to eliminate or at least reduce the effects of one or more of the problems mentioned above.

【0009】

[Means for solving problems]

The present invention provides systems and methods for designing incremental redundancy, adaptively modulated data communication systems using time slot communication channels. This method performs the steps of forming a time slot with at least one fixed size subslot and forms a data block sized to fit the subslot. The header has a data block sequence number in the header for the time slot.

【0010】

Further, the parity block is formed in a size smaller than that of the data block so that the parity block and the data block sequence number fit into the subslot. Data blocks and parity blocks are transmitted in subslots within the time slot. In addition, this method performs the step of identifying the number of data blocks and parity blocks transmitted in the header for the time slot.

【0011】

In general, the present invention includes an incrementally redundant transmission communication system. The system includes a time slot signal generator that produces a time slot signal with at least one fixed size subslot and a data block signal generator that produces a data block signal of a size that fits in the time slot. A header adder is provided that produces a header with the data block signal sequence number in the header for the time slot signal. Also provided in the header for the time slot signal is a receiver that identifies a large number of continuously transmitted data block signals.

【0012】

Further, the present invention includes a method for incremental redundant transmission in a communication system using a radio (retransmit) protocol link frame. This method involves creating a timeslot signal with at least one fixed size subslot, forming a header with a data block signal sequence number in the header for the timeslot signal, and in the header for the timeslot signal. The number of data block signals is transmitted continuously, including the step of identifying.

【0013】

In the header of the time slot signal, a step of providing a data block sequence number for the first data block signal in the sequence of the data block signal and a step of producing a parity block signal smaller than the data block signal are provided, and the parity block is provided. The signal sequence number fits the subslot signal.

【0014】

BEST MODE FOR CARRYING OUT THE INVENTION

Adaptive data rate schemes based on a combination of incremental redundancy coding and adaptive modulation have been described early on for circuit data. Such channel quality measurement techniques are described in US Patent Application No. 08/921454, SYSTEM AND METHOD FOR MEASURING CHANNEL QUALITY INFORMATION, Krishna Balachandran, Sanjiv Nanda, Srinivas R. Kadaba and Richard P. Ejzak, August 24, 1997. Filing and US Patent Application No. 08/938031, ADAPTIVE MODIFICATION OF MODULATED AND CODED SCHEMES IN A COMMUNICATION SYSTEM, Richard P. Ejzak, filed September 21, 1997 (corresponding to Japanese Patent Application No. 10-265035) Has been done.

【0015】

These schemes achieve high throughput under latency constraints. Provided herein by the present invention is a detailed description of the application of these techniques to 136+ packet data services.

【0016】

Shown in U.S. Patent Application 08/938031 by Ejzak uses fixed-size blocks sized so that integers can be used in slots in a time slot transmit channel as a way to enable adaptive modulation. That is. In particular, two, three and four blocks are housed in the QPSK, 8PSK and 16PSKTDMA slots, respectively. The demand for a large number of perblock sequences to identify data and parity packets reduces the efficiency of this method of providing an incrementally redundant adaptively modulated data communication system that uses a time slot communication channel.

【0017】

In the present invention, the application uses media access control (MAC) layer estimation based on the Open Systems Interconnection (OSI) model. OSI is a standard, internationally accepted framework for communication between different systems made by different vendors. Most dominant communication protocols used today have a structure based on the OSI model. The OSI model organizes communication processes into seven different categories and places these categories in a layered sequence based on their relationship to the user. Layers 7-4 handle end-to-end communication message sources and message destinations. Layers 3 to 1 handle network access.

【0018】

Layer 1, the physical layer, deals with the physical means of transmitting data over the line, namely the electrical, mechanical and functional control of the data circuit. The layer, i.e. the data link layer, deals with procedures and protocols for manipulating communication lines. Layer 3, the network layer, determines how data is transferred between computers and routing within and between individual networks.

【0019】

It can be seen that the packet data channel can support multiple modulation. MAC layers are provided in Layer 3 frames and use flag delimiters to translate them into a byte stream. A radio link protocol (RLP), also known as a retransmission link protocol, is used to transfer Layer 2 frames between cells and mobile stations and vice versa. The Layer 3-byte stream is subdivided into RLP frames, and a sliding window retransmission scheme is used for intra-sequence loss and restoration.

【0020】

The MAC layer transaction preferably begins with the transmission of BEGIN frames. On uplinks and downlinks, the MAC layer converts Layer 3 frames into a single byte stream and packs this byte stream into a series of CONTINUE frames. The last new data burst in the transaction is sent using the END frame.

【0021】

The BEGIN frame for each transaction is transmitted using 4-level modulation in stop mode and standby mode to get notification of receipt from the receiver. Upon receipt of the BEGIN frame, the receiver initializes the RLP. BEGIN frames are also used to initialize a partial echo (PE) for a transaction and to identify the mode of operation for subsequent automatic repeat request (ARQ) mode CONTINUE frames in that transaction.

【0022】

ARQ mode on downlink and uplink There are two possible modes of operation for CONTINUE frames. The first is incremental redundancy (mode 0) and the second is fixed coding (mode 1).

【0023】

ARQ checks for errors in the transmitted data. The sender encodes an error detection (check) field in the transmitted data based on the content of the message. The receiver recalculates the check field and compares it with the received check field. If the check fields match, an ACK (receipt notification) is sent to the sender. If both check fields do not match, a NAK (Negative Receipt Notification) is returned and the sender resends the message.

【0024】

Bitmap feedback in the form of ARQ status is provided for both uplink and downlink transmissions. In addition, ACK / NAK feedback is provided based on the par time slot for uplink transmission.

【0025】

Incremental redundancy or fixed coding is combined with adaptive modulation for optimal trade-offs between high throughput goals with delay. The results in the patent application mentioned above show that when a delay goal is set, 8 or 16 level modulation cannot meet the goal across the C / (I + N) range involved. As the ratio of the signal to interference and noise decreases, a smaller placement (ie, level 4 modulation) density is applied. Adaptation to 4-level modulation is adopted in the delayed diffusion state.

【0026】

FIG. 1 is a schematic block diagram of the operation in the packet data channel 100 according to the present invention. Incremental redundancy transmission communication system 102 is shown, layer 3 frame 105 is provided to layer 2, MAC layer 110 of transmitter 115 and translated into a byte stream using flags for partitioning. This allows MAC Layer 110 to provide a unified transport mechanism for different Layer 3 protocols. This byte stream is subdivided into RLP frames and assigned a frame sequence number (FSN). The FSN is not explicitly transmitted as part of the RLP frame.

【0027】

For higher throughput in either mode, Layer 1 120 data is a symbol chosen from 4-level, 8-level, or 16-level modulation based on the Layer 2 backlog and channel visual feedback 125 from receiver 130. Is mapped to. Channel quality is measured in the sense of signal-to-noise ratio C / (I + N) at the input to the decoder in Layer 2 block 135 via the physical layer 140 of the receiver 130. Then, the decoder 135 outputs the layer 3 frame 145.

【0028】

FIG. 2 shows the function of layer 2 110 of FIG. 1 for mode 0 (ie, the procedure for mapping layer 3 frame 105 to layer 1 frame 120). In mode 0, layer 3 frame 105 is translated into a byte stream 155 timeslot signal by the flag delimiter 150.

【0029】

The byte stream 155 is subdivided into fixed-length RLP frames, and the frame check sequence (FCS) is calculated by the arithmetic unit for the data portion (excluding FSN) of the RLP frame by the RLP framer 160 (time slot signal generator). Will be done. The resulting RLP frame is, by way of example, encoded using a rate 1/2 systematic convolution encoder 165. A non-systematic convolution encoder can also be used instead.

【0030】

The subslot of data bit 170 from the systematic encoder 165 and the parity bit 175 (also known as the data block signal generator and the parity block signal generator) are the mode 0 interleaver (first segmenter) 180 and (second segmentor). Separately interleaved in segmenter 185 and blocked by blocker 190 (also known as assembler) into D data (data block signal) and D parity block (parity block signal) 195. These are assigned block identifiers 1, ... D, D + 1, ... 2D, respectively.

【0031】

The block sequence number (BSN), also known as the data block signal sequence number, is determined as a combination of the frame sequence number (FSN) and the block identifier. Fifteen parity bits are destroyed in each parity block so that a parity block header containing the block sequence number can be added.

【0032】

Preferably, these data blocks do not include block headers. Depending on whether 4-level, 8-level, or 16-level modulation is used, the 2, 3, or 4 blocks (data or parity) output from mode 0RLP200 are the MAC and Layer 1 field adders (headers). Adder and Destruction Units) 210 are each combined into a single Layer 1 data segment and transmitted in a single IS-136 timeslot signal.

【0033】

The data segment header indicating the block sequence number of the first data block in the segment is used to identify the data block sequence number. The remaining data blocks have consecutive block sequence numbers. Along with the encoded data segment header (CDSH), other MAC and physical layer headers such as modulation type and partial echo (PE) are added in each time slot signal.

【0034】

In mode 1 of FIG. 3, the layer 3 frame 105 is translated into one byte stream 155 by the flag delimiter (flag marker 150). This byte stream 155 is subdivided into fixed-length RLP frames, and the FCS is calculated for the data portion of the RLP frame by the mode 1 RLP framer 161. The resulting RLP frame is processed by mode 1 RLP220.

【0035】

Depending on whether 4-level, 8-level, or 16-level modulation is used, the 2, 3, or 4 consecutive RLP frames output from Model 1 RLP220 are the data segments, also known as headers and FCS adders, and Each is coupled into a single data segment by the FCS combiner 230. A data segment header containing the FCS calculated in this data segment and the FSN of the first RLP frame is added in the header and FCS adder 230.

【0036】

The header, data and FCS are then encoded using the rate 1/2 convolution encoder 235. The output of the encoder 235 is made by the mode 1 interleaver 240, and additional MAC and physical layer header fields are added by the header adder 210. This output consists of layer 1 data 120 transmitted in a single time slot. The data segment header is in this case transmitted as part of the encoded Layer 1 data segment.

【0037】

The advantage of incremental redundancy (mode 0) is that higher throughput is achieved because redundant bits are sent when needed. A combination of incremental redundancy and adaptive modulation has been proposed for both downlink and uplink directions.

【0038】

FIG. 4 shows both the transmit (shown in FIG. 1 as a Layer 2 function) and receive function for the Mode 0 procedure of FIG. The procedure from receipt of layer 3 frame 105 described at transmitter 115 to output 195 of blocker 190 is the same as described for FIG. The layer 1 frame 120 is output from the header adder 210 and input to the adaptive modulator 250.

【0039】

The adaptive modulator 250 modulates the layer 1 frame 120 and transmits it through the packet data channel 100 to the channel demodulator 255 of the receiver 130. The channel demodulator 255 demodulates the modulated layer 1 frame 120 received from the packet data channel 100 and inputs the result to the receiver RLP260. The receiver RLP260 decodes the data segment header to determine the sequence number of the received data block and the number of the parity block.

【0040】

The receiver RLP260 also decodes the parity block header to determine the sequence number of the parity block. If any header of the data in the parity block is correctly decoded, the data is provided to the Incremental Redundancy Soft Decoder and FCS Checker (IRSD) 265, and the ACK / NAK (Receive Notification / Non-Reception Notification) feedback 270 , Provided to transmit RLP275 indicating receipt notification of data and parity blocks. The transmission RLP275 and the modulation determination unit 278 are functional blocks representing the functions of mode 0RLP200 in FIG.

【0041】

The IRSD265 receives an output from the receiver RLP260 and produces three outputs. The first output is the decrypted data sequence of the received Layer 1 frame 120 input to the flag remover 280. The second output is the ACK / NAK feedback 270 output to the transmit RLP275. The third output is the channel qualification feedback signal 125 sent back to the transmit RLP 275 and the modulation decision unit 278. The flag remover 280 removes the flag from the received data and outputs the received layer 3 frame 285.

【0042】

Figure 5 shows RLP frame 290, or FCS295, with RLP data R._i The output of mode 0RLP framer 160 configured by adding to 300 is shown. FCS295 is the length L calculated for the data bits_DCRCCyclic Redundancy Check (CRC) of 305. FCS295 is L_DATAIt is attached to each RLP frame 300 consisting of 310 data bits. This length L_DATA310 and L_DCRC305 is a design parameter. Length L Frame 315 = L_DATA310 + L_DCRCThe frame of 305 is sent to encoder 165 of FIG.

【0043】

Figure 6 shows the size L of Figure 5._FRAME It is shown that the bits of each RLP frame 290 of 315 are encoded by the encoder 165 using the binary rate 1/2 systematic convolution code. The rate 1/2 binary convolution encoder 165 is preferably a 32-state maximum free distance code with an octadecimal generator. At the output of encoder 165 in FIG. 6, L in FIG._FRAME 315 data bits 170 and L_FRAME There are 315 parity bits 175, which are divided into blocks as follows.

【0044】

L in Figure 5 at the output of encoder 165_FRAME Data bit 170 of 315 has a length of LBLOCK = L_FRAMEIt is subdivided into D blocks of (315) / D. These blocks are D_ijIt is assumed that the data block 320 is represented by 320 (j = 1 ... D). Parameter D determines the delay and / or throughput performance set forth in the patent application above.

【0045】

Parity bit 175 is corrupted and P_ij325 (j = 1 ... D, eg P_i1330, P_i2335 and P_i3It is subdivided into D parity blocks 325 of the same size shown in 340). It can be seen that the destruction of the output of the convolution encoder is the procedure of erasing a predetermined set of bits in order to reduce the number of parity bits. L at the output of encoder 165_FRAME Of the 315 parity bits 175, the Dh parity bit is destroyed (h in each of the D parity blocks 325). h is the size of the header required for each parity block.

【0046】

For each parity block 330,335 and 340, the parity / control block header (PCBH) 345,350 and 355 is the parity block P._ijAdded before 325. For parity blocks, PCBH345,350 and 355 include a 1-bit PCBH header type (= 1 for a parity block) and a 10-bit block sequence number (BSN). PCBH345,350 and 355 are selectively encoded using Hamming codes.

【0047】

Data block D_i1From D_iD320 does not include redundancy and frame R_iRepresents a one-to-one mapping to 290. Parity block P_i1~ P_iD325 is R_i It contains the parity information derived from 290 and is used by the protocol for forward error correction (FEC) due to decoding failure at receiver 130 in FIG. FIG. 6 shows the mapping of data 170 and parity 175 bits to blocks 320 and 325 for D = 3 (ie, 3 data blocks per frame).

【0048】

No separate header is required for each data block 320. Data 320 and parity 325 blocks are R by using a systematic rate 1/2 binary convolution encoder 165._i Derived from 290. The same procedure is used for unsystematic convolution encoders. The output bits of encoder 165 are mapped to blocks 320 and 325 in an interleaved manner to maximize time and sign versatility.

【0049】

Mode 0 RLP200 in Figure 2 is the first RLP data block D_i1... D_iDSend 320, receiver 130 in Figure 1 RLP frame R in Figure 5._i Additional RLP parity block P if 290 cannot be decoded correctly_ijBy sending 325 after that, data is sent sequentially. Transmitter 115 in Figure 1 is R_i RLP frame R until a positive receipt notification is received from receiver 130 in Figure 1 for 290._i Data 170 and parity 175 bits corresponding to 290 cannot be discarded.

【0050】

This protocol works by keeping bitmaps in tables, frame tables and block tables for blocks that have been sent but not yet acknowledged. With feedback from receiver 130 in FIG. 1, the transmission protocol updates the table and determines which data 320 and / or parity 325 blocks should be transmitted in the next time slot.

【0051】

The control block can be inserted in the time slot instead of the parity block 325. The PCBH345 header type bit is set to 0 for each control block. An example of a control block includes an ARQ status block used to indicate the completion of transmission. This ARQ status block shows the last received block sequence number in the sequence and a bitmap of the received block with the END block.

【0052】

The received RLP260 and IRSD265 in FIG. 4 are equivalents of mode 0RLP200 in FIG. 2, and the received block D in FIG._ij320 and P_ijCombine 325 and layer 2 frame R_i Decrypt them together to restore the 290. The receiving RLP260 of FIG. 4 stores the received data and parity blocks and the decoded RLP frame 300 of FIG. 6 until they are lost in the sequence to Layer 3 as Layer 3 frame 285 of FIG. Maintain a table for. These blocks are retrieved from Layer 1 in the soft decision format and stored in the table received by quantization to the q level to reduce memory overhead.

【0053】

The incremental redundancy decoder 265 of FIG. 4 corresponds to the transmit encoder 165 of FIG. This is Soft Decision Block D_ijAnd P_ijSends the received subset of and attempts to decrypt it, preferably using the soft decision Viterbi algorithm. Any lost soft bits are treated as deleted by decoder 265 in FIG. The output of the Viterbi decoder is sent to and received by the FCS decoder that calculates the FCS._i Shows on the receiving RLP 260 whether the 290 was sent to the frame check.

【0054】

The data bitstream 170 and the parity bitstream 175 of FIG. 4 at the encoder output 165 are separately interleaved by the mode 0 interleavers 180 and 185 and subdivided into data and parity blocks by the blocker 190. Mode 0 The combination of 2, 3 or 4 data and parity / control blocks output by RLP200 is transmitted in each time slot corresponding to the use of 4-level, 8-level or 16-level modulation, respectively. The data or parity block is directly and selectively mapped to the Layer 1 data portion of the IS-136 time slot (DATA field shown in Figures 11 and 12). Figures 8, 9 and 10 show the format of the logical Layer 1 frame 120 of Figure 5 as a modulation type function.

【0055】

FIG. 7 shows that the Layer 1 frame of FIG. 4 is associated with the data segment header (DSH) 360. The DSH360 includes a block sequence number (BSN) 365, preferably consisting of 10 bits. This BSN365 is associated with the first data block in the time slot. In the absence of data blocks, BSN365 is given a default value that is ignored by receiver 130 in Figure 4.

【0056】

The DSH360 also includes a pole indicator (PI) 370 of FIG. 7, preferably consisting of 1 bit. The PI370 is used by system 102 in Figure 1 to request an ARQ status frame. The DSH360 also includes a parity / control block pointer (PCBP) 375, preferably consisting of two bits. PCBP375 shows the configuration of the time slot by data and parity / control blocks. The DSH360 also has a reserved (RSVD) 380 header, which is preferably 1 bit long for future needs.

【0057】

The 14-bit DSH360 of FIG. 7 is encoded to obtain the 22-bit encoded DSH (CDSH) 385 of FIGS. 8, 9 and 10. The encoding preferably uses a Hamming code. Each time slot also contains a 12-bit coded partial echo (PE) assigned to the transaction in the assumption that it identifies the recipient of the data on the downlink or the originator on the uplink.

【0058】

In the downlink, each RLP frame with a size of 336 bits (40 octadecimal RLP data frames + 16-bit CRC) is encoded using a rate 1/2, memory 5, and systematic convolution code. The number of data blocks (D) per RLP frame is set to the nominal value of 3. The output of the encoder is subdivided into three data blocks, each 112 bits in size, and three parity blocks, each destroyed from 112 bits, in 97 bits in size. The 15-bit header parity / control block (PCBH) 390 in Figures 8, 9 and 10 is used for each parity block. These blocks are carried 2, 3 or 4 per time slot as described above.

【0059】

In the uplink, each frame sized at 342 bits (41 octal RLP frames + 14-bit CRC) is encoded using rate 1/2 memory 5, systematic convolution code. The number of data blocks (D) per RLP frame is set to 3. The output of the encoder is subdivided into three data blocks, each 114 bits in size, and three parity blocks, each destroyed from 114 bits, in 99 bits in size. The 15-bit header (PCBH) 390 in Figures 8, 9 and 10 is used for each parity block. These blocks carry 2, 3 or 4 per time slot as described above.

【0060】

Figure 8 shows a logical Layer 1 frame format that assumes level 4 modulation with two blocks transmitted in each IS-136 time slot. The value of PCBP375 in DSH360 in Figure 7 is used to identify the composition of the data segment in the time slot by data and parity blocks. As an example, PCBP375 = 00 indicates two parity blocks, PCBP375 = 01 indicates one data and one parity block, and PCBP375 = 10 indicates two parity blocks. FIG. 9 shows the use of PCBP and the configuration of the time slot for 8-level modulation, and FIG. 10 shows the case of 16-level modulation.

【0061】

Fields such as Adaptive Fields (AF) 395 in Figures 8, 9 and 10 and DSH360 in Figure 7 assume special positions in the time slot and are not transmitted as part of Layer 1 data. The block sequence number (BSN) 365 in FIG. 6 in the CDSH385 of FIGS. 8, 9 and 10 refers to the sequence number corresponding to the first data block 320 in the slot. This field is ignored if only parity block 340 is transmitted. In addition to the above fields, the encoded PE assigned to the MAC layer transaction is used as the mobile station identifier.

【0062】

Figures 11, 12, 13 and 14 show an example of the process performed by receive RLP260, IRSD265, feedback 270 to mode 0RLP275, and mode 0RLP275 in FIG. In step 400 of FIG. 11, the receiving RLP260 of FIG. 4 receives the demodulated time slot from channel demodulation 255 and decodes the data segment header (DSH) 360 of FIG. 7 in step 405 of FIG.

【0063】

If the DSH360 of FIG. 7 is successfully decrypted in decision step 410, the process proceeds to step 415 of FIG. If the DSH360 in Figure 7 is not successfully decrypted, the process instead proceeds to step 420 in Figure 11. At step 420, the receive RLP260 of FIG. 4 discards the time slot and proceeds to node A425 of FIG. 11 to start a new process at IRSD265 of FIG.

【0064】

If the DSH360 of FIG. 7 successfully decodes the received RLP260 of FIG. 4, in step 415 of FIG. 11, the PCBP375 of FIGS. 7, 8, 9 and 10 in the DSH360 of FIG. 7 is read and the data 320 of FIG. And the number of parity blocks 325 is determined, and for the parity blocks, PCBH345,350,355 in FIG. 6 and PCBH390 in FIGS. 8,9 and 10 are decoded.

【0065】

Then, the reception RLP260 of FIG. 4 updates the block bitmap table for the received data and the parity block in step 430 of FIG. 11, and sends the software information and the data / parity block sequence number to the IRSD265 in the step 435. And at node A425, continue the process in IRSD265.

【0066】

FIG. 12 shows the process performed by IRSD265 in FIG. This process begins at step 440 in FIG. 12, where IRSD265 in FIG. 4 receives soft information and data / parity block numbers from the receive RLP260. In step 445 of FIG. 12, the IRSD265 of FIG. 4 uses the pre-stored data and / or parity block associated with the RLP frame to the newly received data and / or the RLP frame associated with the parity block. To decrypt.

【0067】

The IRSD265 then checks the FCS associated with the decrypted RLP frame in step 450 of FIG. If the FCS check is successful in decision step 455, the process proceeds to step 460. If the FCS check fails, the process goes to step 465 instead. In step 465, new software information associated with the received data / parity block is stored, and in step 470 the process ends.

【0068】

If the FCS check is successful, IRSD265 in FIG. 4 updates the table from the RLP frame in step 460 in FIG. 12 and stores this successfully decrypted frame in the sequence buffer in step 475. At step 480, IRSD265 in FIG. 4 sends the in-sequence data to the flag remover 280, updates the frame bitmap table, and terminates the process at step 470 in FIG.

【0069】

FIG. 13 shows the process for generating the feedback signal 270 of FIG. The first receiving RLP260 of FIG. 4 obtains a frame bitmap from the frame bitmap table in step 485 of FIG. Then, the receiving RLP260 of FIG. 4 obtains data and / or a parity block bitmap from the block bitmap table in step 490 of FIG. 13, and in step 495 of FIG. 13, the bitmap is obtained by the feedback signal 270 of FIG. Send to mode 0RLP275.

【0070】

FIG. 14 shows the processing of the feedback signal 270 by the mode 0RLP275 of FIG. In step 505, mode 0RLP275 of FIG. 4 receives the bitmap transmitted by the receive RLP260. Mode 0RLP275 then updates the RLP frame bitmap in step 510 of FIG. 14, and updates the data and / or parity block bitmap in step 515.

【0071】

Figure 15 shows the process of transmitting data and / or parity blocks for each RLP frame when only frame bitmaps are used. At step 525, mode 0RLP275 of FIG. 4 receives the newly encoded blocked RLP frame and at step 530 puts a block of RLP frame into the transmission sequence. As an example, D_i1, D_i2, D_i3, P_i1, P_i2And P_i3Round Robin sequence is used, D_i1Is P_i3Is repeated after.

【0072】

In step 535, mode 0RLP275 of FIG. 4 is the data block D._i1, D_i2And D_i3To send. If at decision step 540 the frame bitmap indicates a frame receipt notification (ACK) at the receive RLP260 of FIG. 4, the process proceeds to step 545. Instead, if the NAK is registered in the receive RLP260 of Figure 4, the process proceeds to step 550. At step 550, mode 0RLP275 of FIG. 4 discards the transmission sequence and ends this process at step 555.

【0073】

In step 545, mode 0RLP275 of FIG. 4 transmits the next data or parity block in the transmit sequence and waits for receive RLP260 in step 560 to respond. The process then continues until decision step 540, which continues until all blocks have been properly transmitted.

【0074】

FIG. 16 shows the steps of transmitting data and / or parity blocks for each RLP frame when both blocks and frame bitmaps are used. At step 565, mode 0RLP275 of FIG. 4 receives the newly encoded blocked RLP frame and at step 570 puts a block of RLP frames into the transmit sequence. As an example, D_i1, D_i2, D_i3, P_i1, P_i2And P_i3Round robin sequence is used. Where D_i1Is P_i3Repeat after.

【0075】

In step 575, mode 0RLP275 of FIG. 4 is the data block D._i1, D_i2And D_i3To send. If at decision step 580 the frame bitmap indicates a frame receipt notification (ACK) at the receive RLP260 of FIG. 4, the process proceeds to step 585. Instead, if the NAK is registered in the receive RLP260 of Figure 4, the process proceeds to step 590. At step 590, mode 0RLP275 of FIG. 4 discards the transmit sequence and the process ends at step 595.

【0076】

In decision step 585, if the block bitmap indicates a block non-receipt notification (NAK) in the receive RLP260 of FIG. 4, the process proceeds to step 600. Otherwise, if decision step 585 results in an ACK, the process proceeds to step 605. In step 605, mode 0RLP275 of FIG. 4 transmits the next data or parity block in the transmit sequence and waits for receive RLP260 in step 610 to respond. The process then returns to decision step 580, and the process continues until all blocks have been properly transmitted.

【0077】

If the NAK is the result of decision step 585, the process proceeds to step 600. In step 600, if mode 0RLP275 of FIG. 4 transmits NAK data or parity blocks without a transmit sequence, it waits for receive RLP260 to respond in step 610. The process then returns to decision step 580, and the process continues until all blocks have been properly transmitted.

【0078】

FIG. 17 shows the downlink time slot format for mode 0. The time slot has the following fields. That is, SYNC-synchronous field (SYNC) 615, packet channel feedback (PCF) 620, coded superframe phase (CSFP) and coded adaptive field (CAF) shown as CSFP / CAF625, coded partial echo ( CPE) 630, Coded Data Segment Header (CDSH) 635,385, which are shown in Figures 8, 9 and 10 and are reserved (RSVD) 640 and data block 320, which are Figure 6,8, Shown in 9 and 10.

【0079】

Timeslot structures for downlinks and uplinks preferably use a differentially coded PSK (DPSK) arrangement. When coherent PSK is used, pilot and reference symbols are inserted in appropriate positions in the time slot structure.

【0080】

The PDF420 field is used as a mechanism to provide ACK / NAK270 in Figure 4, channel quality feedback 125 in Figure 4, and time slot allocation on the reverse packet data channel. The CAF625 on the downlink consists of 2 bits indicating the modulation format (4 level, 8 level or 16 level) used for the data. A Layer 1 data field consists of two, three, or four blocks constructed using the procedure described above in Figures 8, 9, 10 and 11.

【0081】

The adaptive field superframe phase and one reserved bit are encoded together using the same Hamming code used as CDVCC in IS-136. The 22-bit is used for the CDSH field 635 and the 12-bit CPE630 field is used to identify the recipient of the data. The SYNC615 field is sent using π / 4-DQPSK. CSFP / CAF625, PCF620, CPE630 and CDSH365 are also transmitted using 4-level modulation.

【0082】

Contention access is transmitted using 4-level modulation. Higher levels of modulation (8 and 16 levels) are used by mobile stations with more than one burst to transmit in ARQ CONTINUE mode, detecting reservation-based transmission opportunities.

【0083】

FIG. 18 shows a preferred uplink time slot structure. The guard (G) 645, ramp (R) 650, preamble (PREAM) 655 and (SYNC) 615 fields are maintained on the IS-136. The newly encoded Adaptive 20 Fields (CAF) 660 is introduced to indicate the modulation format for the data.

【0084】

2 bits are used for the modulation type. These are encoded using the (6,2) code. The CDSH635 uses 22 bits and the 12-bit CPE665 is used to identify mobile stations. G645, R650, PREAM655, CPE665, CDSH635 and CAF660 are transmitted using 4-level modulation.

【0085】

The modulation type is fixed for one time slot, but not for one RLP frame or the entire MAC layer transaction. Layer 1 determines the modulation type for use for the next time slot based on the channel quality feedback 125 of FIG. 4 from the needs of receiver 130 and Layer 2.

【0086】

The modulation formats used are 4-level (DQPSK or π / 4-coherent PSK), 8-level (difference or coherent) and 16-level (PSK, DPSK or QAM) modulation. The 2-bit adaptive field is used to indicate the encoding and / or modulation format used. Table 1 shows the mapping of AF values to the corresponding modulation formats.

【0087】

The default value identifies a default DQPSK format with a rate of 5/6 encoding in the time slot to allow different packet data channel frame formats and interactions between incremental redundancy and coding mode.

【0088】

table 1 -------------------------------------------------- --------------------- AF encoding and / or modulation format -------------------------------------------------- --------------------- 00 4 levels (π / 4-QPSK or π / 4-DQPSK) 01 8 levels (PSK or DPSK) 10 16 levels (QAM, PSK or DPSK) 11 Default (eg rate 5/6, Memory 5 convolution coding with 4-level modulation) -------------------------------------------------- --------------------- [0089]

The channel quality feedback (CQF) 125 of FIG. 4 is provided by the mobile station on the reverse packet data channel in the Layer 2 ARQ status block shown in FIG. The ARQ status block is preferably transmitted in any reserved uplink time slot. A 2-bit channel quality indicator is used to indicate the maximum acceptable modulation type.

【0090】

The PCBH670 for the ARQ status block has a 1-bit PCBH header type (= 0), a 1-bit control block type (= 0, for the ARQ status block), a 2-bit CQF field, and 7 bits to identify the start frame for bitmap feedback. It consists of a frame sequence number (FSN).

【0091】

The PCBH670 is encoded using the (15,11) code. The rest of the ARQ status block consists of bitmap feedback 675 and CRC680 encoded using the default 5/6 rate convolution code.

【0092】

For uplinks, channel quality feedback is provided in the PCF corresponding to the reserved slot. The Subchannel Feedback (SF) field in the PCF provides ACK / NAK and channel quality feedback for preceding slots and channel quality feedback (CQF) that acts as modulation format advice for subsequent allocations to received and perceived mobile stations. .. A simple (6,1) ellipsis code is used for ACK / NAK feedback. The (6,2) code is used for channel quality feedback.

【0093】

The receiver 130 of FIG. 4 combines the received symbol sequence with the decoded symbol sequence in order to obtain an absolute measure of the signal-to-noise ratio C / (I + N) at the input of the decoder 265. Channel quality information is obtained by averaging the Euclidean distances between them. As shown in the patent application described above, this method provides good estimates under noise and jamming limits for different coding modulation schemes over a range of Doppler frequencies. This metric operation is irrelevant to the realization of the actual decoder and can be operated using the decoded information sequence.

【0094】

Table 2 -------------------------------------------------- --------------------- Channel status Channel quality indicator Maximum acceptable modulation format -------------------------------------------------- --------------------- C / (I + N) <θL 00 (4 levels) θL <C / (I + N) <θH 01 (8 levels) C / (I + N)> θH 10 (16 levels) -------------------------------------------------- --------------------- [0095]

Table 2 shows the scheme for determining the maximum acceptable modulation type based on the estimated C / (I + N) at the receiver. Mobile station receivers use channel quality metrics with knowledge of C / (I + N) thresholds, θL, θH. These are transmitted via the Packet Broadcast Control Channel (PBCCH).

【0096】

As in mode 0, the byte stream obtained from the layer 3 frame is subdivided into RLP frames. However, in this mode, RLP frames are smaller in size than in incremental redundancy. Two, three or four RLP frames are transmitted in each modulation type-dependent time slot (ie, when 4-level, 8-level or 16-level modulation is used, respectively).

【0097】

A data segment header in which two, three or four RLP frames contain a 10-bit frame check sequence (FCS) and a 10-bit block sequence number (BSN) and a 1-bit pole indicator (PI) for requesting ARQ status. Concatenated with (DSH).

【0098】

The resulting data segment containing RLP frames, DSH, and CRC bits is encoded using a memory 5, rate 1/2 convolution code. These encoded bits are broken and mapped to a symbol chosen from a 4-level, 8-level, or 16-level arrangement. This destruction depends on the modulation format used for slot transmission, shown in Figures 20 and 21.

【0099】

The frame check is on a data segment consisting of 2, 3 or 4 RLP frames, so if the CRC fails at the receiver, all frames in the slot will be lost and must be restored by ARQ restore. It disappears. Assigning FCS to each "small" RLP frame is inefficient due to excessive overhead.

【0100】

In the downlink, each RLP frame consists of 88 bits (a set of 8 pieces of 11). An 11-bit DSH and a 10-bit CRC are added to each set of 2, 3, or 4 RLP frames. The resulting combination is encoded using the rate 1/2, memory 5 convolution code shown in FIG. At the encoder output, 128,201 or 254 bits are destroyed depending on whether 4-level, 8-level or 16-level modulation is used, and the remaining bits are mapped to the desired modulation format and time. Inserted into the DATA field in the slot.

【0101】

In the uplink, each RLP frame consists of 96 bits (a set of 8 of 12). An 11-bit DSH and a 10-bit CRC are added to each set of 2, 3, or 4 RLP frames. The resulting combination is encoded using the rate 1/2, memory 5 convolution code shown in FIG. At the encoder output, 176,243 or 310 bits are destroyed depending on whether 4-level, 8-level or 16-level modulation is used, and the remaining bits are mapped to the desired modulation format.

【0102】

These slot formats assume the use of DPSK. When coherent PSK or QAM is used, the pilot symbol is inserted in the appropriate position in the time slot.

【0103】

The downlink time slot format is shown in Figure 22. The Packet Channel Feedback (PCF) 800 field is used as a mechanism to provide ACK / NAK and channel quality feedback and time slot allocation on the reverse packet data channel. A Layer 1 data field consists of two, three, or four RLP frames constructed using the procedure described above.

【0104】

The adaptive field (AF) on the downlink consists of 2 bits indicating the modulation format (4 level, 8 level or 16 level) used for the data. The adaptive field, superframe phase (SFP) and one reserved bit are coded together using the same (12,8) Hamming code used for CDVCC in IS-136. The 12-bit CPE810 field is used to identify the recipient of data 805. The SYNC805 field is sent using π / 4-DQPSK. CSFP / CAF820, PCF800 and CPE810 are transmitted using 4-level modulation.

【0105】

FIG. 23 shows the proposed uplink time slot structure. The guard (G) 825, ramp (R) 830, preamble (PREAM) 835 and SYNC815 fields are maintained as in IS-136. A new coding adaptation field (CAF) 840 is introduced to indicate the modulation format for data 845. The 12-bit CPE810 is used to indicate transmitter identity. 2 bits are used for the modulation type. These are encoded using the (6,2) code. G825, R830, PREAM835, CPE810 and CAF840 are transmitted using 4-level modulation.

【0106】

Contention access is transmitted using 4-level modulation. Higher levels of modulation (8th and 16th levels) are used in ARQ mode CONTINUE frames by mobile stations with more than one burst to transmit, and are detecting reservation-based transmission opportunities.

【0107】

In adaptive modulation, as in mode 0, the modulation type is fixed only for the time slot, not for the entire MAC layer transaction. Layer 1 determines the modulation type to use for the next time slot based on channel quality feedback from the receiver and Layer 2 needs. Since the same RLP frame size in mode 1 is chosen regardless of the modulation type, the retransmitted frame can be transmitted in a different modulation type from the original transmission.

【0108】

Possible modulation formats are 4-level (DQPSK or π / 4 coherent PSK), 8-level (difference or coherent) and 16-level (PSK, DPSK or QAM) modulation. A 2-bit adaptive field is used to describe the encoding and / or modulation format used. Table 1 shows the mapping of AF values to the corresponding modulation formats.

【0109】

The default value identifies the default DQPSK format with rate 5/6 encoding. It allows for different packet data channel frame formats and interactions between incremental redundancy and coding modes.

【0110】

Similar to mode 0, downlink channel quality feedback (CQF) is provided by the mobile station in the reverse packet data channel during the Layer 2 ARQ status frame. ARQ status frames may be transmitted in any reserved uplink time slot. A 2-bit channel quality indicator is used to indicate the maximum acceptable modulation type, and the cell transmitter uses this information with knowledge of the Layer 2 data backlog to determine the modulation for use in subsequent slots. use.

【0111】

For uplinks, channel quality feedback is provided in the PCF corresponding to the reserved slot. The Subchannel Feedback (SF) field in the PCF serves as ACK / NAK and channel quality feedback for the preceding slot and channel quality feedback (CQF) as modulation format advice for subsequent allocation to the notified mobile. ) And provide. For ACK / NAK feedback, a simple (6,1) iterative code is used, as in mode 0. The (6,2) code is used for channel quality feedback.

【0112】

In general, the present invention includes the incremental redundant transmission communication system 102 of FIG. The system includes a timeslot signal generator 160 that produces a timeslot signal 155 with at least one fixed size subslot, and a datablock signal generator 165 that produces a datablock signal 170 that fits the timeslot. Also provided is a header adder 210 that produces a header with the data block signal sequence number in the header for the time slot signal. The receiver 130 of FIG. 4 identifies the number of continuously transmitted data block signals 170 in the header for the time slot signal.

【0113】

The present invention further produces a parity block signal 175 that is smaller in size than the data block signal 170 so that the parity block signal 175 and the data block signal sequence number fit within the subslot. , And a transmitter 115 that transmits a data block signal 170 and a parity block signal 175 in a subslot within the time slot signal.

【0114】

The present invention also extends to methods for incremental redundant transmission in communication systems that use wireless (or retransmission) protocol link frames. This method involves creating a timeslot signal with at least one subslot of fixed size, creating a datablock signal 170 of FIG. 2 sized to fit the subslot, and blocking the data in the header for the timeslot signal. It includes forming a header with a signal sequence number and identifying the number of data block signals 170 transmitted continuously in the header for the time slot signal.

【0115】

In the header of the time slot signal, the step of providing the data block sequence number for the first data block signal 170 in the sequence of the data block signal 170 and the data so that the parity block signal 175 sequence number fits the subslot signal. A step is provided that produces a parity block signal 175 that is smaller than the block signal 170.

【0116】

[Effect of the invention]

As described above, according to the present invention, it is possible to provide incremental redundant transmission in a communication system that solves the problems of the prior art.

[Simple explanation of drawings]

[Figure 1]

The block diagram explaining the operation on the packet data channel by this invention.

[Figure 2]

Block diagram showing blocks involved in transmitter operation for mode 0 and conversion from Layer 3 frames to Layer 1 frames.

[Fig. 3]

The figure which shows the block which is involved in the transmitter operation for mode 1 and the conversion from a layer 3 frame to a layer 1 frame.

[Fig. 4]

A block diagram showing a communication link from a mode 0 base station to a mobile and a feedback interaction between an uplink and a downlink.

[Fig. 5]

The figure which shows the format for the time slot frame which has a data and a header frame.

[Fig. 6]

The figure which shows the structure of the data and the parity block from the wireless link protocol (RLP) frame.

[Fig. 7]

The figure which shows the format of the data segment header (DSH) with the number of bits required for each field shown.

[Fig. 8]

The figure which shows the logical layer 1 frame format assuming 4-level modulation.

[Fig. 9]

The figure which shows the logical layer 1 frame format assuming 8-level modulation which has 3 blocks transmitted in each IS-136 time slot.

[Fig. 10]

The figure which shows the logical layer 1 frame format assuming 16 level modulation which has 4 blocks transmitted in each IS-136 time slot.

[Fig. 11]

The figure which shows a part of the logical flowchart of the process executed in the incremental redundancy soft decoder and FCS checker of FIG.

[Fig. 12]

The figure which shows another part of the logical flow chart of the process performed in the received RLP of FIG.

[Fig. 13]

The figure which shows the logical flow chart of the process which generates a feedback signal from a receive RLP and an incremental redundancy soft decoder and an FCS checker to the mode 0 RLP of FIG.

[Fig. 14]

The figure which shows the logical flow chart of the process of updating a bitmap in mode 0RLP from the feedback shown in FIG.

[Fig. 15]

The figure which shows the logical flow chart of the step which determines the transmission of a data and / or a parity block for each RLP frame without using a block bitmap.

[Fig. 16]

Diagram showing a logical flow chart of the process of using block and frame bitmaps to determine the transmission of data and / or parity blocks for each RLP frame.

[Fig. 17]

The figure which shows the mode 0 downlink time slot format.

[Fig. 18]

The figure which shows the mode 0 uplink time slot format.

[Fig. 19]

Diagram showing the 2-bit uplink ARQ status block logical format used for channel quality feedback.

[Fig. 20]

Diagram showing the mapping of RLP frames to Layer 1 data symbols for 4-level, 8-level, and 16-level modulation formats in the downlink.

[Fig. 21]

Diagram showing the mapping of RLP frames to Layer 1 data symbols for 4-level, 8-level, and 16-level modulation formats on the uplink.

[Fig. 22]

The figure which shows the mode 1 downlink time slot structure.

[Fig. 23]

The figure which shows the mode 1 uplink time slot format.

[Explanation of symbols]

102 Incremental Redundancy Transmission Communication System 105 Layer 3 frame 110 Layer 2 RLP, Encoder, MAC 120 layer 1 115 transmitter 125 channel quality feedback 100 packet data channel 145 Layer 3 frame 135 Layer 2 RLP, Decoder, MAC 140 layer 1 130 receiver