Chip size package

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a chip size package, and more particularly to a chip size package in which moisture resistance is improved.

【0002】

[Conventional technology]

As is well known in semiconductor devices, elements are built one after another in the state of a wafer to form an IC circuit having a predetermined function. On the plane, the IC circuit forming portion in which the IC circuit is formed is arranged in a matrix, and the dicing line portion is provided in a grid pattern surrounding the IC circuit forming portion, and dicing is performed along the dicing line portion. It is separated and formed in each semiconductor device (semiconductor chip).

【0003】

For example, Japanese Patent Application Laid-Open No. 9-64049 is detailed. FIG. 2 illustrates the outline of the chip size package 50. A wafer 51 made of a wafer 51 and coated up to a passivation film 52 is prepared, and the uppermost metal electrode 53 (for example, a bonding pad) is exposed. An opening is formed, and the rewiring layer 54 is formed by Cu plating through the opening.

【0004】

A metal post 55 is formed on the rewiring layer 54, and the entire surface is covered with a sealing resin 56. The metal post 55 exposed from the sealing resin 56 has a solder bump or a solder ball 57. Is formed.

【0005】

In this state, dicing is performed along the dicing line portion 58 and individually separated to complete the semiconductor chip 50.

【0006】

[Problems to be Solved by the Invention]

However, on the side wall of this dicing line, the interface of a number of interlayer insulating films laminated on the semiconductor device is exposed. This interface serves as an infiltration path for moisture, and has a problem of causing malfunction and further destruction of the IC circuit.

【0007】

In particular, depending on the number of layers of the metal wiring, the first interlayer insulating film, the second interlayer insulating film, the third interlayer insulating film, and so on are provided in multiple layers, and the interlayer insulating film itself is In consideration of distortion and flatness, a plurality of layers of films, such as a TEOS film and an SOG film, are repeatedly laminated many times. The interface between these films was exposed on the side wall formed in the dicing portion, causing moisture resistance deterioration.

【0008】

[Means for solving problems]

The present invention has been made in view of the above-mentioned problems. First, the present invention is made between the IC circuit forming portion formed on the main surface of the semiconductor chip and the dicing line portion formed surrounding the IC circuit forming portion. This is solved by providing a seal ring that surrounds the IC circuit forming portion.

【0009】

Since the seal ring is provided with a plug that cuts the interface of the interlayer insulating film, it blocks the passage of moisture.

【0010】

In the first means, the dicing line portion includes a first dicing side wall in which the upper side wall of the semiconductor chip is covered with a resin, and a second dicing side wall in which the lower side wall of the semiconductor chip is exposed. It is solved by having it.

【0011】

If the upper side wall reaches the semiconductor substrate, the interface of the interlayer insulating film above the semiconductor substrate is covered with the resin, so that double sealing is possible.

【0012】

Second, a first seal ring surrounding the IC circuit forming portion is provided between the IC circuit forming portion formed on the main surface of the semiconductor chip and the dicing line portion formed surrounding the IC circuit forming portion. The problem is solved by providing the first seal ring, surrounding the first seal ring, and covering the end portion of the interlayer insulating film located at the dicing line portion with a spacer.

【0013】

In addition to the first seal, a spacer covering the side wall of the interlayer insulating film, that is, the interface is provided, so that double, triple, and so on can be sealed.

【0014】

In the second means, the dicing line portion includes a first dicing side wall in which the upper side wall of the semiconductor chip is covered with a resin, and a second dicing side wall in which the lower side wall of the semiconductor chip is exposed. It is solved by having it.

【0015】

The first seal ring, the second seal ring and the resin can block the passage of moisture in and around the dicing line portion.

【0016】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described. Although this embodiment will be described below with the MOS type, it can also be realized with the BIP type and the Bi-CMOS type. In the semiconductor chip 1, a first seal ring 4 is formed between the IC circuit forming portion 2 and the dicing line portion 3. Here, since the IC circuit forming portion 2 of the semiconductor chip 1 itself is composed of two-layer metal, it is a seal ring 4 having a two-story structure. Therefore, a multi-story seal ring is possible depending on the number of metal layers. For example, in the case of three-layer metal, the structure from the first floor to the third floor is possible.

【0017】

Now, the specific structure of the seal ring 4 will be described. For example, in the IC circuit forming unit 2, a diffusion region is formed by a normal process, a TR, a diode, a diffusion resistor, and the like are formed, and an insulating film is formed on the surface.

【0018】

In the MOS type, the gate insulating film 5 is required because the gate is required, but generally, the interlayer insulating film 5 of the first layer is formed under the metal wiring of the first layer. .. In the figure, the metal wiring of the first layer is omitted. A second layer interlayer insulating film 7 is formed between the lower layer of the second layer metal wiring 6 and the first layer metal wiring. In the figure, the metal wiring 6 of the second layer is in direct contact with the semiconductor substrate 1, but generally, the metal wiring 6 of the first layer is in contact with the metal wiring of the first layer through a contact hole.

【0019】

Further, since it is shown by the two-layer metal in the figure, the passivation film 8 is coated on the metal wiring 6 of the second layer. However, in the metal layer of three or more layers, a passivation film is formed on the metal wiring of the uppermost layer, and an interlayer insulating film is formed between the metal wirings below the passivation film.

【0020】

The interlayer insulating films 5, 7, and 8 extend to the dicing line portion 3 or its vicinity. A first seal ring 4 surrounding the dicing line portion 3 is provided between the dicing line portion 3 and the IC circuit forming portion 2.

【0021】

In the forming region of the seal ring 4, a plurality of first seal grooves 9 (three in the figure) from which the interlayer insulating film of the first layer has been removed are provided so as to surround the IC circuit forming portion 2. Further, the interlayer insulating film of the second layer is also provided with a plurality of second seal grooves 10 (two in the figure). A first metal electrode 11 and a second metal electrode 12 are formed in the seal groove so that wiring is provided via the contact.

【0022】

That is, the metal electrode may be made of the same material including the seal groove. However, here, since the IC circuit forming part is interconnected using a tungsten plug, W is embedded in the seal grooves 9 and 10, and the metal electrodes 11 and 12 are mainly made of Al. It is made up.

【0023】

Specifically, the metal that becomes the barrier metal is laminated in the order of Ti and TiN on the entire surface including this seal groove. Ti is covered with about 300 to 500 Å, TiN is covered with about 1000 to 2000 Å, and W is covered with about 5000 to 8000 Å on the entire surface. Then, this W is etched back to form a tungsten plug. The metal electrode is formed by stacking TiN of 500 to 1000 Å, Ti of 100 to 200 Å, and AlCu of about 3000 to 5000 Å from the bottom, and etching the metal electrode into a pattern as shown in the figure.

【0024】

Further, in the vicinity of the dicing line portion 3, the interlayer insulating film 5 of the first layer extends from the IC circuit forming portion 2, and an end portion (side wall) 13 thereof is provided. Further, the second interlayer insulating film 7 also extends from the IC circuit forming portion 2 and is provided with an end portion (side wall) 14 thereof.

【0025】

The interlayer insulating film 5 of the first layer is composed of three layers in the figure, but specifically, the gate insulating film is formed on the surface and laminated, and the BPSG film 4 is about 2000 to 4000 Å. The TEOS film 5 is laminated on it with a thickness of about 8000 to 10000 Å. However, the interlayer insulating film 7 may be a single-layer insulating film or may be laminated in three or more layers. The interlayer insulating film 7 of the second layer is shown as two layers. Specifically, from the bottom, a plasma TEOS film of about 2000 Å, an SOG film of about 2000 Å, a plasma TEOS film of about 500 to 1000 Å, and about 2000 Å. SOG film and plasma TEOS film of about 2000 to 3000 Å are laminated.

【0026】

The feature of the present invention is that the seal ring 4 is first provided in the chip size package to improve the moisture resistance. As described above, a plurality of insulating films are laminated on the interlayer insulating films 5 and 7, and the interface thereof extends from the end portion. However, since the sealing groove is provided and the metal is embedded in the groove, even if moisture enters from the dicing side wall, it can be stopped here.

【0027】

The second point is that spacers 15 and 16 are provided on the first side wall 13 and / and the second side wall 14.

【0028】

The spacers 15 and 16 are generally formed by covering the entire surface of the film and then etching back. Therefore, here, an insulating film such as a silicon oxide film, a Si3N4 film, or a TEOS film, a material containing Al as a main material, an amorphous, single crystal, polycrystalline silicon film, W, or the like can be considered. These are all materials that can be etched back.

【0029】

Similar to the first seal ring 4 described above, the interface of the interlayer insulating film is sealed, and the end face is covered here. In other words, the point is that the very first approach route is sealed.

【0030】

Further, although this spacer is formed on both end faces, either one of them has the effect. Of course, as the number of layers increases, so does the end face, so the spacer placement area increases. This also needs to be sealed at least one.

【0031】

In the drawing, the first seal ring 4, the first spacer 15, and the third spacer 16 are tripled. Further, as will be described later, the dicing side wall may be further covered with a resin.

【0032】

The passivation film 8 is the same as a normal IC. In the IC, a thin metal wire is connected to the metal pad exposed from the passivation film 8, and the other end is connected to the lead of the mounted lead frame.

【0033】

However, since the present invention is a chip size package, a wiring layer 19 and a metal post 20 are further formed on the chip size package, and solder bumps and solder balls 22 are formed on the metal post 20 exposed from the sealing resin 21.

【0034】

The wiring layer 19 is formed by, for example, Cu plating or sputtering. Reference numeral 23 is a material whose surface can be realized to be flat over substantially the entire area. That is, in consideration of the flatness of the wiring layer 19, a fluid resin is applied, and the surface of the wiring layer 19 is flattened by being left to be cured. For example, it can be easily realized by applying with a spin-on or a dispenser. It is also possible with SOG.

【0035】

A metal post 20 is formed at the end of the wiring layer 19. The metal post 20 relieves stress generated due to a difference in thermal expansion coefficient generated when mounted on a printed circuit board, for example. That is, if the mounting board has a higher elongation rate, the metal post is pulled in the direction of the elongation. However, if the height is high, the stress can be absorbed like bamboo does.

【0036】

On the other hand, the dicing line portion 3 is diced once or twice. In the case of one time, it is fully cut along the first dicing side wall 17. This is the usual method for chip size packages.

【0037】

In the two dicing cuts, the half-cut dicing that reaches the semiconductor substrate 1 is performed first. This reveals the side wall 17. Then, the sealing resin 21 is embedded in the dicing groove formed by the half cut, and the sealing resin 21 including the embedded sealing resin 21 is fully cut narrower than the first dicing groove 23.

【0038】

This indicates the outermost seal, as described above. That is, the interface of the passivation film 8 is sealed with a sealing resin in the vicinity of the full cut line 24. That is, the interface of the passivation film 8 is exposed on the dicing side wall 17 in one full cut, but this interface can also be sealed by dividing the dicing twice.

【0039】

Further, the spacers 15 and 16 form an opening having the end portions 13 and 14 as one side wall at the same time as forming the seal grooves 9 and 10, and W is embedded in the groove and the opening and etched back at the same time. , Plugs and spacers can be formed at the same time, the process does not increase. Of course, this step may be formed at the same time as the contact and W embedding formed in the IC circuit forming portion 2.

【0040】

Recently, CSPs (chip size packages) have been developed and are beginning to appear on the market. In these, the amount of resin is extremely small, and improvement of moisture resistance is a very important theme.

【0041】

In particular, in the wafer type CSP, after the IC is built in the wafer state and the passivation film is coated, the sealing resin is placed on the entire surface, and then dicing is performed to separate the chips into individual chips. The interface of the interlayer insulating film is exposed. Therefore, the seal ring has a very important position. If the configuration of the present invention is adopted, multiple seals can be made, and there is an advantage that deterioration of the moisture resistance of the chip can be prevented.

【0042】

Then, the manufacturing method will be specifically described.

【0043】

The IC circuit forming portion 2 is formed in a matrix on the semiconductor wafer 1, and the dicing line portion 3 is formed so as to surround the IC circuit forming portion. A seal ring 4 is provided between the IC circuit forming portion 2 and the dicing line portion 3 so as to surround the IC circuit forming portion 2 in a later process.

【0044】

Reference numeral 4 is a first interlayer insulating film formed in the lower layer of the first layer metal electrode (which is the first metal wiring in the IC circuit forming portion) 11. The first interlayer insulating film 4 is laminated on the surface of which the gate insulating film GI is formed, the BPSG film 4 is laminated at about 3000 Å, and the TEOS film 5 is laminated at about 8000 to 10000 Å.

【0045】

Subsequently, a plurality of sealing grooves 9 and 10 from which the semiconductor substrate 1 is exposed are formed in the first interlayer insulating film 4, and tungsten is embedded therein. The seal groove is formed of three rings (the number is not particularly limited) in a ring shape, and at the same time, an opening having the first side wall 13 as a component is opened. Since this opening is formed at the same time as the first seal groove 9, the semiconductor substrate 1 is exposed, but it may be opened in a separate process. Further, the depth of the first seal groove 9 may be shallower than that shown in the figure. However, it must be at least deep enough to cover the top interface with a spacer. Further, if the chip size is taken into consideration and only the spacer 16 is formed, it is not necessary to open the opening.

【0046】

Subsequently, there is a step of forming a tungsten plug in the first seal groove 9, a spacer in the first opening, and further forming a first layer metal electrode 11 that covers the entire tungsten plug.

【0047】

Specifically, the metal serving as the barrier metal is laminated in the order of Ti and TiN on the entire surface including the seal groove 9. Ti is covered with about 300 to 500 Å, TiN is covered with about 1000 to 2000 Å, and W is covered with about 8000 Å on the entire surface. Then, this W is etched back to form a tungsten plug, and a spacer made of W is formed on the side wall 13 of the first opening. Then, the excess barrier metal other than the first metal electrode 11 region and the spacer region is removed.

【0048】

The first metal electrode 11 is formed by stacking TiN of 500 to 1000 Å, Ti of 100 to 300 Å, and AlCu of about 3000 to 5000 Å from the bottom, and etching the first metal electrode 11 into a pattern as shown in the figure. Three tungsten plugs of the first layer are formed as rings surrounding the IC circuit forming portion 2, and the first metal electrode 11 is formed as one wide ring covering all of them.

【0049】

Here, the first tungsten plug has the same configuration and is also formed in the IC circuit forming portion 2 to contact the source region and the drain region of the transistor, and the first metal electrode is also simultaneously connected to the IC circuit forming portion as wiring. It is formed and is in electrical contact with the tungsten plug formed in the IC circuit forming portion.

【0050】

If the first seal groove 9 is not formed as described above, naturally the spacer is not formed either.

【0051】

Subsequently, the interlayer insulating film 7 of the second layer is coated from the IC circuit forming portion 2 to the dicing line portion 3. Here, the entire surface of the wafer is covered.

【0052】

Here, the interlayer insulating film 7 of the second layer is shown as two layers. Specifically, from the bottom, a plasma TEOS film of about 2000 Å, an SOG film of about 2000 Å, a plasma TEOS film of about 500 to 1000 Å, and about. A 2000 Å SOG film and a plasma TEOS film of about 2000 to 3000 Å are laminated.

【0053】

Further, in the dicing line portion 3, the interlayer insulating film 6 of the second layer covers the spacer 15 that seals the side wall of the first interlayer insulating film 5.

【0054】

Further, a second seal groove 10 that exposes the metal electrode 11 of the first layer is formed, and at the same time, a second opening that constitutes the side wall 14 is formed.

【0055】

Here, the second seal groove 10 is formed at the same time as the formation of the second opening, but etching may be performed in a separate process. The depth may be in the middle of the second interlayer insulating film 7 or may be the depth at which the first interlayer insulating film 5 is removed halfway. As described above, this can function as a seal as long as it can seal at least the interface of the uppermost layer.

【0056】

Subsequently, tungsten is embedded in the second seal groove 10, and at the same time, a W spacer 16 is formed in the second opening.

【0057】

Here, first, a barrier metal consisting of Ti of about 300 to 500 Å and TiN of about 1000 to 2000 Å is formed by sputtering on the entire surface including the second seal groove 10, and W of about 5000 to 8000 Å is formed on this. For example, it is coated by the CVD method.

【0058】

Subsequently, the W is etched back to form a tungsten plug, and a spacer 16 made of tungsten is formed on the second side wall.

【0059】

The spacer 16 which is the covering portion covers the interface exposed on the second side wall 14, and serves as a sealing ring to prevent the ingress of moisture.

【0060】

That is, the IC circuit forming portion 2 is first sealed with a seal ring 4 composed of a tungsten plug, and the outside thereof is sealed with spacers 15 and 16 made of W, so that a triple sealing structure can be realized.

【0061】

Then, the tungsten plug is coated, and the metal electrode 12 of the second layer, which also has a ring shape, is formed. In this metal electrode 12, about 200 to 300 Å of TiN is laminated on the lower layer and about 6000 to 8000 Å of AlCu is laminated on the upper layer, and the metal electrode 12 is etched in a ring shape.

【0062】

Subsequently, a third interlayer insulating film 8 is formed from the IC circuit forming portion 2 to the dicing line portion 3. In addition, resin 23 that flattens the surface is applied.

【0063】

The uppermost metal electrode formed in the IC circuit forming portion 2 is exposed on the interlayer insulating film 8 and the resin 23, and the Cu rewiring layer 19 including this opening is formed. A metal post 20 is formed by plating at the end of the Cu rewiring layer 19, and the resin 21 is sealed on the entire surface. Then, the solder balls 22 are formed on the metal posts exposed from the resin 21.

【0064】

When the resin 21 is sealed, a dicing groove 23 is formed, and the resin 21 is also embedded therein.

【0065】

And finally, it is diced along the full cut line 24 and separated individually.

【0066】

[Effect of the invention]

As is clear from the above explanation, first of all, a seal ring is provided around the IC circuit forming portion, and the plug constituting this seal ring cuts the interface of the interlayer insulating film, thereby blocking the passage of moisture. , It is possible to prevent deterioration of the chip size package.

【0067】

Further, in the first, the dicing line portion has a first dicing side wall in which the upper side wall of the semiconductor chip is covered with a resin, and a second dicing side wall in which the lower side wall of the semiconductor chip is exposed. This makes it possible to seal the interface of the interlayer insulating film above the semiconductor substrate with a resin.

【0068】

Secondly, in addition to the first seal ring, a spacer covering the side wall of the interlayer insulating film, that is, the interface is provided, so that double, triple, and so on can be sealed.

【0069】

In the second, the dicing line portion has a first dicing side wall in which the upper side wall of the semiconductor chip is covered with a resin, and a second dicing side wall in which the lower side wall of the semiconductor chip is exposed. , The first seal ring, the second seal ring and the resin can block the passage of moisture in and around the dicing line portion.

【0070】

As described above, the moisture resistance of the chip size package is greatly improved, and the problem of defects is solved.

[Simple explanation of drawings]

[Figure 1]

It is sectional drawing which shows the chip size package of this invention.

[Figure 2]

It is sectional drawing which shows the conventional chip size package.