Driving circuit for electro-optical device, and electro- optical device
Abstract
[Task] In an electro-optical device in which a drive circuit is formed on one substrate, a relatively simple configuration is used to cope with the miniaturization of pixel pitch.
Solution.In the scanning line drive circuit 104, each transfer signal by the shift register 500 is branched into three, and an enable circuit 502 is provided corresponding to each branch. Then, during the pulse period of the transfer signal, one transfer signal is sequentially shifted in time by the enable signals ENB1y, ENB2y, and ENB3y whose phases are sequentially shifted from each other, divided into three, and each is output as a scanning signal. To do. The same applies to the data line drive circuit.

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Projected expiry passed 17 June 2019, 7.3 years ago.
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31 claims: 5 independent, 26 dependent
- 1【特許請求の範囲】 【請求項1】 複数の走査線と複数のデータ線との交差に対応して設けられたスイッチング素子と、前記スイッチング素子に接続された画素電極とからなる画素を駆動する電気光学装置の駆動回路であって、 前記走査線の本数よりも少ない段数の単位回路からなるシフトレジスタであって、所定周期のクロック信号に基づいて各段の単位回路からの転送信号を順次出力するシフトレジスタと、 前記各段の単位回路から出力された転送信号を時間軸上で複数に分割して、それぞれを走査信号として前記走査線に順次出力する出力手段とを備えることを特徴とする電気光学装置の駆動回路。
- 2【請求項2】 前記出力手段は、 前記単位回路にそれぞれ対応して設けられ、各々は、対応する単位回路から出力された転送信号を複数本に分岐する分岐配線と、 前記分岐配線による分岐に対応して設けられ、各々は、前記分岐配線により分岐された転送信号と、所定のイネーブル信号との論理積信号を走査信号として出力するイネーブル回路とを備え、 同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士においては、アクティブ期間が互いに重複しないイネーブル信号が個別に供給されることを特徴とする請求項1に記載の電気光学装置の駆動回路。
- 3【請求項3】 隣接するイネーブル回路はデータ線の配列方向に沿って、互い違いに配置されていることを特徴とする請求項2に記載の電気光学装置の駆動回路。
- 4【請求項4】 前記イネーブル回路の各々は、 前記転送信号と前記所定のイネーブル信号とを入力するNANDゲートと、その出力を反転するインバータとの直列接続からなることを特徴とする請求項2に記載の電気光学装置の駆動回路。
- 5【請求項5】 前記イネーブル回路の各々は、 前記転送信号が入力され、かつ、前記所定のイネーブル信号が入力されたとき、前記走査信号を出力するトランスミッションゲートであることを特徴とする請求項2に記載の電気光学装置の駆動回路。
- 6【請求項6】 前記イネーブル回路の各々は、 前記転送信号が入力され、かつ、前記所定のイネーブル信号が入力されたとき、前記走査信号を出力する薄膜トランジスタであって、P型またはN型のうち、いずれか一方のチャネル型からなることを特徴とする請求項2に記載の電気光学装置の駆動回路。
- 7【請求項7】 前記駆動回路は、 前記画素電極の形成領域を挟んで両側に形成されて、 前記両側のうち、一方に形成された駆動回路は、前記複数の走査線のうち、奇数本目の走査線に対して走査信号を出力し、他方に形成された駆動回路は、偶数本目の走査線に対して走査信号を出力することを特徴とする請求項1に記載の電気光学装置の駆動回路。
- 8【請求項8】 請求項1に記載の電気光学装置の駆動回路を備えたことを特徴とする電気光学装置。
- 9【請求項9】 複数の走査線と複数のデータ線との交差に対応して設けられたスイッチング素子と、前記スイッチング素子に接続された画素電極とからなる画素を駆動する電気光学装置の駆動回路であって、 前記データ線の本数よりも少ない段数の単位回路からなるシフトレジスタであって、所定周期のクロック信号に基づいて各段の単位回路から転送信号を順次出力するシフトレジスタと、 前記各段の単位回路から出力された転送信号を、時間軸上で複数に分割してサンプリング制御信号として出力する出力手段と、 前記データ線のそれぞれに対応して設けられ、各々は、前記出力手段により分割されたサンプリング制御信号にしたがって、画像信号をサンプリングして対応するデータ線に供給するサンプリングスイッチとを備えることを特徴とする電気光学装置の駆動回路。
- 10【請求項10】 前記出力手段は、 前記単位回路にそれぞれ対応して設けられ、各々は、対応する単位回路から出力された転送信号を複数本に分岐する分岐配線と、 前記分岐配線による分岐に対応して設けられ、各々は、前記分岐配線により分岐された転送信号と、所定のイネーブル信号との論理積信号をサンプリング制御信号として出力するイネーブル回路とを備え、 同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士においては、アクティブ期間が互いに重複しないイネーブル信号が個別に供給されることを特徴とする請求項9に記載の電気光学装置の駆動回路。
- 11【請求項11】 前記イネーブル回路の各々は、 前記転送信号と前記所定のイネーブル信号とを入力するNANDゲートと、その出力を反転するインバータとの直列接続からなることを特徴とする請求項10に記載の電気光学装置の駆動回路。
- 12【請求項12】 前記イネーブル回路の各々は、 前記転送信号が入力され、かつ、前記所定のイネーブル信号が入力されたとき、前記サンプリング制御信号を出力するトランスミッションゲートであることを特徴とする請求項10に記載の電気光学装置の駆動回路。
- 13【請求項13】 請求項9に記載の電気光学装置の駆動回路を備えたことを特徴とする電気光学装置。
- 14【請求項14】 複数の走査線と複数のデータ線との交差に対応して設けられたスイッチング素子と、前記スイッチング素子に接続された画素電極とを有し、所定本数のデータ線毎に、シリアル-パラレル変換された画像信号を同時にサンプリングする電気光学装置の駆動回路であって、 画像信号が同時にサンプリングされるデータ線の本数よりも少ない段数の単位回路からなるシフトレジスタであって、所定周期のクロック信号に基づいて各段の単位回路から転送信号を順次出力するシフトレジスタと、 前記各段の単位回路から出力された転送信号を、時間軸上で複数に分割してサンプリング制御信号として出力する出力手段と、 前記データ線のそれぞれに対応して設けられ、各々は、前記サンプリング制御信号にしたがって、前記画像信号のうちいずれかをサンプリングして、対応するデータ線に供給するサンプリングスイッチであって、相隣接するデータ線の複数本に対応して設けられたもの同士は、同一のサンプリング制御信号によって同時に異なる画像信号をサンプリングするサンプリングスイッチとを備えることを特徴とする電気光学装置の駆動回路。
- 15【請求項15】 前記出力手段は、 前記単位回路にそれぞれ対応して設けられ、各々は、対応する単位回路により出力された転送信号を複数本に分岐する分岐配線と、 前記分岐配線による分岐に対応して設けられ、各々は、前記分岐配線により分岐された転送信号と、所定のイネーブル信号との論理積信号をサンプリング制御信号として出力するイネーブル回路とを備え、 同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士においては、アクティブ期間が互いに重複しないイネーブル信号が個別に供給されることを特徴とする請求項14に記載の電気光学装置の駆動回路。
- 16【請求項16】 前記イネーブル回路の各々は、 前記転送信号と前記所定のイネーブル信号とを入力するNANDゲートと、その出力を反転するインバータとの直列接続からなることを特徴とする請求項15に記載の電気光学装置の駆動回路。
- 17【請求項17】 前記イネーブル回路の各々は、 前記転送信号が入力され、かつ、前記所定のイネーブル信号が入力されたとき、前記サンプリング制御信号を出力するトランスミッションゲートであることを特徴とする請求項15に記載の電気光学装置の駆動回路。
- 18【請求項18】 請求項14に記載の電気光学装置の駆動回路を備えたことを特徴とする電気光学装置。
- 19【請求項19】 複数の走査線と複数のデータ線との交差に対応して設けられたスイッチング素子と、前記スイッチング素子に接続された画素電極とからなる画素を駆動する電気光学装置の駆動回路であって、 前記データ線の本数よりも少ない段数の単位回路からなるシフトレジスタであって、所定周期のクロック信号に基づいて各段の単位回路から転送信号を順次出力するシフトレジスタと、 前記各段の単位回路から出力された転送信号を、時間軸上で複数に分割、または、同時に複数に分配してサンプリング制御信号として出力する出力手段と、 前記データ線のそれぞれに対応して設けられ、各々は、出力手段により分割または分配された転送信号にしたがって、複数本の画像信号線のうち、いずれか1本に供給された画像信号をサンプリングして、対応するデータ線に供給するサンプリングスイッチとを備えることを特徴とする電気光学装置の駆動回路。
- 20【請求項20】 前記出力手段が、転送信号を時間軸上で複数に分割する場合、前記複数本の画像信号線には、同じ画像信号が供給されて、サンプリングスイッチの各々は、当該画像信号を順次サンプリングする一方、 前記出力手段が、転送信号を同時に複数に分配する場合、前記複数本の画像信号線には、1系統の画像信号が時間軸に当該複数倍に伸長されるとともに分配されて、前記サンプリングスイッチのうち、相隣接するデータ線の複数本に対応して設けられたもの同士は、異なる画像信号を同時にサンプリングすることを特徴とする請求項19に記載の電気光学装置の駆動回路。
- 21【請求項21】 前記出力手段は、 前記単位回路にそれぞれ対応して設けられ、各々は、対応する単位回路により出力された転送信号を複数本に分岐する分岐配線と、 前記分岐配線による分岐に対応して設けられ、各々は、前記分岐配線により分岐された転送信号と、所定のイネーブル信号との論理積信号をサンプリング制御信号として出力するイネーブル回路とを備え、 転送信号を時間軸上で複数に分割する場合、同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士においては、当該転送信号が供給される期間でアクティブ期間が互いに重複しないイネーブル信号が個別に供給される一方、 転送信号を同時に複数に分配する場合、同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士においては、当該転送信号が供給される期間でアクティブ期間が同一であるイネーブル信号が個別に供給されることを特徴とする請求項20に記載の電気光学装置の駆動回路。
- 22【請求項22】 前記イネーブル回路の各々は、 前記転送信号と前記所定のイネーブル信号とを入力するNANDゲートと、その出力を反転するインバータとの直列接続からなることを特徴とする請求項21に記載の電気光学装置の駆動回路。
- 23【請求項23】 前記イネーブル回路の各々は、 前記転送信号が入力され、かつ、前記所定のイネーブル信号が入力されたとき、前記サンプリング制御信号を出力するトランスミッションゲートであることを特徴とする請求項21に記載の電気光学装置の駆動回路。
- 24【請求項24】 請求項19に記載の電気光学装置の駆動回路を備えたことを特徴とする電気光学装置。
- 25【請求項25】 前記出力手段において、転送信号を時間軸上で複数に分割するか、または、転送信号を同時に複数に分配するかについて判定する判定手段と、 転送信号を時間軸上で複数に分割する、と判定された場合には、同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士に、当該転送信号が供給される期間でアクティブ期間が互いに重複しないイネーブル信号を個別に供給する一方、転送信号を同時に複数に分配する、と判定された場合には、同一の分岐配線によって分岐された転送信号が供給されるイネーブル回路同士に、当該転送信号が供給される期間でアクティブ期間が同一であるイネーブル信号を個別に供給する供給手段とを備えることを特徴とする請求項24に記載の電気光学装置。
- 26【請求項26】 前記判定手段は、入力した画像信号の種類に基づいて前記判定を行うことことを特徴とする請求項25に記載の電気光学装置。
- 27【請求項27】 入力した画像信号における動きを検出して、その検出信号を出力する動き検出手段をさらに備え、 前記判定手段は、前記検出信号に基づいて、予め設定された時間内に前記動きがあると判定した場合には、転送信号を時間軸上で複数に分割すると判定する一方、前記時間内に前記動きがないと判定した場合には、転送信号を同時に複数に分配すると判定することを特徴とする請求項25に記載の電気光学装置。
- 28【請求項28】 複数の走査線と複数のデータ線との交差に対応して設けられたスイッチング素子と、前記スイッチング素子に接続された画素電極とからなる画素を駆動する電気光学装置の駆動回路であって、 前記データ線の本数よりも少ない段数の単位回路からなるシフトレジスタであって、所定周期のクロック信号に基づいて各段の単位回路から転送信号を順次出力するシフトレジスタと、 前記各段の単位回路から出力された転送信号を、時間軸上で複数に分割する第1の出力手段と、 前記第1の出力手段により分割された転送信号を、さらに、時間軸上で複数に分割、または、同時に複数に分配してサンプリング制御信号として出力する第2の出力手段と、 前記データ線のそれぞれに対応して設けられ、各々は、前記第2の出力手段により分割または分配された転送信号にしたがって、複数本の画像信号線のうち、いずれか1本に供給された画像信号をサンプリングして、対応するデータ線に供給するサンプリングスイッチとを備えることを特徴とする電気光学装置の駆動回路。
- 29【請求項29】 前記第2の出力手段が、転送信号を時間軸上で複数に分割する場合、前記複数本の画像信号線には、同じ画像信号が供給されて、サンプリングスイッチの各々は、当該画像信号を順次サンプリングする一方、 前記第2の出力手段が、転送信号を同時に複数に分配する場合、前記複数本の画像信号線には、1系統の画像信号が時間軸に当該複数倍に伸長されるとともに分配されて、前記サンプリングスイッチのうち、相隣接するデータ線の複数本に対応して設けられたもの同士は、当該画像信号を同時にサンプリングすることを特徴とする請求項28に記載の電気光学装置の駆動回路。
- 30【請求項30】 前記第1の出力手段は、 前記単位回路にそれぞれ対応して設けられ、各々は、対応する単位回路により出力された転送信号を複数本に分岐する第1の分岐配線と、 前記第1の分岐配線による分岐に対応して設けられ、各々は、前記第1の分岐配線により分岐された転送信号と、第1群のイネーブル信号との論理積信号を出力する第1のイネーブル回路とを備え、 同一の第1の分岐配線によって分岐された転送信号が供給される第1のイネーブル回路同士においては、当該転送信号が供給される期間でアクティブ期間が互いに重複しない第1群のイネーブル信号が個別に供給され、 前記第2の出力手段は、 前記第1のイネーブル回路にそれぞれ対応して設けられ、各々は、対応する第1のイネーブル回路により分割された転送信号を複数本に分岐する第2の分岐配線と、 前記第2の分岐配線による分岐に対応して設けられ、各々は、前記第2の分岐配線により分岐された転送信号と、第2群のイネーブル信号との論理積信号をサンプリング制御信号として出力する第2のイネーブル回路とを備え、 転送信号を時間軸上で複数に分割する場合、同一の第2の分岐配線によって分岐された転送信号が供給される第2のイネーブル回路同士においては、当該転送信号が供給される期間でアクティブ期間が互いに重複しない第2群のイネーブル信号が個別に供給される一方、 転送信号を同時に複数に分配する場合、同一の第2の分岐配線によって分岐された転送信号が供給される第2のイネーブル回路同士においては、当該転送信号が供給される期間でアクティブ期間が同一である第2群のイネーブル信号が個別に供給されることを特徴とする請求項29に記載の電気光学装置の駆動回路。
- 31【請求項31】 請求項30に記載の電気光学装置の駆動回路を備えたことを特徴とする電気光学装置。
Independent claims31
389 paragraphs in 1 section, as filed
Description: TECHNICAL FIELD [Detailed description of the invention]
【0001】
[Technical field to which the invention belongs]
The present invention relates to a drive circuit of an electro-optic device for driving an active matrix electro-optic device, and an electro-optic device driven by the drive circuit.
【0002】
[Conventional technology]
Generally, in an electro-optical device driven by an active matrix method, a plurality of scanning lines and a plurality of data lines are arranged vertically and horizontally, and a pixel electrode corresponding to each of these intersections is a thin film diode (Thin Film Diode). It is formed via a switching element such as a thin film transistor (hereinafter referred to as "TFT") or a thin film transistor (hereinafter referred to as "TFD").
【0003】
Of these, scanning signals are sequentially supplied to each scanning line by the scanning line driving circuit. Specifically, the scanning line drive circuit has a Y-side shift register composed of a plurality of stages of unit circuits with respect to the Y direction (longitudinal direction) which is the arrangement direction of the scanning lines. Here, the Y-side shift register sets the start pulse supplied from the external image signal processing circuit at the beginning of the vertical scanning period to the Y-side clock signal CLY (firstly, which is the reference for vertical scanning from the image signal processing circuit. And its inverted signal CLY'), it is sequentially transferred, and secondly, the transfer signal in the unit circuit of each stage is supplied as a scanning signal to the corresponding scanning line.
【0004】
On the other hand, each data line is driven by a data line drive circuit. That is, the data line drive circuit supplies the sampling control signal to the sampling switch that samples the image signal supplied to the image signal line for each data line in synchronization with the sequential supply operation of the scanning signal. It is configured. Specifically, first, the data line drive circuit has an X-side shift register having a plurality of stages with respect to the X direction (horizontal direction), which is the arrangement direction of the data lines. Here, the X-side shift register first sends the start pulse supplied from the external image signal processing circuit at the beginning of the horizontal scanning period to the X-side clock signal CLX (which is the reference for horizontal scanning from the image signal processing circuit). And its inverting signal CLX'), it is sequentially transferred, and secondly, the transfer signal by the unit circuit of each stage is output as a sampling control signal to the sampling switch connected to the corresponding data line. Then, according to this sampling control signal, each sampling switch has a configuration in which the image signal supplied to the image signal line is sampled according to the sampling control signal and supplied to the corresponding data line.
【0005】
In this way, in the active matrix electro-optic device, field-by-field or frame-by-frame vertical scanning, that is, field scanning, frame scanning, etc., is performed based on the scanning signals and sampling control signals sequentially output from the shift register. It is common to be told.
【0006】
By the way, in this type of electro-optical device, the scanning line drive circuit, the data line drive circuit, and the like described above are switched to one of the pair of substrates constituting the electro-optical apparatus, which is connected to a pixel electrode. In many cases, it is put into practical use as a drive circuit built-in type formed together with an element. In this case, by reducing the space of the peripheral circuit including the drive circuit, it is possible to reduce the size of the entire device, and further, the peripheral circuit is actively configured in the same process as the switching element that drives the pixel electrode. By forming the element, it is possible to improve the manufacturing efficiency of the entire device and reduce the cost.
【0007】
However, the size of the substrate is a factor that determines the size of the entire electro-optical device. For this reason, in the peripheral area on the substrate, making the area forming the scanning line drive circuit, the data line drive circuit, etc. unnecessarily larger than the screen display area makes the entire electro-optical device smaller and electric. This results in a result contrary to the basic requirement in the technical field to make the screen display area relatively large with respect to the size of the optical device.
【0008】
Therefore, in order to form a drive circuit on the substrate, first, in the Y-side shift register of the scanning line drive circuit, the circuit pitch in the Y direction in the unit circuit of each stage (hereinafter, simply "the circuit of the Y-side shift register"). "Pitch") is adjusted to the pitch of the scanning line. As a result, the width in the Y direction of the area required for forming the scanning line drive circuit becomes about the same as the width in the Y direction of the screen display area. Similarly, in the X-side shift register of the data line drive circuit, the circuit pitch in the X direction in the unit circuit of each stage (hereinafter, simply referred to as "circuit pitch of the X-side shift register") and the sampling switch in the sampling circuit. The pitch in the X direction (hereinafter simply referred to as "sampling switch pitch") is adjusted to the pitch of the data line. As a result, the width in the X direction of the area required for forming the data line drive circuit becomes about the same as the width in the X direction of the screen display area. Therefore, in the substrate, the widths in the X direction and the Y direction are suppressed, and the size of the substrate is prevented from increasing.
【0009】
By the way, in recent years, there has been a strong demand for higher image quality in electro-optical devices. Therefore, in order to realize a high-definition image, it is necessary to reduce the pixel pitch and drive a larger number of scanning lines and data lines at a high frequency.
【0010】
[Problems to be Solved by the Invention]
However, the shift register described above is provided with a plurality of relatively complicated active elements for each unit circuit of each stage. For example, in the unit circuit of each stage, three clocked inverters consisting of four TFTs, and wiring for supplying positive and negative power supplies, clock signals, and their inversion signals to each of these clocked inverters. However, it is the minimum required. Therefore, in the configuration in which peripheral circuits such as a drive circuit are formed on the substrate of the electro-optical device, as the pixel pitch becomes finer, the circuit pitches of the Y-side and X-side shift registers described above are changed to scanning lines and data lines, respectively. It becomes difficult to match the pitch of. For example, at present, the limit of the circuit pitch of the shift register is around 20 μm in a practical sense, so the circuit pitch of the shift register constituting the drive circuit becomes a bottleneck when miniaturizing the pixel pitch. There is a problem.
【0011】
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a drive circuit of an electro-optic device and the drive circuit thereof, which can cope with miniaturization of a pixel pitch by using a relatively simple configuration. The purpose is to provide a built-in electro-optic device.
【0012】
[Means for solving problems]
In order to achieve the above object, the drive circuit of the first electro-optical device in the present invention is connected to a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the switching element. It is a drive circuit of an electro-optical device that drives a pixel composed of a pixel electrode, and is a shift register composed of a unit circuit having a number of stages smaller than the number of scanning lines, and each stage is based on a clock signal having a predetermined cycle. The shift register that sequentially outputs the transfer signal from the unit circuit of the above and the transfer signal output from the unit circuit of each stage are divided into a plurality of parts on the time axis, and each is sequentially output to the scanning line as a scanning signal. It is characterized by having an output means.
【0013】
In the drive circuit of the first electro-optic device in the present invention, first, the transfer signal is sequentially output by the unit circuit of each stage constituting the shift register. Then, the transfer signal is divided into a plurality of pieces on the time axis by the output means, and is sequentially output to the plurality of scanning lines as a scanning signal. Therefore, in order to reduce the pixel pitch, the circuit pitch of the shift register can be expanded with respect to the pitch of the scanning line according to the number of divisions in the output means.
【0014】
For example, conventionally, if the total number of scanning lines is m (m is an integer of 2 or more), the unit circuit constituting the shift register requires at least the same number of m steps. On the other hand, in the present invention, assuming that the number of divisions in the output means is n (n is an integer of 2 or more), the unit circuit constituting the shift register requires only m / n stages, which is compared with the conventional case. , Reduced to 1 / n. Therefore, the circuit pitch of the Y-side shift register can be expanded n times. Further, in the present invention, since the drive frequency in the shift register is reduced according to the number of divisions n, it is possible to suppress the power consumed accordingly.
【0015】
On the other hand, as for the output means, since it is sufficient to have a configuration in which the transfer signal is divided on the time axis, the configuration is simplified as compared with the unit circuit of the shift register. Therefore, the circuit pitch in the Y direction required to form the output means can be easily configured to be narrower than the circuit pitch of the shift register.
【0016】
By the way, in the drive circuit of the first electro-optical device, in one aspect, the output means is provided corresponding to the unit circuit, and each is a transfer output from the corresponding unit circuit. A branch wiring that branches a signal into a plurality of lines and a branch wiring that corresponds to the branching by the branch wiring are provided, and each uses a logical product signal of the transfer signal branched by the branch wiring and a predetermined enable signal as a scanning signal. The enable circuits provided with the enable circuit for output and to which the transfer signal branched by the same branch wiring is supplied are individually supplied with the enable signals whose active periods do not overlap each other. According to this aspect, each transfer signal output from the shift register is branched by a plurality of branch wirings. Then, the AND signal of the branched transfer signal and the clock signal for enabling is obtained by the enable circuit and supplied to the corresponding scanning line as a scanning signal. Therefore, since the output means can be realized by a relatively simple circuit configuration of a branch wiring and an enable circuit, the circuit pitch in the output means is easily narrowed. Therefore, a situation that becomes a bottleneck when the circuit pitch of the enable circuit is miniaturized can be avoided.
【0017】
Here, in the embodiment in which the output means includes the enable circuit, the adjacent enable circuits may be arranged alternately along the arrangement direction of the data lines. When arranged in this way, the phase-adjacent enable circuits are arranged alternately with respect to the data line arrangement direction (that is, the direction orthogonal to the scanning line formation direction), so that the phase-adjacent enable circuits are arranged as data lines. Compared to the case where the data lines are arranged side by side at the same position (that is, in a straight line along the data line arrangement direction), the circuit elements constituting each enable circuit are formed wider in the scanning line arrangement direction. It becomes possible. As a result, the circuit pitch of the enable circuit can be further narrowed, and the pitch of the scanning lines can be miniaturized.
【0018】
Further, in the embodiment in which the output means includes an enable circuit, each of the enable circuits is configured by connecting a NAND gate for inputting the transfer signal and the predetermined enable signal in series and an inverter for inverting the output thereof. You may. With this configuration, the NAND gate and the inverter can be connected in series, so that the logical product signal of each branched transfer signal and the enable signal can be output reliably and accurately. Further, since the NAND gate and the inverter have a simpler configuration than each unit circuit of the shift register, the circuit pitch of the enable circuit can be narrowed relatively easily.
【0019】
On the other hand, in the embodiment in which the output means includes an enable circuit, each of the enable circuits is a transmission gate that outputs the scanning signal when the transfer signal is input and the predetermined enable signal is input. But it's okay. With this configuration, the transmission gate is a relatively simple circuit, so that the circuit pitch of the enable circuit can be narrowed relatively easily, and the delay required for the process of generating the scanning signal from the transfer signal is required. The time is short.
【0020】
Alternatively, in an embodiment in which the output means includes an enable circuit, each of the enable circuits is a thin film transistor that outputs the scanning signal when the transfer signal is input and the predetermined enable signal is input. It may be composed of either P-type or N-type channel type. With this configuration, if the enable circuit is configured by one of the P-type or N-channel type thin film transistors, the size of the enable circuit becomes relatively small, so that the circuit pitch of the enable circuit can be set relatively easily. Since the number of transistors can be narrowed and the number of transistors is relatively small, the delay time required for the process of generating the scanning signal from the transferred signal can be shortened.
【0021】
By the way, in the drive circuit of the first electro-optical device, in another aspect, the drive circuit is formed on both sides of the formation region of the pixel electrode, and is formed on one of the two sides. The drive circuit formed outputs a scan signal to the odd-th scan line among the plurality of scan lines, and the drive circuit formed on the other side outputs a scan signal to the even-th scan line. .. According to this aspect, since one of the divided drive circuits supplies scanning signals to the odd-numbered scanning lines and the other supplies scanning signals to the even-numbered scanning lines, the circuit pitch of the shift register is doubled. Therefore, the pitch of the scanning line can be further miniaturized in combination with the expansion of the circuit pitch of the shift register according to the number of divisions in the output means.
【0022】
The above object is also achieved by the electro-optical device driven by the drive circuit of the first electro-optic device described above. According to this electro-optical device, in particular, the pitch of scanning lines can be miniaturized by a relatively simple circuit configuration. Examples of the electro-optical device include those using various electro-optical materials between substrates such as a liquid crystal device and an EL (Electro Luminescence) device.
【0023】
Next, in order to achieve the above object, the drive circuit of the second electro-optical device in the present invention includes a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the switching element. A drive circuit of an electro-optical device that drives a pixel composed of pixel electrodes connected to the data line, a shift register composed of a unit circuit having a number of stages smaller than the number of data lines, and based on a clock signal having a predetermined period. A shift register that sequentially outputs transfer signals from the unit circuits of each stage, an output means that divides the transfer signals output from the unit circuits of each stage into a plurality of units on the time axis, and outputs them as sampling control signals. Each of the data lines is provided with a sampling switch that samples an image signal according to a sampling control signal divided by the output means and supplies the image signal to the corresponding data line. There is.
【0024】
In the drive circuit of the second electro-optic device in the present invention, first, the transfer signal is sequentially output by the unit circuit of each stage constituting the shift register. Then, this transfer signal is divided into a plurality of pieces on the time axis by the output means, and is sequentially output to the sampling switch as a sampling control signal. Therefore, in order to reduce the pixel pitch, the circuit pitch of the shift register can be expanded with respect to the pitch of the data line according to the number of divisions in the output means.
【0025】
For example, conventionally, if the total number of data lines is p (p is an integer of 2 or more), the unit circuit constituting the shift register requires at least the same number of p stages. On the other hand, in the present invention, assuming that the number of divisions in the output means is q (q is an integer of 2 or more), the unit circuit constituting the shift register can be in p / q stages, so that it is compared with the conventional one. , Reduced to 1 / q. Therefore, the circuit pitch of the X-side shift register can be expanded q times. Further, in the present invention, since the drive frequency in the shift register is reduced according to the number of divisions q, it is possible to suppress the power consumed accordingly. This effect is more pronounced in data line drive circuits with much higher operating frequencies than in scan line drive circuits. On the other hand, as for the output means, since it is sufficient to have a configuration in which the transfer signal is divided on the time axis, the configuration is simplified as compared with the unit circuit of the shift register. Therefore, the circuit pitch in the X direction required to form the output means can be easily configured to be narrower than the circuit pitch of the shift register.
【0026】
By the way, in the drive circuit of the second electro-optical device, in one aspect, the output means is provided corresponding to the unit circuit, and each is a transfer output from the corresponding unit circuit. A branch wiring that branches a signal into a plurality of lines and a branch wiring that corresponds to the branching by the branch wiring are provided, and each is a sampling control signal that samples a transfer signal branched by the branch wiring and a logical product signal of a predetermined enable signal. The enable circuits to which the transfer signal branched by the same branch wiring is supplied are provided with the enable circuit to output as, and the enable signals whose active periods do not overlap each other are individually supplied. According to this aspect, each transfer signal output from the shift register is branched by a plurality of branch wirings. Then, the AND signal of the branched transfer signal and the clock signal for enabling is obtained by the enable circuit and supplied to the corresponding sampling switch as a sampling control signal. Therefore, since the output means can be realized by a relatively simple circuit configuration of a branch wiring and an enable circuit, the circuit pitch in the output means is easily narrowed. Therefore, the situation that becomes a bottleneck when the circuit pitch is miniaturized can be avoided.
【0027】
Here, in one embodiment in which the output means includes an enable circuit, each of the enable circuits is connected in series with a NAND gate that inputs the transfer signal and the predetermined enable signal, and an inverter that inverts the output. It is composed. With this configuration, the NAND gate and the inverter can be connected in series, so that the logical product signal of each branched transfer signal and the enable signal can be output reliably and accurately. Further, since the NAND gate and the inverter are simpler circuits than the circuit portions constituting each stage of the shift register, the circuit pitch of the enable circuit can be narrowed relatively easily.
【0028】
On the other hand, in another aspect in which the output means includes an enable circuit, each of the enable circuits is a transmission gate that outputs the sampling control signal when the transfer signal is input and the predetermined enable signal is input. The configuration may be. With this configuration, the transmission gate is a relatively simple circuit, so that the circuit pitch of the enable circuit can be narrowed relatively easily, and it is required for the process of generating the sampling control signal from the transfer signal. The delay time can be short.
【0029】
The above object is also achieved by the electro-optical device driven by the drive circuit of the second electro-optic device described above. According to this electro-optical device, in particular, the pitch of the data line can be miniaturized by a relatively simple circuit configuration. Examples of the electro-optical device include a liquid crystal device, an EL device, and the like in which various electro-optical materials are used between the substrates.
【0030】
Next, in order to achieve the above object, the drive circuit of the third electro-optical device in the present invention includes a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the switching element. It is a drive circuit of an electro-optical device that has pixel electrodes connected to and simultaneously samples serial-parallel converted image signals for each predetermined number of data lines, and is a data line in which image signals are sampled at the same time. A shift register consisting of a unit circuit having a number of stages less than the number of the above, and a shift register that sequentially outputs a transfer signal from the unit circuit of each stage based on a clock signal of a predetermined cycle, and a shift register that is output from the unit circuit of each stage. An output means for dividing the transferred signal into a plurality of data on the time axis and outputting the signal as a sampling control signal and a data line corresponding to each of the data lines are provided, and each of the transfer signals of the image signal is provided according to the sampling control signal. A sampling switch that samples one of them and supplies it to the corresponding data line, which is provided corresponding to a plurality of adjacent data lines, is an image signal that is different at the same time due to the same sampling control signal. It is characterized by having a sampling switch for sampling the data.
【0031】
In the drive circuit of the third electro-optic device in the present invention, first, the transfer signal is sequentially output by the unit circuit of each stage in the shift register. Then, this transfer signal is divided into a plurality of pieces on the time axis by the output means, and is sequentially output to the sampling switch as a sampling control signal. At this time, the sampling switches provided corresponding to a plurality of adjacent data lines simultaneously sample different image signals by the same sampling control signal. Therefore, in order to miniaturize the pixel pitch, the circuit pitch of the shift register can be expanded with respect to the pitch of the data line according to the number of divisions in the output means and the number of sampling switches driven at the same time. It will be possible.
【0032】
For example, conventionally, if the total number of data lines is p (p is an integer of 2 or more), the unit circuit constituting the shift register requires at least the same number of p stages. On the other hand, in the present invention, assuming that the number of divisions in the output means is q (q is an integer of 2 or more) and the number of sampling switches driven at the same time is r (r is an integer of 2 or more), the shift is performed. Since the unit circuit constituting the register requires only p / (q × r) stages, it is reduced to 1 / (q × r) as compared with the conventional case. Therefore, the circuit pitch of the X-side shift register can be expanded by q × r times. Further, in the present invention, the drive frequency in the shift register is reduced according to the number of divisions and the number of sampling switches driven at the same time, so that the power consumed accordingly can be suppressed and the life of the circuit can be shortened. It is also possible to extend it. This effect is more pronounced in data line drive circuits with much higher operating frequencies than in scan line drive circuits. On the other hand, as for the output means, since it is sufficient to have a configuration in which the transfer signal is divided on the time axis, the configuration is simplified as compared with the unit circuit of the shift register. Therefore, the circuit pitch in the X direction required to form the output means can be easily configured to be narrower than the circuit pitch of the shift register.
【0033】
By the way, in the drive circuit of the third electro-optical device, in one aspect, the output means is provided corresponding to the unit circuit, and each is a transfer output from the corresponding unit circuit. A branch wiring that branches a signal into a plurality of lines and a branch wiring that corresponds to the branching by the branch wiring are provided, and each is a sampling control signal that samples a transfer signal branched by the branch wiring and a logical product signal of a predetermined enable signal. The enable circuits to which the transfer signal branched by the same branch wiring is supplied are provided with the enable circuit to output as, and the enable signals whose active periods do not overlap each other are individually supplied. According to this aspect, each transfer signal output from the shift register is branched by a plurality of branch wirings. Then, the AND signal of the branched transfer signal and the clock signal for enable is obtained by the enable circuit and supplied as a sampling control signal to the corresponding plurality of sampling switches. Therefore, since the output means can be realized by a relatively simple circuit configuration of a branch wiring and an enable circuit, the circuit pitch in the output means is easily narrowed. Therefore, the circuit pitch bottle when refining situation where the Runekku becomes to be avoided.
【0034】
Here, in one embodiment in which the output means includes an enable circuit, each of the enable circuits is connected in series with a NAND gate that inputs the transfer signal and the predetermined enable signal, and an inverter that inverts the output. It is composed. With this configuration, the NAND gate and the inverter can be connected in series, so that the logical product signal of each branched transfer signal and the enable signal can be output reliably and accurately. Further, since the NAND gate and the inverter are simpler circuits than the circuit portions constituting each stage of the shift register, the circuit pitch of the enable circuit can be narrowed relatively easily.
【0035】
On the other hand, in another aspect in which the output means includes an enable circuit, each of the enable circuits is a transmission gate that outputs the sampling control signal when the transfer signal is input and the predetermined enable signal is input. The configuration may be. With this configuration, the transmission gate is a relatively simple circuit, so that the circuit pitch of the enable circuit can be narrowed relatively easily, and it is required for the process of generating the sampling control signal from the transfer signal. The delay time can be short.
【0036】
The above object is also achieved by the electro-optical device driven by the drive circuit of the third electro-optic device described above. According to this electro-optical device, in particular, the pitch of the data line can be miniaturized by a relatively simple circuit configuration. Examples of the electro-optical device include a liquid crystal device, an EL device, and the like in which various electro-optical materials are used between the substrates.
【0037】
Next, in order to achieve the above object, the drive circuit of the fourth electro-optical device in the present invention includes a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the switching element. It is a drive circuit of an electro-optical device that drives a pixel composed of pixel electrodes connected to the above, and is a shift register composed of a unit circuit having a number of stages smaller than the number of data lines, and is based on a clock signal having a predetermined period. The shift register that sequentially outputs the transfer signal from the unit circuit of each stage and the transfer signal output from the unit circuit of each stage are divided into a plurality of units on the time axis, or are simultaneously distributed into a plurality of sampling control signals. The output means is provided corresponding to each of the data lines, and each is supplied to any one of a plurality of image signal lines according to the transfer signal divided or distributed by the output means. It is characterized by including a sampling switch that samples the generated image signal and supplies it to the corresponding data line.
【0038】
In the drive circuit of the fourth electro-optic device in the present invention, first, the transfer signal is sequentially output by the unit circuit of each stage in the shift register. Then, this transfer signal is divided into a plurality of parts on the time axis by the output means, or is simultaneously distributed into a plurality of parts and output as a sampling control signal. At this time, if the output means divides the transfer signal into a plurality of data on the time axis, the sampling switch samples each one in turn, while if the transfer signal is distributed at the same time, it corresponds to a plurality of adjacent data lines. The sampling switches provided in this way perform sampling at the same time. Therefore, the so-called sequential drive and the so-called simultaneous drive of a plurality of lines can be switched and used by the output means. Further, in the present invention, the circuit pitch of the shift register can be expanded with respect to the pitch of the data line according to the number of divisions in the output means. In addition, in the present invention, it is possible to reduce the drive frequency in the shift register to the reciprocal of the number of divisions in the output means. On the other hand, as for the output means, it is sufficient that the transfer signal is divided on the time axis or distributed at the same time, so that the configuration is simplified as compared with the unit circuit of the shift register. Therefore, the circuit pitch in the X direction required to form the output means can be easily configured to be narrower than the circuit pitch of the shift register.
【0039】
Here, in the drive circuit of the fourth electro-optical device, in one embodiment, when the output means divides the transfer signal into a plurality of pieces on the time axis, the plurality of image signal lines may be used. When the same image signal is supplied and each of the sampling switches sequentially samples the image signal, while the output means simultaneously distributes the transfer signal to a plurality of the same image signals, the plurality of image signal lines may have 1 The image signal of the system is extended and distributed multiple times on the time axis, and among the sampling switches, a plurality of the sampling switches provided corresponding to a plurality of adjacent data lines simultaneously transmit the image signal. It is configured to sample. In this configuration, when the transfer signal is divided into a plurality of pieces on the time axis, the same image signal is supplied to the plurality of image signal lines, so that the transfer signal can be driven sequentially, while the transfer signal is simultaneously distributed to the plurality of pieces. In this case, since each of the plurality of image signal lines is supplied with an image signal in which one system of image signals is extended and distributed by a plurality of times on the time axis, a plurality of image signals can be driven simultaneously.
【0040】
Further, in the drive circuit of the fourth electro-optical device, in another aspect, the output means is provided corresponding to the unit circuit, and each is a transfer output by the corresponding unit circuit. A branch wiring that branches a signal into a plurality of wires and a branch wiring that corresponds to the branching by the branch wiring are provided, and each is a sampling control signal that samples a transfer signal branched by the branch wiring and a logical product signal of a predetermined enable signal. When the transfer signal is divided into a plurality of pieces on the time axis, the enable circuits to which the transfer signal branched by the same branch wiring is supplied have a period during which the transfer signal is supplied. When the enable signals whose active periods do not overlap each other are individually supplied in the above, and the transfer signals are distributed to a plurality of transfer signals at the same time, the transfer signals are supplied between the enable circuits to which the transfer signals branched by the same branch wiring are supplied. Enable signals with the same active period are supplied individually for the period in which they are supplied. According to this aspect, each transfer signal output from the shift register is branched by a plurality of branch wirings. Then, the AND signal of the branched transfer signal and the clock signal for enabling is obtained by the enable circuit and supplied to the corresponding sampling switch as a sampling control signal. Therefore, since the output means can be realized by a relatively simple circuit configuration of a branch wiring and an enable circuit, the circuit pitch in the output means is easily narrowed. Therefore, the situation that becomes a bottleneck when the circuit pitch is miniaturized can be avoided.
【0041】
Here, in one embodiment in which the output means includes an enable circuit, each of the enable circuits is connected in series with a NAND gate that inputs the transfer signal and the predetermined enable signal, and an inverter that inverts the output. It is composed. With this configuration, the NAND gate and the inverter can be connected in series, so that the logical product signal of each branched transfer signal and the enable signal can be output reliably and accurately. Further, since the NAND gate and the inverter are simpler than the unit circuit constituting each stage of the shift register, the circuit pitch of the enable circuit can be narrowed relatively easily.
【0042】
On the other hand, in another aspect in which the output means includes an enable circuit, each of the enable circuits controls the sampling when the transfer signal branched by the branch wiring is input and the predetermined enable signal is input. It may be configured as a transmission gate that outputs a signal. With this configuration, the transmission gate is a relatively simple circuit, so that the circuit pitch of the enable circuit can be narrowed relatively easily, and it is required for the process of generating the sampling control signal from the transfer signal. The delay time can be short.
【0043】
The above object is also achieved by the electro-optical device driven by the drive circuit of the fourth electro-optic device described above. According to this electro-optical device, in particular, the pitch of the data line can be miniaturized by a relatively simple circuit configuration. Examples of the electro-optical device include a liquid crystal device, an EL device, and the like in which various electro-optical materials are used between the substrates.
【0044】
In such an electro-optical device, in one aspect, in the output means, a determination means for determining whether to divide the transfer signal into a plurality of pieces on the time axis or to simultaneously distribute the transfer signal to a plurality of pieces, and transfer. When it is determined that the signal is divided into a plurality of signals on the time axis, the active period is the period during which the transfer signal is supplied to the enable circuits to which the transfer signal branched by the same branch wiring is supplied. When it is determined that the enable signals that do not overlap each other are individually supplied and the transfer signals are distributed to a plurality of signals at the same time, the transfer is transferred to the enable circuits to which the transfer signals branched by the same branch wiring are supplied. A supply means for individually supplying an enable signal having the same active period in the period in which the signal is supplied is provided. According to this aspect, it is determined by the determination means whether to drive sequentially or by a plurality of simultaneous drives, and the enable signal required for the determined drive is supplied to the enable circuit by the supply means.
【0045】
In one embodiment including the determination means and the supply means as described above, the determination means makes the determination based on the type of the input image signal. For example, if the image signal is a video signal such as NTSC, PAL, or SECAM, the determination means determines that the transfer signal is divided into a plurality of signals on the time axis, thereby sequentially driving the image signal. If is a data system signal such as a personal computer, it is determined that the transfer signal is distributed to a plurality of signals at the same time, and a plurality of signals are simultaneously driven.
【0046】
Further, in another aspect including the determination means and the supply means, the motion detection means for detecting the motion in the input image signal and outputting the detection signal is further provided, and the determination means is based on the detection signal. If it is determined that there is the movement within the preset time, it is determined that the transfer signal is divided into a plurality of parts on the time axis, while if it is determined that there is no such movement within the time, the transfer signal is determined. Is determined to be distributed to a plurality of devices at the same time. In this aspect, it is possible to drive each data line by switching between sequential driving and simultaneous driving of a plurality of lines according to the movement of the image signal. In other words, images with a lot of movement are driven sequentially without image unevenness, while images with no movement (or less) are driven simultaneously with multiple images capable of high-resolution display, which is optimal for the characteristics of the image to be displayed. It is possible to output an image by selecting a different drive method.
【0047】
Next, in order to achieve the above object, the drive circuit of the fifth electro-optical device in the present invention includes a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the switching element. It is a drive circuit of an electro-optical device that drives a pixel composed of pixel electrodes connected to the above, and is a shift register composed of a unit circuit having a number of stages smaller than the number of data lines, and is based on a clock signal having a predetermined period. A shift register that sequentially outputs transfer signals from the unit circuits of each stage, a first output means that divides the transfer signals output from the unit circuits of each stage into a plurality of units on the time axis, and the first output means. The transfer signal divided by the output means is further divided into a plurality of pieces on the time axis, or is simultaneously divided into a plurality of pieces and output as a sampling control signal. Each of the provided data is obtained by sampling an image signal supplied to any one of a plurality of image signal lines according to a transfer signal divided or distributed by the second output means, and corresponding data. It is characterized by having a sampling switch that supplies the wire.
【0048】
In the drive circuit of the fifth electro-optic device in the present invention, first, the transfer signal is sequentially output by the unit circuit of each stage in the shift register. Then, this transfer signal is divided into a plurality of pieces on the time axis by the first output means. Further, the divided transfer signal is divided into a plurality of parts or simultaneously distributed by the second output means on the time axis, and is output as a sampling control signal. Therefore, in order to miniaturize the pixel pitch, the circuit pitch of the shift register is expanded with respect to the pitch of the data line according to the number of divisions in the first output means and the number of divisions in the second output means. It becomes possible.
【0049】
For example, conventionally, if the total number of data lines is p (p is an integer of 2 or more), the unit circuit constituting the shift register requires at least the same number of p stages. On the other hand, in the present invention, the number of divisions in the first output means is q (q is an integer of 2 or more), and the number of divisions in the second output means is s (s is an integer of 2 or more). Then, since the unit circuit constituting the shift register requires only p / (q × s) stages, it is reduced to 1 / (q × s) as compared with the conventional case. Therefore, the circuit pitch of the X-side shift register can be expanded by q × s times. Further, in the present invention, it is possible to reduce the drive frequency in the shift register according to the product of the number of divisions. This effect is more pronounced in data line drive circuits with much higher operating frequencies than in scan line drive circuits.
【0050】
On the other hand, for the first output means, it is sufficient if the transfer signal is divided on the time axis, and for the second output means, the transfer signal is divided or simultaneously distributed on the time axis. Since all that is required, their configuration is simplified compared to the unit circuit of the shift register. Therefore, the circuit pitch in the X direction required to form the first and second output means should be configured to be narrower than the circuit pitch of the shift register, especially for the latter corresponding to the scanning line. Becomes easier.
【0051】
Further, in the present invention, when the second output means divides the transfer signal into a plurality of pieces on the time axis, the sampling switches sample each one in turn, and when the transfer signals are distributed at the same time, they are adjacent to each other. A plurality of sampling switches provided corresponding to a plurality of data lines to be used perform sampling at the same time. Therefore, the so-called sequential drive and the so-called simultaneous drive of a plurality of lines can be switched and used by the second output means.
【0052】
By the way, in the drive circuit of the fifth electro-optical device, in one aspect, the first output means is provided corresponding to the unit circuit, and each is output by the corresponding unit circuit. It is provided corresponding to the first branch wiring for branching the transfer signal into a plurality of lines and the branch by the first branch wiring, and each of the transfer signal branched by the first branch wiring and the first The transfer signal is provided between the first enable circuits that are provided with the first enable circuit that outputs a logical product signal with the enable signal of the group and the transfer signal branched by the same first branch wiring is supplied. The first group of enable signals whose active periods do not overlap each other are individually supplied, and the second output means is provided corresponding to the first enable circuit, and each corresponds to the first enable circuit. A second branch wiring that branches the transfer signal divided by the first enable circuit to a plurality of lines and a branch wiring by the second branch wiring are provided, and each is provided by the second branch wiring. When a second enable circuit that outputs a logical product signal of the branched transfer signal and the second group enable signal as a sampling control signal is provided and the transfer signal is divided into a plurality of pieces on the time axis, the same first is provided. In the second enable circuits to which the transfer signal branched by the branch wiring of 2 is supplied, the enable signals of the second group in which the active periods do not overlap each other during the period in which the transfer signal is supplied are individually supplied. On the other hand, when the transfer signal is distributed to a plurality of devices at the same time, the active period is the period during which the transfer signal is supplied between the second enable circuits to which the transfer signal branched by the same second branch wiring is supplied. The same second group of enable signals are supplied separately. According to this aspect, the transfer signal output from the shift register is first branched by a plurality of branch wirings for each of the first branch wirings, and the logical product signal of the transfer signal and the enable signal of the first group is generated. Obtained by the first enable circuit. Further, the AND signal is branched by a plurality of branch wirings for each of the second branch wirings, and the logical product signal is branched. The AND signal of the AND signal and the second group enable signal is obtained by the second enable circuit and supplied to the corresponding sampling switch as a sampling control signal. Therefore, the first output means has a relatively simple circuit configuration of a first branch wiring and a first enable circuit, and similarly, the second output means has a second branch wiring and a second enable. Since each can be realized by a relatively simple circuit configuration called a circuit, the circuit pitch in the first and second output means is easily narrowed. Therefore, a situation that becomes a bottleneck when these circuit pitches are miniaturized can be avoided.
【0053】
The above object is also achieved by the electro-optical device driven by the drive circuit of the fifth electro-optic device described above. According to this electro-optical device, in particular, the pitch of the data line can be miniaturized by a relatively simple circuit configuration. Examples of the electro-optical device include a liquid crystal device, an EL device, and the like in which various electro-optical materials are used between the substrates.
【0054】
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the embodiment described below, an active matrix type liquid crystal device driven by a TFT, which is a liquid crystal device using a liquid crystal as an electro-optical material, will be described as an example of the electro-optical device. The purpose is not to limit the invention to this.
【0055】
(First Embodiment) First, the first embodiment will be described. FIG. 1 is a block diagram showing an overall configuration of an electro-optical device provided with a drive circuit according to the present embodiment on a substrate. In this figure, the liquid crystal device 200 includes a liquid crystal display unit 1a, a data line drive circuit 101, a scanning line drive circuit 104, a sampling circuit 301, and the like.
【0056】
Of these, the data line drive circuit 101, the scanning line drive circuit 104, and the sampling circuit 301 are regions on the TFT array substrate 10 made of, for example, a quartz substrate, hard glass, or a silicon substrate, and are displayed on a liquid crystal display. It is provided in the peripheral area of part 1a. On the other hand, in the liquid crystal display unit 1a on the TFT array substrate 10, a plurality of data lines 35 are formed in parallel along the Y direction in the figure, while a plurality of scanning lines 31 are formed in the X direction in the figure. Along with being formed along, pixel electrodes 11 are formed corresponding to the intersections of the data line 35 and the scanning line 31, respectively. Therefore, the pixel electrodes 11 are arranged in a matrix with respect to the X direction and the Y direction. Here, a TFT 30 is connected to each of the pixel electrodes 11, and the conductive state or the non-conducting state between the pixel electrode 11 and the data line 35 is controlled according to the scanning signal supplied via the scanning line 31. It is configured to be. Further, on the TFT array substrate 10, a capacitance line (storage capacity electrode) 32 is formed parallel to the scanning line 31, and the capacitance line 32 accumulates the voltage applied to the pixel electrode 11 for a long period of time. Storage capacity is configured.
【0057】
The data line drive circuit 101, which is the drive circuit on the data line 35 side (X side), sequentially generates sampling control signals based on the clock signal CLX (and its inverted clock CLX'), which is the reference clock signal on the X side. Then, it is output to each of the sampling control signal lines 306.
【0058】
Next, the sampling circuit 301 includes sampling switches 302 provided for each data line 35. Here, one end of each sampling switch 302 is connected to the corresponding data line 35, while the other end is commonly connected to the image signal line 400, and both ends thereof are supplied via the corresponding sampling control signal line 306. It is configured to be closed by the sampling control signal. Therefore, as will be described later, when the sampling control signals are sequentially and exclusively supplied to each of the sampling control signal lines 306, each sampling switch 302 sequentially samples the image signal Vi supplied to the image signal line 401. As a result, the image signal Vi is sequentially applied to each of the data lines 35.
【0059】
On the other hand, the scanning line driving circuit 104, which is the driving circuit on the scanning line 31 side (Y side), sequentially generates scanning signals based on the clock signal CLY (and its inverted clock CLY'), which is the reference clock signal on the Y side. Therefore, it is output to each of the scanning lines 31.
【0060】
(Scanning Line Drive Circuit) Here, the details of the scanning line driving circuit 104 described above will be described. FIG. 2 is a block diagram showing the configuration of the scanning line drive circuit 104. In this figure, the shift register 500 has a configuration in which the unit circuits LY1, LY2, ... That operate according to the clock signal CLY and its inverted clock signal CLY'are vertically connected in a plurality of stages. Here, the clock signal CLY is a signal supplied from an external image signal processing circuit, and its frequency coincides with the horizontal scanning frequency. Further, the inverted clock signal CLY'is a signal whose level is inverted from the clock signal CLY, and is similarly supplied from an external image signal processing circuit. Further, the unit circuit LY1 in the first stage has a configuration in which the start pulse DY is supplied from the external image signal processing circuit at the beginning of the vertical scanning period, but the other unit circuits are in the previous stage (in FIG. 2). It is configured to input the transfer signal by the unit circuit of (upper side).
【0061】
Of the unit circuits, the odd-numbered unit circuits LY1, LY3, ... Counting from the top take in and output the input signal at the rising edge of the clock signal CLY, while the even-numbered unit circuits LY2, LY4, ... Takes in and outputs an input signal at the rising edge of the inverted clock signal CLY'.
【0062】
Therefore, the output signals A1p, A2p, ... of each unit circuit LY1, LY2, ... Are as shown in FIG. 3, respectively. That is, the output signal A1p of the unit circuit LY1 of the first stage captures the start pulse DY at the rising edge of the clock signal CLY, and the output signals A2p, A3p, A4p, of the following unit circuits LY2, LY3, LY4, ... ... is a signal in which the output signal A1p is sequentially delayed by half a cycle of the clock signal CLY (inverted clock signal CLY').
【0063】
In FIG. 2, each unit circuit includes a clocked inverter 501a that inverts the input signal, an inverter 501b that re-inverts the inverted signal, and a clocked inverter 501c that feeds back the re-inverted signal to the input of the inverter 501b. It is composed of and. Then, the clocked inverter 501a in the unit circuit of the odd-stage inverts the input signal when the clock signal CLY is H level (the inverted clock signal CLY'is L level), and is clocked in the unit circuit of the same stage. The inverter 501c inverts the input signal when the clock signal CLY is L level (inverted clock signal CLY'is H level). On the other hand, in the clocked inverters 501a and 501c of the even-numbered unit circuit, the relationship of the clock signal that inverts the input signal is replaced with that of the odd-numbered stage.
【0064】
Regarding the specific configuration of such clocked inverters 501a and 501c, when the notation in FIG. 2 is generalized as shown in FIG. 4 (a), the configuration is as shown in FIG. 4 (b). It becomes. That is, as shown in FIG. 4 (a), the notation in which the clock signal CLY is supplied is the gate electrode between the high-level power supply VDD and the low-level power supply VSS as shown in FIG. 4 (b). A P-channel TFT that inputs the inverted clock signal CLY'to the gate electrode, a complementary P-channel TFT / N-channel TFT that inputs the input signal to the gate electrode, and an N-channel TFT that inputs the clock signal CLY to the gate electrode. The configuration connected in series is shown. On the other hand, as shown in the parentheses in FIG. 4 (a), the notation in which the inverted clock signal CLY'is supplied is the clock signal CLY and the inverted clock signal CLY as shown in the parentheses in FIG. 4 (b). 'Is replaced with the configuration.
【0065】
Returning to FIG. 2 again, the NAND gate G1 and the inverter G2 are connected in series on the output side of each unit circuit LY1, LY2, .... Of these, one NAND gate G1 outputs a negative logical product signal of the transfer signal by the corresponding unit circuit and the transfer signal by the unit circuit in the subsequent stage (lower side in FIG. 2), and is located on this output side. The inverter G2 inverts and outputs the negative AND signal.
【0066】
Therefore, the transfer signals A1, A2, ... Output from the inverter G2 of each stage are as shown in FIG. 3, respectively. That is, the transfer signals A1, A2, ... Are H level in the overlapping period of the transfer signal by the corresponding unit circuit and the transfer signal by the unit circuit in the subsequent stage, so that they are H level exclusively and in order. You can see that it will be a level.
【0067】
Returning to FIG. 2 again, the transfer signals A1, A2, ... Output from the inverter G2 in each stage are branched into a plurality of systems (3 in this embodiment). Each system is provided with an enable circuit 502 including a NAND gate 503 and an inverter 504 connected in series. This enable circuit 502 is provided corresponding to one of the scanning lines 31 (see FIG. 1), and this output signal is supplied to the corresponding scanning line 31 as a scanning signal.
【0068】
Here, in the NAND gate 503 constituting the enable circuit 502, a branched transfer signal is supplied to one of the input ends, and any of the enable signals ENB1y, ENB2y, or ENB3y is supplied to the other end. Has been done. Specifically, at the other end of the j-th NAND gate 503 counting from the top in the figure, if the remainder of j divided by 3 is 1, the enable signal ENB1y is set, and if j is divided by 3, the remainder is 2. If the enable signal ENB2y is supplied, and if the remainder obtained by dividing j by 3 is 0, the enable signal ENB3y is supplied.
【0069】
These enable signals ENB1y, ENB2y, and ENB3y are supplied from, for example, an external image signal processing circuit, and are signals having waveforms as shown in FIG. 3, respectively. That is, the enable signals ENB1y, ENB2y, and ENB3y are signals having twice the frequency of the clock signal CLY (inverted clock signal CLY'), and their pulse width is that of the clock signal CLY (inverted clock signal CLY'). It is a signal that is about 1/3 and whose pulse width periods are sequentially shifted without overlapping each other.
【0070】
Therefore, the scanning signals Y1, Y2, ... Output from each enable circuit 502 are as shown in FIG. That is, first, the transfer signal A1 is sequentially divided into three on the time axis by the enable signals ENB1y, ENB2y, and ENB3y to become scanning signals Y1, Y2, and Y3, and then the transfer signal A2 becomes the enable signal ENB1y, Similarly, ENB2y and ENB3y sequentially divide the signal into three on the time axis to obtain scanning signals Y4, Y5, and Y6, and the same division is repeated thereafter.
【0071】
As a result, the scanning signals Y1, Y2, Y3, ... Are output in order and exclusive to each other in one vertical scanning period, so that the scanning lines 31 are selected one by one in order from the top, and this All TFTs 30 connected to scan line 31 will be turned on.
【0072】
Since such a scanning line drive circuit 104 generates a scanning signal by sequentially dividing the transfer signals A1, A2, A3, ... Based on the unit circuit of the shift register 500 into three on the time axis, respectively. The number of stages of the unit circuit is only 1/3, which is the inverse of the number of divisions of the transfer signal, as compared with the total number of scanning lines 31. Therefore, on the Y side, it is sufficient to form the unit circuit constituting the shift register 500 at a pitch three times that of the scanning line 31.
【0073】
On the other hand, an enable circuit 502 is required for each scanning line 31, but since the enable circuit 502 itself can be connected in series with the NAND gate 503 and the inverter 504, the enable circuit 502 should be formed at a narrow pitch. Is easy. For example, when the limit of the Y-direction pitch of the unit circuit in the shift register 500 is, for example, about 23 μm, when the NAND gate 503 and the inverter 504 are formed by applying the same miniaturization technique, the Y in the enable circuit 502 The directional pitch can be narrowed to about 15 to 18 μm.
【0074】
Therefore, according to the scanning line drive circuit 104, the Y-direction pitch of the unit circuit constituting the shift register 500 does not become a bottleneck in miniaturizing the scanning line pitch. Therefore, the pitch of the scanning line can be made narrower than the pitch limit in the Y direction of the unit circuit.
【0075】
Moreover, since the operating frequency of the shift register 500 is reduced to 1/3, which is the reciprocal of the number of divisions of the transfer signal in the enable circuit 502, the clocked inverters 501a, 501c, and the inverter 501b, which are the constituent elements of the shift register 500, are used. , Not so good characteristics are required. Therefore, in the shift register 500, the specifications such as the circuit accuracy, the circuit scale, the wiring resistance, the time constant, the capacitance, and the delay time are relaxed.
【0076】
In FIG. 2, the transfer signals A1, A2, ... Are divided into three, but the present invention is not limited to this, and the transfer signals A1, A2, ... May be divided into two or four or more. However, when the number of divisions is small, the pitch of the scanning lines tends to depend on the pitch in the Y direction in the unit circuit. On the other hand, in the present embodiment, the pitch of the scanning lines cannot be narrower than the limit of the pitch in the Y direction in the enable circuit 502. Therefore, even if the number of divisions is increased unnecessarily, the number of signal lines for supplying the enable signal increases. It only complicates the wiring process. Therefore, in practice, it is desirable to set the number of divisions of the transfer signal in consideration of various circumstances.
【0077】
(Other Examples of Enable Circuits) The enable circuit 502 shown in FIG. 2 is composed of a NAND gate 503 and an inverter 504 connected in series, but in the present invention, various forms other than this can be used. Is. Therefore, next, another configuration example of the enable circuit will be described.
【0078】
First, in the enable circuit 502b shown in FIG. 5A, the series connection of the NAND gate 503 and the inverter 504 is replaced with the transmission gate 505. That is, the transmission gate 505 divides the branched transfer signal according to any one of the enable signals ENB1y, ENB2y, and ENB3y and supplies the branched transfer signal as a scanning signal. Therefore, the transmission gate 505 is also provided corresponding to one of the scanning lines 31 as in the case of the series connection.
【0079】
Here, when the transmission gate 505 adopts, for example, a configuration in which the P-channel TFT and the N-channel TFT are complementarily connected as shown in FIG. 5 (b), both TFTs have a level-reversed relationship with each other. It is necessary to supply two transfer signals. Therefore, for example, in addition to the branched transfer signal A1, the inverting transfer signal A1'is supplied to the first to third transmission gates 505 counting from the top. The same applies to the transmission gate 505 to which the transfer signals A2, A3, ... Are supplied.
【0080】
Note that FIG. 5B is a diagram showing the configuration of the j-th transmission gate 505 counting from the top. The transfer signal and enable signal supplied to the transmission gate 505 are the same as in the case of the NAND gate 503 (see FIG. 2).
【0081】
When the enable circuit 502b is configured by the transmission gate 505 provided for each scanning line 31 in this way, the constituent elements of the transmission gate 505 need only two TFTs, so that the Y-direction pitch of the enable circuit 502b is sufficient. Can be further narrowed. For example, if the Y-direction pitch of the enable circuit 502 shown in FIG. 2 is about 18 μm, the Y-direction pitch of the enable circuit 502b using the transmission gate 505 is further narrowed to about 12 to 16 μm. In addition, since the transmission gate 505 has two constituent elements, it is advantageous because the delay time required for the process of generating the scanning signal from the branched transfer signal in the enable circuit 502b can be shortened.
【0082】
In the enable circuit 502b, instead of the transmission gate 505 shown in FIG. 5 (b), an N-channel TFT as shown in FIG. 5 (c), that is, an N-channel TFT 507 that opens and closes according to a transfer signal. Or a P-channel TFT that opens and closes according to an inverting transfer signal may be used. That is, the enable circuit may be configured by using a TFT of either N or P type channel type instead of complementary. In this way, when the enable circuit is configured by the TFT of either channel type, the number of constituent elements is further reduced (1), and the transfer signal of one system can be supplied to the gate of the TFT. The Y-direction pitch of the enable circuit can be further narrowed. Further, the delay time required for the process of generating the scanning signal from the branched transfer signal is further shortened, which is also advantageous in this respect.
【0083】
(Arrangement of Enable Circuit) Next, the arrangement of the enable circuit will be described. In the enable circuits shown in FIGS. 2 and 5 (a), they are arranged so as to be aligned in the Y direction, but in reality, such an arrangement is aimed at narrowing the pitch in the Y direction. Is unsuitable. Therefore, a practical arrangement that is as advantageous as possible for narrowing the pitch in the Y direction will be described.
【0084】
First, in the example shown in FIG. 6A, the enable circuits 502c are sequentially shifted in the X direction at a certain distance from each other. Specifically, the j-th enable circuit 502c counted from the top is arranged on the leftmost side in the figure if the remainder of dividing j by 3 is 1, and if the remainder of dividing j by 3 is 0, in the figure. It is placed on the far right side, and if the remainder of dividing j by 3 is 2, it is placed between the two in the figure. In this way, the enable circuits 502c that are adjacent to each other are arranged at different positions in the X direction. Therefore, as compared with the configuration in which the enable circuits 502 shown in FIG. 2 are arranged in the same row in the Y direction, The NAND gate 503 and the inverter 504 that make up each enable circuit 502c can be formed with a wider width in the Y direction. Therefore, the circuit pitch of the enable circuit 502c can be further narrowed, and the scanning line pitch can be miniaturized.
【0085】
Next, in the example shown in FIG. 6B, the enable circuits 502d are arranged alternately (alternately) shifted in the X direction at a certain distance from each other. Even with such an arrangement, the NAND gate 503 and the inverter 504 can be formed wider in the Y direction as compared with the configuration in which the enable circuits 502 shown in FIG. 2 are arranged in the Y direction. ..
【0086】
Although the enable circuit 502c or 502d has been described here as being composed of the NAND gate 503 and the inverter 504 connected in series in FIG. 6A or FIG. 6B, the transmission gate described above has been described. Of course, a configuration substituted with 505 or 507 may be used.
【0087】
(Data Line Drive Circuit) Next, the details of the data line drive circuit 101 of the liquid crystal device in FIG. 1 will be described. FIG. 7 is a circuit diagram showing the configuration of the data line drive circuit 101. In this figure, the shift register 600 has a configuration in which the unit circuits LX1, LX2, ... That operate according to the clock signal CLX and its inverted clock signal CLX'are vertically connected in a plurality of stages. Here, the clock signal CLX is a signal supplied from an external image signal processing circuit, and its frequency coincides with the dot frequency. Further, the inverted clock signal CLX'is a signal whose level is inverted from the clock signal CLX, and is similarly supplied from an external image signal processing circuit. Further, the unit circuit LX1 in the first stage has a configuration in which the start pulse DX is supplied from the external image signal processing circuit at the beginning of the horizontal scanning period, but the other unit circuits are in the previous stage (in FIG. 7). It is configured to input the transfer signal by the unit circuit of (left side).
【0088】
Of the unit circuits, the odd-numbered unit circuits LX1, LX3, ... counting from the left take in and output the input signal at the rising edge of the clock signal CLX, while the even-numbered unit circuits LX2, LX4, ... captures and outputs an input signal at the rising edge of the inverted clock signal CLX'.
【0089】
Therefore, the output signals B1p, B2p, ... of each unit circuit LX1, LX2, ... Are as shown in FIG. 8, respectively. That is, the output signal B1p of the unit circuit LX1 of the first stage captures the start pulse DX at the rising edge of the clock signal CLX, and the output signals B2p, B3p, B3p, of the following unit circuits LX2, LX3, LX4, ... B4p, ... Are signals in which the output signal B1p is sequentially delayed by half a cycle of the clock signal CLX (inverted clock signal CLX').
【0090】
In FIG. 7, each unit circuit includes a clocked inverter 601a that inverts the input signal, an inverter 601b that re-inverts the inverted signal, and a clocked inverter 601c that feeds back the re-inverted signal to the input of the inverter 601b. It is composed of and. Here, the clocked inverters 601a and 601c and the inverter 601b are the same as the clocked inverters 501a and 501c and the inverter 501b in the scanning line drive circuit 104 (see FIG. 2), and the clock signal CLY (and) on the Y side are the same. The inverted clock signal CLY') is replaced with the clock signal CLX (and the inverted clock signal CLX') on the X side.
【0091】
Returning to FIG. 7 again, the NAND gate G3 and the inverter G4 are connected in series on the output side of each unit circuit LX1, LX2, .... Of these, one NAND gate G3 outputs a negative logical product signal of the transfer signal by the corresponding unit circuit and the transfer signal by the unit circuit in the subsequent stage (right side in FIG. 7), and the inverter located on this output side. G4 reversely outputs the negative conjunction signal.
【0092】
Therefore, the transfer signals B1, B2, ... Output from the inverter G4 of each stage are as shown in FIG. 8, respectively. That is, the transfer signals B1, B2, ... Are H level in the overlapping period of the transfer signal by the corresponding unit circuit and the transfer signal by the unit circuit in the subsequent stage, so that they are H level exclusively and in order. You can see that it will be a level.
【0093】
Returning to FIG. 7 again, the transfer signals B1, B2, ... Output from the inverter G4 in each stage are branched into a plurality of systems (3 in this embodiment). Each system is provided with an enable circuit 602 composed of a NAND gate 603 and an inverter 604 connected in series. This enable circuit 602 is provided corresponding to one of the sampling control lines 306 (see FIG. 1). The output signal of the enable circuit 602 is supplied to the corresponding sampling control line 306 as a sampling control signal.
【0094】
Here, in the NAND gate 603 constituting the enable circuit 602, a branched transfer signal is supplied to one of the input terminals, and any of the enable signals ENB1x, ENB2x, or ENB3x is supplied to the other end. .. Specifically, at the other end of the i-th NAND gate 603 counting from the left in the figure, if the remainder of i divided by 3 is 1, the enable signal ENB1x is, and if i is divided by 3, the remainder is 2. If the enable signal ENB2x is supplied, and if the remainder obtained by dividing i by 3 is 0, the enable signal ENB3x is supplied.
【0095】
These enable signals ENB1x, ENB2x, and ENB3x are supplied from, for example, an external image signal processing circuit, and are signals having waveforms as shown in FIG. 8, respectively. That is, the enable signals ENB1x, ENB2x, and ENB3x are signals having twice the frequency of the clock signal CLX (inverted clock signal CLX'), and their pulse width is that of the clock signal CLX (inverted clock signal CLX'). It is a signal that is shorter than about 1/3 and whose pulse width periods are sequentially shifted by a time interval ΔT from each other.
【0096】
Therefore, the sampling control signals S1, S2, ... Output from each enable circuit 602 are as shown in FIG. That is, first, the transfer signal B1 is sequentially divided into three by the enable signals ENB1x, ENB2x, and ENB3x on the time axis, and becomes the sampling control signals S1, S2, and S3 with a time interval ΔT, and then becomes the sampling control signals S1, S2, and S3. The transfer signal B2 is similarly divided into three by the enable signals ENB1x, ENB2x, and ENB3x on the time axis, and becomes sampling control signals S4, S5, and S6 with a time interval ΔT. Is repeated.
【0097】
As a result, the sampling control signals S1, S2, S3, ... Are output in order and exclusive to each other in one horizontal scanning period, so that the sampling switches 302 are turned on one by one in order from the left in FIG. .. As a result, the image signal Vi applied to the image signal line 400 is sequentially sampled on the data line 35 and written in order via the TFT 30 connected to the selective scanning line 31 in the horizontal scanning period. ..
【0098】
Such a data line drive circuit 101 generates a sampling control signal by sequentially dividing the transfer signals B1, B2, B3, ... Based on the unit circuit of the shift register 600 into three on the time axis. Therefore, the number of stages of the unit circuit is only 1/3, which is the inverse of the number of divisions of the transfer signal, as compared with the total number of data lines 35. Therefore, even on the X side, it is sufficient to form the unit circuit constituting the shift register 600 at a pitch three times that of the data line 35. On the other hand, an enable circuit 602 is required for each data line 35. In this respect, it is easy to form the enable circuit 602 at a narrow pitch for the same reason as the enable circuit 502 on the Y side. ..
【0099】
Moreover, since the operating frequency of the shift register 600 is reduced to 1/3, which is the reciprocal of the number of divisions of the transfer signal in the enable circuit 602, the clocked inverters 601a, 601c, and inverter 601b, which are the components of the shift register 600, are used. , High-speed response characteristics are not required. This point is remarkable as compared with the shift register 500 on the X side. Therefore, in the shift register 600, the specifications such as the circuit accuracy, the circuit scale, the wiring resistance, the time constant, the capacitance, and the delay time are relaxed.
【0100】
By the way, the reasons why the X-side enable signals ENB1x, ENB2x, and ENB3x are separated by the time interval ΔT between the pulses compared to the Y-side enable signals ENB1y, ENB2y, and ENB3y (see Fig. 3) are as follows. Is. That is, the frequency of the clock signal CLX on the X side (inverted clock signal CLX') is overwhelmingly higher than that of the clock signal CLY on the Y side (inverted clock signal CLY'). For this reason, if the sampling control signals S1, S2, and S3 that are adjacent to each other have even a slight overlap in the H level due to operation delay, crosstalk and ghosting will occur. In order to prevent this, the pulses are provided with a time interval ΔT.
【0101】
Other points are the same as on the Y side. That is, the enable circuit on the X side may be configured by using the transmission gate shown in any of FIGS. 5 (a) to 5 (c) or any channel type TFT, or the enable circuit. Similar to the Y side, the 602 may be sequentially shifted and arranged at a certain distance in the Y direction, or may be shifted and arranged alternately at a certain distance in the Y direction. Is.
【0102】
As described above, according to the liquid crystal apparatus according to the first embodiment, both the scanning line pitch and the data line pitch can be formed narrower than the pitch limit of the unit circuit constituting the shift register. Therefore, the pixel pitch can be made very narrow, which greatly contributes to high definition of the display.
【0103】
(Second Embodiment) Next, the liquid crystal apparatus according to the second embodiment of the present invention will be described. FIG. 9 is an overall block diagram showing the configuration of this liquid crystal device. In the liquid crystal device shown in this figure, a point in which a serial-parallel converted image signal is supplied via a plurality of image signal lines 401, and correspondingly, a plurality of one sampling control signals ( This embodiment differs from the liquid crystal apparatus according to the first embodiment (see FIG. 1) in that it is simultaneously supplied to the sampling switch 302 of 6). Others are the same as those of the liquid crystal apparatus according to the first embodiment. That is, in each of the image signals VID1 to VID6, as shown in FIG. 10, one system of image signals Vi is extended 6 times along the time axis by an external image signal processing circuit, and six image signal lines 401 It is a signal sequentially distributed to. Further, the sampling control signal divided on the time axis by the enable circuit 602 of the data line drive circuit 101 is supplied to the six phase-adjacent sampling switches 302 via the sampling control signal line 307 which is further branched into six. It is configured to be. Therefore, in the second embodiment, the enable circuit 602 of the data line drive circuit 101 is not provided for each of the data lines 35 as in the first embodiment, but is provided for each of the six data lines 35. It will be provided for each case.
【0104】
Next, the operation of the liquid crystal apparatus according to the second embodiment will be described. As shown in FIG. 10, the sampling control signals S1, S2, S3, ... Are exclusive to each other and in order in one horizontal scanning period. It is the same as the first embodiment in that it is output to. Here, when the sampling control signal S1 reaches the H level, the six sampling switches 302, which are the 1st to 6th sampling switches 302 counted from the left in FIG. 9, are turned on at the same time, so that the image signal is connected to the 1st to 6th data lines 35. VIDs 1 to 6 are each sampled and written in order via the TFT 30 connected to the selective scanning line 31 in the horizontal scanning period. Next, when the sampling control signal S2 reaches the H level, six of the 7th to 12th sampling switches 302 are turned on at the same time, so the image signals VID1 to 6 are sampled on the 7th to 12th data lines 35, respectively. , The data will be written in order via the TFT 30 connected to the selective scanning line 31 in the horizontal scanning period. Then, the same operation is repeated.
【0105】
As described above, according to the second embodiment, the number of stages of the unit circuit in the data line drive circuit 101 is the number of divisions of the transfer signal based on the transfer circuit and the number of sampling switches 302 simultaneously driven by the same sampling control signal. It is reduced to the reciprocal of the product of. That is, in the second embodiment, the number of divisions of the transfer signal is the same as that in the first embodiment, so it is "3", and the number of sampling switches 302 driven at the same time is "6", so that the data line drive circuit The number of stages of the unit circuit in 101 is reduced to 1/18 of the total number of data lines 35. Therefore, the pitch of the unit circuit in the shift register, particularly the shift register 600 on the X side (see FIG. 7) is greatly relaxed, so that the pitch of the data line 35 can be narrowed. Further, as the number of stages of the unit circuit is reduced, the drive frequency of the shift register 600 on the X side can be reduced to 1/18 in the present embodiment.
【0106】
In the second embodiment, the number of conversions (expansion) of the image signal is set to "6", and "6" sampling switches 302 are driven at the same time. However, this number of conversions (and simultaneous driving of the sampling switches 302) The number) is determined according to the performance of the sampling switch 302. For example, if the sampling capability of the sampling switch 302 is high, the image signal Vi (not serial-parallel converted) is sequentially supplied to one data line 35 as in the first embodiment. Alternatively, if the sampling capacity is low, the image signal Vi may be serial-parallel converted and supplied to two or more data lines 35. Here, the number of conversions is preferably a multiple of 3 in order to simplify control and circuits because the color image signal is composed of signals related to three colors.
【0107】
Other points are the same as those in the first embodiment. That is, in the scanning line drive circuit 104, the pitch of the unit circuit constituting the shift register 500 (on the Y side) is narrowed, and the enable circuit on the X side and the Y side is a transmission gate or one of the channel type TFTs. The points that may be configured, the points that these enable circuits may be sequentially shifted and arranged at a certain distance in the Y direction or the X direction, or the points that they may be arranged alternately, etc., are the first implementation. Similar to form.
【0108】
(Third Embodiment) Next, the liquid crystal apparatus according to the third embodiment of the present invention will be described. FIG. 11 is an overall block diagram showing the configuration of this liquid crystal device. The liquid crystal apparatus shown in this figure is common to the liquid crystal apparatus according to the second embodiment (see FIG. 9) in that the image signals VID1 to VID3 are supplied via the plurality of image signal lines 402. However, it differs from the liquid crystal apparatus according to the second embodiment in that one sampling control signal is supplied to one sampling switch 302. Therefore, the sampling control signal line 308 is connected to only one corresponding sampling switch 302 without branching into a plurality of sampling control signal lines 308 as in the second embodiment. Therefore, in the third embodiment, the enable circuit 602 of the data line drive circuit 101 is provided corresponding to each of the data lines 35 as in the first embodiment. Others are the same as those of the liquid crystal apparatus according to the first and second embodiments.
【0109】
Here, the liquid crystal apparatus according to the third embodiment performs a display operation in one of the following two operation modes. That is, in this liquid crystal device, the image signal Vi is not serial-parallel converted, and the first operation mode (sequential drive) supplied to the three image signal lines 402, or the image signal Vi is serial-serialized into three systems. The display operation is performed in one of the second operation modes (simultaneous drive of a plurality of lines) that are converted in parallel and sequentially distributed to the three image signal lines. Here, the operation of the scanning line drive circuit 104 is the same as in the first or second embodiment in both the first operation mode and the second operation mode. Regarding the operation of the data line drive circuit 101, until the transfer signals B1, B2, ... Are sequentially shifted and output every half cycle of the clock signal CLX (inverted clock signal CLX') on the X side. , The same as the first and second embodiments, the difference in operation after this point will be mainly described.
【0110】
Therefore, first, the display operation in the first operation mode will be described. In this first operation mode, the enable circuit 602 (see FIG. 7) is supplied with the following enable signals ENB1x, ENB2x, and ENB3x. That is, the enable signals ENB1x, ENB2x, and ENB3 are signals having twice the frequency of the clock signal CLX (inverted clock signal CLX') as shown in FIG. 12, and the pulse width thereof is the clock signal CLX ( It is shorter than about 1/3 of the inverting clock signal CLX'), and its pulse width period is sequentially shifted by a time interval ΔT and supplied.
【0111】
Therefore, as in the first embodiment, the transfer signal B1 output from the first-stage inverter G4 is sequentially divided into three by the enable signals ENB1x, ENB2x, and ENB3x on the time axis, and the time interval ΔT is set. , Sampling control signals S1, S2, S3, ..., and then the transfer signal B2 is sequentially divided into three by the enable signals ENB1x, ENB2x, ENB3x on the time axis, and the sampling control signal S4, It becomes S5 and S6, and the same division is repeated thereafter.
【0112】
As a result, the sampling control signals S1, S2, S3, ... Are output in order and exclusive to each other in one horizontal scanning period, so that the sampling switches 302 are turned on one by one in order from the left in FIG. .. As a result, the image signals VID1 to VID3 applied to the image signal line 402, that is, the image signal Vi itself, are sequentially sampled by the data line 35 and passed through the TFT 30 connected to the selective scanning line 31 in the horizontal scanning period. Will be written in order.
【0113】
As described above, in the liquid crystal apparatus according to the third embodiment, in the first operation mode, an image signal is sampled for each data line 35, whereby each corresponding pixel portion is sequentially driven. It becomes.
【0114】
Next, the display operation in the second operation mode will be described. In this second operation mode, the enable circuit 602 (see FIG. 7) is supplied with the following enable signals ENB1x, ENB2x, and ENB3x. That is, the enable signals ENB1x, ENB2x, and ENB3x are signals having twice the frequency of the clock signal CLX (inverted clock signal CLX') as shown in FIG. 13, but the pulse width is the clock signal CLX. It is shorter than the pulse width of (inverted clock signal CLX'), and its pulse width period is supplied in phase with each other.
【0115】
Therefore, the transfer signal B1 output from the first-stage inverter G4 is simultaneously distributed by the enable signals ENB1x, ENB2x, and ENB3x, and as a result, the sampling control signals S1, S2, and S3 become the same signals. As a result, in FIG. 11, the 1st to 3rd sampling switches 302 counted from the left are turned on at the same time, so that the image signals VID1 to VID3 are serial-parallel converted to the 1st to 3rd data lines 35 counting from the left. It will be sampled at the same time and written via the TFT 30 connected to the selective scan line 31 during the horizontal scan period.
【0116】
Next, the transfer signal B2 is similarly distributed simultaneously by the enable signals ENB1x, ENB2x, and ENB3x, resulting in sampling control signals S4, S5, and S6, which are the same signals. As a result, in FIG. 11, the 4th to 6th sampling switches 302 counted from the left are turned on at the same time, so that the image signals VID1 to VID3 are serial-parallel converted to the 4th to 6th data lines 35 counting from the left. It is sampled at the same time and written via the TFT 30 connected to the selective scanning line 31 during the horizontal scanning period. Hereinafter, the same operation is performed every three sampling switches 302 (every three data lines 35). Is repeated in.
【0117】
As described above, in the liquid crystal apparatus according to the third embodiment, in the second operation mode, the serial-parallel converted image signal is sampled for each of the three data lines 35, and the corresponding pixel portions are three. Each piece will be driven at the same time. Therefore, in the end, the liquid crystal apparatus according to the third embodiment can be driven by either a sequential drive system or a plurality of simultaneous drive systems.
【0118】
Other points are the same as those of the first and second embodiments. That is, in the scanning line drive circuit 104, the pitch of the unit circuit constituting the shift register 500 (on the Y side) is narrowed, and the enable circuit on the X side and the Y side is a transmission gate or one of the channel type TFTs. The points that may be configured, the points that these enable circuits may be sequentially shifted and arranged at a certain distance in the Y direction or the X direction, or that they may be arranged alternately are the above-described embodiments. Is similar to.
【0119】
(Configuration of Image Signal Processing Circuit) Next, in addition to the image signals VID1 to VID3, various enable signals ENB1x, ENB2x, ENB3, etc. according to the first or second operation mode are applied to the liquid crystal device according to the third embodiment. The configuration of the image signal processing circuit that supplies the timing signal of the above will be described. FIG. 14 is a block diagram showing the configuration of the image signal processing circuit DPa including the liquid crystal device 200.
【0120】
In this figure, the RGB decoder 201 extracts a red signal, a green signal, and a green signal corresponding to the so-called three primary colors of light from a video signal Sv input from an external, for example, a video playback device, and sets the selector 202 as the primary color signal Sdv. In addition to supplying to one input terminal, the composite synchronization signal Scs is extracted from the video signal Sv and supplied to one input terminal of the synchronization signal separation unit 208. Such a video signal Sv is, for example, a video signal such as NTSC, PAL, or SECAM.
【0121】
On the other hand, the RGB signal Spc is an image signal input from an external computer, for example, and is supplied to the other input terminal of the selector 202 and to the other input terminal of the synchronization signal separation unit 208. The RGB signal Spc is a so-called data signal.
【0122】
Next, the selector 202 selects either the primary color signal Sdv or the RGB signal Spc based on the selection signal Sc from the microcomputer 211, and outputs the selected image signal Sga to the A / D converter 203. is there. Subsequently, the A / D converter 203 digitizes the selected image signal Sga and supplies it as a digital image signal Sdg to the signal processing unit 204.
【0123】
In the image signal processing circuit DPa, when the primary color signal Sdv and the RGB signal Spc are input at the same time, the selector 202 selects one of them, and either the primary color signal Sdv or the RGB signal Spc. When only one is input, there are two ways, when the selector 202 selects and outputs the input signal.
【0124】
Now, the synchronization signal separation unit 208 extracts the synchronization signal contained therein from either the composite synchronization signal Scs or the RGB signal Scc based on the selection signal Sc, and generates the horizontal synchronization signal Shd and the vertical synchronization signal Svd. It is supplied to the PLL circuit 207 and the signal processing unit 204, respectively. Subsequently, the PLL (Phase Locked Loop) circuit 207 generates and supplies the clock signal Sclk used for signal processing in the signal processing unit 204 based on the input horizontal synchronization signal Shd.
【0125】
On the other hand, the input unit 209 includes an operation unit (not shown) operated by the user, and outputs a signal Sin indicating the setting content. In particular, the input unit 209 according to the present embodiment sets the setting contents regarding whether to set the first operation mode (sequential drive) or the second operation mode (simultaneous drive of a plurality of lines) in the liquid crystal device 200. The signal Sin shown is generated and supplied to the interface unit 210. Here, when the user normally displays an image by the video signal Sv to the input unit 209, the user usually sets the first operation mode in order to maintain the uniformity of the image and display it. On the other hand, when displaying an image by RGB signal Spc, an operation is performed to set a second operation mode in order to ensure the high speed of the image and display it.
【0126】
Next, the interface unit 210 converts the signal Sin from the input unit 209 into a signal suitable for processing by the microcomputer 211. Then, when the signal Sin indicates the setting of the first operation mode, the microcomputer 211 has a selection signal Sc instructing the selection of the video signal Sv and a control signal instructing that the control should be performed in the first operation mode. While outputting Sch, when the signal Sin indicates the setting of the second operation mode, the selection signal Sc instructing the selection of the RGB signal Spc and the control instructing that control should be performed in the second operation mode. Outputs the signal Sch. At this time, the microcomputer 211 exchanges necessary information Sm with the EEPROM (Electrically Erasable and Programmable Read Only Memory) 212.
【0127】
By the way, the signal processing unit 204 performs the following processing. That is, the signal processing unit 204 first performs signal processing such as gamma correction on the input digital image signal Sdg and outputs it as an image signal Svd, and secondly, the operation mode indicated by the control signal Sch. The timing signal Svt required in the above is generated based on the horizontal synchronization signal Shd, the vertical synchronization signal Svd, and the clock signal Sclk, and supplied to the D / A converter 205 and the sample hold unit 206, respectively. The timing signal Sdt required for driving in and in the operation mode indicated by the control signal Sch is generated based on the horizontal synchronization signal Shd, the vertical synchronization signal Svd, and the clock signal Sclk, and supplied to the level shifter 213. To do. Here, the timing signal Sdt is the clock signal CLX (and inverted clock signal CLX') on the X side, the clock signal CLY (and inverted clock signal CLY') on the Y side, the start pulse DX on the X side, and the start on the Y side. Pulse DY, X-side enable signal ENB1x, ENB2x, ENB3x, Y-side enable signal ENB1y, ENB2y, ENB3y, etc. are generic signals, but these are signals with low logic amplitude. Of these, the enable signals ENB1x, ENB2x, and ENB3x are the waveforms shown in FIG. 12 in the first operation mode and the waveforms shown in FIG. 13 in the second operation mode, respectively, and have low logical amplitudes (by logical product). The obtained signal with a short pulse width) is output.
【0128】
The D / A converter 205 converts the digital image signal Svd processed by the signal processing unit 204 into an analog signal Savd according to the timing signal Svt, and the sample hold unit 206 converts the digital image signal Svd into an analog signal Savd according to the timing signal Svt. It samples and holds the analog image signal Sadv. In particular, the sample hold unit 206 distributes to the same image signals VID1 to VID3 in the first operation mode, and converts them into three image signals VID1 to VID3 in the second operation mode. Then, it is supplied to the liquid crystal device 200. On the other hand, the level shifter 213 converts each signal included in the timing signal Sdt into a high logic amplitude (a signal having a long pulse width obtained by the logical product) and supplies the signal to the liquid crystal apparatus 200.
【0129】
In such an image signal processing circuit DPa, when the first operation mode is set in the input unit 209, the microcomputer 211 outputs a selection signal Sc instructing the selection of the video signal Sv. Therefore, the video signal Sv is selected by the selector 202 and supplied to the signal processing unit 204 via digital conversion by the A / D converter 203, and is extracted from the video signal Sv by the synchronous signal separation unit 208. The composite sync signal Scs is selected and the sync signals contained therein are further extracted. Further, the microcomputer 211 also outputs a control signal Sch instructing that control should be performed in the first operation mode. Therefore, in the signal processing unit 204, the enable signals ENB1x, ENB2x, and ENB3x are sequentially shifted and output so that the pulse widths do not overlap in the half cycle of the clock signal CLX (and the inverted clock signal CLX'). Further, the signal processing unit 204 outputs the timing control signal Svt for the first operation mode, whereby the analog image signal Savd in the sample hold unit 206 is the same image without serial-parallel conversion. It will be supplied as signals VID1 to VID3.
【0130】
On the other hand, when the second operation mode is set in the input unit 209, the selection signal Sc instructing the selection of the RGB signal Spc is output from the microcomputer 211. Therefore, the selector 202 selects the RGB signal Spc and supplies it to the signal processing unit 204 via digital conversion by the A / D converter 203, and the synchronous signal separation unit 208 selects the RGB signal Spc. , The synchronization signal contained therein is extracted. Further, the microcomputer 211 also outputs a control signal Sch instructing that control should be performed in the second operation mode. Therefore, the signal processing unit 204 outputs the enable signals ENB1x, ENB2x, and ENB3x in the same phase in a half cycle of the clock signal CLX (and the inverted clock signal CLX'). Further, the signal processing unit 204 outputs the timing control signal Svt for the second operation mode, whereby the analog image signal Savd is serial-parallel converted in the sample hold unit 206, and in detail, the time axis. In addition to being extended three times, it is distributed to three image signal lines and supplied as image signals VID1 to VID3.
【0131】
Therefore, in the liquid crystal device 200, if the input image signal is a video signal Sv, the drive is sequentially performed, while if the input image signal is an RGB signal Spc, a plurality of simultaneous drives are performed. Generally, in a video signal such as a video signal Sv, the image has a lot of movement, so sequential driving is suitable. On the contrary, in a data signal such as an RGB signal Spc, the image has little movement (or). (Nothing at all), so it is said that simultaneous drive of multiple lines is suitable. According to such an image signal processing circuit DPa, either sequential drive or simultaneous drive of a plurality of signals can be switched according to the operation mode setting by the input unit 209. Therefore, the liquid crystal device 200 inputs the video signal Sv. Even if the RGB signal Sv is input, high quality display is possible.
【0132】
(Application Example of Image Signal Processing Circuit) Next, an application example of the image signal processing circuit will be described. In the image signal processing circuit DPa shown in FIG. 14, the configuration is such that the first operation mode (sequential drive) and the second operation mode (multiple simultaneous drive) are switched according to the setting of the input unit 209 by the user. However, the image signal processing circuit according to this application example detects the presence or absence of motion of the image to be displayed, and switches the operation mode according to the detection result.
【0133】
FIG. 15 is a block diagram showing the configuration of the image signal processing circuit according to this application example, including the liquid crystal device 200. In the image signal processing circuit DPb shown in FIG. 15, the portion different from the image signal processing circuit DPa shown in FIG. 14 is a movement in which the signal processing unit 204 detects whether or not the image to be displayed has motion. The point that the detection unit 214 is provided, the point that the microcomputer 211 sets the operation mode according to the detection signal Smv by the motion detection unit 214, and the function in the input unit 209 do not set the operation mode, but simply. , The point that only sets whether to display the image input as the video signal Sv or the image input as the RGB signal Spc, for a total of three points. Others are the same as the image signal processing circuit DPa shown in FIG. 14, and the description thereof will be omitted.
【0134】
By the way, in this application example, when the input unit 209 is set to display the image by the video signal Sv, the microcomputer 211 outputs the selection signal Sc instructing the selection of the video signal Sv. Therefore, the video signal Sv is selected by the selector 202 and supplied to the signal processing unit 204 via digital conversion by the A / D converter 203, and is extracted from the video signal Sv by the synchronous signal separation unit 208. The composite sync signal Scs is selected and the sync signals contained therein are further extracted.
【0135】
On the other hand, when the input unit 209 is set to display the image by the RGB signal Spc, the microcomputer 211 outputs the selection signal Sc instructing the selection of the RGB signal Spc. Therefore, the selector 202 selects the RGB signal Spc and supplies it to the signal processing unit 204 via digital conversion by the A / D converter 203, and the synchronous signal separation unit 208 selects the RGB signal Spc. , The synchronization signal contained therein is extracted.
【0136】
Therefore, in any case, the digital image signal Sdg is supplied to the signal processing unit 204. Here, the motion detection unit 214 in the signal processing unit 204 detects the presence or absence of motion in the digital image signal Sdg, generates the detection signal Smv, and outputs the detection signal Smv to the microcomputer 211.
【0137】
On the other hand, the microcomputer 211 determines the operation mode as follows based on the motion detection signal Smv. That is, the microcomputer 211 sets the operation mode to the first operation mode (sequential drive) if there is movement within a preset predetermined time (for example, 1 second) in the image by the digital image signal Sdg. While generating the control signal Sch, if there is no movement within the predetermined time, a control signal Sch to set the operation mode to the second operation mode (simultaneous drive of a plurality of lines) is generated and supplied to the signal processing unit 204. To do.
【0138】
After that, in the signal processing unit 204, the same operation is performed according to the control signal Sch. That is, when the control signal Sch indicates that the control should be performed in the first operation mode, in the signal processing unit 204, the enable signals ENB1x, ENB2x, and ENB3x are used for half a cycle of the clock signal CLX (and the inverted clock signal CLX'). In addition to being sequentially shifted and output so that the pulse widths do not overlap, the timing control signal Svt for the first operation mode is output, whereby in the sample hold unit 206, the analog image signal Savd is serial-parallel. It will be supplied as the same image signals VID1 to VID3 without being converted.
【0139】
On the other hand, when the control signal Sch indicates that the control should be performed in the second operation mode, in the signal processing unit 204, the enable signals ENB1x, ENB2x, and ENB3x are used for half a cycle of the clock signal CLX (and the inverted clock signal CLX'). In addition to being output in the same phase, the timing control signal Svt for the second operation mode is output, whereby in the sample hold unit 206, the analog image signal Savd is serial-parallel converted, and the image signals VID1 to VID3 Will be supplied as.
【0140】
Therefore, according to the image signal processing circuit DPb according to such an application example, if there is motion of the image due to the input video signal Sv or RGB signal Spc (or if the motion is intense), the drive is sequentially performed. On the other hand, if there is no movement in the image (or if there is little movement), multiple simultaneous drives will be performed. Therefore, when the image signal processing circuit DPb according to the application example is used, it is possible to switch to an appropriate drive method regardless of whether the image is moving or not, so that high-quality display is possible in the liquid crystal device 200.
【0141】
(Fourth Embodiment) Next, the liquid crystal apparatus according to the fourth embodiment of the present invention will be described. The overall configuration of the liquid crystal apparatus according to this embodiment is the same as that of the third embodiment (see FIG. 11) described above. That is, the liquid crystal apparatus according to the fourth embodiment has a configuration in which the image signals VID1 to VID3 are supplied via the three image signal lines 402 and one sampling control signal is supplied to one sampling switch 302. It has become. Further, the liquid crystal apparatus according to the fourth embodiment is also driven in either the first operation mode (sequential drive) or the second operation mode (multiple simultaneous drive). It is common with the form.
【0142】
However, the data line drive circuit 101 has the configuration shown in FIG. That is, in the data line drive circuit 101a according to the fourth embodiment, the logical product signal of the output signal of the unit circuit constituting the shift register 600 and the output signal of the unit circuit located in the subsequent stage is the NAND gate G3 and the inverter. It is the same as the data line drive circuit 101 (see FIG. 7) according to the first to third embodiments described above in that it is obtained by connecting the G4 in series and is output as a transfer signal, but the transfer signal is It is branched into two, each of which is provided with a first enable circuit 612, and the output signal of the first enable circuit 612 is further branched into three, each of which is provided with a second enable circuit 622. In that respect, it is different from the data line drive circuit 101 according to the first to third embodiments described above.
【0143】
The first enable circuit 612 outputs a negative logical product signal of one of the two branched transfer signals and one of the first group of enable signals ENB11x and ENB12x. It is composed of a series connection of a gate 613 and a first inverter 614 that reversely outputs the negative AND signal. Of the two first NAND gates 613 to which the same transfer signal (branch source) is supplied, the one located on the left side in FIG. 16 is supplied with ENB11x belonging to the enable signal of the first group. On the other hand, the one located on the right side is supplied with ENB12x belonging to the enable signal of the first group.
【0144】
Here, the enable signals ENB11x and ENB12x of the first group are fixed signals that are not changed by the operation mode. Specifically, the enable signals ENB11x and ENB12x of the first group are signals having twice the frequency of the clock signal CLX (inverted clock signal CLX') on the X side, respectively, as shown in FIG. 17 or FIG. The pulse width is about 1/2 of the clock signal CLX (inverted clock signal CLX'), and the pulse width periods are sequentially shifted without overlapping each other.
【0145】
For convenience of explanation, assuming that the output signals by each of the first enable circuits 612 are C1, C2, C3 ... In order from the left in FIG. 16, these output signals C1, C2, C3 ... Are shown in FIG. Or as shown in Figure 18. That is, first, the transfer signal B1 is sequentially divided into two by the enable signals ENB11x and ENB12x on the time axis to become output signals C1 and C2, and then the transfer signal B2 is similarly divided by the enable signals ENB11x and ENB12x. It is sequentially divided into two on the time axis to become output signals C3 and C4, and the same division is repeated thereafter regardless of the operation mode.
【0146】
The output signal from one of the first enable circuits 612 is further branched into three, and a second enable circuit 622 is provided corresponding to each of the branches. Specifically, the second enable circuit 622 outputs a negative logical product signal of one of the output signals branched into three and one of the enable signals ENB21x, ENB22x, and ENB23x of the second group. The NAND gate 623 of the above is connected in series with the second inverter 624 that inverting and outputs the negative logical product signal, and the inverting output signal of this second inverter 624 is one sampling control signal line (see FIG. 11). ) It is configured to be output as a sampling control signal via 308. Of the three second NAND gates 623 to which the same signal (branch source) is supplied, the one located on the left side in FIG. 16 is supplied with ENB21x belonging to the second group of enable signals. The one located in the middle is supplied with ENB22x belonging to the enable signal of the second group, and the one located to the right is supplied with ENB23x belonging to the enable signal of the second group.
【0147】
Here, the enable signals ENB21x, ENB22x, and ENB23x of the second group are signals that are changed depending on the operation mode, unlike the enable signals ENB11x and ENB12x of the first group. Specifically, the enable signals ENB21x, ENB22x, and ENB23x of the second group are the clock signals CLX (inverted clock signal CLX') on the X side, respectively, as shown in FIG. 17 in the first operation mode (sequential drive). The signal has four times the frequency of the signal, and its pulse width is about one-third of the enable signals ENB11x and ENB12x of the first group, and the pulse width periods are sequentially shifted without overlapping each other. On the other hand, in the second operation mode (simultaneous drive of a plurality of signals), as shown in FIG. 18, each signal has four times the frequency of the clock signal CLX (inverted clock signal CLX') on the X side. , The pulse width is shorter than the pulse widths of the enable signals ENB11x and ENB12x of the first group, and the pulse width periods are in phase with each other.
【0148】
Therefore, the sampling control signals S1, S2, S3 ... By each of the second enable circuits 622 are as shown in FIG. 17 in the first operation mode. That is, first, the output signal C1 of the first enable circuit 612 located at the leftmost end in FIG. 16 is sequentially divided into three on the time axis by the second group of enable signals ENB21x, ENB22x, and ENB23x, and sampling control is performed. The signals S1, S2, and S3, and then the output signal C2 of the first enable circuit 612, which is located second from the left, is similarly driven by the second group of enable signals ENB21x, ENB22x, and ENB23x on the time axis. The sampling control signals S4, S5, and S6 are sequentially divided into three, and the same division is repeated thereafter. Therefore, in the first operation mode, the sampling control signals S1, S2, S3, ... Are sequentially shifted and output without overlapping their pulse widths.
【0149】
On the other hand, the sampling control signals S1, S2, S3 ... By each of the second enable circuits 622 are as shown in FIG. 18 in the second operation mode. That is, first, the output signal C1 of the first enable circuit 612 located at the leftmost end in FIG. 16 is simultaneously distributed into three by the enable signals ENB21x, ENB22x, and ENB23x of the second group, and the sampling control signal S1. S2 and S3, and then the output signal C2 of the first enable circuit 612, which is located second from the left, is similarly distributed to three by the enable signals ENB21x, ENB22x, and ENB23x of the second group at the same time. Then, the sampling control signals S4, S5, and S6 are obtained, and the same distribution is repeated thereafter. Therefore, in the second operation mode, the sampling control signals S1, S2, S3, ... Are the same for every three, and the sampling control signals S1 to S3, S4 to S6, S7 to S9, .. Will be output with a sequential shift.
【0150】
As described above, in the fourth embodiment, first, the transfer signal output corresponding to each unit circuit of the shift register 600 on the X side is sequentially divided into two on the time axis by the first enable circuit 612. This results in two signals whose pulse widths do not overlap each other. Further, one of the two signals is sequentially divided into three on the time axis by the second enable circuit 622 in the first operation mode, whereby the pulse widths do not overlap each other. While three sampling signals are obtained, in the second operating mode, the second enable circuit 622 simultaneously distributes the three sampling signals to three sampling signals having the same pulse width.
【0151】
It should be noted that the writing of the sequential drive in the first operation mode and the writing of the plurality of simultaneous drives in the second operation mode are as described in the third embodiment, respectively. The explanation is omitted.
【0152】
After all, in the present embodiment, six sampling control signals are generated for one stage of the unit circuit constituting the shift register 600 on the X side, and therefore, as compared with the third embodiment. Further, the X-direction circuit pitch of the unit circuit in the shift register 600 can be further relaxed. Specifically, the number of constituent stages of the unit circuit in the shift register 600 is the reciprocal "1/6" of the product of the number of divisions "2" by the first enable circuit 612 and the number of divisions "3" by the second enable circuit 622. Therefore, in combination with the narrowing of the pitch on the Y side in the first embodiment, it greatly contributes to the narrowing of the pixel pitch. Further, since the drive frequency in the shift register is reduced to 1/6, it is possible to reduce the power consumption accordingly.
【0153】
Other points are the same as those in the first to third embodiments. That is, in the scanning line drive circuit 104, the pitch of the unit circuit constituting the shift register 500 (on the Y side) is narrowed, and the enable circuit on the X side and the Y side is a transmission gate or one of the channel type TFTs. The points that may be configured, the points that these enable circuits may be sequentially shifted and arranged at a certain distance in the Y direction or the X direction, or that they may be arranged alternately are the above-described embodiments. Is similar to.
【0154】
The enable signals ENB11x and ENB12x of the first group and the enable signals ENB21x, ENB22x and ENB23x of the second group are set by the input unit 209 as the timing signal Sdt by the signal processing unit 204 in FIGS. 14 and 15, for example. Or, it is generated according to the movement of the image.
【0155】
Further, in the fourth embodiment, the number of divisions by the first enable circuit 612 is set to "2" and the number of divisions by the second enable circuit 612 is set to "3", but the present invention is not limited to this. Needless to say.
【0156】
(Overall Configuration of Liquid Crystal Device) Next, the overall configuration of the liquid crystal device according to each of the above-described embodiments will be described with reference to FIGS. 19 and 20. Here, FIG. 19 is a plan view showing the configuration of the liquid crystal device, and FIG. 20 is a cross-sectional view of the HH'line in FIG.
【0157】
As shown in these figures, in the liquid crystal apparatus 200, the TFT array substrate 10 on which the TFT 30 and the pixel electrodes are formed and the counter substrate 20 on which the counter electrodes and the like are formed face each other so that the electrode forming surfaces face each other. In addition, it is sandwiched with a certain gap. The liquid crystal device 200 has a structure in which a liquid crystal 50, which is an example of an electro-optical material, is sealed by a sealing material 52 in a gap between the TFT array substrate 10 and the opposing substrate 20. Here, a light-shielding film 53 for separating the screen display area and the peripheral area is provided as a so-called picture frame on the facing surface of the facing substrate 20 and inside the sealing material 52. On the other hand, a data line driving circuit 101 is formed together with a sampling circuit 302 (not shown in FIG. 19 or 20) on the outer side of the sealing material 52, which is the facing surface of the TFT array substrate 10, to form data lines. It is configured to drive. Further, a plurality of connection electrodes 102 are formed on this side, and various timing signals and image signals from the image signal processing circuit are input. Further, a scanning line driving circuit 104 is formed on each of the two sides adjacent to the one side, and the scanning lines are driven from both sides. If the delay of the scanning signal supplied to the scanning line does not matter, the scanning line drive circuit 104 may be formed on only one side. In addition, in order to reduce the writing load on the data lines, the TFT array substrate 10 may be formed with a precharge circuit that precharges each data line at a predetermined potential at a timing preceding the image signal. An inspection circuit for inspecting the quality of the liquid crystal device, defects, etc. may be formed.
【0158】
On the remaining side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line drive circuits 104 provided on both sides of the screen display area are provided. Further, at the four corners of the opposing substrate 20, electrical conduction is achieved between the TFT array substrate 10 and the opposing substrate 20 by the conductive material 106.
【0159】
In addition, on the facing substrate 20, for example, first, color filters are provided in a predetermined arrangement, and a gap black matrix of the color filters is provided, depending on the application and need of the liquid crystal device 200. Is provided with a backlight that irradiates the liquid crystal device 200 with light. In particular, in the case of color light modulation applications, a black matrix is provided on the facing substrate 20 without forming a color filter.
【0160】
In addition, an alignment film (not shown) that has been rubbed in a predetermined direction is provided on the facing surfaces of the TFT element array substrate 10 and the facing substrate 20, while liquid crystal coordination is provided on each back surface side thereof. A polarizer according to the direction, a retardation plate, etc. (both not shown) are provided. However, if a polymer-dispersed liquid crystal in which fine particles are dispersed in the polymer is used as the liquid crystal 50, the above-mentioned alignment film, polarizer, retardation plate, etc. are not required, and as a result, the light utilization efficiency is improved. It is advantageous in terms of high brightness and low power consumption.
【0161】
By the way, as shown in FIG. 19, the scanning line drive circuit 104 used in each embodiment is provided by being divided into two on the left and right sides of the screen display area, and the scanning lines 31 are alternately provided from the left and right sides of the screen display area. It may be configured to be wired to. Specifically, for example, counting from the top, for the odd-numbered scanning lines 31, one of the scanning line drive circuits 104 provided on both the left and right sides, and for the even-numbered scanning lines 31, the other. The scanning line drive circuit 104 may be used to drive each of the above. With this configuration, the scanning line 31 is alternately driven from the left and right sides of the screen display area by the scanning line driving circuit 104 divided into two, so that the unit constituting the shift register 500 in the scanning line driving circuit 104 It is possible to double the circuit pitch in the Y direction of the circuit. However, a configuration in which the scanning lines are simultaneously driven from both sides is advantageous from the viewpoint of reducing the delay time of the scanning signal.
【0162】
In each of the above-described embodiments, the TFT array substrate 10 is composed of a transparent insulating substrate such as glass, and the switching element (TFT116) of the pixel portion and the element of the drive circuit are configured on the substrate. As described above, the present invention is not limited to this. For example, the substrate 10 may be composed of a semiconductor substrate, and a pixel switching element or a drive circuit element may be configured by an insulated gate type field effect transistor in which a source, a drain, and a channel are formed on the surface of the semiconductor substrate. .. When the substrate 10 is made of a semiconductor substrate in this way, it cannot be used as a transmissive type, so that the pixel electrode 11 is formed of aluminum or the like and is used as a reflective type. Further, the substrate 10 may be simply a transparent substrate, and the pixel electrode 11 may be a reflective type.
【0163】
Further, in each of the above-described embodiments, the switching element of the pixel portion has been described as a 3-terminal element represented by a TFT, but a 2-terminal element such as a diode may be used. However, when a two-terminal element is used as the pixel switching element, the scanning line 31 is formed on one substrate, the data line 35 is formed on the other substrate, and the two-terminal element is formed on the scanning line 31 or the data line. It is necessary to form between one of the 35 and the pixel electrode 11.
【0164】
Further, although each of the above-described embodiments has been described as a liquid crystal device using a liquid crystal as an electro-optical material, the present invention is not limited to this. For example, as an electro-optical material, in addition to a liquid crystal, an electroluminescence element or the like is used, and it can be applied to a display device that displays by its electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to that of the liquid crystal device described above.
【0165】
(Application of Liquid Crystal Device: Liquid Crystal Projector) Next, a liquid crystal projector will be described as an example of an electronic device using the liquid crystal device according to each of the above-described embodiments. FIG. 21 is a plan view showing a configuration example of a liquid crystal projector. Here, the liquid crystal projector 1100 refers to three sets of liquid crystal modules including the liquid crystal device as the above-mentioned electro-optical device, which are R (red), G (green), and B (blue) color light valves 100R, 100G, respectively. It was used as 100B.
【0166】
As shown in FIG. 21, in the liquid crystal projector 1100, the light emitted from the lamp unit 1102 of a white light source such as a metal halide lamp is emitted by the three mirrors 1106 and the two dichroic mirrors 1108 in the three primary colors of RGB. It is separated into R light, G light, and B light corresponding to, and is guided to the light valves 100R, 100G, and 100B corresponding to each color, respectively. Here, in particular, B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an outgoing lens 1124 in order to prevent light loss due to a long optical path. Then, the light components corresponding to the three primary colors light-modulated by the light valves 100R, 100G, and 100B are recombined by the dichroic prism 1112 and then projected as a color image on the screen 1120 by the projection lens 1114. Become.
【0167】
It should be noted that the light bulbs 100R, 100B, and 100G do not need to be provided with a color filter because light corresponding to each of the primary colors R, G, and B is incident on the light bulbs 100R, 100B, and 100G by the dichroic mirror 1108.
【0168】
In addition to LCD projectors, examples of electronic devices include LCD TVs, viewfinder-type and monitor-view-type video tape recorders, car navigation devices, pagers, electronic organizers, calculators, word processors, workstations, and videophones. , POS terminals, devices equipped with a touch panel, etc. Needless to say, the electro-optical device according to the present invention can be applied to these various electronic devices.
【0169】
[Effect of the invention]
As described above, according to the present invention, it is possible to cope with the miniaturization of the pixel pitch by using a relatively simple circuit configuration.
[Simple explanation of drawings]
[Figure 1]
It is a block diagram which shows the whole structure of the liquid crystal apparatus which concerns on 1st Embodiment of this invention.
[Figure 2]
It is a circuit diagram which shows the structure of the scanning line drive circuit in the liquid crystal apparatus.
[Fig. 3]
It is a timing chart for demonstrating the operation of the scanning line drive circuit.
[Fig. 4]
(a) is a diagram showing a clocked inverter, and (b) is a circuit diagram showing an actual configuration thereof.
[Fig. 5]
(a) is a circuit diagram showing a modified example of the scanning line drive circuit (or data line drive circuit), and (b) is a circuit diagram showing an example of a practical configuration of the transmission gate. c) is a circuit diagram showing other examples.
[Fig. 6]
(a) is a diagram showing an example of the arrangement of the enable circuit in the scanning line drive circuit (or the data line drive circuit), and (b) is a diagram showing another arrangement.
[Fig. 7]
It is a circuit diagram which shows the structure of the data line drive circuit in the liquid crystal apparatus.
[Fig. 8]
It is a timing chart for demonstrating the operation of the data line drive circuit.
[Fig. 9]
It is a block diagram which shows the whole structure of the liquid crystal apparatus which concerns on 2nd Embodiment of this invention.
[Fig. 10]
It is a timing chart for demonstrating the operation of the data line drive circuit in the liquid crystal apparatus.
[Fig. 11]
It is a block diagram which shows the whole structure of the liquid crystal apparatus which concerns on 3rd Embodiment of this invention.
[Fig. 12]
It is a timing chart for demonstrating the operation in the case of the 1st operation mode in the data line drive circuit of the liquid crystal apparatus.
[Fig. 13]
It is a timing chart for demonstrating the operation in the 2nd operation mode in the data line drive circuit of the liquid crystal apparatus.
[Fig. 14]
It is a block diagram which shows an example of the structure of the image signal processing circuit including the liquid crystal apparatus.
[Fig. 15]
It is a block diagram which shows another example of the structure of the image signal processing circuit.
[Fig. 16]
It is a circuit diagram which shows the main part structure of the data line drive circuit among the liquid crystal apparatus which concerns on 4th Embodiment of this invention.
[Fig. 17]
It is a timing chart for demonstrating the operation in the case of the 1st operation mode in the data line drive circuit.
[Fig. 18]
It is a timing chart for demonstrating the operation in the case of the 2nd operation mode in the data line drive circuit.
[Fig. 19]
It is a top view which shows the structure of the liquid crystal apparatus which concerns on each embodiment.
[Fig. 20]
FIG. 19 is a cross-sectional view taken along the line HH'in FIG.
[Fig. 21]
It is a top view which shows the structure of the liquid crystal projector using any liquid crystal apparatus of each embodiment.
[Explanation of symbols]
1a ... Liquid crystal display 10 ... TFT array board 11 ... Pixel electrode 20 ... Opposed board 30 ... TFT 31 ... scan line 32 ... capacity line 35 ... Data line (source electrode) 101 ... Data line drive circuit 104 ... Scanning line drive circuit 200 ... LCD device 204 ... Signal processing unit 209 ... Input section 211 ... Microcomputer 214 ... Motion detector 302 ... sampling switch 400 ~ 402 ... Image signal line 500 ... (Y side) shift register 502 ... Enable circuit (on Y side) 503 ... NAND gate 504 ... Inverter 505 ... Transmission gate 507 ... TFT 600 ... shift register (on the X side) 602 ... Enable circuit (on the X side) 603 ... NAND gate 604 ... Inverter 612 ... 1st enable circuit 613 ... 1st NAND gate 614 ... 1st inverter 622 ... 2nd enable circuit 623 ... 2nd NAND gate 624 ... Second inverter Vi, VID1, VID2, VID3 ... Image signal LY2 ~ ... Unit circuit (on Y side) LX1 ~ ... Unit circuit (on the X side) A1 ~, B1 ~ ... Transfer signal ENB1y, ENB2y, ENB3y ... (Y side) enable signal ENB1x, ENB2x, ENB3x ... (X side) enable signal ENB11x, ENB12x, ENB13x ... 1st group enable signal ENB21x, ENB22x, ENB23x ... 2nd group enable signal Y1 ~ ... scanning signal S1 ~ ... Sampling control signal Smv ... detection signal
22 sheets
Sheet 1 Sheet 2 Sheet 3 Sheet 4 Sheet 5 Sheet 6 Sheet 7 Sheet 8 Sheet 9 Sheet 10 Sheet 11 Sheet 12 Sheet 13 Sheet 14 Sheet 15 Sheet 16 Sheet 17 Sheet 18 Sheet 19 Sheet 20 Sheet 21 Sheet 22
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| Document | Office | Kind | Date |
|---|---|---|---|
| 10214597 | Japan | – | |
| 21459798 | Japan | A | |
| 21459798 | Japan | A | |
| 10339604 | Japan | – | |
| 33960498 | Japan | A | |
| 33960498 | Japan | A | |
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| JP3781019B2 | Japan | B2 | |
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Numbers
- Publication
- 2000-227784
- Publication, DOCDB
- 2000227784
- Publication, EPODOC
- JP2000227784
- Application
- 11171260
- Application, DOCDB
- 17126099
- Application, EPODOC
- JP19990171260
Titles2
- Japanese
- 電気光学装置の駆動回路および電気光学装置
- English
- INDUSTRIAL APPLICABILITY: Drive circuit of electro-optical device and electro-optic device
Classification
- CPC, 5
- G09G3/3688
- G09G3/20
- G09G3/3677
- G09G2300/0408
- G09G2310/0297
- IPC, 5
- G02F1 133
- G02F1 136
- G02F1 1368
- G09G3 20
- G09G3 36