Clock phase error detection circuit and clock phase error detection method

Description: TECHNICAL FIELD [Detailed description of the invention]

[Technical field to which the invention belongs]

The present invention is a clock phase error detection circuit and a clock phase for obtaining a clock phase error signal used for phase correction of a clock reproduction circuit used in a receiving device in a system that transmits a digital signal using a band-limited pulse signal. Regarding the error detection method.

【0001】

[Conventional technology]

In a system that transmits a digital signal using a band-limited pulse wave, code transmission is generally performed using a roll-off spectrum-shaped pulse. Therefore, a slight deviation in the sample timing on the receiving side will abruptly deteriorate the characteristics.

【0002】

Conventionally, simple sample timing, that is, clock reproduction, rectifies the input signal, extracts the clock component, and passes the extracted clock component through a narrow band castle-passing filter to reproduce the clock. .. However, in recent years, in order to further save the transmission bandwidth, spectrum shaping characteristics with a small roll-off factor have been used, and therefore, further improvement in clock reproduction performance has been required.

【0003】

As a clock reproduction circuit that meets such a demand, for example, a control method as shown in FIG. 11A has been proposed. This is to detect the phase control signal of the clock before and after the zero cross point, and here, this control method is called the zero cross control method.

【0004】

The zero cross control method will be described. (A) of FIG. 11 (A) shows a simplified eye pattern of a binary digital signal, and on average, there is no problem with the signal state itself. Then, when sampling this binary digital signal, if the sample timings match the phase of the signal as in S1 and S2, the transmission code can be correctly captured, so that the data can be reproduced correctly.

【0005】

Next, as shown in (b) of FIG. 11 (A), let us consider what happens when the sample timing shifts to the S1'and S2'positions with a delay of Te seconds. In this case, the shift from S1 to S1' narrows the eye pattern opening of the binary digital signal from W0 to W1, while the timing that should be sampled at S2, which is the zero crosspoint position, also shifts by Te seconds. The input signal is sampled at the timing position of S2'in (c) of Fig. 11 (A), and if the sampled value (sample value) at this sampling timing is e, this e was originally near zero. It will take a larger value than it should be.

【0006】

By the way, in this case, if the transmission code changes from "-1" to "+1" before and after the zero cross point, the sample value takes a positive value of e (-+), and conversely from "+1". When it changes to "-1", the sample value takes a negative value of e (+-). Therefore, by knowing the transmission code before and after the zero cross point, it is possible to know the deviation of the sample timing. This is the principle of zero cross control.

【0007】

As described above, since the zero cross control method uses the value near the zero cross point, it has a characteristic that it operates regardless of the amplitude of the eye pattern. However, in reality, the eye pattern has a waveform as shown in Fig. 12, and e (-+) and e (+-) may not be zero even if the clock phases are synchronized. Since a control signal is generated, the problem of a large amount of jitter remains.

【0008】

On the other hand, a control method as shown in Fig. 11 (B) has also been developed. This is a method of detecting the phase control signal of the clock before and after the eye pattern convergence point, and here, this is referred to as an eye convergence point control method. That is, the eye convergence point control method is the following control method. (A) of FIG. 11 (B) shows the eye pattern of the binary digital signal, and T-1, T0, and T1 of (b) of FIG. 11 (B) show the optimum clock phase. In this example, sampling is performed by a 2-bit A / D converter at reference levels L1, L2, and L3, but an example using a multi-value A / D converter will be considered. When the transmission code changes to a-1, B0, C1, if the clock phase is shifted by + Δt, the sample value will be larger than the reference level L1, and if it is shifted by -Δt, the sample value will be higher than the reference level L1. It will be a small value.

【0009】

Therefore, the deviation of the sample timing can be detected by the difference value between the transmission code before and after the control point and the reference level at the control point.

【0010】

As described above, since the value near the eye convergence point is used in the eye convergence point control method, the jitter at the time of phase synchronization can be reduced. However, when the amplitude of the eye pattern changes, the difference value from the reference level does not accurately indicate the deviation of the sample timing, so that there is a problem that the clock phase cannot be controlled.

【0011】

Therefore, as a clock reproduction circuit for solving these problems and improving the performance of clock reproduction, a technique as shown in Japanese Patent Application No. 4-126041 (see Japanese Patent Application Laid-Open No. 5-327681) has been developed. ..

【0012】

This is as shown in FIG. 13, and is called a clock phase error detection control method. This clock phase error detection control method will be described. FIG. 13 (a) shows the eye pattern, and shows the case where the sample values of the eye convergence points are L0 and -L0. Now, consider the case where the clock phase is shifted by + Δt. If the transmission code changes to "A1" and "B2" in this state, the sample value of "A1" is "-(L0-Δl)" and the sample value of "B2" is "(L0 + Δl)". Become. Here, comparing the absolute values of each sample value, | L0 + Δl |-|-(L0-Δl) | = 2Δl> 0 In terms of absolute value, the sample value of "B2" is larger.

【0013】

When the transmission code changes to B1 and A2, the sample value of B1 becomes (L0-Δl) and the sample value of A2 becomes -(L0 + Δl). Here, comparing the absolute values of each sample value, |-(L0 + Δl) |-| (L0-Δl) | = 2Δl> 0 It can be seen that the sample value of "A2" is larger in absolute value.

【0014】

That is, when the clock phase is delayed (clock phase + Δt), the absolute value of two consecutive samples is larger than the latter value, and the clock phase is similarly advanced (clock phase -Δt). In the case of "), it can be seen that the absolute value of two consecutive samples is smaller than the later value.

【0015】

As a result, the phase difference can be obtained by obtaining the amplitude difference between two consecutive samples.

【0016】

That is, when the phase error in the clock phase error detection control method can be detected, as shown in FIG. 14, which is a diagram schematically showing the principle described in FIG. 13, four consecutive symbols of the input pulse code are used. When the input pattern, which is the generation pattern of, takes the positions of the symbols "A0", "A1", "B2", and "B3", if the sample points are shifted by Δt, the phase error can be calculated as 2Δl. You can.

【0017】

On the contrary, FIG. 15 shows an example in which the phase error cannot be detected. In this example, the input pattern of the input signal, which is the generation pattern of four consecutive symbols of the input pulse code, is the symbol ". When the positions of "B0", "A1", "B2", and "A3" are taken, if the sample points are shifted by Δt, the phase error becomes O and cannot be obtained.

【0018】

Therefore, the clock phase error detection control method disclosed in Japanese Patent Application No. 4-126041 can detect the phase error by monotonically increasing or monotonically increasing the input signal between immediately before the sample timing T1 and immediately after the next sample timing T2. Only when it is decreasing.

【0019】

This is the case where the signal is as shown in Fig. 14, and the input pattern of four consecutive symbols takes the positions of "A0", "A1", "B2", "B3", and "B0", "B1". There are a total of two cases in which the positions of "," A2 ", and" A3 "are taken. Since there are 16 input pattern variations of 4 consecutive symbols, the phase error can be detected by the clock phase error detection control method only with a probability of "1/8" for the input data, and "1/8". The phase error can only be obtained with a low probability of ".

【0020】

As described above, since the probability that the phase error can be detected is low, the clock reproduction at a low C / N is insufficient.

【0021】

[Problems to be Solved by the Invention]

In a system that transmits a digital signal using a band-limited pulse wave, in order to save the transmission bandwidth, a spectrum shaping characteristic with a small roll-off factor is used, and therefore the performance of clock reproduction is further improved. Has come to be required. Then, as a clock reproduction circuit that meets such a demand, a technique as shown in Japanese Patent Application No. 4-126041 (see Japanese Patent Application Laid-Open No. 5-327681) has been developed.

【0022】

However, this technique can detect a phase error only when the input signal is monotonically increasing or decreasing between immediately before the sample timing and immediately after the next sample timing.

【0023】

There are only two input patterns, but there are 16 input patterns for four consecutive symbols. Therefore, it is the input data that can detect the phase error by the clock phase error detection control method. On the other hand, the phase error can be obtained only with a probability of "1/8" and a low probability of "1/8".

【0024】

As described above, since the probability that the phase error can be detected by the conventional method is low, there is a problem that the clock reproduction performance at a low C / N is insufficient.

【0025】

Therefore, an object of the present invention is to be able to detect a phase error with a high probability, obtain a clock phase error signal used for phase correction of a clock reproduction circuit, and satisfy the clock reproduction performance at a low C / N. An object of the present invention is to provide a clock phase error detection circuit and a clock phase error detection method.

【0026】

[Means for solving problems]

In order to achieve the above object, the present invention is configured as follows. That is, in a clock phase error detection circuit that obtains a clock phase error signal for reproduction clock phase correction used in a circuit that reproduces a clock synchronized with a predetermined phase from a band-limited pulse code signal, the pulse code signal is used as the clock. A determination means that detects the code pattern of the signal obtained by sampling and determines the pattern, and a phase error calculation that obtains a clock phase error signal from the determined code pattern and the sampled signal by a predetermined phase error operation. It is characterized by having means. Further, in particular, the phase error calculation means is configured by an FIR filter, and the phase error calculation is characterized in that the coefficient of the FIR filter is switched according to the detected code pattern.

【0027】

In the present invention, when reproducing a clock synchronized with a predetermined phase from a band-limited pulse code signal, the code pattern of the signal obtained by sampling the pulse code signal by the clock is detected and the pattern is determined. The phase error is obtained by a predetermined calculation from the determined code pattern and the sampled signal. Then, the obtained phase error is used for phase correction of clock reproduction.

【0028】

Further, if the FIR filter is used, the phase error calculation means can be easily configured, and the error calculation can detect the phase error in all the continuous code patterns by changing the filter coefficient to correspond to the input pattern. This makes it possible to quickly correct the phase shift when the clock phase shift occurs during clock reproduction.

【0029】

In particular, the present invention detects a code pattern of a signal sampled by the clock in a circuit that reproduces a clock synchronized with a predetermined phase from a band-limited pulse code signal, and responds to the detected code pattern. By calculating the phase error, it becomes possible to detect the phase error in all the continuous code patterns, so that the phase error can be detected in many cases, and therefore, the probability that the phase error can be detected from the input signal. It is possible to improve the clock reproduction performance at a low C / N (carrier noise ratio).

【0030】

Therefore, according to the present invention, it is possible to reproduce a clock that satisfies the clock reproduction performance at a low C / N.

【0031】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, examples of the present invention will be described with reference to the drawings.

【0032】

(Example 1) FIG. 1 shows a block diagram of an embodiment of the clock phase error detection circuit of the present invention. In the figure, 1 is a phase error calculation circuit, 2 is a pattern judgment circuit, 3 is a level judgment circuit, 4 is a valid judgment circuit, 5 is a hold circuit, 6 is an input terminal, 7 is a threshold input terminal, and 8 is an output terminal. Is.

【0033】

Of these, the input signal obtained by sampling the received pulse code signal at the reproduction clock timing is input to the input terminal 6. The pulse code signal here is a band-limited pulse code signal. The phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal, and gives the error data which is the calculation result to the hold circuit 5.

【0034】

The pattern determination circuit 2 is for determining the code pattern of the input signal input from the input terminal 6, and the level determination circuit 3 is for determining the level of the input signal input from the input terminal 6. Therefore, it is detected that the level of the input signal is higher than the threshold value supplied from the threshold value input terminal 7.

【0035】

The valid determination circuit 4 determines whether the pattern determination result by the pattern determination circuit 2 and the level determination result by the level determination circuit 3 are satisfied at the same time, and if they are satisfied, they are "valid", and if they are not satisfied, they are "invalid". When the determination result of the valid determination circuit 4 is "valid", the hold circuit 5 passes the error data output by the phase error calculation circuit 1 as it is, and passes this as it is to the clock phase error signal. If the determination result of the valid determination circuit 4 is "invalid", the error signal of the phase error calculation circuit 1 immediately before that is held as a hold signal and output as a clock phase error signal. The clock phase error signal from the hold circuit 5 is output to the output terminal 8.

【0036】

In this apparatus having such a configuration, an input signal obtained by sampling a pulse code signal at the reproduction clock timing is input from the input terminal 6. This input signal is branched into the phase error calculation circuit 1, the level determination circuit 3, and the pattern determination circuit 2.

【0037】

First, the level determination circuit 3 detects that the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Since it is a problem if this threshold value is too large or too small, the optimum value is empirically selected according to the purpose, but as shown in Fig. 2, the input is standard. A value close to 50% of the signal levels + L0 and -L0, for example, + L0 / 2 and -L0 / 2 are preferable.

【0038】

In this embodiment, since the phase error is calculated using "4 samples" as described later, in the level determination circuit 3, continuous "4 samples" are simultaneously larger than the threshold value even in this level determination. Try to judge. The determination result is supplied to the validity determination circuit 4.

【0039】

Next, the pattern determination circuit 2 determines the code pattern of the 4 samples. Then, the determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for the phase error calculation, and is also supplied to the validity determination circuit 4 to determine whether or not the pattern is effective for the error calculation. Will be done.

【0040】

The valid determination circuit 4 determines whether or not the pattern determination result and the level determination result are satisfied at the same time. That is, when the continuous "4 samples" code pattern matches the pattern in which the phase error calculation can be performed and the signal amplitude is larger than the predetermined threshold value, it is determined to be "effective". If the above two determinations are not satisfied at the same time, it is determined as "invalid", and the "invalid" determination signal is supplied to the hold circuit 5 as a hold signal.

【0041】

On the other hand, the phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal, and supplies the error data which is the calculation result to the hold circuit 5. The hold circuit 5 outputs the error data supplied from the phase error calculation circuit 1 to the output terminal 8 as a clock phase error signal. However, when the hold signal is supplied from the valid determination circuit 4, the clock phase error signal immediately before that is held, and the error data supplied from the phase error calculation circuit 1 is determined to be "invalid".

【0042】

Therefore, when the determination result of the valid determination circuit 4 is "valid", the hold circuit 5 passes the error data output by the phase error calculation circuit 1 as it is, and outputs this as a clock phase error signal to the output terminal 8. If the determination result of the valid determination circuit 4 is "invalid", the error signal of the phase error calculation circuit 1 immediately before that is held as a hold signal and output to the output terminal 8 as a clock phase error signal. <Structure of Phase Error Calculation Circuit> Next, a specific embodiment of the phase error calculation circuit 1 will be described with reference to FIG. As shown in FIG. 3, the phase error calculation circuit 1 adds the delay elements 201,202,203,204 of the serial connection, the variable coefficient devices 205,206,207,208 and the variable coefficient devices 205,206,207,208 to which the delay outputs from the respective delay elements 201,202,203,204 are supplied. It is realized by the FIR filter composed of the adder 209.

【0043】

The sampling signal is supplied from the sampling signal input terminal 210. The sampling signal supplied from the sampling signal input terminal 210 is supplied in the order of the delay element 201, the delay element 202, the delay element 203, and the delay element 204. The delayed signals are amplified by the corresponding variable coefficients 205, 206, 207, 208 of the variable coefficients 205, 206, 207, 208 according to the respective coefficients, and then added by the adder 209 to complete the error calculation, and the error calculation is completed from the output terminal 212. It is output to the hold circuit 5 as error data.

【0044】

A coefficient switching signal is supplied to the input terminal 211 from the pattern determination circuit 2, and the coefficients C3, C2, C1, C0 of the variable coefficient devices 205, 206, 207, 208 are controlled according to the coefficient switching signal to switch the filter characteristics.

【0045】

<Method of error calculation> The method of error calculation will be described with reference to FIG. (A) in FIG. 4 is a sampling signal supplied from the input terminal 210. The code patterns of the signals shown here are A0 (= -L0), A1 (= -L0), B2 (= + L0) , and A3 (= + L0) in FIG. For this code pattern, as shown in FIG. 4 (b), the variable coefficient device (C0) 205, the variable coefficient device (C1) 206, the variable coefficient device (C2) 207, and the variable coefficient device (C3) 208 When a FIR filter is configured by setting the coefficients to "-1", "+2", "0", and "-1" in order, the FIR filter output, that is, the error calculation result has a clock delay of 1 clock. If there is, it will be "-3L0", if there is no clock delay, it will be "0", and if there is one clock advance, it will be "+ 3L0", as shown in Fig. 4 (c).

【0046】

The coefficients in FIG. 4 (b) indicate C0 = -1, C1 = 2, C2 = 0, and C3 = -1, and the values shown in FIG. 4 (a) are used. When the sample value is taken (sample value is L0 or -L0), the phase error is zero, and the value at time t in Fig. 4 (c) is the error calculation. The result.

【0047】

Here, consider the case where the clock phase error is one clock. Then, as can be seen from Fig. 4 (c), when the time t is delayed by 1 clock, the time t is in the state of t = -1, so the filter output at this time is -3L0, which is advanced by 1 clock. In this case, since the time t is in the state of t = + 1, it can be seen that the filter output at this time is + 3L0.

【0048】

The above considers the input signal as a sampled value, but when a continuous signal with a band-limited pulse code is input, a continuous result as shown in FIG. 4 (d) can be obtained. This means that when the sampling timing shift, that is, the sampling phase error occurs, the filter output changes in the vicinity of the time t = 0 shown in FIG. 4 (d).

【0049】

As described above, in the phase error calculation circuit 1 in this embodiment, the filter output constituting the phase error calculation circuit 1 takes a positive value when the clock phase is delayed, and takes a negative value when the clock phase is delayed. Further, since it becomes zero when there is no phase error, the filter output, that is, the output of the phase error calculation circuit 1 represents the phase error.

【0050】

FIG. 5 shows the filter coefficients that can be calculated for errors in each input pattern. Although it depends on the symbol values before and after "4 symbols", according to the phase error calculation circuit 1 configured by the filter in FIG. 3, all of them continuously increase from the phase delay time to the phase advance time as shown in FIG. 4 (d). You can get the filter output to do.

【0051】

Then, according to the phase error calculation circuit 1 configured by the filter of FIG. 3, the error calculation is possible for "16 patterns" among the "16 patterns" of the code pattern of "4 symbols" as shown in FIG. Is.

【0052】

That is, when the phase error can be detected, the input patterns are [1] A0, A1, B2, as shown in FIG. 6, which is a diagram schematically showing the principle described in FIG. When arranging "B3", when arranging [2] "B0", "B1", "A2", "A3", when arranging [3] "A0", "A1", "B2", " When arranging "A3", [4] When arranging "B0", "B1", "A2", "B3", [5] "A0", "B1", "A2", "A3" When arranging [6] B0, A1, B2, B3, when arranging [7] A0, A1, A2, B3 When arranging, [8] "B0", "B1", "B2", "A3" When arranging, [9] "B0", "A1", "A2", "A3", When taking the arrangement of [10] "A0", "B1", "B2", "B3", when taking the arrangement of [11] "A0", "B1", "B2", "A3" When [12] B0, A1, A2, B3 are arranged, and [13] A0, B1, A2, B3 are arranged, [14] When the arrangement of "B0", "A1", "B2", and "A3" is taken, the phase error can be obtained according to the phase shift of the sample points in a total of 14 patterns.

【0053】

Contrary to this, Fig. 7 shows an example in which the phase error could not be detected in the past, but in this example, when the input patterns are "B0", "B1", "B2", "B3", and , "A0", "A1", "A2", "A3", even if the sample points deviate, the phase error becomes "O" and cannot be obtained.

【0054】

However, this can also detect the phase error in the present invention.

【0055】

In other words, the variation of the code pattern of "4 symbols" is [15] "B0", "B1", "B2", "B3" when the arrangement is taken as shown in Fig. 5, [16] "A0", There are a total of "16 patterns" including when "A1", "A2", and "A3" are arranged, but such signs do not change "A0", "A1", "A2". Error calculation is possible, including a total of two patterns, one with the arrangement of "A3" and the other with the arrangement of "B0", "B1", "B2", and "B3". This means that the phase error detection accuracy is higher than that of the conventional error calculation method.

【0056】

In order to prevent deterioration of phase error detection accuracy due to pattern judgment error at low C / N, if the amplitude of the sampling signal is smaller than the predetermined threshold value, the error calculation result is not used immediately before. The hold circuit 5 operates to hold the phase error signal of.

【0057】

Then, the phase error signal obtained through the hold circuit 5 is used as the phase control signal to perform phase control of the clock reproduction circuit, and the phase shift of the reproduction clock is corrected to correspond to the phase control signal.

【0058】

In this embodiment, if the sample points deviate from a total of 16 patterns including 2 patterns in which the appearance form of four consecutive symbols does not change at all, this phase error can be obtained. The phase error signal obtained can be used as a phase control signal to control the phase of the clock reproduction circuit, and the phase shift of the reproduction clock can be corrected to correspond to the phase control signal. Therefore, it is possible to obtain phase error signals for all 16 patterns out of 16 patterns, which are all variations of the symbol arrangement. Therefore, the phase error detection accuracy is dramatically increased as compared with the conventional error calculation method, and the clock reproduction circuit When a phase shift occurs, the phase shift correction control can be quickly executed.

【0059】

Therefore, the phase error can be detected with a high probability, the clock phase error signal used for the phase correction of the clock reproduction circuit can be obtained, and the clock phase error detection at a low C / N can be satisfied. The circuit is obtained.

【0060】

Next, another embodiment of the present invention will be described as Example 2.

【0061】

(Example 2) FIG. 8 is another embodiment of the present invention. In FIG. 8, 1 is a phase error calculation circuit, 502 is a pattern judgment circuit, 3 is a level judgment circuit, 4 is a valid judgment circuit, 5 is a hold circuit, 6 is an input terminal, 7 is a threshold input terminal, and 8 is an output. The terminal 501 is an absolute value circuit that obtains the absolute value of the input signal input from the input terminal 6.

【0062】

In this embodiment, an absolute value circuit 501 is provided in front of the phase error calculation circuit 1, and the input signal input to the input terminal 6 is given to the phase error calculation circuit 1 via the absolute value circuit 501. , The level determination circuit 3 is also different from the first embodiment in that the input signal input from the input terminal 6 is given an absolute value by the absolute value circuit 501 so that the level determination is performed. The configuration of is basically the same as that of the first embodiment. However, in this embodiment, when the input signal sampled at the reproduction clock timing is input to the input terminal 6, the pattern determination circuit 502 determines the pattern for this.

【0063】

Further, the phase error calculation circuit 1 uses an absolute value circuit 501 in which the code pattern of the input signal is converted into an absolute value as an input, performs an error calculation according to the code pattern of the input signal, and performs error calculation as an calculation result. Is given to the hold circuit 5.

【0064】

The level determination circuit 3 is for determining the level of the input signal input from the input terminal 6 that has been converted into an absolute value by the absolute value circuit 501, and is supplied from the threshold input terminal 7. It detects that the level of the input signal is larger than the threshold value, and whether the valid determination circuit 4 is satisfied with the pattern determination result by the pattern determination circuit 502 and the level determination result by the level determination circuit 3 at the same time. If it is satisfied, it is determined to be "valid", and if it is not satisfied, it is determined to be "invalid". The hold circuit 5 determines whether the validity is "valid" when the determination result of the valid determination circuit 4 is "valid". Passes the error data output by the phase error calculation circuit 1 as it is, outputs this as a clock phase error signal, and if the judgment result of the valid judgment circuit 4 is "invalid", uses this as a hold signal and performs the phase error calculation immediately before that. The error signal of the circuit 1 is held and output as a clock phase error signal. The clock phase error signal from the hold circuit 5 is output to the output terminal 8.

【0065】

In this apparatus having such a configuration, an input signal sampled at the reproduction clock timing is input from the input terminal 6. This input signal is branched to the absolute value circuit 501 and the pattern determination circuit 502.

【0066】

Then, the absolute value circuit 501 performs absolute value conversion of the input signal, and then supplies the input signal to the phase error calculation circuit 1 and the level determination circuit 3. Therefore, the phase error calculation circuit 1 and the level determination circuit 3 are given an absolute value of the code pattern of the input signal.

【0067】

Then, the level determination circuit 3 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using "4 samples", it is determined that the continuous "4 samples" are larger than the threshold value at the same time even in this level determination. The determination result is supplied to the validity determination circuit 4.

【0068】

Further, the pattern determination circuit 502 determines the code pattern of the "4 samples" for the input signal from the input terminal 6. Then, the determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for the phase error calculation, and is also supplied to the validity determination circuit 4 to determine whether or not the pattern is effective for the error calculation. To.

【0069】

The valid determination circuit 4 determines whether or not the pattern determination result and the level determination result are satisfied at the same time. That is, when the continuous "4 samples" code pattern matches the pattern in which the phase error calculation can be performed and the signal amplitude is larger than the predetermined threshold value, it is determined to be "effective". If the above two determinations are not satisfied at the same time, it is determined as "invalid", and the "invalid" determination signal is supplied to the hold circuit 5 as a hold signal.

【0070】

On the other hand, the phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal that has been converted into an absolute value, and supplies the error data that is the calculation result to the hold circuit 5. The hold circuit 5 outputs the error data supplied from the phase error calculation circuit 1 to the output terminal 8 as a clock phase error signal. However, when the hold signal is supplied from the valid determination circuit 4, the clock phase error signal immediately before that is held, and the error data supplied from the phase error calculation circuit 1 is determined to be "invalid".

【0071】

Therefore, when the determination result of the valid determination circuit 4 is "valid", the hold circuit 5 passes the error data output by the phase error calculation circuit 1 as it is, and outputs this as a clock phase error signal to the output terminal 8. If the determination result of the valid determination circuit 4 is "invalid", the error signal of the phase error calculation circuit 1 immediately before that is held as a hold signal and output to the output terminal 8 as a clock phase error signal.

【0072】

Then, using this phase error signal as the clock phase error signal, the phase control of the clock reproduction circuit is performed by the amount corresponding to this signal, and the phase shift of the reproduction clock is corrected to correspond to the phase control signal.

【0073】

As described above, the present embodiment is characterized in that the error calculation is performed on the input signal subjected to the absolute value conversion.

【0074】

That is, in this embodiment, the difference from the first embodiment will be described as follows with reference to FIG. In order to obtain the same error calculation result as in the above embodiment for the input signal subjected to the absolute value conversion, the symbol whose sign is converted by the absolute value conversion, that is, the variable coefficient through which the signal having a negative value passes. You just have to convert the sign of the vessel. This can be easily determined from the configuration of the FIR filter.

【0075】

Therefore, if the filter coefficients having 16 variations in FIG. 5 are code-converted when the corresponding input pattern is a negative value to reduce the variations, the filter coefficients become variations as shown in FIG. Focusing on the variation of the filter coefficient, there are seven types of filter coefficient, "A", "A'", "B", "B'", "C", "C'", and "D". I understand.

【0076】

That is, the number of filter coefficients can be reduced by converting the input signal to an absolute value.

【0077】

This means simplification of the circuit configuration, that is, reduction of the circuit scale and facilitation of control. In addition, it can be seen that the coefficients of the filter coefficient variations "A" and "A'", "B" and "B'", and "C" and "C'" are only inverted. For example, when the filter coefficient of variation "A'" is required, if the error calculation is performed with the filter coefficient of variation "A" and the sign of the calculation result is inverted, the filter coefficient of variation "A'" is used. The exact same result as the error calculation is obtained.

【0078】

By doing so, only four types of filter coefficients are required, and it can be seen that error calculation is possible by preparing these four types of filter coefficients.

【0079】

Then, the phase error signal obtained through the hold circuit 5 is used as the phase control signal to perform phase control of the clock reproduction circuit, and the phase shift of the reproduction clock is corrected to correspond to the phase control signal.

【0080】

In this embodiment, if the sample points deviate in all 16 patterns including 2 patterns in which the appearance form of four consecutive symbols does not change at all, this phase error can be obtained. Using the obtained phase error signal (clock phase error signal) as the clock phase control signal, the clock phase control of the clock reproduction circuit can be performed, and the phase shift of the reproduction clock can be corrected to correspond to the phase control signal. Therefore, it is possible to obtain phase error signals for all 16 patterns out of 16 patterns, which are all variations of the symbol arrangement, so that the phase error detection accuracy is dramatically increased compared to the conventional error calculation method, and the clock reproduction circuit When a phase shift occurs, it becomes possible to quickly execute the phase shift correction control.

【0081】

Moreover, in this embodiment, the number of filter coefficients used in the filter constituting the phase error calculation circuit by converting the input signal to an absolute value is changed from 16 patterns to 7 patterns, which is half of the absolute value. It can be further reduced to 4 patterns. Therefore, the circuit configuration can be simplified, that is, the circuit scale can be reduced and the control can be facilitated.

【0082】

Therefore, the phase error can be detected with a high probability, the clock phase error signal used for the phase correction of the clock reproduction circuit can be obtained, and the clock phase error detection at a low C / N can be satisfied. The circuit is obtained.

【0083】

(Example 3) FIG. 10 is an application example of the above embodiment in the case of a receiver that demodulates a quadrature amplitude modulation signal, for example, a QPSK modulation signal.

【0084】

Since the QPSK modulated signal is composed of an I signal and a Q signal, an error calculation is performed on each of the I signal and the Q signal, and a phase error signal is output from each validity determination result. Basically, the configuration shown in FIG. 8 is prepared for two systems, one for the I signal and the other for the Q signal. For the I signal system, the absolute value circuit 501 and the phase error calculation circuit 1 are prepared. It is composed of a pattern judgment circuit 502, a level judgment circuit 3, and a valid judgment circuit 4, and for the Q signal system, an absolute value circuit 706, a phase error calculation circuit 701, a pattern judgment circuit 702, and a level judgment circuit 703. And the validity determination circuit 704.

【0085】

Here, the absolute value circuit 706 is the absolute circuit 501, the phase error calculation circuit 701 is the phase error calculation circuit 1, the pattern judgment circuit 702 is the pattern judgment circuit 502, and the level judgment circuit 703 is the level judgment circuit 3. The circuit 704 is the same as the valid determination circuit 4.

【0086】

In addition to this configuration, an average circuit 707, a selector 708, a delay circuit 709, and an IQ determination circuit 710 are added. The average circuit 707 takes the average of the error data from the I signal and the error data from the Q signal, and obtains the average value of these by receiving the outputs of the phase error calculation circuit 1 and the phase error calculation circuit 701. It is given to the selector 708.

【0087】

In addition, the selector 708 receives the output of the phase error calculation circuit 1, the output of the phase error calculation circuit 701, the output of the average circuit 707, and the output of the delay circuit 709, and makes any of these compatible with the selection signal of the IQ judgment circuit 710. It is selected and output.

【0088】

Further, in the IQ judgment circuit 710, both systems are "valid" based on the validity judgment result of the I signal system output from the validity judgment circuit 4 and the validity judgment result from the Q signal system output from the validity judgment circuit 704. In this case, the output of the average circuit 707, and if only the valid judgment result of the I signal system is "valid", the output of the phase error calculation circuit 1 is displayed, and only the valid judgment result of the Q signal system is "valid". In the case of "", the output of the phase error calculation circuit 701 is selected, and in the case of both the I signal system and the Q signal system, the output of the delay circuit 709 is selected. It is given to the selector 708.

【0089】

Further, the delay circuit 709 delays the output of the selector 708 by one clock and outputs it to the selector 708 again, and obtains a phase error signal delayed by one clock. Therefore, although the hold circuit is not provided in the third embodiment, the delay circuit 709 and the selector 708 play the role of the hold circuit in the second embodiment.

【0090】

In the present device having such a configuration, the I signal sampled at the reproduction clock timing is input from the input terminal 6, and the Q signal sampled at the reproduction clock timing is input from the input terminal 705.

【0091】

Then, the input I signal is branched to the absolute value circuit 501 and the pattern determination circuit 502, and the input Q signal is branched to the absolute value circuit 706 and the pattern determination circuit 702.

【0092】

Then, the absolute value circuit 501 of the I signal system to which the I signal is input performs the absolute value conversion of the input signal and then supplies it to the phase error calculation circuit 1 and the level determination circuit 3. Therefore, the phase error calculation circuit 1 and the level determination circuit 3 are given an absolute value of the code pattern of the input signal.

【0093】

Then, the level determination circuit 3 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using "4 samples", it is determined that the continuous "4 samples" are larger than the threshold value at the same time even in this level determination. The determination result is supplied to the validity determination circuit 4.

【0094】

Further, the pattern determination circuit 502 determines the code pattern of the "4 samples" for the I signal, which is a direct input signal from the input terminal 6. Then, the determination result is supplied to the phase error calculation circuit 1 as a coefficient switching signal for the phase error calculation, and is also supplied to the validity determination circuit 4 to determine whether or not the pattern is effective for the error calculation. To.

【0095】

The valid determination circuit 4 determines whether or not the pattern determination result and the level determination result are satisfied at the same time. That is, when the continuous "4 samples" code pattern matches the pattern in which the phase error calculation can be performed and the signal amplitude is larger than the predetermined threshold value, it is determined to be "effective". If the above two determinations are not satisfied at the same time, it is determined to be "invalid", and the "invalid" determination signal is supplied to the IQ determination circuit 710 as a hold signal.

【0096】

On the other hand, the phase error calculation circuit 1 performs an error calculation according to the code pattern of the input signal that has been converted into an absolute value, and the I error data (error calculation result of the I signal system) which is the calculation result is averaged circuit 707 and the selector 708. Supply to. Then, the averaging circuit 707 outputs the Q error data (error calculation result of the Q signal system) from the phase error calculation circuit 701 for the Q signal system, and outputs the averaged result and gives it to the selector 708.

【0097】

On the other hand, the absolute value circuit 706 of the Q signal system to which the Q signal is input performs the absolute value conversion of the input signal and then supplies it to the phase error calculation circuit 701 and the level determination circuit 703. Therefore, the phase error calculation circuit 701 and the level determination circuit 703 are given an absolute value of the code pattern of the input signal.

【0098】

Then, the level determination circuit 703 detects whether the absolute value of the input signal level is larger than the threshold value supplied from the threshold value input terminal 7. Here, since the phase error is calculated using "4 samples", it is determined that the continuous "4 samples" are larger than the threshold value at the same time even in this level determination. The determination result is supplied to the validity determination circuit 4.

【0099】

Further, the pattern determination circuit 702 determines the code pattern of the "4 samples" for the Q signal, which is a direct input signal from the input terminal 705. Then, the determination result is supplied to the phase error calculation circuit 701 as a coefficient switching signal for the phase error calculation, and is also supplied to the validity determination circuit 704 to determine whether or not the pattern is valid for the error calculation. To.

【0100】

The validity determination circuit 704 determines whether or not the pattern determination result and the level determination result are satisfied at the same time. That is, when the continuous "4 samples" code pattern matches the pattern in which the phase error calculation can be performed and the signal amplitude is larger than the predetermined threshold value, it is determined to be "effective". If the above two determinations are not satisfied at the same time, it is determined to be "invalid", and the "invalid" determination signal is supplied to the IQ determination circuit 710 as a hold signal.

【0101】

On the other hand, the phase error calculation circuit 701 performs an error calculation according to the code pattern of the input signal that has been converted into an absolute value, and the Q error data (error calculation result of the Q signal system) that is the calculation result is the average circuit 707 and the selector. Supply to 708. Then, the averaging circuit 707 outputs the result of averaging the I error data (error calculation result of the I signal system) from the phase error calculation circuit 1 for the I signal system, and gives it to the selector 708.

【0102】

The IQ judgment circuit 710 to which the validity judgment result of the I error data and the validity judgment result of the Q error data are supplied performs the validity judgment and outputs the switching signal corresponding to the judgment result to the selector 708.

【0103】

That is, when the judgment of the IQ judgment circuit 710 is "valid only for the I signal", the I error data from the phase error calculation circuit 1 is selected so as to select the error data from the I signal, and the judgment of the IQ judgment circuit 710 is also performed. When is "valid only for Q signal", the Q error data from the phase error calculation circuit 701 is selected so that the error data from the Q signal is selected, and the judgment of the IQ judgment circuit 710 is "both I signal and Q signal". When "invalid", the output of the delay circuit 709 is selected so as to select the error data one clock before, and when the judgment of the IQ judgment circuit 710 is "both I signal and Q signal are valid", the error from the I signal. The output of the averaging circuit 707 is selected to select the average data of the data and the error data from the Q signal, and this is output to the output terminal 711 as a clock phase error signal.

【0104】

That is, the system of the third embodiment is provided with error calculation and validity judgment functions for the I signal system and the Q signal system, respectively, and the average circuit 707 averages the error data from the I signal and the error data from the Q signal. Is taken and supplied to the selector 708, and the error data from the I signal, the error data from the Q signal, and the phase error signal obtained by delaying the output of the selector 708 by one clock are also supplied to the selector 708, and the IQ judgment circuit. In 710, the switching signal is output to the selector 708 based on the valid judgment result from the I signal and the valid judgment result from the Q signal, and when the valid judgment is only the I signal, the error data from the I signal is selected. When the validity judgment is only the Q signal, the error data from the Q signal is selected, and when both the I signal and the Q signal are "invalid", the phase error signal delayed by one clock is selected. In addition, when both the I signal and the Q signal are "valid", the average of the error data from the I signal and the error data from the Q signal is selected and output as a clock phase error signal. Then, using this clock phase error signal as a phase control signal for correcting the phase shift of the reproduction clock, the phase control of the clock reproduction circuit is performed, and the phase shift of the reproduction clock is corrected to correspond to the phase control signal. I did. This makes it possible to further improve the phase error detection accuracy even in the QPSK method.

【0105】

It should be noted that the present invention is not limited to the QPSK method, and of course, the present invention can be applied to modulation methods such as the BPSK method and the 8PSK method.

【0106】

[Effect of the invention]

As described above, according to the present invention, it is possible to significantly increase the number of input patterns capable of calculating the phase error, so that the clock reproduction performance can be significantly improved. Therefore, the phase error can be detected with a high probability, the clock phase error signal used for the phase correction of the clock reproduction circuit can be obtained, and the clock phase error detection at a low C / N can be satisfied. Circuit and clock phase error detection methods can be provided.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the clock phase error detection circuit configuration example as an Example of this invention.

[Figure 2]

It is a figure for demonstrating the setting example of the threshold value of the level determination circuit used in the apparatus of this invention.

[Fig. 3]

It is a block diagram which shows the structural example of the phase error calculation circuit used in the apparatus of this invention.

[Fig. 4]

It is a figure for demonstrating the operation example of the clock phase error detection circuit of this invention.

[Fig. 5]

It is a correspondence figure of the input signal pattern and the filter coefficient of the phase error calculation circuit of this invention.

[Fig. 6]

It is a figure for demonstrating the pattern of an input signal.

[Fig. 7]

It is a figure for demonstrating the pattern of the input signal which conventionally could not detect the clock phase error at all.

[Fig. 8]

It is a block diagram explaining another embodiment of the clock phase error detection circuit of this invention.

[Fig. 9]

It is a correspondence figure of the input pattern and the filter coefficient of the phase error calculation circuit in another embodiment of this invention.

[Fig. 10]

It is a block block diagram which shows the example of the clock phase error detection circuit of this invention when applied to the orthogonal detection output.

[Fig. 11]

It is a figure for demonstrating the prior art.

[Fig. 12]

It is a figure which shows the example of the eye pattern.

[Fig. 13]

It is a figure for demonstrating the prior art.

[Fig. 14]

It is a figure which showed typically the conventional clock phase error detection method.

[Fig. 15]

It is a figure which shows typically the conventional clock phase error detection method, and is the figure for demonstrating the pattern of the input signal which cannot detect the clock phase error.

[Explanation of symbols]

1,701 ... Phase error calculation circuit, 2,502,702 ... Pattern judgment circuit, 3,703 ... Level judgment circuit, 4,704 ... Valid judgment circuit, 5 ... Hold circuit, 501,706 ... Absolute value circuit, 707. .. average circuit, 708 ... selector, 709 ... delay circuit, 710 ... IQ judgment circuit.