Variable word length data memory

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a microcomputer memory architecture, and more particularly to providing a microcomputer variable word length data memory without increasing processing overhead.

【0002】

[Conventional technology]

Memory architecture design considerations Microprocessor designs need to determine the length of words used to hold the data. Determining the number of bits that make up a word must take into account some design parameters. Such parameters include code efficiency, memory usage, execution time, overall cost, and the like. Generally, in the decision process, each parameter is given the same weight. This equal weighting is widely used, especially in general purpose processors for which a particular application, or even the type of application, is not yet known. However, microprocessors such as dedicated DSPs (or "ASICs") can be designed for specific applications. In such cases, the above design parameters may take different weights with respect to their overall importance in the processor architecture.

【0003】

Word length selection Choosing to provide a long word length, for example 64 bits, generally reduces the overall processing time. The longer the word length, the more data is read and written to memory at one time. The 64-bit architecture also includes a 64-bit data path for transferring data to and from memory one word at a time. Therefore, multiple reads or writes are rarely required to perform complex tasks. However, long word lengths often result in poor memory usage. Most instructions do not require 64-bit for the processor to uniquely identify and execute, even for 64-bit processors. In addition, most data stored in memory does not use 64-bit. That is, a word in memory usually represents a single number, such as 32,543, or a single alphanumeric character, such as "H". Although 64-bit words can represent over trillion numbers, most ordinary alphanumeric characters can be stored in less than 8 bits. Therefore, more than 56 bits of memory are not used per word for each alphanumeric character. Software can be used to increase memory usage. Software techniques include data packing and unpacking, or the use of native bit format words. However, such techniques can have undesired effects on code efficiency, code development time, and the length of time required to execute an instruction. Without such a technique, the data path would be wide, the cost would be high, and the chip area would be large, justifying the resulting speed advantage in the light of the inefficient use of expensive memory. Can't.

【0004】

Choosing to provide short word lengths, for example 8 bits, can make it impossible to perform some relatively complex data functions. Shorter word lengths require fewer data paths, but fewer bits of data are read from or written to memory at one time. Therefore, a large number of reads or writes may be required to perform some tasks. Conversely, as will be explained later, the 8-bit architecture will use memory more efficiently. Choosing a shorter word length reduces the overall production cost. However, the performance of the entire chip also decreases in proportion to the overall cost.

【0005】

Byte length The choice of 16-bit architecture represents a cost-performance compromise. The data path for a 16-bit architecture is relatively narrow. However, such data paths provide acceptable performance for speed-independent applications such as low resolution digital signal processors (ie, DSPs).

【0006】

There are two data lengths that are known to occur frequently in data processing. 8-bit lengths are often found because data formats such as ASCII (US Standard Code for Information Exchange) are commonly used. ASCII represents 256 different characters using the 8-bit format. A one-bit data length representation exists in the data processing algorithm. This single piece of information is useful when a flag or logical tree implementation is desired.

【0007】

Both 8-bit and 1-bit data lengths can be processed with a standard 16-bit word length architecture. In a 16-bit word architecture, an 8-bit data length is called a byte. In such an architecture, each byte of information can be processed separately.

【0008】

[Problems to be Solved by the Invention]

The 16-bit word architecture currently in use has several implementations of 1-bit data. For example, software (or firmware) can be written to track 16 different 1-bit words in a single word of memory. At this time, the software masks all but one bit required for a particular instruction. Another approach is to use an entire word of memory to represent a bit of information. This approach is achieved by setting all 16 bits of a word to be the desired 1-bit value, eg, all 0s or all 1s. Both of these approaches increase overhead. The software masking approach decomposes a single logical bit from a 16-bit word, which increases the number of processing steps and thus increases the processing time. As a result of using an entire word of memory for 1-bit logic, storage space usage is inefficient.

【0009】

The third approach is the use of tagged memory. Such memory is used by dedicated processors that need to represent the characteristics of tagged data types, such as integers, strings, and so on. Currently, processors that use the tagged 1-bit memory approach to store logic levels (or flag types) have increased overhead. The 1-bit memory array is addressed (read or written) separately from the 16-bit word memory array. Memory arrays are not connected in parallel so that reading or writing to one address retrieves information from both.

【0010】

Normally, the word length of internal memory matches the width of the register length of the data path. Some processors can perform byte (ie, half-word) operations in addition to full-word read and write. However, most processors do not use single-bit memory locations and instead use the software techniques described above.

【0011】

[Means for solving problems]

Variable word length data memory The present invention discloses a more efficient method of storing and manipulating data of different bit lengths. Handles data with different word lengths, such as full 16-bit data words, 8-bit half-words, and 1-bit data. As with most 16-bit architectures, the lower 16 bits of this architecture are read into two byte-width (8-bit) registers. With this configuration and arrangement, writing of data bytes to 16-bit data memory and reading of data bytes from 16-bit data memory are performed with zero overhead. All bytes are right-justified within a central processing unit (CPU) of byte length. Therefore, the data is efficiently read and written as bytes in the CPU.

【0012】

To handle 1-bit flags or logical data, 1-bit data RAM is connected in parallel with 16-bit data RAM, effectively forming 17-bit RAM. The address source is shared by 1-bit data RAM and 16-bit data RAM per CPU cycle. As a result, the 16-bit length data RAM and the 1-bit length data RAM form one addressable data word that is effectively 17 bits long. However, the write control of the data memory is independent for each of these two RAMs.

【0013】

The value stored in the corresponding 1-bit data RAM is read for each read access of a certain location in the 16-bit data RAM. Next, this 1-bit value is stored in the status register. Next, the program judgment can be made directly based on the bit value of the stored status register.

【0014】

When 16 bits of data are written to the 16-bit data RAM, the 17th bit, that is, the bit stored in the 1-bit data RAM, is unchanged. A 1-bit arithmetic logic unit (ALU) and a 1-bit arithmetic logic unit (ALU) to read, write, modify, and test a 1-bit data RAM without changing the contents of the data stored in the 16-bit data RAM. A class of program instructions is provided. In this way, direct procedures are provided for manipulating 1-bit data without the need for 16-bit overhead or utilization, and more efficient and natural programming procedures are provided to manage algorithmic decisions. Be done.

【0015】

The advantage of this disclosure is that efficient memory utilization for logic bits and flags does not require encoding and decoding logic, a simpler ALU structure, and more natural logic decisions in combined software programs. It is suitable.

【0016】

One particularly advantageous use for this extension bit is for conditional execution of instructions, especially branch and jump instructions.

【0017】

As another example, an instruction can be executed in a range of locations, conditionally depending on the status of the extension bits at each address.

【0018】

As another example, extended bits can be used as flags to chain a large number of words together to perform extended precision operations, as described further below.

【0019】

As another example, the extension bit can be used as a tag so that the execution branches at the tag when the extension bit is set.

【0020】

As another example, the extension bit can be used as a flag to mark the boundaries of the circular buffer. This is particularly useful, for example, to perform a finite impulse response filtering function.

【0021】

The disclosed invention will be described with reference to the accompanying figures. The accompanying figures show important embodiments of the present invention and are incorporated herein by reference.

【0022】

BEST MODE FOR CARRYING OUT THE INVENTION

A number of innovative teachings of the present application will be described in particular with reference to current preferred embodiments. However, it should be understood that examples of this type provide only a few examples of the numerous advantageous uses of the innovative teachings of this application. In general, the description of the present specification does not necessarily limit any of the various claimed inventions. Moreover, depending on the description, it may correspond to some invention features, but may not correspond to other invention features.

【0023】

Suitable system background The system background of this preferred embodiment is a mixed signal processor (MSP) such as the MSP58P70 manufactured by Texas Instruments. A product preview for this chip is available from Texas Instruments, Dallas, TX, Dallas, Texas, USA, as of the effective filing date of this application. A functional block diagram of a suitable system is shown in FIG. This figure shows a block diagram of the architecture of MSP58P70. The MSP58P70 is an MSP with enhanced microcontroller functionality and a limited set of digital signal processor (DSP) instruction. DSP functionality is supported by the basic multiplier / accumulator structure. In addition to DSP functionality, this chip provides efficient string and bit manipulation capabilities.

【0024】

Microprocessors according to preferred embodiments, or more simply processors, are generally useful and are particularly useful in applications such as high speed computers and medium speed digital signal processor (DSP) systems. Processors can be used with a variety of different memory configurations and with a variety of different peripherals to create a variety of application-specific consumer products.

【0025】

The basic architecture of the processor of this preferred embodiment includes a high-speed computational unit (CU) and a full-featured data memory address unit (DMAU). Separate memory spaces for data and programs are provided on the processor die or chip, allowing parallel access and maximum computational throughput. To minimize power consumption, static logic circuit implementations form the functional blocks of the processor, and most functional blocks are disabled when not in use. Combining a number of different internal memory sizes and types with customized peripherals and interrupt logic can provide a variety of customized devices, each of which is different and useful.

【0026】

In this preferred embodiment (but not limited to this preferred embodiment), the memory of programs and data is limited to internal memory blocks that cannot be expanded by the use of external memory. Program memory contains, for example, a 17-bit word 64K amount of ROM, EPROM, or OTP. The data memory is RAM. According to the gist and scope of the present invention, different embodiments include different combinations of program and data memory sizes, the program memory generally containing at least 16K of 17-bit words. When a large-capacity data storage device is required, an auxiliary data memory peripheral interface can be provided.

【0027】

To merge the numerical processing requirements in both the computer and DSP areas, the processor has a 16-bit word length. This choice also sets the processor's program address limits to approximately 64K words, each 16-bit long.

【0028】

Processor architecture As shown in FIG. 8, the processor 10 according to the preferred embodiment includes a number of major subblocks such as program-data memory block 11, data memory block 12. The main subblocks include the above computational unit or CU13, the above data memory address unit or DMAU14, the program counter unit or PCU15, and the instruction decoder 16. .. Other functions are provided by the iteration or chain counter register 17, the status register 18, two timers 19 and 20, the interrupt logic circuit 21, and the peripheral extension interface 22.

【0029】

The 17-bit data bus (DB) 23 provides communication between functional blocks within processor 10. Most of the registers in processor 10 have read and write access to DB23. Bus drivers (not shown) are static devices to avoid unnecessary power consumption and to give maximum logical propagation time. The minimum instruction cycle of processor 10 is about 100 ns, and a 10 MHz processor clock (not shown) is provided.

【0030】

The data memory 12 of FIG. 8 is configured as a plurality of 17-bit parallel words. The number of words varies depending on the intended use of the processor 10, but the range of 256 words to 2048 words is typical. Figure 8 shows 1152 words. Each address 51 given by DMAU14 addresses 17 bits of data. These 17 bits are subjected to a number of different actions, depending on the instruction being executed. For most instructions, this data is interpreted in 16-bit word format. For 2-byte instructions such as LACB and SACB, processor 10 reads and writes data in an 8-bit word format, also known as the byte format. In this byte format mode, the processor hardware reads and writes the high or low byte of the addressed 16-bit word. The fetched bytes are right-justified on DB23.

【0031】

In flag data mode, the instruction operates only on the 17th bit of the fetched word. For all reads in data memory 12, the 17th bit is always read and then loaded into the MTAG bit in status register 18 in FIG. 8, so word or byte data can be tagged. .. In byte mode, two consecutive bytes are combined with the same tag. Tagged data is used by the FIR, FIRK, COR, and CORK instructions to emulate a circular buffer. The MTAG bit in the status register can also be tested as a condition for a branch / call instruction, or it can be combined with other test conditions and other flags to create a new state.

【0032】

MSP58P70 architecture The MSP58P70 has a powerful instruction set. Instructions can individually address bits, bytes, words, word strings, or byte strings. The program memory is 17 bits wide and the entire 17 bit width is used to code the instruction set. The program is executed from the internal program memory. It cannot be executed from external memory. Both the MSP58P70 program and data memory are limited to internal blocks and cannot be extended externally. In this preferred embodiment, the program memory is a One Time Programmable ROM (OTP) and is limited to 32K 17-bit words. 2K in it is reserved for internal test code and cannot be accessed by user programs. In this preferred embodiment, the data memory is also static RAM and is limited to 1024 17-bit words. The 16 bits of it are calculated values, and the 17th bit is used as a flag or tag.

【0033】

17-bit memory The MSP data memory array is organized in 17-bit words. FIG. 2 shows a block diagram of the memory organization of a typical 16-bit data memory array. The memory array 102 is organized so that bit 0-7, which is the lower byte of the word, is accessed by line 0-7 of the memory array data path. However, the high-order byte of each word can be read to the internal register of the MSP by line 0-7 of the data path of the memory array and can be read on line 8-15 of the data path. Bytes of data sent on lines 8-15 of the memory array data path can be written to the upper or lower bytes of the word in memory array 102. Byte-based instructions in the MSP instruction set properly multiplex byte data into upper or lower bytes.

【0034】

FIG. 1 is a block diagram showing a memory organization of a variable length data memory array. The 1-bit memory array 104 is connected in parallel with the 16-bit memory array 102, effectively creating a 17-bit memory array. The address source is shared by both the 1-bit and 16-bit memory arrays. The entire contents of a 17-bit word can be read with a single address. However, write control is independent for each of these two arrays. The write control for the lower 16 bits of the word is the same as that of the memory array described in FIG. When writing bytes or words, the data is written to the 17th bit.

【0035】

Data memory format The data memory blocks shown in Figure 1 are physically organized as 17-bit parallel words. The 17th bit can be used as a tag bit or flag bit for complex branching conditions. That is, a branch without a corresponding test can be performed based on the flag bit. The third data mode is flag data when the MSP instruction operates only for the 17th bit.

【0036】

In this preferred embodiment, the size of the MSP58P70 data memory block is 1024 17-bit locations. Each address given directly by the data memory address unit (DMAU) addresses 17 bits of the data. These 17 bits are subjected to different actions depending on the instruction being executed. For most instructions, the data is interpreted as a 16-bit word format. Byte instructions such as MOVB (instructions ending in B generally use byte-addressable arguments) allow the processor to read and write data in 8-bit byte format. Byte mode allows the hardware to read or write the high or low byte of a 16-bit word based on the least significant byte (LSB) of the address (the address is a byte address, not a word address). , Words are right-justified on the data bus.

【0037】

Data memory organization and addressing MSP has instructions for addressing bits, bytes, words, and strings in both data and program memory. Figure 4 shows the data memory organization of bytes, words, and flag data. Data memory is accessed in bytes by hardware. The instructions used to retrieve the data treat the retrieved data as bytes, words, strings, or flags.

【0038】

Individual bytes can be addressed by MSP. In general, MSPs address individual bytes with just a load or store instruction (these instructions usually end with a "B" suffix). Otherwise, the entire word will be addressed. Load and storage routines that address bytes can take advantage of physically multiplexing the high-order bytes of a word into the low-order bytes of memory or a search register. A byte string is one byte longer than the string. The length of the string is stored in the string register (STR). Byte string data is fetched one byte at a time until the string length (in bytes) is reached. One word consists of two consecutive bytes. Instructions that work on a word have internal hardware that properly increments the byte address to load two consecutive bytes in one clock cycle. Like byte strings, word strings use STR registers to receive strings of words that are STR word lengths.

【0039】

Flag (or tag) addressing uses linear addressing from 0 to the size of data memory in words. In flag addressing, only the 17th bit of each word can be addressed. However, when a word or byte data memory location is read, the corresponding flag for that location is always loaded into the TAG bit in the status register (STAT). In this case, the flag address used to read the 17th bit is a valid address created by shifting the word or byte address one bit to the right. If a string instruction is used, the flag bit of the last memory location in the string is loaded into the STAT TAG bit. The following global or relative flag addressing is used to address the flags. In this preferred embodiment, class 8 instructions can be used to individually set or reset the flag bits.

【0040】

Flag address specification In this preferred embodiment, the MSP machine level instruction set is divided into classes according to the memory, hardware registers, and field references combined with the control fields. The MSP executes a class of instructions (class 8) that is supposed to be used to access the 17th bit (flag bit) of each word in data memory. All flag instructions are executed in one instruction cycle. Flag addressing can be used to load or save flag bits, or to perform various logical actions without affecting the remaining 16 bits of the selected word. Two addressing modes are provided. The first addressing mode is called global flag addressing. In the global flag address specification, bit 0 is set to zero and a 6-bit field (b1-b6) defines the flag address. Flag global addressing gives access to 64 global flags from a base offset of 000h. These flags are located at the first 64 addresses in memory. The second mode is called relative flag addressing. In the relative flag address specification, bit 0 is set to 1, and the same 6-bit field defines the relative flag address for the contents of register R6, that is, valid address = (contents of R6) + (offset of 6 bits). FIG. 3 is a block diagram showing a relative flag addressing offset derivation. Flag relative addressing gives access to 64 different flags from the positive offset values stored in the MSP page (R6) registers.

【0041】

In the following instruction example, bits 0-6 of the flag instruction are indicated by {flagadrs} and are assigned to the instruction syntax by known values during execution. For example, the instruction AND TFn, {flagadrs} can be written as:

【0042】

AND TF1, * 0x21 Global flag address specification, flag address is 0x21 absolute or AND TF2, * R6 + 0x21 Relative flag address specification, flag address is R6 + 0x21 absolute.

【0043】

Here, TF1 and TF2 are the test flags (bits 14 and 15 of the MSP's 17-bit status register, respectively). R6 indicates that the page register is the source of the flag address offset. If bit 0 of either of these instructions is 0, then bits 1-6 of {flagadrs} are used as the bit addresses starting at data memory location 0. When bit 0 is 1, by using bits 1 to 6 as an offset from the page register R6, the relative address operation is performed as follows.

【0044】

Flag {flagadrs} Flag addressing mode encoding flagadrs Address Syntax 6543210 Mode flag address bit global / relative bit Glow * dma6 dma6 0 Bar Relative * R6 + offset6 1 offset6 [0045]

Logic and bit instructions In this preferred embodiment, the class of instructions acting on the 17th bit is intended for use with both logical and flag type applications. Instructions of this class provide a flexible and efficient means of making complex logical decisions. Instead of making a series of single-bit decisions to construct a logical statement through a branch decision tree, the program can directly construct the final logical value (TF1 or TF2) by sequentially combining several status conditions. it can. This final logical value can be used to connect subsequent branches or procedure calls. This class contains two subclasses. Subclass 8a instructions update one of the test flags (TF1 or TF2) with a logical combination of the old test flag value and the addressed memory flag value. Subclass 8b instructions provide a flexible way to logically combine test flags (TF1 or TF2) with status conditions and return the results to test flags for storage.

【0046】

In this preferred embodiment, the instruction is represented to the MSP by the following operation code.

【0047】

[table 1]

<img file="JP2000200215A_D0001.tif" />【0048】

The 8a code indicates the specific bit instruction to be executed. For example:

【0049】

8a mnemonic description code 000 MOV TFn, {flagadrs} Single bit valid flag memory Address value or * its complement to TF1 or TF2 in the status register To Addressed by the 010 OR TFn, {flagadrs} instruction Single-bit valid flag memory address (or inverted value if N = 1) ) And TF1 or TF2, and return to TF1 or TF2, respectively. And remember. Addressed by the 100 AND TFn, {flagadrs} instruction Single-bit valid flag memory address (or inverted value if N = 1) ) And TF1 or TF2, and set them to TF1 or TF2, respectively. Return and memorize. Addressed by 110 XOR TFn, {flagadrs} instruction Single-bit valid flag memory address (or inverted value if N = 1) ) And TF1 or TF2, and find the exclusive OR, respectively, TF1 or TF Return to 2 and memorize. Memory of 001 MOV {flagadrs}, TFn TF1 or TF2 Remember in location. 011 RFLAG {flagadrs} Single bit valid flag memory Reset the address value to 0. 101 SFLAG {flagadrs} Single bit valid flag memory Set the address value to 0.

【0050】

Similarly, the 8b code represents a particular 8b imperative type to be performed.

【0051】

8b mnemonic description code 00 MOV TFn, {cc} [, Rx] The logical value of the tested condition Low to one of the test flag bits in the status register, TF1 or TF2 To do. 01 OR TFn, {cc} [, Rx] Two in the status register One of the two test flags (TF1 or TF2) with the specified status condition And OR are obtained to change logically. 10 AND TFn, {cc} [, Rx] Two in the status register One of the two test flags (TF1 or TF2) with the specified status condition And AND, it changes logically. 11 XOR TFn, {cc} [, Rx] Two in the status register One of the two test flags (TF1 or TF2) with the specified status condition And logically change by finding the exclusive OR. For this instruction, the pole of N The sex is reversed (N = 1 for XOR, N = 0 for XNOR).

【0052】

Figure 5 shows a bit logic unit (BLU) in combination with a flag register. A bit logical unit is a single-bit arithmetic logic unit (ALU) that operates on tag and flag data. The above MSP class 8 instructions control this BLU. Test flags TF1 and TF2 are bit-length logical indicators physically placed in the MSP's status register (SR). However, both TF1 and TF2 can be written and read as registers. MEM (16) is connected to the 17th line of the data bus to receive the tag / flag bits. Status conditions are given by a multiplexer connected to the data bus. BLU efficiently generates a judgment flag for program control. The result of bit logic operation is stored in the memory tag / flag (17th bit) or TF1 or TF2 of STAT. An example of bit logic generation in this preferred embodiment is shown below.

【0053】

Given the following programming instruction:

【0054】

If {((value1 = 0 AND speak) OR (NOT (value2&gt; 0))) AND last frame AND inhibit AND ic7)} goto END [0055]

Here, speak, last frame, inhibit, and ic7 are flags maintained in the flag memory, and value1 and value2 are 16-bit data values stored in the parallel memory.

【0056】

In this case, the assembly program that uses the BLU, flag memory, and flag processor is coded as follows:

【0057】

Load LTF, 1, speak; speak flag into TF1 Ru LAC, a0, value1; value1 as an accumulator (accumu) lator) load to 0 ANDCF, 1, AZ; status condition for accumulator equal to zero And TF1 AND LAC, a0, value2; value2 as accumulator (accumu) Get status value by loading to lator) LCF,2,! AGT; ACC complement greater than zero TF2 Load to ANDF, 2, last frame; last frame flag and TF2 Seeking AND with ORCF, 1, TF2; Find the OR of TF1 and TF2 and get the result In TF1 ANDF, 1, inhibit; A with inhibitor flag and TF1 Ask for ND ANDF, 1, ic7; ic7 AND with TF1 Ask BR, TF1, END If TF1 is true, branch to END Ru [0058] [0058]

Circular buffering In addition to efficient branching, tag / flag data memory links to specialized hardware / software to provide a highly efficient circular buffer for DSP routines such as FIR filters. Without such tag / flag bits, both a buffer header and a word indicating the length of the buffer that should be used in memory for each circular buffer are needed for circular buffering. Tagged 16-bit data can also be extended to link hardware / software with other data buffering requirements. For example, a 1-bit tag may be used to indicate the physical end of a display buffer. This causes an interrupt when the liquid crystal display (LCD) controlled state machine reads the last buffer value.

【0059】

The MSP58P70 is designed to perform DSP functions with intermediate performance. Fundamentally for many filtering algorithms, the main function of DSP is the FIR structure. Figure 6 shows the structure of the FIR filter. The FIR structure requires several parallel operations to perform for each tap of the filter. Each tap has 1 multiplication and 1 accumulation. As a result, the output for N + 1 taps is obtained as expressed by the following equation.

【0060】

[Number 1]

<img file="JP2000200215A_D0002.tif" />【0061】

For N taps, ideally 2N multiplication and addition operations are required.

【0062】

In this preferred embodiment, four instructions FIR, FIRK, COR, and CIRK are executed to perform the operation of this equation.

【0063】

The FIR instruction and FIRK instruction perform 16 × 16-bit multiplication and 32-bit accumulation operation (per tap) in 2 clock cycles. When used with the preceding RPT instruction, the FIR of N + 2 taps runs in twice the number of taps, or 2 (N + 2) clock cycles. To perform the FIR tap filter section using program memory to store fixed filter coefficients (pointed by DP) and data memory to store variable sample values (pointed by Rx) FIRK is used for. Both FIR instructions perform the same function on two sets of operands stored in data memory. FIRK is useful for fixed filters and requires a minimum amount of data memory. The FIR instruction is useful for adaptive filtering or applications where the coefficients are given by an external source.

【0064】

The COR and CORK instructions can perform 16x16-bit multiplication and 48-bit accumulation in 3 clock cycles. When used with the preceding RPT instruction, the FIR of N + 2 taps runs in 3 times the number of taps, or 3 (N + 2) clock cycles. The COR and CORK instructions are the same in operation and argument, except that they add an additional 16-bit extended cumulative cycle to prevent computational overflow that is common with autocorrelation filters.

【0065】

FIR (COR) instruction Some initial setup is required to use the FIR (COR) instructions. Consecutive Rx vs. {Rxeven, Rxeven + 1} should be selected with Rxeven pointing to the sample buffer area (sample buf) of data memory and Rxeven + 1 pointing to the coefficient array area (coeff array) of data memory. .. The first coefficient h [0] should be loaded into the MR register. FIR (COR) can now be executed with repetitive instructions for N taps. The value of the Rxeven pair is incremented during execution. After execution is complete, the last value of Rxeven points to a sample buffer location where new sample data can be stored.

【0066】

FIRK (CORK) instruction The FIRK (CORK) instruction works exactly like the FIR (COR) instruction, except that the coefficient array is located in program memory 0. Instead of loading the pointer to the coefficient array in the data memory into Rxeven + 1, the value of the coefficient array, the coeff array, is loaded into the data pointer DP. The value of this coefficient array is essentially a look-up table commonly stored in program ROM.

【0067】

Manipulation of the sample buffer by the DSP is generally done using circular buffering. Registers, parallel counters, and parallel comparators are generally required to perform circular buffering. Moreover, registers, parallel counters, and parallel comparators cannot be shared by parallel circular buffers. By using the tag / flag memory bits to configure the circular buffer, the implementation of this general circular buffer overhead is no longer necessary. In this preferred embodiment, the number of circular buffers that can be written is limited only by the size of the data memory.

【0068】

Iterative use of all filter instructions takes place in the circular buffer, where new samples are cyclically loaded into the sample buffer. FIG. 7 shows the operation of the circulation buffer in this preferred embodiment. A circular buffer is created by setting the TAG bit at the Nth location of the sample buffer to 1. The filter instruction interprets the TAG bit in data memory as a circular buffer marker. In FIG. 7, the TAG bit of the Nth location of sample buf, that is, the location sample buf + N, is set to 1. If the filter instruction finds a TAG bit set to 1 during execution in the sample buffer, the value of R5 is added instead of incrementing Rxeven. R5 is generally loaded with a negative sample buffer length before any filter instruction is executed, pointing to the beginning of the buffer. For the circular buffer to work consistently, the status register (STAT) should be saved in a temporary variable after the completion of the filter instruction and reloaded just before the execution of the filter instruction. In Figure 7, the sample buffer is sample It starts with first. The sample first is initially loaded with the start address of the buffer. After the filter instruction is executed once, the new Rxeven points to the (N + 1) th location from the beginning of the buffer. New samples are stored in this location, Rx^evenIs the new value for sample first. The effect of the circular buffer configured in this way is to move all new samples x [k] and the pointer Rxeven backwards. This is the same as replacing the oldest sample. The number of data memory locations used by configuring this circular buffer is N + 1. Where N is the number of taps on the filter. This is consistent with the behavior of FIR filters and works well with any MSP58P70 filter instruction. A typical program for an FIR filter using the FIR (COR) instruction is shown below.

【0069】

[Table 2]

<img file="JP2000200215A_D0003.tif" />L1 MOV R5, (-2 * N); Circular buffer length R5 Load to L2 MOV R1, coeff array; Inting L3 MOV MR, * R1; Multiply the initial coefficient (h0) Load into a number register L4 MOV R0, sample first; R2 is the first sample R Initialize to AM location L5 RPT0; y points by An Stored in the accumulator L6 ZACS A0; Initialize y to zero Ru L7 MOV STAT, mtag stat; previous sample TAG Restored to status register L8 RPT N-2; paired with N tap filter Actual filter routine to do L9 FIR A0, * R0; Put FIR in COR Can be changed L10 MOV mtag stat, STAT; T for the next sample Save AG status L11 MOV A2, sample new; new sample data Is stored in the sample buffer L12 MOV A2, * R0; L13 MOV * R1, sample first; This is the first sample The start of FIR L14 MOV A0, data y, ++ A; 16-bit result y To memorize Other processing if necessary IRET; return from interrupt [0070]

A typical program for an FIR filter using the FIRK (CORK) instruction is shown below.

【0071】

[Table 3]

<img file="JP2000200215A_D0004.tif" />L1 MOV R5, (-2 * N); Circular buffer length R5 Load to L2 MOV A2, coeff array; Coefficient memory in ROM Pointing to the beginning of L3 MOV A2, * A2; Find the first value (h0) Search L4 MOV MR, A2; Initial coefficient (h0) is squared Loaded into a number register L5 MOV R2, sample array; First sample RAM Initially set to location L6 RPT0; AN is pointing Y is stored in the accumulator L7 ZACS A0; Initialize y to zero Ru L8 MOV STAT, mtag stat; previous sample TAG Restored to status register L9 RTP N-2 ; Against N tap filter Actual filter routine to do L10 FIRK A0, * R2; FIRK to CORK Can be replaced L11 MOV mtag stag, STAT; for the following sample Save TAG status L12 MOV A2, sample new; new sample data Is stored in the sample buffer L13 MOV A2, * R2; L14 MOV * R2, sample first; This is the first sample F IR start MOV A0, data y, ++ A; 16-bit result y To memorize Other processing if necessary IRET; return from interrupt [0072]

Other features and details not required for the practice of the claimed invention, which are also considered for use in preferred embodiments, are disclosed in the co-pending application below. Agent File No. TI-24705P, Application No. 60 / 090,668-Method for Insuring Security of Program Data in One-Time Programmable Memory, Agent File Number TI-24707P, Application No. 09/305891-"Variable Word Length Data Memory", Agent File Number TI-24708P, Application No. 60 / 090,589-"Low cost multiplication with chain capability" Low Cost Multiplier Block with Chain Capability), and agent file number TI-24711P, application number 60 / 090,671- Flexible Accumulator Register File for Use in High Performance Microprocessors. All of these are the property of the Applicant and are valid filing dates at the same time as the Application and are incorporated herein by reference.

【0073】

Answering machine Variadic data memory, and the microprocessors in which it is embedded, are designed for use in consumer electronics such as answering machines. A block diagram of an answering machine device incorporating the present invention is shown in FIG. In this device, the processor 902 is operationally connected to the telephone line interface 904, the microphone 906, and the speaker 908. The microprocessor 902 sends and receives voice data over the telephone line 910 via the telephone line interface 904. The microprocessor sends audio data to the peripheral region via the speaker 908 and receives audio data from the peripheral region via the microphone 906.

【0074】

According to the disclosed class of the innovative embodiment, it is a programmable processing system that is stored in memory at each location containing not only multiple data or program bits but also one or more tag bits. A programmable process comprising a programmable processor connected to execute an instruction, the processor being connected to execute at least some instructions determined by the tag bit rather than the data bit or program bit. The system is provided.

【0075】

According to another disclosed class of the innovative embodiment, a variable length data memory array, the first memory array having one or more bits, connected in parallel with the first memory array. It also includes a second memory array with one or more bits and a plurality of multiplexers connected to read or write the appropriate bits of the array, the contents of both arrays being one address. A variable length data memory array is provided, which can be read with, but the data is written independently to each address.

【0076】

According to another disclosed class of the innovative embodiment, a variable length data memory array, the first memory array having one or more bits, connected in parallel with the first memory array. In addition, data is received from a second memory array having one or more bits, a plurality of multiplexers connected to read or write appropriate bits of the array, and the first memory array. It includes a 1-bit logical unit connected to execute instructions based on data, the contents of both arrays can be read at one address, and data can be written to each array at one address. A variable length data memory array is provided that is done independently using.

【0077】

According to another disclosed class of innovative embodiments, a mixed signal processor chip that is connected in parallel to a central processing unit and a program memory that is operational and connected to the central processing unit, said central processing unit. It includes a data memory composed of two memory arrays connected to a processing unit, the two memory arrays can be read independently or simultaneously at the same address, and the two memory arrays have the same address. A mixed signal processor chip that can be used and written independently is provided.

【0078】

According to another disclosed class of innovative embodiments, the answering machine is a central processing unit and a program memory operating and connected to the central processing unit, which is connected in parallel to the central processing unit. A data memory composed of two memory arrays connected to the device, an interface for operating and connecting the central processing unit to a telephone line so as to send and receive messages, and a storage device in an answering machine record voice. The two memory arrays include a microphone that is operationally connected to the central processing unit and a speaker that is operational and connected to the central processing unit so as to reproduce the voice stored in the answering machine. An answering machine is provided that can be read independently or simultaneously at the same address, and the two memory arrays can be written independently using the same address.

【0079】

Transform and change As will be appreciated by those skilled in the art, the innovative concepts disclosed in this application can be transformed and modified in a tremendously wide range of applications. Therefore, the scope of the subject matter of a patent is not limited by any of the particular representative teachings presented herein, but only by the claims.

【0080】

More importantly, over time, single chips tend to incorporate more and more features. Even if the assignment of functions to a plurality of chips is changed, the disclosed invention may still be useful as long as the above-mentioned functional operating principle is maintained.

【0081】

This preferred embodiment discloses a 1-bit plus 16-bit architecture. However, for special applications, other architectures such as 1-bit plus 32-bit or 1-bit plus 8-bit are also available for disclosed innovations.

【0082】

This preferred embodiment discloses a 1-bit plus 16-bit architecture. However, for special applications, it is possible to take advantage of other architectures that also disclose other architectures in which more than one bit is wired in parallel to a second memory array that is equal to the word length of the processor architecture. it can.

【0083】

The disclosed variable-length data memory-based instructions enable flag / tag memory and logical processing. However, the function of the variable length data memory can be extended by extending the instructions that utilize the data memory. Other uses for data memory may be obtained by such an extension. For example, the use of circular buffers can be extended beyond the implementation of FIR filters. Circular buffering allows you to move blocks of sample within the MSP without worrying about the physical beginning or end of a particular memory block.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the memory organization of the variable length data memory array.

[Figure 2]

It is a block diagram which shows the memory organization of a 16-bit data memory array.

[Fig. 3]

It is a block diagram which shows the relative flag address designation offset derivation.

[Fig. 4]

It is a figure which shows the data memory organization of byte, word, and flag data.

[Fig. 5]

It is a figure which shows the bit logic unit combined with a flag register.

[Fig. 6]

It is a figure which shows the structure of the FIR filter.

[Fig. 7]

It is a figure which shows the operation of the circulation buffer in this preferred embodiment.

[Fig. 8]

It is a block diagram which shows the architecture of MSP58P70.

[Fig. 9]

It is a block diagram which shows the answering machine device which incorporated the variable length data memory.

[Explanation of symbols]

10 processors 12 data memory blocks 102 16-bit memory array 104 1-bit memory array 902 microprocessor 904 Telephone line interface 906 microphone 908 speaker