Memory managing device

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a memory management device that detects / avoids a memory leak in a memory (storage device) of a computer or the like.

【0002】

[Conventional technology]

Conventionally, a memory management device that detects / avoids a memory leak is widely used in a computer for detecting an unnecessary allocation of memory.

【0003】

Conventional examples of such a memory management device or method are disclosed in, for example, "Memory Leak Detection Method and Device" in JP-A-9-244948. In such a conventional example, the memory allocation table that tracks memory allocation and deallocation should be deallocated with the corresponding memory allocation before the occurrence of the event, in addition to the file name and line number. A memory leak is detected by storing the expiration event indicating that the memory is released and the deallocation information including the dependent pointer indicating the current allocation of the memory.

【0004】

[Problems to be Solved by the Invention]

However, the problem is that conventional memory management devices and methods are complicated and large-scale. This is because in traditional systems that detect memory leaks, the operating system (OS) dynamically allocates computer memory to programs, or multiple processes used for specific functions, with each process This is because the purpose is to detect the case where the allocation is not released when the allocation is completed.

【0005】

In other words, the time interval between the memory allocation of the computer and its release depends on the processing time of each process. The processing time of each process is not unconditionally determined depending on the processing content, for example, because there are processes that are processed in an extremely short time and processes that are required during the operation of the computer. Therefore, for the purpose of determining the memory area allocated to the valid process and the memory area allocated to the invalid process, that is, for the purpose of detecting a memory leak, the file information corresponding to the process and the current memory A means of managing information about allocated blocks and deallocation information is needed.

【0006】

Therefore, an object of the present invention is to provide a simple memory management device adapted for data processing in a packet switching device or a router device.

【0007】

Another object of the present invention is to provide a memory management device that prevents / avoids a decrease in data processing capacity due to an expansion of an unusable memory area due to unnecessary allocation of memory.

【0008】

[Means for solving problems]

In order to solve the above-mentioned problems, the memory management device according to the present invention has the following characteristic configurations.

【0009】

(1) The data memory that stores the input data based on the write request signal and reads it as output data based on the read request signal, the link list of each packet of the input data, and the link list of the free data memory area are stored. A memory management device including a link list memory and an address control unit connected between the data memory and the link list memory to generate an address to the data memory.

【0010】

(2) The address control unit has a free area management unit for outputting written address information, a used area management unit, and an address / link list control unit connected to the free area and the used area management unit (1). Memory management device.

【0011】

(3) The free area management unit is the memory management device according to (2) above, which has a start address management unit that holds the free area start address of the data memory and a end address management unit that holds the end address of the free area.

【0012】

(4) The used area management unit is the memory management device according to (2) or (3) above, which has an unopened address bit processing unit composed of a counter for counting a set fixed time and a logic circuit.

【0013】

(5) The address / link list control unit includes a page number management unit including a down counter and an initial value setting circuit, a link list memory address control unit for address generation, and a link list memory data processing unit (2). Memory management device of 3) or (4).

【0014】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the configuration and operation of a preferred embodiment of the memory management device according to the present invention will be described in detail with reference to the attached drawings.

【0015】

First, with reference to FIG. 1, the overall system configuration of the packet switching device including the memory management device according to the present invention will be described. This system consists of an input data processing unit 2, a memory management device 1, an output request control unit 6, a route search processing unit 7, a switch control unit 8, and an output data processing unit 9 connected to a plurality of communication lines. The output of the data processing unit 9 is sent to the communication line. Here, the memory management device 1 is composed of a data memory 3, an address control unit 4, and a link list (chain information) memory 5.

【0016】

In the system of FIG. 1, the input data processing unit 2 divides packets from a plurality of communication lines into units (pages) unique to the device for each packet in order to switch each packet independently at high speed. Also, an attribute for determining the processing method of each packet is generated. The output request control unit 6 controls the output request for switching according to the attributes of each packet generated by the input data processing unit 2.

【0017】

The route search processing unit 7 determines the output destination for the output request of the output request control unit 6, controls the switch, and generates information for reading the packet divided into the output request source page from the data memory. .. The memory management device 1 has a data memory 3 that stores the divided pages as described above and is read out when necessary, and controls this appropriately as described later.

【0018】

The switch control unit 8 switches the page read from the data memory 3 to the destination as determined by the route search processing unit 7. The output data processing unit 9 reassembles and outputs the packet data divided into pages switched by the switch control unit 8 so as to match the format of the output communication line.

【0019】

The description of the memory management device 1 will be further supplemented. The data memory 3 of the memory management device 1 stores the data from the input data processing unit 2 at the address generated by the address control unit 4, and the address control unit 4 generates it in response to a read request from the route search processing unit 7. The address data is output to the switch control unit 8.

【0020】

The address control unit 4 generates a write address and a read address to the data memory 3 from a write request from the input data processing unit 2 and a read request from the route search processing unit 7. Then, the link list memory 5 that stores the link list of each packet and the link list of the free area of the data memory 3 is managed for the page link of each packet. Also, for some reason, the read request from the route search processing unit 7 for reading the data written in the data memory 3 is incorrect, and the page that should be read from the data memory 3 is not read, which is an unnecessary area. If you have, it has a memory leak avoidance function that releases it. The details will be described later.

【0021】

Next, with reference to FIG. 2, the detailed configuration of the memory management device 1 of FIG. 1, particularly the address control unit 4 in the memory management device 1, will be described. The address control unit 4 is composed of a free area management unit 41, a used area management unit 42, and an address / link list control unit 43. The address / link list control unit 43 receives a write request and a read request, and is interconnected to the free area management unit 41 and the used area management unit 42, and is also connected to the data memory 3 and the link list memory 5. .. Write address information is output from the free area management unit 41.

【0022】

Here, the free area management unit 41 includes a means for storing the start address information and the end address information of the free area in the data memory 3 in the free area link list of the link list memory 5, and sets the write address to the data memory 3. , The start address information of the free area is output to the address / link list control unit 43 in order to search from the link list memory 5. The start address information of this free area is also output to the output request control unit 6.

【0023】

The address / link list control unit 43 reads the address of the free area starting from the free area of the received link list memory 5 as a write address to the data memory 3 from the link list memory and outputs it to the data memory, and at this time. , The means for reading the new free area start address from the link list memory and updating the free area start address information of the free area management unit 41, and the start page address information of the read packet included in the read request as the read address. , Pass to data memory 3, and if there is a page following it, read the corresponding link list in link list memory 5 and output it to data memory 3, and when all pages of the packet are read, link the packet By adding the list to the end address information of the free area management unit, there is a means to set the area as a free area again.

【0024】

The used area management unit 42 counts a set fixed time so that the address of the linked list memory that has never been allocated to the free area in a fixed time can be identified, and a counter for writing to the linked list memory 5. , There is a means for managing the unopened address display bit, and a means for determining the address as a memory leak area when the contents of the linked list memory 5 are read at regular intervals and the unopened address display bit is recognized.

【0025】

Next, FIG. 3 is a detailed block diagram of the address control unit 4 of FIG. In FIG. 3, the free area management unit 41 holds the start address of the free area of the data memory, the start address management unit 11, and the end address management unit 12 that holds the end address of the free area from the flip-flop (FF). It is a registered register. The used area management unit 42 includes a counter 21 that counts a set fixed time by an in-device clock, and an unopened address bit processing unit 22 that is composed of a logic circuit.

【0026】

The address / link list control unit 43 is a page number management unit 31 composed of a down counter and a logic circuit for setting an initial value, and a link list memory address control unit composed of a counter for address generation and a logic circuit. It is composed of 32 and a linked list memory data processing unit 33 composed of a logic circuit and the like.

【0027】

Hereinafter, the operation of a preferred embodiment of the memory management device according to the present invention will be described. First, the operation of the system shown in FIG. 1 will be described. It is assumed that the data memory 3 of FIGS. 1 and 2 is a RAM (random access memory), and the linked list memory 5 is a dual port memory (DPM).

【0028】

The system of FIG. 1 has a plurality of communication lines, and a plurality of packets are input from each of them. Therefore, first, each packet is divided into data lengths (pages) unique to the device in the input data processing unit 2, and is multiplexed for each packet for passing to the next stage.

【0029】

Next, attribute data including the packet length and destination of each packet is created, and the attribute data is output to the output request control unit 6. At the same time, during the route search process for determining the destination and the processing time for switching, the address control unit 4 sends the data to the data memory 3 for storing the data and obtains the write address. As a write request, data including the number of pages of the packet is sent, and the page of each packet is stored in the write address specified by the address control unit 4 of the data memory 3. At this time, the linked list information of which address in the data memory the page for each packet is stored in is written in the linked list memory 5.

【0030】

Next, as information for switching the packet to the correct requested destination, the attribute information of the packet passed to the output request control unit and the write address of the first page of the packet to the data memory are input to the route search processing unit 7 Pass to. The route search processing unit 7 passes the switch control information from the set route information to the switch control unit 8 and reads the switching data (packet) on the first page of the packet written in the data memory. The address is passed to the address control unit 4 as a read request.

【0031】

The address control unit 4 outputs the read address to the data memory 3 from the received address and the link list of the corresponding packet written in the link list memory 5. The page read from the corresponding address in the data memory 3 is switched by the switch control unit 8 according to the switching information together with the attributes from the route search processing unit for each packet, and the output data processing unit 9 of the specified destination is switched. Is sent to. The output data processing unit 9 reassembles the received page based on the attribute information, converts it into a data format suitable for the communication line, and sends it out.

【0032】

In this series of operations, the read request processed and generated by the route search processing unit 7 is not correctly passed to the address control unit 4 for some reason, and the data that should be read from the data memory 3 is not read. A memory leak is defined as the fact that the information remains in the linked list memory 5 and an area that cannot be allocated to the address to which new data is written occurs after that.

【0033】

Here, in order to help understanding, a concrete example will be given for explanation. For example, when packet 1 and packet 2 are input from the two communication lines, respectively, the input data processing unit 2 first divides the data into data lengths (pages) unique to the device. Here, it is assumed that the packet length of packet 1 is 28 bytes and the packet length of packet 2 is 20 bytes. Then, assuming that one page length is 10 bytes, packet 1 is divided into 3 pages, and dummy data is put in the remaining 2 bytes of the last 1 page. Packet 2 is divided into two pages, which are just divisible by the page length, so no dummy data is inserted.

【0034】

Then, attribute data including the packet length and destination of each packet is created, and the attribute data is output to the output request control unit 6. At the same time, in order to write the packet divided into pages to the data memory 3, as a write request to the address control unit 4, if the packet is 1, the page number information 3 is sent, and the pages of the packet 1 are sent to the data memory in order. To do.

【0035】

Next, the operation of the memory management device according to the present invention will be described with reference to FIGS. 2 and 3. The address control unit 4, the address / link page number management unit 31 of the list control unit 43 has received, write the number of pages Komu 3 pages are set to an initial value of the down counter.

【0036】

The linked list memory address control unit 32 sees the set value 3 and prepares an address for writing the free pages for 3 pages to the data memory. In order to prepare an address, the head address management unit 11 of the free area management unit 41 Receives the start address of the free area from, refers to the contents of the linked list memory of that address, and at the same time decrements the down counter value of the page number management unit 31 by one. Further, the free area start address is output to the address of the data memory as the write address of the first page. The contents referred to here are output to the write address of the data memory as the address of the second page, and the contents of the linked list memory of that address are referred to as the write address of the third page. At this time, the value of the down counter is decremented by one again. Output the address on the third page to the write address of the data memory, and refer to the contents of the linked list of that address.

【0037】

When the address / link list control unit recognizes that the value of the down counter that is decremented by one here becomes 0, the referenced value is the new start address of the free area, and the start address management unit 11 Is written to the register of. Similarly, 0, which is a reserved value to indicate that the page written to this address is the last page of the packet, is written to the linked list in the linked list memory. Now, the data for 3 pages of packet 1 is written in order. Further, at this time, the data of the link list address read as the write address to the data memory is displayed as an unopened address for identifying the area of the data memory that has not been allocated to the free area within a certain period of time. 1 is written in the bit. This bit is used area management unit so that if it is allocated to a free area even once for a certain period of time, even if that area is allocated to the address to write a page to the data memory again, 1 is not written. It is controlled by 42 unopened address bit processors. Further, this fixed time is a value set in the counter 21 of the used area management unit 42, and the set value is obtained from the packet length processed by the device, the route search processing unit, and the switching ability, and is stored in the data memory. One cycle with the maximum time that is normally accumulated as the minimum value is taken as a value taken several cycles for protection. Further, the first page address initially held by the first address management unit 11 is output as the write address information of the first page. Similarly, packet 2 is also processed.

【0038】

FIG. 4 is an address map of the linked list memory and the data memory according to the embodiment of the present invention. Figure 4 (A) shows the address map of the linked list before the paginated packets are written to the data memory, where all the areas from 0 to 9 are free and free. The start address of the area is 2, the end address of the free area is 9, and the linked list of the free area is 2-3-5-6-8-1-4-7-9 in order. Figure 4 (B) shows the address map of the data memory after packet 1 and packet 2 are written to the data memory. Page 3 of packet 1 and page 2 of packet 2 are the link list memory mentioned earlier. Indicates that the data was written in order from the beginning of the free space shown in the address map of.

【0039】

FIG. 5 is an address map of the linked list after packet 1 and packet 2 are written to the data memory. Here, the linked list of packet 1 is in the order of addresses 2-3-5, and 0 indicating the last page is written in the contents of address 5. Similarly, the linked list of packet 2 is 6-8, and the linked list of free space is 1-4-7-9.

【0040】

In order to switch the packet to the correct requested destination, the attribute information of the packet passed to the output request control unit and the write address of the first page of the packet to the data memory are passed to the route search processing unit 7. The route search processing unit 7 passes the switch control information from the set route information to the switch control unit 8 and reads the switching data (packet) on the first page of the packet written in the data memory. If the address is packet 1, the address 2 is passed to the address control unit 4 as a read request.

【0041】

With reference to FIGS. 2 and 3, the address control unit 32 of the address / link list control unit 43 that received the read request uses that address as the start address and starts from the link information of the packet stored in the link list. The contents are output as a read address to the data memory 3 until 0 indicating the page of is recognized. The read address of the data memory output in the case of packet 1 is 2-3-5, and 3 pages of packet 1 are output from the data memory. At this time, the read address is written with the read start address as the data at the end of the free area of the linked list memory indicated by the register of the end address management unit 12 of the free area management unit 41, and the address on the third page is new. It is reassigned to free space by updating it as the free space end address. At this time, 0 is written in the unreleased address bit of the linked list memory allocated to the free area.

【0042】

The page output from the data memory is switched by the switch control unit 8 according to the switching information together with the attributes from the route search processing unit for each packet, and is sent to the output data processing unit 9 of the specified destination. The output data processing unit 9 reassembles the received page based on the attribute information, converts it into a data format suitable for the communication line, and sends it out.

【0043】

Next, in addition to packets 1 and 2, new packets are not processed, and the operation when a read request for packet 2 does not come after a certain period of time when packets 1 and 2 should have been read will be explained. To do.

【0044】

FIG. 6 is an address map of the linked list memory in which only packet 1 is read from the address map of the linked list memory in the state where packets 1 and 2 of FIG. 5 are written. Here, it is assumed that the read information of the packet 2 does not come and the addresses 6 and 8 are invalid areas. The address control unit 32 and the data processing unit 33 of the address / link list control unit are all based on the values set in the counter 21 of the used area management unit 42 from one port of the link list memory configured by the DPM. The unopened address display bit of the address is being scanned.

【0045】

Here, the time required to scan all the addresses once is a fixed time set in the counter 21. When scanning after a certain period of time from the previous scan, addresses 6 and 8 in which 1 is written in the unopened address display bit are regarded as a memory leak area. The address of this area is written in the content indicated by the end address of the free area and updated as a new end address. Also, by writing 0 to the memory leak address, the memory leak area is reassigned as a free area. In this case, the address map of the linked list memory 5 is the same as that in FIG. 4 (A).

【0046】

The configuration and operation of the preferred embodiment of the memory management device according to the present invention have been described in detail above. However, the present invention should not be limited to such embodiments, and those skilled in the art can easily understand that various modifications can be made without departing from the gist of the present invention.

【0047】

[Effect of the invention]

As understood from the above description, according to the memory management device of the present invention, the dynamically used memory is managed by two chain information (link list) of a used area and a free area. There is. The invalid area is allocated to 1 bit of the data in the linked list memory that stores the linked list. The unopened address bit is detected by scanning at regular time intervals determined by the processing capacity of the device. Therefore, a memory leak can be detected / avoided only by adding a configuration for checking one bit of data in the linked list memory, a counter that counts a certain period of time, and an unopened address bit in the linked list memory. Therefore, it has a remarkable practical effect that the intended memory leak can be detected / avoided with a simple configuration.

【0048】

That is, according to the memory management device of the present invention, the dynamically allocated memory is always written / read repeatedly in the entire area in a long time, and the data processing time peculiar to the device is counted and never. A memory leak area is detected due to the area that is not allocated to the free area. Therefore, there is an effect that a plurality of special information and control hardware are not required.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram of the bucket communication system which uses the memory management apparatus by this invention.

[Figure 2]

It is a block diagram of the preferred embodiment of the memory management apparatus shown in FIG.

[Fig. 3]

It is a detailed block diagram of the address control part of the memory management apparatus shown in FIG.

[Fig. 4]

It is a figure which shows the example of the address map (A) of the link list memory of the memory management apparatus shown in FIG. 2 and the address map (B) of a data memory.

[Fig. 5]

It is a figure which shows the address map of the link list memory after packets 1 and 2 are written in the data memory of the memory management apparatus shown in FIG.

[Fig. 6]

It is a figure which shows the address map example of the link list memory in the state where the packets 1 and 2 shown in FIG. 5 are written.

[Explanation of symbols]

1 Memory management device 3 data memory 4 Address control unit 5 Linked list memory 11 Start address management department 12 End address management department 21 counter 22 Unopened address bit processing unit 31 Page number management department 32 Link list memory address control unit 33 Linked list memory data processing unit 41 Free space management department 42 Used area management department 43 Address / Linked List Control Unit