Digital integrated circuit

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to an improvement of a digital integrated circuit that protects digital data to be kept secret from the outside inaccessible.

【0002】

[Conventional technology]

As is well known, for example, in a digital integrated circuit for performing encryption processing on digital data, data that is the key to the encryption processing, program data for executing the encryption processing algorithm, and the like. The data to be kept secret will be stored in the internal memory.

【0003】

In this case, in the digital integrated circuit, the secret data stored in the internal memory is not read or rewritten illegally from the outside, that is, the secret data is accessed from the outside. Protective measures have been taken to make this impossible.

【0004】

On the other hand, in this type of digital integrated circuit, after being manufactured in a factory, a test is performed to confirm whether or not various internal circuits including its internal memory operate normally. As this test, a method is adopted in which predetermined data is actually input to various internal circuits and it is confirmed whether or not the expected output can be obtained.

【0005】

Therefore, as described above, the internal memory is protected so that the data stored in it cannot be accessed from the outside, and the test at the time of manufacturing can be easily performed. This is a contradictory technology, which makes it difficult to design and manufacture digital integrated circuits.

【0006】

Normally, inspections during LSI (Large Scale Integrated circuit) manufacturing are performed using an LSI tester, and it is required that the inspection can be completed in a short time and that the number of uninspected circuit parts is reduced as much as possible. .. In particular, in the inspection of RAM (Random Access Memory) inside the LSI, it is necessary to check whether writing and reading are normally performed over all the addresses.

【0007】

For this purpose, if a test mode is set for each circuit part of the LSI and, for example, a RAM test mode is specified, the RAM address terminal and the data terminal are connected to the tester via the LSI connection pin, and the tester is also connected. When the test mode of a special arithmetic circuit for encryption processing is specified, the LSI is designed so that the input / output terminals of the circuit are connected to the tester via the connection pins of the LSI.

【0008】

On the other hand, for the circuit part where protection measures are taken so that it cannot be accessed from the outside, the wire connecting the elements inside the LSI is connected to the power supply end or the ground end to create fixed data, and the public encryption is used. It is possible to test only according to the procedure. In addition, consideration is given so that the output of each circuit portion does not go out so that the data in the middle of inspection does not leak to the outside.

【0009】

In this way, if intermediate data cannot be retrieved outside the LSI and can only be tested according to public cryptographic procedures, then a particular circuit can be inspected via multiple circuits. Therefore, the input data pattern for the test becomes long, and it becomes difficult to activate as many circuit elements as possible in the part to be inspected.

【0010】

In particular, when the confidential data is different for each LSI or for each device equipped with the LSI, for example, as shown in Japanese Patent Application Laid-Open No. 7-45782, for each LSI or for each device. It is necessary to mold a data chip for writing and reading different data and a chip for encryption processing on the same substrate.

【0011】

Here, conventionally, a cryptographic processing LSI C as shown in, for example, Japanese Patent Application Laid-Open No. 5-75597 has been proposed. This cryptographic processing LSI C includes a memory unit that stores secret data, a control unit that controls whether or not the data read from this memory unit can be output to the outside, and a storage unit that stores the write address of the secret data to the memory unit. , A comparison unit that compares the write address stored in this storage unit with the read address to the memory unit is provided, and the control unit can be output only when the comparison results of the comparison unit match in the test mode. It is something that I tried to do.

【0012】

However, in this cryptographic processing LSIC, it is a necessary condition that all the stored contents of the storage unit are reset when the test mode is set. For this reason, in the actual usage state, if the test mode is entered for some reason, it is necessary to write the secret data to the memory unit again and store the write address in the storage unit. There is a problem that it is inconvenient to handle.

【0013】

[Problems to be Solved by the Invention]

As described above, in the conventional digital integrated circuit, the point of protecting the confidential data from the outside and the point of facilitating the test at the time of manufacturing are sufficiently practical. It has the problem that it has not reached the level to be obtained.

【0014】

Therefore, the present invention was made in consideration of the above circumstances, and it is possible to reliably block access from the outside to confidential data, and to easily perform a highly reliable inspection at the time of testing. It is an object of the present invention to provide a very good digital integrated circuit.

【0015】

[Means for solving problems]

The digital integrated circuit according to the present invention is intended to be one that is accessible from the outside and includes a storage means including a specific storage area in which data to be kept secret is written. Then, it is provided with a control means for disabling access to the specific storage area from the outside by writing the specific data from the outside.

【0016】

According to the above configuration, before the specific data is written from the outside, the storage means can be accessed from the outside including the specific storage area, so that a highly reliable test can be easily performed. .. Further, after the specific data is written from the outside, the specific storage area of the storage means becomes inaccessible from the outside, so that the access to the confidential data from the outside can be surely blocked.

【0017】

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, FIG. 7 shows the appearance of the digital LSI chip 10 described in this embodiment. The digital LSI chip 10 is composed of a main body 10a formed by sealing a semiconductor substrate 11 on which various circuits described below are formed in a resin package, and a plurality of leads 10b protruding from the main body 10a. There is.

【0018】

FIG. 1 shows various circuits formed on the semiconductor substrate 11. First, the scramble circuit 12 performs scramble processing on the input plaintext data, converts it into ciphertext data, and outputs it.

【0019】

The host I / F (Inter / Face) circuit 13 is an interface for communicating with a computer (not shown) provided outside the digital LSI chip 10. The host I / F circuit 13 has a function of inputting address data sent from a computer, a chip select signal CS, a write enable signal WE, a read enable signal RE, and the like, a function of bidirectionally communicating data with the computer, and an interrupt. It has a function to output a signal INT, a standby signal WAIT, etc. to a computer.

【0020】

The control circuit 14 controls the inside of the digital LSI chip 10 and controls the calculation of the encryption key decompression program. ROM (Read Only Memory) 15 stores fixed data such as public key data and programs. RAM16 provides an I / F area and a calculation work area for data communication with an external computer.

【0021】

Furthermore, the EEP (Electrically Erasable and Programmable) ROM 17 can rewrite different data for each device, and has a function of saving data even without a battery. ALU (Arithmetic Logical Unit) 18 is a special four arithmetic unit that performs special operations for encryption.

【0022】

Further, the test circuit 19 selectively switches each circuit portion to a state in which it can be inspected from the outside of the digital LSI chip 10 based on the test mode signal input externally. The initialization circuit 20 generates an initialization pulse for initializing each circuit portion based on the initialization request signal INIT supplied when the power of the device is turned on.

【0023】

Here, although the details will be described later, the security circuit 21 controls so that the area in which the confidential data of each circuit portion is written cannot be accessed from the outside when a certain specific data is input. In addition, before specific data is input, each circuit part can be freely accessed from the outside, and the test can be easily performed.

【0024】

FIG. 2 shows the detailed configuration of the host I / F circuit 13 and the security circuit 21. That is, the write data WDATA output from the host I / F circuit 13 is supplied to the write data input terminal of the one-time ROM 22 of the security circuit 21.

【0025】

This one-time ROM 22 is a non-volatile memory that enables writing of data only once. The read data output end of this one-time ROM 22 is connected to one input end of a plurality of EX (exclusive) or circuits 23 provided for each bit (only one is shown for simplicity in the figure).

【0026】

Fixed data stored in the non-volatile memory 24 is supplied to the other input terminal of the EX or circuit 23. Each output of these EX or circuit 23 is subjected to OR operation processing by the or circuit 25, and then latched on the flip-flop circuit 26.

【0027】

That is, the EX or circuit 23, the or circuit 24, and the flip-flop circuit 26 determine that the data written in the one-time ROM 22 matches the fixed data stored in the memory 24. Then, when both data match, an L (Low) level disable signal is supplied to each circuit portion as an output of the security circuit 21.

【0028】

Further, this disable signal is supplied to the AND circuit 27, and is a write enable signal WE output from the host I / F circuit 13 and a fourth chip output from the address decoder 28 of the host I / F circuit 13. It is ANDed with the select signal CS4. The output of this AND circuit 27 is supplied to the write enable end of the one-time ROM 22.

【0029】

In the configuration shown in FIG. 2, first, at the time of inspection after manufacturing of the digital LSI chip 10, no data is written in the one-time ROM 22, and the data does not match the fixed data of the memory 24. An H (High) level digital signal is output from the security circuit 21.

【0030】

In this state, each circuit part can be freely accessed from the outside, and the test can be easily performed. However, since the one-time ROM 22 cannot be rewritten once the data is written, the write / read test is not performed.

【0031】

After the test is completed, the specific data of the same value as the fixed data stored in the memory 24 in the one-time ROM 22 directly with the tester for the inspection or from the external computer via the host I / F circuit 13. To write. Then, since the data written in the one-time ROM 22 and the fixed data in the memory 24 match, the security circuit 21 outputs an L-level disable signal.

【0032】

In this state, of each circuit portion of the digital LSI chip 10, the portion in which the confidential data is written is set so as not to be accessible from the outside. Then, when specific data having the same value as the fixed data stored in the memory 24 is written to the one-time ROM 22 in this way, the contents of the one-time ROM 22 cannot be rewritten. It will be fixed at the level and will ensure that confidential data is protected.

【0033】

FIG. 3 shows another example for generating the disabled signal described above. That is, the security circuit 21 is provided with an EEPROM 29 instead of the one-time ROM 22. Then, the write data WDATA output from the host I / F circuit 13 is supplied to the write data input end of the EEPROM 29.

【0034】

Further, the disable signal output from the flip-flop circuit 26, the write enable signal WE output from the host I / F circuit 13, and the fourth chip output from the address decoder 28 of the host I / F circuit 13. The output of the AND circuit 27 that logically ANDs the select signal CS4 is supplied to the write enable end of the EEPROM 29.

【0035】

Further, the read data output end of the EEPROM 29 is connected to one input end of the EX or circuit 23, and is also connected to the read data RDATA transmission line via the 3-state buffer 30.

【0036】

Then, the disable signal output from the flip-flop circuit 26, the read enable signal RE output from the host I / F circuit 13, and the fourth chip select output from the address decoder 28 of the host I / F circuit 13. The output of the AND circuit 31 that performs a logical product operation with the signal CS4 is supplied to the enable end of the 3-state buffer 30.

【0037】

In the configuration shown in FIG. 3, the external computer writes specific data having the same value as the fixed data stored in the memory 24 to the EEPROM 29 of the security circuit 21. Then, since the data written in the EEPROM 29 and the fixed data in the memory 24 match, the security circuit 21 outputs an L-level disable signal.

【0038】

In this way, once the disable signal reaches the L level, the output of the AND circuit 27, that is, the write enable end of the EEPROM 29 becomes the L level, so that the data cannot be rewritten to the EEPROM 29 thereafter. ..

【0039】

Further, once the disabled signal reaches the L level, the output of the AND circuit 31, that is, the enable end of the 3-state buffer 30 becomes the L level, so that the specific data read from the EEPROM 29 is subsequently transmitted as the read data RDATA. It will not be supplied to the line, and specific data will be prevented from being read out.

【0040】

On the other hand, at the time of the test immediately after the manufacture of the digital LSI chip 10, since no data was written in the EEPROM 29, the data in the EEPROM 29 and the fixed data stored in the memory 24 did not match, and the disabled signal was at H level. It has become.

【0041】

Therefore, if the data is other than the above-mentioned specific data, the data can be written and read from the outside to the EEPROM 29, and the EEPROM 29 can be easily tested.

【0042】

In the configuration shown in FIG. 3, when writing data to the EEPROM 29, there is a memory in which the same data needs to be repeatedly written. In this case, the flip-flop circuit 26 is used during the period until the data writing is completed. It is necessary to hold the output of the above at the H level, but the description of the holding means will be omitted.

【0043】

FIG. 4 shows yet another example for generating the disabled signal described above. That is, the security circuit 21 is provided with a register 32 instead of the one-time ROM 22 and the EEPROM 29. The data input end of this register 32 is connected to the transmission line of the read data RDATA, and the data output end is connected to one input end of the EX or circuit 23. Further, a strobe signal output from the initialization circuit 20 is supplied to the clock input end of the register 32.

【0044】

A logic circuit 33 is installed in the security circuit 21. The logic circuit 33 includes a write enable signal WE output from the host I / F circuit 13, a read enable signal RE, first to third chip select signals CS1 to CS3, and a disable output from the flip-flop circuit 26. Based on the signal and the initialization pulse output from the initialization circuit 20, the chip select signal CS, the write enable signal WE, and the read enable signal RE are generated for the EEPROM 17.

【0045】

The write data input end of the EEPROM 17 is connected to the write data WDATA transmission line, and the read data output end is connected to the read data RDATA transmission line.

【0046】

Further, the security circuit 21 has a memory 34 in which the address data for designating the specific address A1 of the EEPROM 17 is written, and the address data written in the memory 34 and the host I / F circuit 13 The output lower address data is selectively guided to the EEPROM 17 by the switch 35 controlled by the initialization pulse.

【0047】

Here, in the above logic circuit 33, CS output = CS1 + CS2 + CS3 + initialization pulse bar, WE output = (CS1 + CS2 * disable signal + CS3 * disable signal) * input WE, RE output = (CS1 The chip select signal CS, write enable signal WE, and read enable signal RE are generated by performing the operation + CS2 + CS3 * disable signal) * input RE + (initialization pulse bar).

【0048】

In the configuration shown in FIG. 4, when the initialization request signal INIT is supplied to the initialization circuit 20 during the test immediately after manufacturing, the initialization circuit 20 generates an L-level initialization pulse. Then, the switch 35 switches to the memory 34 side, and the address data stored in the memory 34 is supplied to the EEPROM 17.

【0049】

At this point, both the write enable signal WE and the read enable signal output from the host I / F circuit 13 are at L level, the chip select signals CS1 to CS3 are indefinite, and the disk output from the flip-flop circuit 26 is undefined. Although the possible signal is at H level, since the initialization pulse is at L level, the logic circuit 33 outputs an H level chip select signal, an L level write enable signal, and an H level read enable signal. Will be done.

【0050】

Therefore, the EEPROM 17 is in the read state of the data stored in the address A1 (nothing is written at the present time), and the read data is output to the transmission line of the read data RDATA.

【0051】

After that, when the supply of the initialization request signal INIT to the initialization circuit 20 is stopped, a strobe signal having an H level for one clock period is generated from the initialization circuit 20, so that the read data RDATA transmission line is used. The output data is latched in the register 32. Then, after one clock period has elapsed, the initialization pulse becomes H level, so that the switch 35 is switched to the transmission line side of the lower address data.

【0052】

In this case, since the data latched in the register 32 is a value in which nothing is written, it does not match the fixed data in the memory 24, and the flip-flop circuit 26 outputs an H-level disable signal. .. Then, in the logic circuit 33, the calculation of the above equation is CS output = CS1 + CS2 + CS3, WE output = (CS1 + CS2 + CS3) * input WE, RE output = (CS1 + CS2 + CS3) * input RE. Become. That is, the entire address area of the EEPROM 17 can be accessed from the outside, and the test can be easily performed.

【0053】

In this state, the specific data having the same value as the fixed data stored in the memory 24 is written to the address A1 of the EEPROM 17, and the initialization request signal is supplied to the initialization circuit 20 again to stop the operation. Then, this time, the specific data stored in the address A1 of the EEPROM 17 is latched in the register 32, and as a result, the L level disable signal is output from the flip-flop circuit 26.

【0054】

At this time, in the logic circuit 33, the calculation of the above equation is CS output = CS1 + CS2 + CS3, WE output = CS1 * input WE, RE output = (CS1 + CS2) * input RE. That is, the area specified by the chip select signal CS1 can be written and read from the EEPROM 17, the area specified by the chip select signal CS2 can be read without being writable, and the area specified by the chip select signal CS3 can be read. Is controlled so that writing and reading are disabled.

【0055】

FIG. 5 (a) shows the access area of EEPROM 17. It is assumed that the upper part of the figure is the area where the address value is small. In the area specified by the chip select signal CS1 generated by the host I / F circuit 13 based on the address specified from the outside, both reading and writing from the outside are possible.

【0056】

Further, in the area specified by the chip select signal CS2 generated by the host I / F circuit 13 based on the address specified from the outside, only reading from the outside is possible. Further, in the area specified by the chip select signal CS3 generated by the host I / F circuit 13 based on the address specified from the outside, both reading and writing from the outside are disabled.

【0057】

The address A1 written in the memory 34 is the address of the area specified by the chip select signal CS3. Therefore, by writing the secret data to the area specified by the chip select signal CS3, writing the same specific data as the fixed data to the address A1, and initializing the data, the secret data can be made inaccessible from the outside. ..

【0058】

In such an inaccessible area of EEPROM 17, it is effective to write secret key data, a private cryptographic parameter, an execution program of a private cryptographic processing algorithm, or the like. Further, it is effective to write the public key data or the like in the readable area of the EEPROM 17.

【0059】

Cryptographic private parameters include data with different values for each device and data with the same value for each device, and the latter data can be written to ROM 15 shown in FIG. It is preferable to write to the inaccessible area of EEPROM17.

【0060】

This is because when writing to ROM15, if the specific data written to address A1 of EEPROM17 changes to a value different from the fixed data and is stored for some reason, ROM15 becomes accessible from the outside and confidential data becomes available. It will be read.

【0061】

On the other hand, writing to the inaccessible area of EEPROM 17 not only enables manufacturing inspection, but also writes to the same area if the data written to the inaccessible area of EEPROM 17 changes for some reason. Since it is considered that the private data of the above is changed in the same manner, it is possible to prevent the original legitimate private data from being read out.

【0062】

FIG. 5B shows the access area of RAM 16 in the digital LSI chip 10. For this RAM 16, as in the case of EEPROM 17, an external read-write area specified by the chip select signal CSi and an external read-only area specified by the chip select signal CSi + 1 are also provided. It is possible to set the inaccessible area from the outside specified by the chip select signal CSi + 2.

【0063】

Then, for example, the read-write area of the RAM 16 is used as a data communication area with the outside, the read-only area is used as a storage area such as a flag indicating an internal state, and the inaccessible area is during encryption processing. Used to process private data such as intermediate data in.

【0064】

Figure 6 illustrates the testing and protection of confidential data in the scrambling process. That is, the scramble circuit 12 includes a shuffle circuit 12a that scrambles the input data, an address decoder 12b that decodes the address from the host I / F circuit 13 and the control circuit 14, a register 12c that writes the scramble key, and scramble. It includes a control register 12d that determines the mode and a state register 12e that indicates the state of the scramble circuit 12 and the state of the input data.

【0065】

Further, the control circuit 14 includes a general register 14a, an instruction register 14b, and an address generator 14c. Further, the ALU18, which is a special arithmetic unit for decompressing the encryption key, includes an input register 18a, an output register 18b, and an arithmetic unit 18c.

【0066】

When an instruction is written to the instruction register 14b of the control circuit 14 from the outside, the control circuit 14 controls each circuit of the digital LSI chip 10 in response to the instruction. For example, in the case of decompression of a scramble key, after the encryption key data is written to RAM 16 from the outside, the decompression instruction of the key is written to the instruction register 14b.

【0067】

The control circuit 14 writes the encryption key data of the RAM 16 to the input register 18a of the ALU 18. Then, the operation result of ALU18 appears in the output register 18b. The control circuit 14 executes a series of programs in which the data in the output register 18b is read into the general register 14a and written to the register 12c in the scramble circuit 12. When the execution of the instruction from the outside is completed, the control circuit 14 sets the status flag inside the control circuit 14 or generates an interrupt to notify the outside.

【0068】

At the time of manufacturing inspection of the digital LSI chip 10, test mode data is given to the test circuit 19 so that each circuit part can be tested. For example, when testing the scramble circuit 12, the internal connection is controlled so that all the registers of the scramble circuit 12 can be accessed from the outside via the host I / F circuit 13.

【0069】

After that, the temporary scramble key is written to the register 12c, and the temporary specified data is supplied to the shuffle circuit 12a as input data. Then, it is determined whether or not the predetermined expected value data can be obtained as output data. If a part of the scramble circuit 12 is defective, it can be determined that the scramble circuit 12 is defective because the output data is different from the expected value. ALU18 can be tested in a similar way.

【0070】

Here, since the data to be kept secret is latched in the register 12c of the scramble circuit 12, the general register 14a of the control circuit 14, and the output register 18b of the ALU18, the contents of these registers 12c, 14a, 18b can be read from the outside. Making it inaccessible is essential.

【0071】

The security circuit 21 described above makes the internal circuit freely accessible from the outside when the disabled signal is H level, and accesses the contents of the registers 12c, 14a, 18b from the outside when the disabled signal is L level. By setting it so that it cannot be set, the test can be easily performed, and the confidential data can be reliably protected. The present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist thereof.

【0072】

[Effect of the invention]

As described in detail above, according to the present invention, it is possible to reliably block access from the outside to confidential data, and it is possible to easily perform a highly reliable inspection at the time of testing. An integrated circuit can be provided.

[Simple explanation of drawings]

[Figure 1]

The block block diagram which shows the embodiment of the digital integrated circuit which concerns on this invention.

[Figure 2]

The block block diagram which shows an example of the main part in the same embodiment.

[Fig. 3]

The block block diagram which shows the other example of the main part in the same embodiment.

[Fig. 4]

The block block diagram which shows still another example of the main part in the same embodiment.

[Fig. 5]

The figure which shows for demonstrating the access area of the memory in this embodiment.

[Fig. 6]

The figure which shows for demonstrating the scramble operation in the same embodiment.

[Fig. 7]

The external view which shows the digital LSI chip in the same embodiment.

[Explanation of symbols]

10 ... Digital LSI chip, 11 ... Semiconductor substrate, 12 ... scrambled circuit, 13 ... Host I / F circuit, 14 ... Control circuit, 15 ... ROM, 16 ... RAM, 17 ... EEPROM, 18 ... ALU, 19 ... test circuit, 20 ... initialization circuit, 21 ... Security circuit, 22 ... One-time ROM, 23 ... EX or circuit, 24 ... memory, 25 ... or circuit, 26 ... Flip-flop circuit, 27 ... and circuit, 28 ... Address decoder, 29 ... EEPROM, 30 ... 3 state buffer, 31 ... and circuit, 32 ... register, 33 ... Logic circuit, 34 ... memory, 35 ... switch.