Multiprocessor system, processor duplexing method therefor and record medium recorded with control program therefor

Description: TECHNICAL FIELD [Detailed description of the invention]

【0001】

[Technical field to which the invention belongs]

The present invention relates to a multiprocessor system, a method for duplicating the processor thereof, and a recording medium on which a control program thereof is recorded, and particularly to a method for dealing with a failure at the time of system startup in the multiprocessor system.

【0002】

[Conventional technology]

Conventionally, in a multiprocessor system having a plurality of CPUs (central processing units), if there is a failed CPU at the time of system startup, the failed CPU is separated and the system is retracted to start up. It is configured.

【0003】

Alternatively, in a system in which a failure that occurs at startup is fatal, a redundant CPU is provided and the CPU control circuit is also provided with a redundant configuration to prepare for the failure.

【0004】

[Problems to be Solved by the Invention]

In the conventional multiprocessor system described above, when a failed CPU exists at the time of system startup, if the failed CPU is separated and the system is retracted to start up, the number of operating CPUs will decrease at the time of failure. There's a problem. As a result, the performance may be significantly reduced when executing a program optimized for the number of installed CPUs.

【0005】

Further, in a conventional system having a redundant configuration equipped with a redundant CPU, a redundant configuration is required for the CPU control circuit in addition to the redundant CPU, and the control logic that is not originally required is installed.

【0006】

Therefore, an object of the present invention is to solve the above-mentioned problems, to minimize the possibility that the number of operating CPUs is reduced and the performance is significantly deteriorated in the event of a failure, a multiprocessor system, a processor duplication method thereof, and control thereof. The purpose is to provide a recording medium on which a program is recorded.

【0007】

Another object of the present invention is to provide a multiprocessor system capable of equipping a redundant CPU in place of a failed CPU, a processor duplication method thereof, and a control program thereof without equipping a control logic that is originally unnecessary. The purpose is to provide a recording medium for recording.

【0008】

[Means for solving problems]

The multiprocessor system according to the present invention is a multiprocessor system composed of a plurality of central processing units, and one of the spare central processing units arranged in advance and the plurality of central processing units at the time of initialization fails. It is provided with a means for activating the spare central processing unit in place of the central processing unit in which the failure occurred when the above occurs.

【0009】

In addition to the above configurations, the other multiprocessor system according to the present invention is provided in advance to the central processing unit in which the failure has occurred when the spare central processing unit is started in place of the central processing unit in which the failure has occurred. It is provided with means for imparting the obtained logical identification information to the spare central processing unit.

【0010】

The processor duplication method according to the present invention is a processor duplication method for a multiprocessor system composed of a plurality of central processing units, and the failure occurs when a failure occurs in any of the plurality of central processing units at the time of initialization. It is provided with a step of activating a pre-arranged spare central processing unit in place of the central processing unit.

【0011】

In addition to the above steps, another processor duplication method according to the present invention is applied in advance to the central processing unit in which the failure has occurred when the spare central processing unit is started in place of the central processing unit in which the failure has occurred. It includes a step of giving the obtained logical identification information to the spare central processing unit.

【0012】

The recording medium on which the processor duplication control program according to the present invention is recorded is used to deal with the occurrence of a failure at system startup in a multiprocessor system including a plurality of central processing units and a chipset that controls the plurality of central processing units. It is a recording medium on which the processor duplication control program of the above is recorded, and the failure occurs when the processor duplication control program causes a failure in any one of the plurality of central processing units when initializing the chip set. Instead of the central processing unit, a spare central processing unit arranged in advance is activated.

【0013】

In addition to the above operations, the recording medium on which the other processor duplex control program according to the present invention has the above-mentioned operation, the processor duplex control program causes the failure in each of the plurality of central processing units and the spare central processing unit. When the spare central processing unit is started instead of the central processing unit, the logical identification information given in advance to the central processing unit in which the failure occurred is given to the spare central processing unit.

【0014】

That is, the processor duplication method of the present invention prevents deterioration of system performance by disconnecting the failed CPU from the system and operating a spare CPU instead when the CPU (central processing unit) fails in the multiprocessor system. is there.

【0015】

Further, when the spare CPU operates, the ID number of the failed CPU is assigned to the spare CPU so that the configuration does not change logically.

【0016】

More specifically, if two CPUs that normally operate and a spare CPU are provided and either of the two CPUs that normally operate is determined to be defective by the initial diagnosis at startup, the failed CPU The startup is interrupted, a spare CPU is started in its place, the logical ID number of the failed CPU is assigned to this, and the performance is not degraded as a system of two CPUs that is logically exactly the same as in the case of no failure. to start.

【0017】

As a result, by equipping a spare CPU and duplicating it, the spare CPU can be operated instead of the failed CPU, so even if there is a failed CPU, the system can be operated without reducing the number of operating CPUs. It will be possible.

【0018】

By assigning the logical ID number assigned to the failed CPU to the spare CPU that runs instead, the CPU with the same logical ID number always runs, and the spare CPU is physically used due to the CPU failure. Even if it is done, there is no change in the control logic on the chipset side, and the software does not need to be aware of it. Therefore, it is possible to minimize the possibility that the number of operating CPUs will be reduced and the performance will be significantly reduced in the event of a failure without equipping the control logic that is not originally required.

【0019】

BEST MODE FOR CARRYING OUT THE INVENTION

Next, examples of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a multiprocessor system according to an embodiment of the present invention. In the figure, the multiprocessor system according to the embodiment of the present invention has two normally movable CPUs (central processing units) 1 and 2, a spare CPU 3, a chipset 4, and an I / O (input / output) bus 5. It is composed of memory 6 and CPU bus 7.

【0020】

Physical ID numbers (identification numbers) # 0 to # 2 that are unique to each of CPU1 and CPU1 and spare CPU3 and are unique to the system are assigned. Of these, two CPUs 1 and 2 normally operate, the protocol of system bus 7 supports up to 2 CPUs, and chipset 4 has dedicated lines for each CPU up to the spare CPU 3. It is basically a logic circuit that controls two CPUs, except for the fact that it is.

【0021】

FIG. 2 is a block diagram showing the internal configuration of the chipset 4 of FIG. In the figure, in addition to the logic circuit 47 that controls the 2-CPU system, the chipset 4 has a start register 41 indicating the CPU to be started, a diagnosis result register 42 indicating the CPU failure status, a reset register 43, and an initialization completion register 44. It is composed of a signal port 45 dedicated to each CPU, a selector 46, and a timer 48.

【0022】

The value of the start register 41 indicates the start information of the CPU, and chipset 4 releases the reset and starts only the CPU in which '1' is set here. Immediately after startup, physical ID numbers # 0 and # 1 are set to '1' and physical ID number # 2 is set to '0' in the start register 41. Therefore, CPU1 of physical ID numbers # 0 and # 1 are set. It is set so that 2 is started and the spare CPU 3 is not started.

【0023】

In addition, the diagnosis result register 42 is set to '0' as an initial value. Initial diagnosis is performed each time the CPU is started, and the CPU that has completed this normally writes '1' to the diagnosis result register 42. On the other hand, the CPU that detects the abnormality does not write the value to the diagnosis result register 42. That is, '0' remains set.

【0024】

If a failure is detected from either CPU 1 or 2 in the initial diagnosis, a normal CPU writes to the reset register 43, and the chipset 4 that detects it sets the next startup information in the startup register 41. , Reset the CPU and restart. At this time, the value of the diagnosis result register 42 is used for the start information written in the start register 41, and the failed CPU is not started, but the spare CPU 3 is set to be started instead.

【0025】

In addition, an initialization completion register 44 is provided, and the master CPU writes "1" here after the initialization is completed to ignore subsequent writing to the reset register 43 and prevent malfunction.

【0026】

Whether or not there is a failure in the CPU is determined by reading the value of the diagnosis result register 42 after waiting for a certain period of time after the CPU finishes the initial diagnosis. Here, it is assumed that the waiting period is sufficient for other CPUs to complete the initial diagnosis.

【0027】

On the other hand, in case both of the started CPUs are out of order, a timer 48 is provided inside the chipset 4, and when this overflows, the start information is written to the start register 41 and the start CPU is switched. Reboot.

【0028】

Therefore, the measurement period of the timer 48 is set to be sufficiently longer than the time required for the initial diagnosis of the CPU and the internal wait. Also, when '1' is written to any bit of the diagnosis result register 42, the timer 48 stops.

【0029】

If there is only one CPU that operates normally even after rebooting, it will start as a system with 1 CPU. In logic circuits 47 and CPU bus 7 that support 2 CPUs, the logical ID number is used to distinguish each operating CPU. Normally, the CPUs 1 and 2 to be started are logical ID numbers = physical ID numbers, and when the spare CPU3 is started, the physical ID number of the failed CPU is assigned as the logical ID number.

【0030】

Therefore, even in this case, the logical ID numbers used in the system are # 0 and # 1. In addition, as for the signal from the dedicated signal port 45 directly connected to the three CPUs including the spare CPU 3, the signal of the two CPUs to be started by the selector 46 is selected based on the status of the start register 41, and the logical ID number is selected. It is connected to the logic circuit 47 corresponding to 2 CPUs as a signal of CPUs # 0 and # 1.

【0031】

Similarly, as the dedicated signal from the logic circuit 47 to the spare CPU3 of the physical ID number # 2, the signal of the logic ID number # 0 or the logic ID number # 1 is selected and output based on the status of the start register 41. Will be done.

【0032】

In this way, even if there is a CPU failure, the system can be started up without changing the number of operating CPUs or the logical configuration. In addition, when a failure is detected from any of the CPUs, a failure detection is displayed on a console screen or the like (not shown) to prevent the failure from being left unattended.

【0033】

FIG. 3 is a flowchart showing the processing operation at the time of system initialization in the chipset 4 of FIG. 1, and FIG. 4 is a flowchart showing the processing operation at the time of system initialization in the CPU of FIG.

【0034】

Further, FIG. 5 is a flowchart showing a procedure for setting a logical ID number according to an embodiment of the present invention, and FIG. 6 (a) is a diagram showing an initial state of the start register 41 of FIG. 1 and FIG. 6 (b). Is a diagram showing writing of start information to the start register 41 in FIG.

【0035】

A system startup procedure according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6. Although not shown, the CPUs 1 and 2 and the spare CPU 3 are provided with control memories corresponding to each, and the CPUs 1 and 2 and the spare CPU 3 and the chipset 4 are provided in the control memory and the memory 6 respectively. By executing the stored program, the processing operations shown in FIGS. 3 to 5 shall be realized. In addition, ROM (read-only memory), floppy disk, or the like can be used as the control memory.

【0036】

First, after resetting the system (step S1 in Fig. 3), the initial state [see 301 in Fig. 6 (a)] is set in the start register 41 of the chipset 4, and the initialization completion register 44 is '0'. Is set to (Fig. 3, step S2). In addition, all '0' is set in the diagnosis result register 42 (step S3 in FIG. 3).

【0037】

After this, the CPU whose start register 41 is set to '1' in chipset 4 (the CPU with physical numbers # 0 and # 1 by default) is released (Fig. 3, step S4), so the CPU Start the operation (Fig. 4, step S21). At this time, the chipset 4 waits until the timer 48 overflows or the diagnosis result register 42 is written (Fig. 3, steps S5 and S6).

【0038】

The started CPU first determines its own logical ID number (Fig. 4, step S22). Here, the detailed operation of this step S22 is shown in FIG. If the own device is not a spare CPU (step S41 in Fig. 5), the started CPU uses its own physical ID number as the logical ID number (step S42 in Fig. 5).

【0039】

On the other hand, if the own device is a spare CPU (step S41 in Fig. 5), the started CPU reads the value of the start register 41 in the chipset 4 (step S43 in Fig. 5), and the CPU is out of order (startup register). The smallest physical ID number of the CPUs that have not been started (that is, the value of is '0') is set as the own logical ID number (Fig. 5, step S44).

【0040】

Next, each CPU executes the initial diagnostic program (Fig. 4 step S23), and if the diagnosis is not completed normally (Fig. 4 step S24), it stops there (Fig. 4 step S25).

【0041】

When the initial diagnosis is completed normally (Fig. 4, step S24), each CPU writes '1' to the corresponding bit in the diagnosis result register 42 (Fig. 4, step S26). If there is a '1'write in the diagnostic result register, Chipset 4 stops timer 48 (step S7 in Figure 3) and monitors the write to reset register 43 or initialization complete register 44 (step S8, Figure 3). S9).

【0042】

A CPU that has successfully completed the initial diagnosis waits for a sufficient period for another CPU to complete the initial diagnosis (Fig. 4, step S27). After that, the values of the diagnosis result register 42 and the start register 41 are read out (step S28 in FIG. 4), the master CPU is determined (step S29 in FIG. 4), and the values of the diagnosis result register 42 and the start register 41 are compared. Detects a failed CPU (Fig. 4, step S30).

【0043】

In the master CPU determination in step S29, the CPU with the youngest logical ID number among the CPUs that have successfully completed the initial diagnosis becomes the system master CPU. If there is no failed CPU in step S30, or if there is a failed CPU but it has been restarted (Fig. 4, step S35) (This is determined by the bit value corresponding to the spare CPU 3 in the startup register. The master CPU writes '1' to the initialization completion register 44 (Fig. 4, steps S31 and S32). This completes the CPU initialization (Fig. 4, step S33) and proceeds to the chipset 4 initialization (Fig. 4, step S34).

【0044】

When the chipset 4 detects that '1' has been written to the initialization completion register 44 as in the case of the above CPU (step S9 in FIG. 3), the initialization of the CPU is completed (step S10 in FIG. 3). Proceed to chipset 4 initialization (Fig. 3, step S11).

【0045】

If there is a failed CPU in step S30 and it has not been restarted in step S31 (Fig. 4 step S35), the CPUs other than the master stop operating (Fig. 4 steps S36, S38), and the master CPU A write operation is performed to the reset register 43 (step S37 in FIG. 3), and the operation is stopped (step S38 in FIG. 4).

【0046】

Chipset 4 detects the overflow of timer 48 in step S5 and before restarting (step S12 in FIG. 3), or when there is a write operation from the CPU while monitoring the reset register 43 (step S12 in FIG. 3). Fig. 3 Step S8), set the next start information in the start register 41 (Fig. 3 step S14), reset the CPU (Fig. 3 step S15), and return to step S3.

【0047】

The value written to the start register 41 in step S14 is a value based on the contents of the diagnosis result register 42 [see 302 in FIG. 6 (b)]. The bit corresponding to the physical ID numbers # 0 and # 1 is the value of the diagnosis result register 42, and the bit corresponding to the failed CPU is '0', and it will not start next time.

【0048】

Also, set the bit corresponding to the spare CPU3 (physical ID number # 2) to '1' and make sure that it starts. Even if the overflow of timer 48 is detected in step S5, if it is restarted in step S12, it indicates that there is no CPU that has completed the initial diagnosis normally, so it cannot be started and the system stops (Fig.). 3 steps S13).

【0049】

In the above-described embodiment, the timer 48 is stopped if there is even one CPU for which the diagnosis has been normally completed, and the subsequent processing is performed by the CPU. It is also possible to do this under the initiative of the chipset.

【0050】

FIG. 7 is a block diagram showing an internal configuration of a chipset according to another embodiment of the present invention. In the figure, the chipset according to another embodiment of the present invention has the same configuration as that of one embodiment of the present invention shown in FIG. 2 except that the reset register 43 is deleted and the comparison circuit 49 is provided. The elements have the same code. Moreover, the operation of the same component is the same as that of one embodiment of the present invention.

【0051】

The comparison circuit 49 is a circuit that compares the values of the start register 41 and the diagnosis result register 42. The system configuration including the chipset 4 according to another embodiment of the present invention has the same system configuration as one embodiment of the present invention shown in FIG.

【0052】

FIG. 8 is a flowchart showing the processing operation at the time of system initialization in the chipset 4 of FIG. 7, and FIG. 9 is a flowchart showing the processing operation at the time of system initialization in the CPU of FIG.

【0053】

The system starting procedure according to another embodiment of the present invention will be described with reference to FIGS. 1 and 7 to 9. The processing operations shown in FIGS. 8 and 9 are realized by the CPUs 1 and 2, the spare CPU 3, and the chipset 4 executing the programs stored in the control memory (not shown) and the memory 6. And. A ROM, floppy disk, or the like can be used as the control memory.

【0054】

After the reset release of step S51, steps S51 to S54 of the chipset 4 and steps S71 to S76 of the CPU are the same as S1 to S4 of FIG. 3 and S21 to S26 of FIG. After that, the chipset 4 waits until the diagnosis result register 42 matches the start register 41 in the overflow of the timer 48 or the comparison circuit 49, that is, until all the start CPUs are available (Fig. 8, steps S55 and S56).

【0055】

On the other hand, the CPU that wrote '1' to the diagnosis result register 42 in step S76 enters a loop that continues reading until the initialization completion register 44 becomes '1' (Fig. 9, steps S77, S78, S83). ..

【0056】

When the values of the diagnosis result register 42 and the start register 41 match in step S56, the chipset 4 stops the timer 48 (step S57 in FIG. 8) and sets '1' in the initialization completion register 44 (FIG. 8). After completing the CPU initialization (Fig. 8 step S59), proceed to the chipset 4 initialization (Fig. 9 step S60).

【0057】

Even if the overflow of the timer 48 is detected in step S55, if it is after restarting (step S61 in FIG. 8), '1' is written to the initialization completion register 44 to complete the initialization (step S58 in FIG. 8). , S59).

【0058】

When the CPU confirms that '1' is written in the initialization completion register 44 in step S78, it reads the value of the diagnosis result register 42 (Fig. 9 step S79) and determines the master CPU based on it. Then, the CPU initialization is completed (Fig. 9 step S81), and the chipset 4 initialization is proceeded (Fig. 9 step S82).

【0059】

If the chipset 4 detects the overflow of the timer 48 in step S55 and has not restarted in step S61, set the next start information in the start register 41 (Fig. 8 step S62) and reset the CPU. Multiply (Fig. 8 step S63). At this time, the CPU that normally completed the initial diagnosis is in the loop stage of steps S77 and S78, and returns to step S71 when the reset occurs (step S83 in FIG. 9).

【0060】

In the above embodiment, the operation of the chipset 4 becomes a little complicated, so that the amount of hardware increases a little, but there is an advantage that the initialization program of the CPU becomes simple.

【0061】

In this way, by equipping and duplicating the spare CPU3, the spare CPU3 can be operated instead of the failed CPU, so even if there is a failed CPU, the system can be operated without reducing the number of operating CPUs. Can be made to.

【0062】

Also, by assigning the logical ID number assigned to the failed CPU to the spare CPU3 that runs in place of that CPU, the CPU with the same logical ID number can always run, so it is physical due to a CPU failure. Even if a spare CPU 3 is used, there is no change in the control logic on the chipset 4 side, and the software does not need to be aware of it.

【0063】

In connection with the description of the claims, the present invention may further take the following aspects.

【0064】

(1) A multi-processor system including a plurality of central processing units and a chipset that controls the plurality of central processing units, and a spare central processing unit arranged in advance and provided in the chipset. A multi characterized by having a means for activating the spare central processing unit in place of the central processing unit in which the failure occurred when a failure occurs in any of the plurality of central processing units at the time of initialization. Processor system.

【0065】

(2) When the spare central processing unit is started in place of the central processing unit in which the failure has occurred, the logical identification information previously given to the central processing unit in which the failure has occurred is given to the spare central processing unit. The multiprocessor system according to (1), wherein each of the plurality of central processing units and the spare central processing unit includes the means for processing.

【0066】

(3) The chip set includes a logic circuit for controlling the plurality of central processing units, a start register indicating the central processing unit to be activated, a diagnosis result register indicating the failure status of each of the plurality of central processing units, and a re-action. It includes a reset register indicating a central processing unit to be activated at startup and an initialization completion register indicating the completion of initialization of the plurality of central processing units, and rewrites the contents of the activation register based on the contents of the diagnosis result register. The multi-processor system according to (1) or (2), wherein the spare central processing unit is activated in place of the central processing unit in which the failure has occurred.

【0067】

(4) It is a processor duplication method of a multi-processor system including a plurality of central processing units and a chipset that controls the plurality of central processing units, and at the time of initialization, one of the plurality of central processing units is used. A processor duplication method, characterized in that the chipset has a step of activating a pre-arranged spare central processing unit in place of the central processing unit in which the failure occurred when a failure occurs.

【0068】

(5) When the spare central processing unit is started in place of the central processing unit in which the failure has occurred, the logical identification information previously given to the central processing unit in which the failure has occurred is given to the spare central processing unit. The processor duplication method according to (4), wherein each of the plurality of central processing units and the spare central processing unit includes the steps to be performed.

【0069】

[Effect of the invention]

As described above, according to the multi-processor system of the present invention, in a multi-processor system composed of a plurality of central processing units, any of the plurality of central processing units is provided when a spare central processing unit is arranged in advance and initialized. By starting a spare central processing unit instead of the central processing unit that failed in the event of a failure, the possibility that the number of operating CPUs will decrease and the performance will drop significantly in the event of a failure should be minimized. It has the effect of being able to.

【0070】

Further, according to the other multiprocessor system of the present invention, in addition to the above configuration, the central processing unit in which the failure occurred when the spare central processing unit is started in place of the central processing unit in which the failure occurred is previously used. By assigning the assigned logical identification information to the spare central processing unit, there is an effect that it is possible to equip a redundant CPU in place of the failed CPU without equipping the originally unnecessary control logic.

[Simple explanation of drawings]

[Figure 1]

It is a block diagram which shows the structure of the multiprocessor system by one Example of this invention.

[Figure 2]

It is a block diagram which shows the internal structure of the chipset of FIG.

[Fig. 3]

It is a flowchart which shows the processing operation at the time of system initialization in the chipset of FIG.

[Fig. 4]

It is a flowchart which shows the processing operation at the time of system initialization in the CPU of FIG.

[Fig. 5]

It is a flowchart which shows the setting procedure of the logical ID number by one Embodiment of this invention.

[Fig. 6]

(a) is a diagram showing the initial state of the activation register of FIG. 1, and (b) is a diagram showing the writing of activation information to the activation register of FIG.

[Fig. 7]

It is a block diagram which shows the internal structure of the chipset by another Example of this invention.

[Fig. 8]

It is a flowchart which shows the processing operation at the time of system initialization in the chipset of FIG.

[Fig. 9]

It is a flowchart which shows the processing operation at the time of system initialization in the CPU of FIG.

[Explanation of symbols]

1,2 CPU 3 Spare CPU 4 chipset 5 I / O bus 6 memory 7 CPU bus 41 Startup register 42 Diagnostic result register 43 reset register 44 Initialization complete register 45 Dedicated signal port for each CPU 46 Selector 47 Logic circuit 48 timer 49 Comparison circuit