System and multiplexer/ demultiplexer for the transmission/ reception of digital television information

The present invention refers to a system for transmitting / receiving digital television information (video + audio), in particular for High Definition television information (HDTV).

The invention also includes the multiplexers / demultiplexers used for the realization of the system in question.

In the multiplexing / demultiplexing systems, the data are usually arranged in transmission at a fixed distance in the frame and in reception are separated according to this predetermined sequence. However, in the case where data must be transmitted at different speeds, things get complicated and the classic system is no longer usable. To date there is not an adequate system for solving the problem, precisely because of the need to transmit data series at different speeds.

The first object of the present invention is to provide a simple and effective system for transmitting data at different speeds.

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Another object of the invention is to provide a multi-unit / dematerial plator structure, particularly suited to the system in question. The system according to the invention is now characterized substantially by the fact that the data at different speeds are no longer sent as such directly to the multiplexing stage but are collected externally from the multiplexer, in pack forming means of predetermined structure; whenever such means have formed a package they send a request to the multiplexing stage; different priorities are assigned to the different sources, so that in case of simultaneous transmission requests the one coming from the packet source to which the highest priority is associated is accepted.

Figures 1 and 2 show the transmission or reception patterns of the system according to the invention. The data at different speeds VI, V2 .... Vn arrive separately to collectors-formers of RFP1 packets, RFP2 ..... RFPn, constituted in this case by buffers 1, 2,

3 .... n, which are connected via the lines Ll .... Ln and the common line to the MUX multiplexer. According to the invention when one of the buffers (e.g.) shows that there is a number of data ready to be sent, that is equal to the length of a packet, the RQo request is generated at the MUX to inform it of the availability of the package and to have permission to send it. MUX processes the request from RQo together with the possible other simultaneous requests from RQ1 to RQn and if these do not have higher priority than the one assigned to RQo, it authorizes the output of the accumulated data packet at VI speed in buffer 1. The in this case, the higher priority will correspond to the data concerning the audio, followed by the fixed data of the video part.

These priorities can be changed at any time.

Once the RQi Send request has been recognized, MUX generates the corresponding timings and synchronisms K1 and SIN: MUX communicates with the packet forming circuits via lines lj, I2 »11.

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Director Ricueu or Centrel Development »(Fnncosco Molo)

The data transmission is performed after having made a redundancy insertion for a future correction of errors by means of an FEC (Forward Error Corrector).

In reception {figure 2) the circuit must recognize to which buffer ', 2¹'No ....¹each package received must be destined.

To do this we rely on the definition of the type of package contained at the beginning of the package itself (as you will see 'about fig.9 that makes' understand how to build the plot and packages) assigning to each area certain types of packages. In order to make this information alterable and programmable according to the future needs of the global system, the output decision does not take the DEMUX demultiplexer in a fixed manner, but supplies said information, after having extracted it from the frame, to an external decision circuit of the destination of the information itself PAL, via 11 PT bus. PAL decides correspondingly to the assignment table agreed on a case-by-case basis (which as with the priority 'RQi can' be easily modified) and from '

In accordance with the information given by OS 11 DEMUX demultiplexer decides what type of synchronism and timing ΚΊ, SIN 'must generate for the data output; these signals are transmitted on the lines i, 1, 1,., while the information is transmitted on the lines I, L'2 .... The no.

As speed of data output and according to the quantity of information to be sent, the following channel speeds are foreseen:

channel to 34 Mbits / s channels at 34 Mbits / s channel at 140 Mbits / s

Each possibility gives us a "higher quality" the higher the speed for the obvious greater amount of data we can send at the same time.

In the first two cases, the whole part of multiplexing / demultiplexing is carried out in the semicustom circuit, and in the last case, given the high speed of the final stages, the series-parallel conversions, paralleloseries and the interfaces of the lines are realized in logic ECL externally.

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The distribution of the information is based on frames {fig.9) formed by two data packets with 238 words of 16 bits, plus a first word that contains in the first 8 bits the definition of the type of package, mentioned above , the said information being protected by a Hamming code, error corrector, plus 16 other 16-bit redundancy words for error correction. The plot will be initiated by a 24-bit alignment word, plus 8 bits which will be a status word given by an external system.

As a continuation of the alignment word, a 16 bit information will be inserted, which will be the one that will allow us to recover the synchronism of the video.

All these data are transmitted in the form of 8-bit words, even if after the buffers they can be grouped into words of greater or lesser length.

In the case of 34 Mbit / s the functioning of the mux / demux is similar to a normal system, with the exception that the sending of data is carried out by packages and not according to a fixed sequence. Demultiplexing is carried out by revealing the alignment word and once the alignment has been acquired, the initial heads of the packets are revealed and the information relating to the area to which the packet received is to be sent is obtained.

In the case of 140 Mbit / s data are multiplexed in MUX, however, the series and line code conversion is performed externally to the circuit, in the ECL logic, for obvious reasons of speed of work; in reception 1 data enter DEMDX, already converted in parallel, directly to the input elastic memory, and follow the normal course of first.

The most interesting part is the one related to the 2 * 34 Mbits / s in which two independent channels Cl, C2 (resp. C'I, C'2) are used to transmit all the information. Up to now, always to increase the speed of data to be transmitted in a system, we resorted to the use of a higher hierarchy of data, with the consequent need to use a transmission medium at a higher frequency. This obliges to use, in the case of radio communication, for example, increasingly higher channels with the consequent problems of frequency increase, in the microwave field.

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Director of Research and Development Centrtl · (Frtnceico Molo)

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In our case a speed of 2x34Mbit / s with 8 bit words has been advantageously adopted, but the following explanation refers to a generic system.

The system according to the invention allows a given hierarchy to be used to transmit a double velocity information using two independent flows for the transmission of a single information.

In this way it is advantageously possible to use the same type of transmission means (duplicated) without needing to access another higher means.

According to an aspect of the invention, the information is divided into two streams, separating one part from the other and returning to collect it in reception to obtain the original information. In order to act in this way we have to synchronize the two independent flows and compensate for the time differences between the flows for the different delays to which they are subject for differences in the transmission medium.

In Fig. 3 the system according to the invention has been schematically represented. In transmission the flow of words to N bit, Fri, is divided into two flows of words with N / 2 bits, FI, F'I. Due to the differences in the transmission time TO and the variations in the delays, the two flows FI and F'I arrive with delays DELAY1 and DELAY2, in addition to variations in speed.

In reception we must now compensate these variations in order to return to having the original words to Nbit.

According to an aspect of the invention, as an indication of the difference between the transmission times of the two flows, the information obtained from the time difference in the appearance of the alignment word is used.

In transmission, the N / 2 bits with the highest weight of the word of N and the other N / 2 with the lowest weight (eg fig.l) are sent on a channel Cl. In reception, several factors must be taken into account:

each channel to be independent will have different delays, therefore we will have to compensate for the differences in time between the two information, as already mentioned;

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Rlctrcj and Cantrw Development Guidelines · (Frtncotcp Molo) as additional performance you can add a channel detection by assigning each of the information;

For this second possibility a different detection of words of alignment is introduced for each channel, generating a high or low channel indication. This automatically compensates for changes in entry channels.

For the compensation of the delay a more complex process is followed which can be better understood with reference to figures 4, 5 and 6. In fig. 4 are the flows FI, F'1 of entry which are now introduced into an elastic memory Me with different clocks. The name of elastic memory is given because it is a memory where the reading-writing distance is variable, being data entered with a clock and being read with another clock. The function of a memory of this type is to absorb the instantaneous variations of the writing clock and, moreover, in our case, to synchronize the bits, since for the writing each flow uses a clock, while for the reading one uses one same master clock in the two memories. Obviously a PLL must be used to obtain that the writing and reading frequencies are the same, in order to avoid fills and emptying of the elastic memory ME, which, as already said, must absorb the instantaneous variations. Therefore, at the output of the elastic memory we will obtain the two information synchronized in the duration of the bits, read in the two fuses with the same clock, as we can see from fig. There will be a clock-level synchronization and a bit-level realignment. read in the two fuses with the same clock, as you can see from fig. There will be a clock-level synchronization and a bit-level realignment. read in the two fuses with the same clock, as you can see from fig. There will be a clock-level synchronization and a bit-level realignment.

Each of the information (packets PA11 ... PA21, PA12 ... PA22) switches to an alignment detector that provides us with the words correctly aligned and formed as they were originally, thanks to the revelation of the word of alignment, and so we will know what is the correct bit to start each word. Therefore, at the entry of the RI 1ineator, as shown in Figure 5, we will have the two flows, (represented by the continuous line) which must be correctly aligned.

At the exit we will have the words aligned correctly, but there is one

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Director

Htelettra siait or ba to radio eM · Research and Development Centtel · time difference between the appearance of the alignment words in each flow. This difference gives us the average of the delay between the two plots, which we will have to compensate. So far we have achieved word synchronism.

To understand how we compensate for the time difference, we will begin by defining a flow as a master and the other as a slave. The master flow is the one to which we have hooked the clock frequency of the circuit. The difference between the appearance of the alignment words in the secondary flow, can be positive or negative, with respect to the master flow, that is 'can' go ahead or late. In other words, the time difference can be positive or negative. One can only reveal the difference in time between the appearance of the two words of alignment. This difference must be compensated. To do so, the master stream is always delayed by a fixed value T so that the alignment word always appears at the output, T words after being revealed.

Slave flow can travel in advance or late compared to the other flow. To find out, the alignment detector starts a counter for each of the flows. At the instant when the alignment word has appeared in the two channels, the difference in time between the two will be given by the difference between the two counters CNT1-CNT2 (CNT1 - master channel counter, CNT2 - slave channel counter). This value can be positive or negative, depending on whether the alignment word in the master channel or in the slave channel has appeared before.

We will call this value D so that:

CNT1-CNT2 = D

As mentioned above, the master flow was however delayed by a fixed value T, therefore we will have that at the instant of time tOI the alignment word appears in the master channel and at the instant t02 in the slave channel. The difference between 1 two will be:

tOl-tO2 = D * tp; [1]

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Piatren Director and Central Development (Frenetico Molo)

t.lUA where tp is the duration of a word.

The alignment word after the delay appears in the time tOtl, given by the expression tOtl-tOl + T * tp;

In the slave channel we will have to include a delay TS that will give us the output at the instant t0t2, given by:

t0t2 = t02 + TS * tp;

The solution we are looking for is that t0tl = t0t2, from which:

tOtl «tOl + T * tp]] t01 + T * tp = t02 + TS * tp;

tOt2 «= tO2 + TS * tp]

TS * tp = tOl-tO2 + T * tp;

replacing [1]

TS * tp = D * tp + T * tp;

TS-D + T

Therefore we will have a variable delay line, in which we assume that the minimum value of TS * = 0, (delay the signal of a negative number would be equivalent to accelerate it) so that:

D + T = 0;

-T <D <T;

from which

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0 <TS <2T;

In our case, the value of T has been chosen equal to 64 so that, as we speak of words, it will be a delay of 64 * 4 bit-256 bits; TS can vary between 0 and 512 bits, which in the case 2 * 34 Mbit / s, gives us a bit time of 1/34 / us and a delay compensation of 256 * 1 / 34,368 / us- -7.5 / lis , in advance or late.

Comparing this total time value of the plot, which would have a length (always for our particular application)

2 * (238 * 16 + 16 + 16 * 16) + 2 * 16 + 16 = 8208 bits with a frame time for 2 * 34 of

8208 * 1 / (2 * 34.368) Is.-119.413 / us

By expressing compensation in another way, we can see how

256 ________ - 3.118%

8208

The realization of the variable delay line admits two variants: a memory in which the distance reading-writing would fix the delay of the same;

a line of sliding registers, forming delays of 2'N and electing the delay to be applied by means of a selection of multiplexers.

As a preferable embodiment the second option has been adopted which is easier to implement. A representation of the realization of the two options is shown in Figures 7 and 8 respectively. At the output of the delay lines we will have the frame synchronism, with which, provided that the difference in delay between the two frames is less than the fixed value, we will have the two channels totally synchronized. In the event that it is not possible to compensate for the delay, we generate an external alarm.

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This alarm should only reveal that the absolute value of D is greater than the maximum expected.

As can be seen from Figure 6, at the output of the system SC of compensation of the delay, we will have the two plots totally synchronized and the only thing we have to do is to join the two words of N / 2 bits in words of N bit for return to having the original information.

Another performance that is contemplated by the circuit is the possibility of working as a "repeater", directly introducing data from another demultiplexer, and through an external selection to replace those packages that interest us in the point of the contribution network and adding more information in those packages that we have left free in transmission in anticipation of this possibility ', as' said before.

This is accomplished by the introduction of data for another bus and, in the case of detection of a "replaceable" package, it is replaced by one of those set externally.

To summarize and better fix the ideas:

in Fig. 3 is represented by Fn the flow consisting of words of length N, which at the time TO is divided into two flows FI and F'1, of words of length N / 2. FI arrives at demultiplexer DEMUX at the time TO + delay 1, F'1 arrives at TO + delay 2; DEMUX puts together FI and F'2 compensating the respective delays 1 and 2 and thus reconstructing the original flow F'n of words of length N .;

Figure 4 shows the resilient memory ME which realigns at the bit level between FI and F2 and the synchronization at the clock level;

Fig. 5 shows the synchronization detector RI and therefore at word level;

1n figure 6 shows the compensation system with realignment at the package level;

Fig. 7 shows the variable delay line (to compensate for the delay of Fig.6) realized with a classical scheme, that is a memory that receives the input data IN and returns it to the output OUT with a delay which is 'equal to the distance between read-write; for this purpose gtelettra (Frencetpo Molo) the writing is controlled by the WC counter whose count added by the delay TS controls the reading;

in fig.8 the delay line is advantageously realized by a series of MUXs preceded by registers that give shift 2'N, 2 '(NI) .... respectively 1. At the first MUX the IN signal arrives, the one from the register with shift 2'N and that of a LATCH supplied by the delay signal TS. Each MUX following the first will receive signals from the previous MUX, from the descending shift register 2 (N-1) etc., and from the LATCH.

Figure 9 shows the diagram for the formation of two packages (first second packet PACI, PAC2) as examples.

In a particularly simple and advantageous embodiment, the frame consists of two PACI packages, PAC2 of 255 words of 16 bits each; at the top of each package are placed two 16-bit words reserved for the alignment words (24 bits) ALIN1, ALIN2, ALIN3, and the status word (STATUS) (8 bits) plus two other 16-bit words for synchronization video (VIDEO FREC). Each package is protected by an error correction code (FEC). The first 16 bits of each package contain information about the source it comes from (PACKET ΤΥΡΕ). Transmission from the Bi buffer to the MUX multiplexer and from the DEMUX demultiplexer to the ΒΊ buffer takes place using 8-bit words (PI, P2). It has already been said that the multiplexer can operate at three different speeds: 1 flow at 34 Mb / s; 2 flows at 34 Mb / s; 1 flow at 140 Mb / s. In the first two cases all the mu-demultiplation operations are advantageously carried out internally to the semicustom circuit while in the third case the series / parallel conversion and the interface of lines are performed in ECL logic externally due to the very high speed. In the case of 2 flows at 34 Mb / s, there is the advantage of working at a double frequency of 34 Mb / s, but using the transmission rate of 34 Mb / s on two independent flows. To obtain the original information, in reception we will gather 1 two flows in a correct way synchronizing the two incoming streams. In transmission, the 8-bit words are divided into two by 4 bits (the 4 most significant and the 4 least significant) and transmitted independently. On receiving it is

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IKltWtUnt IKtoaii T «itiURfSftP òirtfriW CffmnW Mstolf different words of alignment) thus compensating for possible channel exchanges. The two received streams are written in two elastic memories with different writing clocks extracted from the flows and are read with the same clock that is the one related to the master flow (fig.4). Then there is an aligner RI (fig. 5) on each way, at the exit from each of them a correctly aligned flow is obtained; since there may be a time difference between the position of the alignment word in one flow relative to the other, it is compensated by the variable delay line SC (FIG. 6) which in the preferred embodiment of FIG. registers entered via MUX. As already noted, the system can ' to work as a repeater in which case free packets are replaced with those that are of interest. For scruple of illustrative clarity the invention has been described with reference to the embodiments shown in the drawings; it is obvious, however, that various variations, modifications, substitutions and the like can be made without departing from the spirit or scope of the invention.