Optic inspection method and apparatus

OPTIC INSPECTION METHOD AND APPARATUS

OPTIC INSPECTION METHOD AND APPARATUS

FIELD AND BACKGROUND OF THE INVENTION

The present invention relates to a method and apparatus for optically inspecting the surface of an article for defects. The invention is particularly useful for optically inspecting patterned semiconductor wafers used in producing integrated-circuit dies or chips, and the invention is therefore described below particularly with respect to this application.

The inspection of unpatterned semiconductor wafers for surface-lying particles is relatively simple and can be easily automated. In one known type of such system, the. wafer is scanned by a laser beam, and a photodetector detects the presence of a particle by collecting the light scattered by the particle.

However, the inspection of patterned semiconductor wafers for defects in the pattern is considerably more difficult because the light scattered by the pattern overwhelms the light scattered from the particles or defects, thereby producing high rates of false alarms.

The existing inspection systems for inspecting patterned wafers are generally based on analyzing high resolution two-dimensional images of the patterned wafer utilizing an opto-electric converter, such as a CCD (charge-coupled device), on a pixel-by2 pixel basis. However, the extremely large number of pixels involved makes such systems extremely slow. For this reason, the inspection of patterned wafers is done at the present time almost only for statistical sampling purposes. As a result, microdefects in patterned semiconductor wafers remain largely undetected until a considerable number of such wafers have been fabricated and have begun to exhibit problems caused by the defects. The late discovery of such defects can therefore result in considerable losses, low yields, and large downtimes.

There is therefore an urgent need to inspect patterned semiconductor wafers at relatively high speeds and with a relatively low false alarm rate in order to permit inspection during or immediately after the fabrication of the wafer so as to quickly identify any process producing defects and thereby to enable immediate corrective action to be taken. This need is made even more critical by the increasing element density, die size, and number of layers in the integrated circuits now being produced from these wafers, and now being designed for future production, which requires that the number of microdefects per wafer be drastically reduced to attain a reasonable die yield.

OBJECTS AND BRIEF SUMMARY OF THE INVENTION

An object of the present invention is to provide a novel method and apparatus having advantages in the above respects for inspecting the surface of articles for defects.

In particular, an object of the invention is to provide a method and apparatus for automatically inspecting patterned semiconductor wafers characterized by a relatively high speed and relatively low rate of false alarms such that the patterned wafers may be tested while the wafers are in the production line to quickly enable the fabrication personnel to identify any process or equipment causing yield reduction, to receive fast feedback information after corrective actions, and to predict potential yield loss.

A still further object of the invention is to provide an inspection method and apparatus which are capable of inspecting all the critical layers, and which supply data on defects caused by the presence of particles and defects in the patterns.

According to the present invention, there is provided a method of inspecting the surface of articles for defects, comprising: placing the article to be inspected on a table; in a first phase examining the complete surface of the article on the table at a relatively high speed and with a relatively low spatial resolution; outputting information indicating suspected locations on the article having a high probability of a defect; storing the outputted information in a storage device; and automatically, in a second phase while the article is still oh the table, examining with a relatively high spatial resolution only the suspected locations stored in the storage device for the presence or absence of a defect in the suspected locations.

According to further features of the invention, the first examining phase is effected by optically scanning the complete article surface to be inspected; and the second examining phase is effected by imaging only the suspected locations on a converter which converts the images to electrical signals and then analyzes the electrical signals.

According to still further features in the preferred embodiment of the invention described below, the surface of the article to be inspected includes a pattern, e.g., a patterned wafer used for. producing a plurality of integrated-circuit dies or chips. The first examining phase is effected by making a comparison between the inspected pattern and another pattern, serving as a reference pattern, to identify locations on the inspected pattern wherein there are sufficient differences with respect to the reference pattern to indicate a high probability of a defect in the inspected pattern. The second examining phase is also effected by making a comparison between the inspected pattern and the reference pattern, to identify locations on the inspected pattern wherein the comparison shows sufficient differences with respect to the reference pattern to indicate the presence of a defect in the suspected location of the inspected pattern.

It will thus be seen that the novel method of the present invention primarily monitors changes in the defect density while maintaining a high throughput with a relatively low false alarm rate. Thus, the first examination is done at a relatively high speed and with a relatively low spatial resolution to indicate only suspected locations having a high probability of a defect; and the second examination is done with a relatively high spatial resolution but only with respect to the suspected locations having a high probability of a defect. The sensitivity of the two phases may be adjusted according to the requirements for any particular application. Thus, where the application involves a relatively low number of defects, the sensitivity of the first examination phase may be increased to detect very small defects at a high speed but at the expense of an increased false alarm rate. However, since only relatively few suspected locations are examined in the second phase, the overall inspection can be effected relatively quickly to enable the fabrication personnel to identify defects caused by any process or equipment, and to immediately correct the cause for such defects.

According to a further feature of the invention, the first examining phase is effected by generating a first flow of N streams of data representing the pixels of different images of the inspected pattern unit; generating a second flow of N streams of data representing the pixels of different images of the reference pattern unit; and comparing the data of the first flow with the data of the second flow to provide an indication of the suspected locations of the inspected pattern unit having a high probability of a defect.

According to still further features of the invention, the pattern is based on a grid of angularlyspaced lines (e.g., 45° spacing); and the N streams of data in each flow are generated by a circular array of light collectors. The light collectors are located to collect the light in regions midway between the angularly-spaced lines of the grid. Such an arrangement minimizes the amount of pattern-reflected light, collected by the light collectors; that is, such an arrangement does not see most of the pattern, except pattern irregularities, corners and curves.

Preferably, there are eight light collectors each located to collect the light in a region midway between each pair of the angularly-spaced lines of the grid; it is contemplated, however, that the system could include another member, e.g., four such light collectors equally spaced between the grid lines.

According to still further features of the invention, the second examining phase is effected by imaging on a converter each suspected location of the inspected pattern unit and the corresponding location of the reference pattern unit to output two sets of electrical signals corresponding to the pixels of the inspected pattern unit and the reference pattern unit, respectively; and comparing the pixels of the inspected pattern unit with the corresponding pixels of the reference pattern unit to indicate a defect whenever a mismatch of a predetermined magnitude is found to exist at the respective location. Each suspected location of the inspected pattern unit and the reference pattern unit is imaged at a plurality of different depths, and the electric signals of one set are shifted with respect to those of the other set to match the respective depths of the images.

The invention also provides apparatus for inspecting articles, particularly patterned semiconductor wafers, in accordance with the above method.

Further features and advantages of the invention will be apparent from the description below.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:

Fig. 1 is a pictorial illustration of one form of apparatus constructed in accordance with the present invention;

Fig. 2 is a block diagram of the apparatus of Fig. 1;

Fig. 3 is a diagram illustrating the wafer handling and image-acquisition system in the apparatus of Figs. 1 and 2;

Fig. 4 is a diagram illustrating the optic system in the first examining phase of the apparatus of Fig. 1;

Fig. 5 is a top plan view illustrating the disposition of the light collectors in the optic system of Fig. 4;

Fig. 6 is a diagram more particularly illustrating the disposition of the light collectors in Fig. 5, Fig. 6a showing a variation;

Figs. 7 and 7a are diagrams illustrating one of the light collectors in the arrangements of Figs. 6 and 6a, respectively;

Figs. 8 and 8a are diagrams more particularly illustrating the light collecting zones in the arrangements of Figs. 6 and 6a, respectively.

Figs. 9-11 are diagrams illustrating the manner of scanning the wafer in the Phase I examination;

Fig.12 is a block diagram illustrating the Phase I processing system;

Fig. 13 is a block diagram illustrating the main components of the preprocessor in one channel of the processing system of Fig. 12;

Fig. 14 is a block diagram illustrating one channel in the processing system of Fig. 12 following the preprocessor, Fig. 14a illustrating the algorithm involved in one of the operations performed by that system;

Fig. 15 is a block diagram particularly illustrating a portion of the processing system of Fig. 14;

Fig. 16 is a block diagram particularly illustrating the Threshold Processor in the processing system of Fig. 12;

Fig. 17 is a block diagram more particularly illustrating the Pixel Characterizer of Fig. 15, Fig. 17a illustrating the algorithm involved;

Figs. 18, 19 and 20 are block diagrams more particularly illustrating the Ratio, Gradient and Maximum Definition Calculator in the system of Fig. 17;

Figs. 21a and 21b illustrate the nine registers in the Ratio Calculator and Gradient

Calculator, respectively;

Fig. 22 illustrates the Score Calculator in the image processor channel of Fig. 14, Fig. 22a being diagrams helpful in understanding the operation of the crossbar switch (73i) of Fig. 22;

Fig. 23 is a block diagram helpful in understanding the operation of the score calculator of Fig. 22;

Fig. 24 is a block diagram illustrating more particularly the Defect Detector portion of the image processor of Fig. 14;

Fig. 25 is a block diagram illustrating more particulars of the comparator 77 of Fig. 24, Fig. 25a illustrating the algorithm involved;

Fig. 26 is a diagram illustrating the main elements of the Phase II optic system; and

Figs. 27-31 are diagrams illustrating the construction and operation of the Phase II examination system.

DESCRIPTION OF A PREFERRED EMBODIMENT

Overall System

The system illustrated in the drawings is designed particularly for automatically inspecting patterned semiconductor wafers having a plurality of

11׳ like integrated-circuit dies each formed with like patterns. The system inspects each pattern, called the inspected pattern/ by comparing it with at least one other pattern on the wafer, serving as the reference pattern, to detect any differences which would indicate a defect in the inspected pattern.

The inspection is made in two phases: In the first phase, the complete surface of the wafer is inspected at a relatively high speed and with a relatively low spatial resolution; and information is outputted indicating suspected locations on the wafer having a high probability of a defect. These locations are stored in a storage device. In the second phase, only the suspected locations stored in the storage device are examined with a relatively high spatial resolution; and a determination is made as to the presence or absence of a defect. This facilitates identification and correction of the process that created the defect.

The inspection apparatus illustrated in Figs. 1-3 of the drawings includes a table 2 for receiving the wafer W to be inspected. The first phase inspection of the wafer is by a laser 3 outputting a laser beam which scans the complete surface of the wafer W; and a plurality of light collectors 4 arranged in a circular array to collect the light scattered from the wafer and to transmit the scattered light to a plurality of detectors 5. The outputs of the detectors 5 are fed via a Phase I preprocessor 6 to a Phase I image processor 7, which processes the information under the control of a main controller 8. The Phase I image processor 7 processes the outputs of the detectors 5 and produces information indicating suspected locations on the wafer having a high probability of a defect. These suspected locations are stored within a storage device in the main controller 8.

Only the suspected locations having a high probability of a defect are examined by the Phase II examining system. This system includes an optic system for imaging the suspected location on an opto-electric converter, e.g., a CCD matrix 9, which converts the images to electric signals. These signals are fed via a Phase II preprocessor 10 to a Phase II image processor 11 which, under the control the main controller 8, outputs information indicating the presence or absence of a defect in each suspected location examined in Phase II.

In the block diagram illustrated in Fig. 2, the table 2 of Fig. 1, and associated elements involved in the wafer handling system, are indicated generally by block 12. Table 2 is controlled by a movement control system, indicated by block 13, to effect the proper positioning of the wafer on the table 2 in each of the Phase I and Phase II examination phases, and also the scanning of the wafer W in the Phase I examination.

The light detectors 5 of Fig. 1 are included in the Phase I image acquisition sensor indicated by block in Fig. 2; and the opto-electric converter 9 of Fig. 1 is included within the Phase II image acquisition sensor indicated by block Sj in Fig. 2.

Fig. 2 also illustrates a post processor 14 processing the information from the Phase I processor 7; the main controller 8 which manages and synchronizes the data and controls the flow; a keyboard 15 enabling the operator to input information into the main controller 8; and a monitor 16 enabling the operator to monitor the processing of the information.

All the elements in the wafer handling and image acquisition subsystem for both phases are included within the broken-line box generally designated A in Fig. 2; all the elements of the image processor subsystem (both the algorithms and the hardware) for both phases are indicated by the brokenline block B; and all the elements in the operator console subsystem are indicated by the broken-line block C. The latter subsystem includes not only the main controller 8, keyboard 15, and monitor 16, but also a graphic terminal unit, shown at 17 in Fig. 1.

The other elements illustrated in Fig. 1 are described more particularly below in connection with their respective subsystems.

Wafer Handling and Image Acquisition

Fig. 3 more particularly illustrates the wafer handling and image acquisition subsystem Sa (Fig. 2).

This subsection includes the table 2 which is of a large mass (such as of granite). It is mounted on vibration isolators 20 to dampen high frequency vibrations from the outside world.

The subsection illustrated in Fig. 3 also includes the movement controller 13 controlled by the main controller 8. Movement controller 13 controls a one-directional scanning stage 21. This stage moves a vacuum chuck 24 which holds the wafer flattened during its movement in one orthogonal direction with respect to the Phase I sensors 5, as the laser beam from the laser 3 is deflected in the other orthogonal direction to scan the complete surface of the wafer during the Phase I examination.

Movement controller 13 further controls a two-dimentional scanning stage 22 effective, during the Phase II examination, to position the wafer at any desired position with respect to the Phase II detector 9 (the CCD matrix). As described in detail below, the control of one of the axes of this stage serves also during the Phase I examination. Movement controller 13 further controls a rotation/level/focus stage 23, which rotates the wafer about its axis to align it angularly, to level it, and to keep it in focus during scanning. Stage 23 also moves the vacuum chuck 24 and its wafer towards or away from the Phase II sensor 9 to enable producing a plurality of images at different depths during the Phase II examination, as will be described more particularly below.

Fig. 3 also schematically illustrates a wafer handler 25 which transfers the wafer W between the vacuum chuck 24, a wafer prealigner 26, and cassettes 27 and 28. The wafer prealigner 26 initially aligns the wafer angularly and centers it, and also schematically illustrated in Fig. 3 is an optical character recognition unit 29 which reads the wafer identification code.

The foregoing components are generally individually well-known and are therefore not described herein in detail.

Phase I Optic System

As shown in Fig. 4, the laser 3 (e.g., an argon laser) outputs a laser beam which is passed through a polarizer beam splitter 30 oriented in such a way to transmit the laser light to the wafer W, but to reflect the reflected light from the wafer to a photodetector 31. The latter outputs an electric signal controlling the Phase I preprocessor 6. The laser beam from beam splitter 30 is passed through a beam expander 32, then through a cylindrical lens 33a, a deflector 34, another cylindrical lens 33b, a folding mirror 35, a multi-magnification telescope 36, a beam splitter 37, a quarter wavelength plate 38 which converts the linearly polarized light to a circularly polarized light and vice versa, and finally through a microscope objective 39, which focuses the laser beam on the wafer W.

The beam expander 32 expands the laser beam diameter to fill the optic aperture of the deflector 34, and the cylindrical lens 33a focuses the laser beam onto the deflector 34. Deflector 34 is an acoustooptic deflector. It scans the laser beam in one orthogonal direction in a sawtooth pattern in the time domain, while the motion controller moves the table (and the wafer thereon) in the other orthogonal direction in order to scan the complete surface of the wafer. The folding mirror 35 reflects the laser beam into the multi-magnification telescope 36, which matches the laser beam diameter and scan aperture to fit the input requirements of standard microscopic optics. Slit 40 within telescope 36 permits only the first order detracted light of the laser beam to impinge the wafer W.

Beam splitter 37 passes a part of the beam to the wafer, as described above, and reflects another part to an autofocus unit 41, which determines whether the wafer is in the focus of the microscope objective 39. The autofocus unit can be a standard one, such as the one used in the Leitz Ergolux microscope.

The light reflected from the laser beam by the wafer W being inspected is collected by a plurality of light collectors 42 arranged in a circular array around the objective lens 39, as shown more particularly in Figs. 5 and 6. The pattern on the wafer W is based on a grid of lines spaced 45° from each other. The circular array of light collectors 42 are located to collect the light in the regions midway between the angularly-spaced lines of the grid, in order to minimize the amount of pattern-reflected light collected by them. In the example illustrated in Figs. 5 and 6, there are eight of such light collectors 42, each spaced midway between two adjacent grid lines. The apparatus, however, could include only four of such light collectors, as described more particularly below with respect to Figs. 6a, 7a and 8a.

Baffles 43 (Fig. 7) keeps spurious laser light from reaching the wafer W. Further baffles 44 (Fig. 6) between the light collectors 42 limit the field of view of the light collectors 42 to the predetermined region on the wafer to minimize the amount of spurious laser light collected by them.

Each of the light collectors 42 includes an optic fibre having an inlet end 42a (Fig. 7) adjacent to the point of impingement of the laser beam on the wafer W, in order to collect the light scattered by the wafer, and an outlet end 42b adjacent a lens 45 for focussing the light onto a photodetector sensor 46.

The inlet end 42a of each optic fibre is confined to a shaped, curved region, as more particularly illustrated at 47 in Fig, 8. This end of each region has a pair of sides 47a, 47b, converging from a base 47c, which base is located substantially parallel to the table 2 receiving the wafer W to be inspected. The two sides 47a, 47b converge to a pointed tip 47d overlying the table receiving the wafer.

As shown in Fig. 8, the inlet ends of the optic fibres 42 thus define light collecting zones a, separated by non-collecting zones fl. In the illustrated example, the width of each light-collecting zone a is 16° at the bottom surface (47c), and its height (φ) is 49°. Such an arrangement minimizes the pattern-reflected light, and maximizes the defectreflected light, collected by the light collectors.

Another example of the light-gathering optics which may be used is illustrated in Figs. 6a, 7a and 8a, corresponding to the above-described Figs. 6, 7 and

8, respectively. In this example, there are only four light collectors, therein designated 42', located at angles of 45°, 135°, 225° and 315°, respectively. This configuration is useful when the object to be inspected consists of lines in only two orthogonal directions (0° and 90°). Another advantage of this configuration is that the objective 39' may have a higher numerical aperture, and thus the spot size used for scanning may be smaller. The light collecting zones in this configuration are illustrated at 47' in Fig. 8a. As one example, the width a of the light collecting zones may be 30°, and their height may be 45°.

As shown in Fig. 9, the wafer W being inspected is formed with a plurality of integratedcircuit dies D.j-D_n each including the same pattern. In the Phase I examination, the complete surface of the wafer is scanned by the laser beam 3, and the resulting scattered light is collected by the above-described light collectors 42 in order to detect defects, or at least those suspected areas having a high likelihood of including a defect and therefore to be more carefully examined during the Phase II examination. As also indicated above, during the Phase I examination (and also the Phase II examination), the pattern of one die D, serving as the inspected pattern, is compared with the light pattern of at least one other die, serving as the reference pattern, to determine the likelihood of a defect being present in the inspected pattern.

Figs. 9-11 illustrate the manner of carrying out the scanning of the wafer in the Phase I examination.

Thus, as shown in Fig. 9, the laser beam is deflected in the X-direction by the acousto-optic deflector 34 (Fig. 4) so as to form a scanning line shown at 50 in Fig. 11. At the same time, the scanning stage 21 of the table 2 supporting the wafer W moves the wafer beneath the wafer spot at a continuous constant velocity in the Y-direction, to thereby produce a raster scan indicated at 51 in Fig. 11. In the example illustrated, the scanning length of line 50 is 1 mm (1,000 microns); the distance between two adjacent lines is 0.6 microns; and the distance equal to the sampling distance (S ) in the X-direction is similarly 0.6 microns. The spot size of the laser beam, shown at 52, is about 3.0 microns (i.e., covering approximately 5 sample points).

Thus, the scanning stage 21 scans the wafer between the points a and b in the Y-direction, as shown in Fig. 9. As a result, an area is covered having a width (w) of about 1 mm, and a length equal to the distance between point a and b.

The wafer is then moved in the X-direction from point b to point c (Fig. 9) by the scanning stage (Fig. 3), and the area between points c and d is then scanned, and so forth.

The scanning is done in such a way that there is an overlap (t, Fig. 10) between adjacent stripes scanned by the laser beam 52. In the example illustrated in the drawings, the overlap (t) is 0.2 mm.

In this manner, different dies on the same wafer are continuously scanned to produce the scattered light collected by the light collectors 42 (or 42', Figs. 6a-8a) so as to enable a die-by-die comparison to be made of each die, called the inspected die, with another die, called the reference die, to produce an indication of the probability of a defect in the inspected die.

As indicated earlier, the Phase I examination system may include eight light detectors 46 (or four light detectors where the variation of Figs. 6a-8a is used) for inspecting the wafer for defects. However, it may also include a further detector (a reflected light detector) to provide additional information for the registration procedure. Thus, the misalignment may be detected from the reflected light detector image by computing the cross-correlation between a rectangle of pixels in the inspected image, and the rectangle of pixels in the reference image in all possible misalignments. This information may be used where the score matrix computed in the alignment control circuit does not provide a significant indication of the correct misalignment.

Phase I Image Processor

The Phase I examination is effected by: (a) generating a first flow of N streams of data (N being the number of light collectors 42, or 42') representing the pixels of different images of the inspected pattern; (b) generating a second flow of N streams of data representing the pixels of different images of the reference pattern; and (c) comparing the data of the first flow with the data of the second flow to provide an indication by the comparison of the suspected locations of the inspected pattern having a high probability of a defect. The comparison is effected by correcting any misalignment between the two flows of data; comparing the data of each stream of the first flow with the data of the corresponding stream of the second flow to provide a difference or alarm value indicating the significance of the presence of a suspected pixel in the stream; and detecting a defect at a pixel location according to N difference or alarm values corresponding to the N streams of data.

Fig. 12 is a functional block diagram of the Phase I image processor. It includes an input from each of the eight sensors 46a-46b (each corresponding to photodetector sensor 46 in Fig. 7) to their respective preprocessors 6a-6h. The sensors convert the light signals to analog electrical signals, and the preprocessors sample the latter signals at pixel intervals and convert them to digital data. The outputs of the preprocessors are thus in the form of streams of pixel values forming a digital version of the image.

As shown in Fig. 13, the preprocessor 6 in each channel includes a preamplifier 56 which converts the current received from its respective sensor 46 into a voltage and amplifies it to a level suitable as an input to an A/D converter 57. The parameters of amplification can be controlled in accordance with the characteristics of the signal received from the inspected wafer. The A/D converter 57 samples the analog voltage and converts it to a digital value. Sampling of the image is carried out continuously to obtain a two-dimensional image of the object.

Two flows of eight streams of data are thus generated: One flow represents the pixels of eight different images of the reference pattern previously stored in a temporary memory; and the other flow represents the pixels of different images of the inspected pattern to be compared with those of the reference pattern in order to provide an indication of the presence of a defect in the inspected pattern. The detection of defects is made in a Defect Detector circuit 60a-60h for each of the eight streams.

The processing system illustrated in Fig. 12 further includes an Alignment Control Circuit 62 which controls a Registrator Circuit 64a-64h for each second Defect Detector circuit 60a-60h. Thus, the Registrator Circuits 64a, 64c, 64e and 64g continuously monitor the registration between the reference and inspected images. They produce a score matrix for each of the chosen registration points, and output a score matrix (i.e., a matrix of values) for each of the possible shift positions around the current registration point. The Alignment Control Circuit 62 analyzes the score matrices obtained from four of the sensor channels (i.e., every other one). It computes the value of alignment error signals (D , D ) where the best match x y occurs, and outputs the alignment control signals to the Defect Detector circuits 60a-60h to correct misalignment between the two flows of data streams.

The Defect Detector circuits 60a-60h feed their outputs to a Decision Table 66 which makes a decision, based on the alarm values obtained from all eight sensor channels, as to whether a Global Defect Alarm (i.e., a logical output indicating the existence of a defect at a given location) should be issued or not. The Decision Table 66 thus receives, as inputs, the alarm values from all eight channels, and outputs a Defect flag.

Each of the eight alarm values has one of ✓ three values (0, 1 or 2) indicating no alarm, low alarm, and high alarm, respectively. The decision table is set to output a defect flag 1, indicating the existence of a defect if, and only if: (a) at least one alarm value is 2; and (b) at least two adjacent alarm values are 2 or 1 (alarm values 1 and 8 are adjacent).

The output of Decision Table 66 is applied to a parameters buffer circuit 68 which records the parameters describing each defect, such as the exact coordinates and the type (to be explained later) and intensity of the pixels in the immediate vicinity of the defect in both the inspected and reference images. It receives as inputs the alarm flag trigger (0 indicates no defect, and 1 indicates a defect), and all the parameters to be recorded, the latter are received from temporary memories associated with each of the eight channels. The parameters buffer 68 outputs a list of the defects accompanied by their parameters to the post processor 14.

The post processor 14 receives the list of suspected defects, together with their relevant parameters, and makes decisions before passing them on to the main controller for processing by the Phase II image processor system. It outputs a list of suspected points to transmit to the Phase II examination system, including their parameters, and also a list of defects which will not be transmitted to the Phase II examination system.

Fig. 14 more particularly illustrates the Defect Detector (e.g., 60a) and its associated Registrator (64a) in one channel of the image processor of Fig. 12.

Detection of defects by the defect detector in each channel is based on the comparison of each pixel in the stream with the corresponding pixel in the corresponding stream. Pixels are compared relative to an adaptive threshold determining detection sensitivity according to pixel type. The type of each pixel is determined by pixel characteristics, such as signal intensity and shape in a 3x3 neighbourhood.

Thus, the digital image from the preprocessor (6a-6h) in the respective stream is fed to a Threshold Processor 70, and also to a Delay Buffer 71. The outputs from the Threshold Processor 70 and the Delay Buffer 71 are applied to Pixel Characterizers 72 and 74. Pixel Characterizer 72 is in the Registrator Circut 64a (Fig. 12) which circuit outputs signals to a Score Calculator 73 (Fig. 14) controlling (with three other streams as indicated above) the Alignment control circuit 62 (Fig. 12). Pixel Characterizer 74 is used for comparison. It is connected to a Reference Die

Memory 75 which also receives the signals from the delay buffer 71 and outputs signals to the Score

Calculator 73 and also to a Pixel Aligner 76, the latter outputting signals to a Comparator 77.

Comparator 77, which is included in the Defect Detector 60 for each channel, carries out a comparison between the inspected image in the vicinity of the current pixel, and the reference image in the vicinity of the corresponding pixel. The comparison is made with respect to a threshold level which is dependent on the pixel type of the current pixels in the reference image and inspected image.

Thus, Comparator 77 includes four inputs: (1) reference pixels input 77a, corresponding to the intensity of the pixels in the reference image; (2) reference type input 77b, corresponding to the type of pixel in the reference image; (3) inspected type input 77c, corresponding to the type of the pixels in the inspected image; and (4) inspected pixels input 77d, corresponding to the intensity of pixels in the inspected image. As a result of the comparison performed by Comparator 77, it outputs an alarm value, via its Alarm output 77e, of three possible results of the comparison: (a) exceeds higher thresholds; (b) exceeds lower threshold only; and (c) below the threshold. As shown in Fig. 12, the outputs of

Comparator 77 in all eight streams are fed to the

Decision Table 66.

The Threshold Processor 70 computes the thresholds for classification of the pixels as they are scanned. The computation is based on histograms of the characteristic parameters. There are three thresholds for each parameter: (a) for decision on registration points; (b) for classification of pixels in the reference image; and (c) for classification of pixels in the inspected image.

Threshold Processor 70 receives the pixel stream from the scanned object via its preprocessor (e.g., 6a, Fig. 12), and outputs its threshold levels to the Pixel Characterizers 72 and 74, one for registration and one for the comparison.

Delay Buffer 71 delays the processing in the respective Defect Detector (e.g., 60a) and Registrator (e.g., 64a) until the thresholds have been computed. This ensures that the thresholds are set according to the parameters in the area which is being scanned. Thus, it receives the pixel stream from the object being scanned via its respective preprocessor, and outputs the same to the two Pixel Characterizers 72, 74, and to the Reference Die Memory 75, after a suitable delay.

Pixel Characterizer 74 computes the type of the current pixel. Thus, during the scanning of the reference pattern it computes the type of each pixel in that image for storage in the Reference Die Memory 75;

and during scanning of the inspected pattern, it continuously computes the type of the current pixel which is transmitted directly to Comparator 77.

Pixel Characterizer 72 selects registration points on the basis of the pixel type, determined from the results of the computation of pixel parameters and their comparison with thresholds. Thus, its inputs are the inspected image from the Delay Buffer 71, and the thresholds for all the pixel parameters from the Threshold Processor 70; and it outputs registration point flags to the Score Calculator 73 for points chosen as the registration points.

The Score Calculator 73 computes the score matrix of correlation between the inspected and reference images in all the possible shifts around the current pixel, up to the maximum allowed. It receives three inputs: (a) the inspected image, to define the area around which the correlation is checked; (b) the reference image, to define the range of possible matches within the maximum range of horizontal and vertical shifts; and (c) a control input, from Pixel Characterizer 72, allowing the choice of registration points on the basis of pixel type.

The outputs of four (of the eight) streams are fed to the Alignment Control Circuits 62 (Fig. 12) in order to calculate the proper registration.

Pixel Characterizer 74 computes the type of the current pixel. Thus, during the scanning of the reference pattern, it computes the type of each pixel in that image for storage in the Reference Die Memory 75; and during the scanning of the inspected pattern it continuously computes the type of the current pixel, which is transmitted directly to the Comparator 77.

Pixel Characterizer 74 includes two inputs: (a) the digital image, outputted from the Delay Buffer 71; and (b) the threshold values from the Threshold Processor 70 for the relevant parameters, to enable a decision to be made as to the pixel type. Pixel Characterizer 74 is described more particularly below with respect to Fig. 17.

The Reference Die Memory 75 stores an image of the reference pattern. This image contains both the intensities of the pixels and their classification type. It includes a Pixels input, receiving the gray level for each pixel from the Delay Buffer 71, and a Type input, receiving the pixel classification from the Pixel Characterizer 74. The inputs are active only when the reference pattern is being scanned, and the reference image is retrieved when needed for the purpose of comparison with the inspected image. It

- ו3 includes a Pixels output applied to the Score

Calculator 73 and also to the Pixel Aligner 76, and a

Type output applied to the Pixel Aligner 76.

The Pixel Aligner 76 executes an advance or a delay in the pixels being outputted by the Reference Die Memory 75 before they reach the comparison stage, in order to align them with the current pixel in the inspected image. Its inputs are the pixels intensity and type outputs from the Reference Die Memory 75, and also an alignment control input from the Alignment Computer 62 (Fig. 12); and it outputs the reference image pixel streams with an advance or delay.

Comparator 77 carries out a comparison between the inspected image in the vicinity of the current pixel, and the reference image in the vicinity of the corresponding pixel. This comparison is made with respect to a variable threshold level, which is dependent on the pixel type of the current pixel in the reference and inspected images. Thus, its inputs include the pixels intensity and type in the reference image from the Pixel Aligner 76, and the pixel intensity and type in the inspected image from the Delay Buffer 71 and Pixel Characterizer 74, respectively.

Fig. 15 more particularly illustrates the Registrator (e.g., 64a) of Fig. 14, especially the

Threshold Processor 70, Delay Buffer 71, Pixel Characterizer 72 and Score Calculator 73.

As described earlier, the Threshold Processor 70 computes the thresholds for classification of the pixels as they are scanned, the computation being based on histograms of the characteristic parameters. The Threshold Processor thus includes a Pixel Parameters Calculator 70a, which calculates the parameters of the current pixel on the basis of its immediate surroundings; a Histogrammer 70b which computes the histogram of the current pixels parameters; and a Threshold Calculator 70c which examines the histogram for each parameter and determines from it the proper value of threshold for that parameter.

The Delay Buffer 71 corrects the timing of the arrival of the reference and inspected images to that of the arrival of the registration point flags from the Pixel Characterizer 72. Thus, Delay Buffer 71 includes a buffer 71a for the inspected iamge, and a buffer 71b for the reference image.

The Pixel Characterizer 72, as described with reference to Fig. 14, chooses the registration point on the basis of the pixel type. It includes the following subunits: a Pixel Parameters Calculator 72a, which calculates the parameters (gradient, ratio, maximum) of the current pixel on the basis of its immediate surroundings; Threshold Comparators 72b which compare these parameters with the thresholds which have been set separately for each parameter by the Threshold Processor 70; and a Decision Type Table 72c, which determines, on the basis of the results of the comparison by the Threshold Comparators 72b, whether the current pixel is suitable at the sampling point to carry out registration.

For every registration point the correspondance of its 3x3 pixels neighbourhood is measured against pixels in a range of +R in the corresponding stream. Fig. 14a illustrates the algorithm. For each of the (2R+1)x(2R+1) possible misalignments, a correlation measure is computed as the normalized sum of absolute difference. The correlation matrices computed for different registration points are summed, and the minimal value in the matrix corresponds to the correct misalignment.

The Score Calculator 73, as described earlier with reference to Fig. 14, computes the score matrix of correlation between the inspected and reference images in all the possible shifts around the current pixel, up to the maximum allowed (plus or minus vertical and horizontal ranges). This unit includes the following circuits: delays 73a, 73b, to correct the timing of the arrival of the inspected and reference images, respectively, to that of the arrival of the Registration Point flags from the pixel characterizer

72; Neighbourhood Normalizers 73c, 73d, to normalize the pixels in the neighbourhood of the current pixel; Absolute Difference Calculator 73e, which finds the absolute difference between the inspected image in the vicinity of the current pixel as against all the possible matches in the reference image within the maximum range of shifts in the vertical and horizontal axes, and computes the score matrix for these matches; and Score Matrix accumulator 73f which sums and stores all the score matrices which are accumulated during the scanning of a number of successive rows, before transmitting them to the Alignment Computer 62 (Fig. 12) for computation of the best match.

The Neighbourhood Normalizers 73c, 73d, normalizer the pixels in the neighbourhood of the current pixel in accordance with the following formula:

1

Σ Σ P(i+n,j+m) Pnew = P(ij) - n(ij) where oij = n=-1 m=-1 9

The Threshold Processor 70 of Figs. 14 and 15 is more particularly illustrated in Fig. 16. As described earlier, it computes the thresholds for classification of the pixels as they are scanned, the computation being based on histograms of the characteristic parameters. It includes, in addition to the Parameters Calculator 70a, the Histogranuner 70b and the Threshold Calculator 70c described above with reference to Fig. 15, also a delay line 70c, which delays the pixels received at the input to the pixel flow circuit until a column of three pixels from three adjacent rows are received. These pixels are delayed in a pipeline delay subunit 70d before being applied to the Histogrammer 70b.

The Parameters Calculator 70a includes a

Ratio Calculator 70e, and a Gradient Calculator 70f.

The Ratio Calculator 70e computes the ratio between the current pixel P(ij), and the average of the pixels in the surrounding area in the vertical and horizontal directions. If outputs the following signals: the ratio in the horizontal direction (Rh); the ratio in the vertical direction (Rv); and the ratio to the average of the four surrounding pixels (Rij).

The Gradient Calculator 70f calculates the gradient in the surroundings of the current pixel P(ij) in a matrix of 3 x 3 adjacent pixels by operation of a convolvor with the following coefficients:

<td> In the VERTICAL DIRECTION:</td><td> 1- 4. ו- !-</td><td> 0 0 0</td><td> 1 1.4 1</td>

<td> In the HORIZONTAL direction:</td><td> 1 0 -1</td><td> 1.4 0 -1 .4</td><td> 1 0 -1</td>

The outputs of the Ratio Calculator 70e are applied to a Ratio Table of Levels 70g, before being fed to the Histogrammer 70b, and the outputs of the Gradient Calculator 7Of are applied to a Gradient Table of Levels 7Oh before being fed to the Histogrammer 70b.

The Threshold Processor illustrated in Fig. 16 further includes a Maximum Definition circuit 70i, which makes a decision on the current pixel in relation to its surroundings, to define the following parameters: M(ij) = 1, if the pixel is larger (higher in intensity) than all the eight surrounding pixels; M(v) = 1, if the pixel is larger than its two neighbours in the same column; and M(h) = 1, if the pixel is larger than its two neighbours in the same row.

The outputs of the Maximum Definition circuit 70i are applied, via a pipeline delay circuit 70j, to the Histogrammer 70b.

The Ratio Table of Levels 70g divides the ratio results into K groups in order to build the histogram. The K groups are obtained by comparison with a vector of K threshold level Cr(K), which indicates a different area of the table for each threshold.

The Gradient Table of Levels 70h divides the gradient results into L groups for the purpose of building the histogram. The L groups are obtained by comparison with a vector of L threshold levels Cr(L), which indicate a different area of the table for each threshold.

Hisogrammer 70b executes a histogram of the pixel intensities P(ij) in different cells of the memory in accordance with the following parameters: M(Maximum); L(Gradient); and K(Ratio).

The Threshold Calculator 70c in the Threshold Processor 70 illustrated in Fig. 16 is a microprocessor which receives the results of the Histogrammer, analyzes them, and computes the thresholds for a decision on the pixel type, for: Registration, Reference Image, and Inspected Image. It outputs the results to the Pixel Type Characterizer 72 and 74, as described above with reference to Fig. 14.

Thus, the Pixel Type Characterizer 74 includes five Comparators 74b^-74bg which compare the various parameters (Ratio, Gradient and Maximum) which have been previously computed in units 74a.j, 7432, 74a_3׳ with the threshold levels coming from the Threshold Processor 70. Thus, Comparator 74b^ compares the pixel flow with the Intesity threshold I from the Threshold Processor 70; Comparators 74b274 _׳b₃ compare the outputs of the Ratio Calculator 743ן with the Ratio thresholds R and Rhv, respectively from the Threshold Processor; and Comparators 74b^, 74bg compare the outputs of the Gradient Calculator 74β2 with the

Gradient thresholds G and Ghv of the Threshold

Processor 70.

The results of these comparisons are fed to the Decision Table 74c, which also receives the output parameters from the Maximum Definition Unit 74a^ M(ij) to decide on the pixel type.

The output of the Decision Table 74c is a two-bit word indicating the pixel type. The output is applied to a Type Updating unit 74d, which modifies the results of the Pixel type in certain exceptional cases, such as a pixel slope next to a pixel peak (i.e., to distinguish between an isolated peak and a multipeak).

A pixel is assigned a type according to the following four parameters computed for its 3x3 pixels neighbourhood: (1) local maxima indicator, (2) intensity, (3) ratio, and (4) gradient. Fig. 17a illustrates the algorithm to determine the pixel type from these parameters, computed as follows:

1. Local maxima - indicates if a pixel is a maximum relative to its neighbours. .

m (F- ,) = 1 if F_ -ZF, . for all 1 s i &lt; 3, 1 s j s 3.

2. Intensity - indicates if the intensity of the pixel is significant relative to a threshold defined dynamically in a window of η x m pixels.

¹ <^F2,2> = ^{1 if f}2,2 * ^T1 *

3. Ratio - indicates if the intensity of the pixel is significant with respect to its neighbours relative to a threshold defined dynamically in a window of n x m pixels.

x F_ ₂ r (F, 1 ־ (&lt;׳ if -------------------- * ^T_r^F1,2^+F2,1^+F2,3^+F3,2

4. Gradient - indicates if the pixel is located in a slope area of 3 x 3 pixels relativel to a threshold defined dynamically in a window of n x m pixels.

^g(F2,2 if max 1=1,2 i=1,2

Where 0ן are gradient

0 operators and 0 is convolution.

.4 0

4. ו1 0

ו⁰2

The type assigned to .4 ו-

4. ווa pixel may be one of the following: isolated peak, multipeak, slope and background. The type is assigned according to the pixel's parameters as follows:

Isolated peak - if the pixel is a local maxima with significant intensity and ratio .

t(F_ 1=(_ר if m(F₀ ~) = 1 and I(F_ -)=1 and r(F2,2)=1

2. Multipeak - if the pixel is not an isolated peak, it has significant intensity and none of its neighbours is an isolated peak.

t(F, _o)=2 if I(F- ,)-1 and t(F. .)/1 1iis3, 1sjs3

Z | Z * f * If J

3. Slope - if either one of the pixel's neighbours is an isolated peak or it has significant gradient.

t(F₂₂)3־ ii 1 ־ for some

1ii, js3 except F2 2 or

9(F₂1־(_2׳

4.

Background - if the pixel has no significant intensity, or gradient and none of its neighbours is an isolated peak.

t(F_{2 2}) = 4 if 1^2,2^^{1 and 9}^2,2^^{1 and t(f}i,j⁾/¹1si&lt;3, 1sjs3

The foregoing are implemented by the Ratio Calculator 743ן illustrated in Fig. 18, by the Gradient Calculator 74a₂ illustrated in Fig. 19, and by the Maximum Definition Calculator 74a^ illustrated in Fig.

20.

Thus, the Ratio Calculator 743ן makes a decision about the central pixel in the matrix, and computes the ratio of the pixel intensity to its immediate neighbourhood.

The possible decisions about the central pixel in the matrix are as follows: (a) maximum, i.e., greater than any of its neighbours; (b) vertical maximum, i.e., greater than its vertical neighbours; and (c) horizontal maximum, i.e., greater than its horizontal neighbours.

The computation of the ratio of the pixel intensity to its immediate neighbourhood is: (a) in relation to the four immediate neighbours, if it is a maximum; and (b) in relation to the two relevant neighbours, if it is a vertical or horizontal maximum.

The Ratio Calculator includes nine registers, shown in Fig. 18a. Their functions are to record the nine values, designated by the letter A-I, of the pixels in a 3 x 3 matrix.

The Gradient Calculator 74β2 is more particularly illustrated in Fig. 19. Its function is to compute the values of Gradient of the matrix in the vertical and horizontal directions. The calculation is based on the following formulae:

<td> 2 X Gh = {(A+B+C)*2+B}</td><td> - {(G+I+H)*2+H}</td>

<td> 2 x Gv = {(A+G+D)*2+D}</td><td> - {(C+I+F)*2+F}</td>

<td colspan="2"> such that the calculation represents multiplying the</td>

<td> following matrices:</td><td></td>

<td> 2</td><td> 3 2</td>

<td> Horizontal: 0</td><td> 0 0 *1/2</td>

<td></td><td> 2־ 3-</td>

<td> 2</td><td> 0 -2</td>

<td> Vertical: 3</td><td> 0 -3 *1/2</td>

<td> 2</td><td> 2־ 0</td>

The circuit calculates the values of the

Gradient which includes the following components:

a) Register Matrix: A to I, in which the values of the pixels in the matrix are recorded.

b) Left Vertical: adds the pixels in the left column according to the formula:

(A+G+D) *2+D

c) Right Vertical: adds the pixels in the right column according to the formula:

(C+I+F)*2+F

d) Horizontal Up: adds the values of the pixels in the upper row, accordign to the formula:

(A+C+B)*2+B

e) Horizontal Down: adds the values of the pixels in the lower row according to the formula:

(G+I+H)*2+H

The Maximum Definition Calculator 74a^ in Fig. 17 is more particularly illustrated in Fig. 20. Its function is to compare, by means of comparators, the value of the central pixel E with those of its neighbours, to determine the following parameters:

a) Mv(i,j) - A logical signal which shows the condition that the central pixel E is greater than its vertical neighbours B and H.

b) Mh(i,j) ־ A logical signal which indicates that the central pixel E is larger than its horizontal neighbours D and F.

c) M(i,j) - A logical signal which indicates that the central pixel E is larger than all its neighbours A, B, C, D, F, G, Η, I.

The ratio definition calculator computes the value of the Ratio parameter from the following two values:

a) Rij - The ratio of the central pixel to its surroundings.

E

Rij = ----------------— (B + H + D + F) /4

b) Rvh - The ratio of the central pixel to the average of its vertical and horizontal neighbours.

E if Mv(i,j) = 1 then Rv = ---------(B + H)/2

E if Mh(i, j) = 1 then Rh = ----------(D + F)/2

The Registration Score Matrix Calculator 73 (Fig. 14) is more particularly illustrated in Fig. 22. This calculator includes a dual-port memory 73a-73c to temporarily store a window of up to 25 consecutive rows in the reference image, for the purpose of computing the score matrix of matches to a smaller window (up to three rows) in the inspected image. The memory has two channels of access: channel 3d, to store the image by input of the stream of pixel data continuously; and channel 73e, to output a window containing a strip of three rows wide, as required.

An input Address Counter 73f generates the pointer for the address at which the current pixel is stored; and an output Address Counter 73g generates the pointer for the address from which is outputted the window on which registration is kept out. The input Address Counter 73f selects the memory via a memory selector 73h. The storage of a window from the reference image is carried out in such a manner that each new row is inputted to a different one of the three memories 73a-73c, so that the first memory

<td> contains rows</td><td> 1/</td><td> 4,</td><td> 7,</td><td> etc.; the second memory 73b</td>

<td> contains rows</td><td> 2,</td><td> 5,</td><td> 8,</td><td> 11, etc.; and a third memory 73c</td>

<td> contains rows</td><td> 3,</td><td> 6,</td><td> 9,</td><td> 12, etc.</td>

<td> The</td><td colspan="4"> Registration Score Matrix Calculator 73</td>

illustrated in Fig. 22 further includes a crossbar switch 73i. Its function is to transmit three consecutive rows, and to allow switching of these rows each time that a computation of a full row of the score matrix is completed, and there is a need to move to the next row. As an example, initially rows 1, 2, 3 are passed to outputs A, B, C; next, rows 2, 3 and 4 are passed to outputs A, B, C, respectively; and so on.

The combinations are shown in the diagrams illustrated in Fig. 22a.

The Registration Score Matrix Calculator 73 illustrated in Fig. 22 further includes a converter 73k which converts the stream of current pixels to three pixels in parallel from three consecutive rows. The conversion is carried out by means of two FIFO (firstin, first-out) delay lines 73k^, 73k_2׳ connected in series and each having a length of one complete row. Calculator 73 further includes a delay 731 for the purpose of synchronizing the appearance of the current pixel in the inspected image with the corresponding pixel in the output of the reference image, before inputted into the score matrix calculator for storage of the respective window.

The Score Matrix Calculator 73j computes the score matrix between the inspected and reference images for all possible shifts of the window. This method of computation is described more particularly below with respect to Fig. 23.

The Score Matrix Calculator 73j receives three pixels from three consecutive rows, from which are produced the nine pixels which form the inspection image. The nine pixels are frozen while the score matrix is being computed. Calculator 73j also receives three pixels from three consecutive rows from which are produced the nine pixels which form the reference image. The nine pixels change with each clock pulse, until all possible combinations of the 3x3 matrix within the search window have been completed.

The result of the normalized difference between the inspected image and the reference image is outputted every clock pulse, until all possible combinations of the 3x3 adjacent pixels within the search window are completed.

The Score Calculator 73 further includes a Score FIFO Memory 73m. Its function is to regulate the timing of the transfer of the normalized results, which represent the score matrix, from the Registration Score Calculator 73j to the Score Accumulator 73f.

The Score Accumulator 73f sums the score matrix which has been calculated for one registration point, to that for a second registration point. It thus assembles a sample of registration points until the final matrix is passed to the Alignment Computer 62 (Fig. 12) to compute the Dx and Dy alignment control signals.

The Registration Score Matrix Calculator 73j illustrated in Fig. 22 is more particularly shown in Fig. 23. It computes the score matrix based on the normalized difference between the inspected image (3x3 pixels in extent), and all the N x N possible matches in the corresponding matrix in the reference image.

ר4

Calculator 73j includes a Pixel Normalizer 81 (Fig. 23) for the inspected image; a Pixel Normalizer 82 for the reference image; a Difference Calculator 83; a Summation Calculator 84; a Division Table 85; a Multiplier 86; a Results Storage device 87; and a Score Accumulator 88.

Pixel Normalizer 81 for the inspected image includes a registrator window 81a whose function is to convert the format of the inspected image from a serial stream of pixels to a format of a sequence of columns of pixels from three consecutive rows; it thus enables, by the use of three shift registers of length of three pixels each, immediate access to a matrix of 3 x 3 pixels.

Pixel normalizer 81 further includes a nineaddition circuit 81b, which sums the intensities of the 3x3 pixel matrix around the current pixel. It further includes a 1/9 table. 81c which divides the sum of the pixel intensities in the matrix by 9, and thereby obtains the average value of the pixels in the matrix.

A delay 81d delays the image data stream until the results of the average intensity from table 81c are available. The output of table 81c is applied directly, and via delay 81d, to a group of nine registers 81e, which subtract the average value from each of the nine pixels in the matrix. The nine results, representing the normalized values of the pixels, are available simultaneously at outputs A-I of the Pixel Normalizer 81. These pixel values will be frozen, and will serve as the reference for comparison throughout the process of computing the score matrix in relation to the reference image.

The Pixel Normalizer 82 for the reference image includes a moving window 82a whose function is to produce three consecutive rows in the search area having a size of N x N times a 3 x 3 matrix in the reference image. The three consecutive rows will supply the pixels needed to produce all the possible 3x3 matrices in the search area. Three additional pixels are acquired once per clock pulse in order to enable a new 3x3 matrix to be produced.

Pixel Normalizer 82 further includes a Nine-Addition circuit 82b which sums the values of the matrix, and a 1/9 Table 82c which computes the average of the pixels in the matrix. The reference data stream from the moving window 82a is delayed by a delay circuit 82d until the results of the average intensity from table 82c is available, so that both may be supplied simultaneously to the nine registers 82e. The nine registers 82e subtract the average value from each of the nine pixels in the matrix, so that the nine results representing the normalized values of the pixels are available simultaneously at outputs A-I.

Difference Calculator 83 computes the sum of the absolute, differences of the 3x3 matrix of the inspected image versus the reference image. For this purpose, Calculator 83 includes, for each of the two Pixel Normalizers 81 and 82, a Subtraction Circuit 83a, 83b consisting of nine subtractors which compute the difference betweene each pixel in the inspected image versus the corresponding pixel in the reference image; an Absolute Value Circuit 83c, 83d, which computes the absolute value of the differences; and a Matrix Circuit 83e, 83f, which sums all the nine absolute values. The result of the absolute sum of the differences is passed to the Multiplier 86.

Multiplier 86 also receives the output from the Summation Calculator 84 via the Division Table 85. Thus, the Summation Calculator 84 computes the absolute sum of the two matrices on which the processing will be carried out. It includes, for each Pixel Normalizer 81, 82, an Absolute Value Circuit 84a, 84b, which computes the absolutes values of each normalized pixel; and a Matrix Sum Circuit 84c, 84d, which sums the nine absolute values.

Division Table 85 prepares the results of the summation for the operation of division by means of the Multiplier 86. Division Table 85 executes the arithmetic operation 1 divided by the sum, by converting the values using a PROM (Programmable Read

Only Memory) table.

Mulitipler 86 computes the result 0 the normalized difference for the point under test. The computation is carried out using the formula:

SCORE = (ElPj-Pj)*[1/(Z|Ρ_χ|+|P_r|)] where P_T, P_D are the normalized values of the pixels.

X R

The Result Storage Device 87 temporarily stores the results of the score at a storage rate which is the same as that at which the results appear, and at an output rate matching the timing of acceptance of the results by the Score Accumulator 88. The Score Accumulator 88 sums the score matrix obtained at the current registration point with the score matrix obtained at the previous registration point. Summing of the matrices at the registration point is carried out for the defined sequence of windows, up to K consecutive rows, before the result of the Score Matrix is passed to the Alignment control circuits 62 (Fig.

12) for processing.

The construction and operation of the Defect Detector, as illustrated for example in Fig. 14, will be better understood by reference to Figs. 24 and 25. As describer earlier, the function of Comparator 77 is to carry out a comparison between the inspected image in the vicinity of the current pixel, and the reference image in the vicinity of the corresponding pixel, and to output an Alarm signal, via buffer 68, to the Post Processor 14 indicating whether or not there is a suspected defect. As also indicated earlier, the comparison is made with respect to a variable threshold level, which is dependent on the Type of the current pixel in the reference and inspected images.

The comparison algorithm is illustrated in Fig. 25a. As shown therein, a pixel in a stream of the inspected image is compared against the corresponding pixel in the reference image. The comparison is done under the assumption that a local misalignment of plus or minus one pixel may exist. Accordingly, a pixel is compared to the nine pixels in the 3x3 neighbourhood centered at the corresponding reference pixel.

Each of the nine comparisons is made by comparing the difference between the energies of the compared pixels against a threshold determined by the pixel type. The energy of a pixel is the sum of the nine pixels in the 3x3 neighbourhood centered at the pixel. The alarm value is set to 2, if the difference in all nine comparisons is above the high threshold; to 1, if it is above the low threshold; and to 0 in all other cases.

Comparator 77 thus includes a neighbourhood Energy Calculator 77a, 77b for the inspected image and the reference image, respectively. Calculators 77a, 77b compute the energy of the surroundings of the current pixel in a 3 x 3 matrix of the near neighbours in the inspected image, and in the corresponding reference image. Delay lines 77c, 77d (Fig. 25) are provided before these calculators in order to produce suitable delays before and after the current pixel in order to obtain the three relevant rows for computation of the energy in the vicinity of the current pixel. The two calculators receive, as inputs, the relevant pixels in the three relevant rows surrounding the current pixel, and output the arithmetic sum of the nine pixels in the 3x3 matrix around the current pixel.

Comparator 77 further includes Neighbourhood Registers 77e, 77f for storing the energies in the two Calculators 77a, 77b, respectively, and further Neighbourhood Registers 77g, 77h. Their function is to prepare, in parallel form, the nine relevant Types (T1-T9) around the current pixel in the reference image, in order to determine the threshold level to be used in the execution of nine simultaneous comparisons. Thus, the Energy Neighbourhood Registers 77e, 77f, output nine energies E1-E9; while the Type Neighbourhood Registers 77g, 77h output nine types T1-T9 around the current pixel.

Comparator 77 further includes nine conversion tables 77i for the low threshold level, and nine conversion tables 77j for the higher threshold levels. These tables are loaded prior to the inspection session. The tables are selected from a set of tables according to the required sensitivity of the detection, as set by the user. Their function is to mutliply each one of the energies around the pixel being examined by a constant which depends both on the type of the examined pixel in the reference image, and the type of the current pixel in the inspected image.

Thus, tables 77i, 77j receive as inputs:

(a) Type (ij), namely the type of the current pixel in the inspected image; (b) Type (1-9), namely the type of the pixel examined around the current pixel in the reference image; and (c) Energy E (1-9), namely the energy of the examined pixel in the reference image.

The tables output signals EK(1-9), namely the multiplication results of the input energy E(1-9), by a constant which depends on the type of both the current pixel and the examined pixel. That is:

EK(1-9)=K(Tij,T) * E(1-9).

Each of the tables 77i, 77j, is connected to a Compare circuit 77k, 771, whose purpose is to compare the current energy Eij and the multiplication results of the energy of the pixel and a constant, EK(1-9). The Compare circuit outputs logical indications of the result of the comparison, namely:

If EK(1-9)sE(ij)

If EK(1-9)>E(ij).

A High Threshold Decision unit 77m tests whether all the comparison outputs exceeded the high threshold; and a Low Threshold Decision unit 77n tests whether all the comparison outputs exceeded the low threshold. The combination of the outputs of decision table 77n and 77m is the alarm value. These eight alarm values are inputted to the decision table 66 which outputs the defect flag to the post-processor 14 (Fig. 12) via the parameters buffer 68.

The post-processor 14 (Fig. 12) thus receives the list of suspected defects, together with their relevant parameters, and makes decisions before passing them onto the Phase II examination system. These decisions include: (a) clustering; (b) choosing the points which will be passed to Phase II; and (c) the optimum route in Phase II. The latter functions are carried out by microprocessor programs.

Phase II EXAMINATION

Overall System

As briefly described earlier, the Phase II examination is effected automatically upon the completion of the Phase I examination while the wafer is still on the table 2, but only with respect to those locations of the wafer W indicated during the Phase I examination as having a high probability of a defect.

Thus, while the Phase I examination is effected at a relatively high speed and with a relatively low spatial resolution, the Phase II examination is effected at a much lower speed and with a much higher spatial resolution, to indicate whether there is indeed a defect in those locations suspected of having a defect during the Phase I examination.

Briefly, the Phase II examination is effected by: imaging on converter 9 (Figs. 1 and 26), e.g., a CCD, each suspected location of the inspected pattern, and the corresponding location of the reference pattern, to output two sets of electrical signals corresponding to the pixels of the inspected pattern and the reference pattern, respectively; and comparing the pixels of the inspected pattern with the corresponding pixels of the reference pattern to indicate a defect whenever a mismatch of a predetermined magnitude is found to exist at the respective location. To accommododate variations in the thickness of the wafer and/or pattern, and/or multi-layer patterns, each suspected location of the inspected pattern, and the reference pattern, is imaged at a plurality of different depths, and the electric signals of one set are shifted with respect to those of the other set to match the respective depths of the images.

Phase II Optic System

The Phase II optic system is shown generally in Fig. 1 and more particularly in Fig. 26. It includes a microscope objective 100 mounted in a rotating turret 101 carrying different objectives to enable bringing a selected one into the optical path between the wafer w and the image converter 9. The wafer W is illuminated by a flashlamp unit 102 via an optical device 103 having a beamsplitter 104 and a second beamsplitter 105. Unit 102 also contains a continuous light source, such as a standard tungsten lamp, which is used with a standard TV camera 110 and/or viewing system III, described below.

Beamsplitter 104 reflects the infrared portion of the light reflected from the wafer to an autofocus unit 106, while beamsplitter 105 reflects the flash light to the wafer W on the vacuum chuck 24 via the selected objective 100. Beamsplitter 105 also passes the light reflected by the wafer W via an imaging lens 107 and another beamsplitter 108 to the image converter 9. Beamsplitter 108 reflects a part of the image via another beamsplitter 109 to a standard TV camera 110 and/or to a viewing system 111 having binocular eyepieces. The binocular viewing system 111 permits an observer to view the wafer visually, while the TV camera 110 permits viewing the wafer via a TV monitor.

Phase 2 Image Processor

Fig. 27 illustrates both the Phase 2 image preprocessor and the Phase 2 image processor, as designated by blocks 10 and 11, respectively, in both Figs. 2 and 27.

Thus, as more particularly shown in Fig. 27, the information detected by the image converter 9 is fed to a preamplifier 120 in the preprocessor 10, to a digitizer 121, and then to a memory buffer 122 in the image processor 11. The image processor 11 further includes a digital signal processor which, under software control (block 124) from the main controller (8, Fig. 2), performs the following operations as indicated in Fig. 27: a matching operation 125, a registration operation 126, a comparison operation 127, and a classification operation 128. The output from the digital signal processor 123 is then returned to the main controller 8.

Fig. 27 further illustrates the Phase 2 image processor 11 as including a hardware accelerator 129 for accelerating particularly the registration and comparison operations.

The foregoing operations are described more particularly below with reference to Figs. 28-31.

As described earlier, the input to the Phase II image processor includes two sets of images, taken from the inspected pattern and the reference pattern.

respectively. Each set includes five images taken with focusses at different depths in order to accommodate variations in the thickness of the wafer or pattern, or to accommodate multi-layer patterns.

As more particularly shown in Fig. 28, the reference images and the inspected images are subjected to a depth matching operation 125 matching the two depth sets, and also to a registration operation 126, in which misalignment between the reference and inspected images is detected in each depth. The list of misalignments is fed to the compare circuit 127, Circuit 127 compares the grey level images, pixel by pixel, using surrounding pixels and adaptive thresholds obtained from a dynamic range equalization circuit 129, the latter circuit compensating for process, illumination and other variations. The output of compare circuit 127 indicates suspected defects, location and score, and is fed to the defect classification circuit 128. Circuit 128 characterizes the data defects utilizing, not only the output of the compare circuit 127, but also previously gathered data as stored in the data base 130. The output of the defect classification circuit 128 is fed to the main controller (8, Figs. 1, 2) for display, print-out, or the like.

Depth Matching

Figs. 29-31 more particularly illustrate how the depth matching operation is performed. Thus, the sequence of images taken from the inspected pattern is matched with those taken from the reference pattern. The goal is to match each image of the inspected pattern with the image of the reference pattern taken at the corresponding depth of focus. Two assumptions are made: (1) the images are taken in the order of increasing depth with a fixed difference between each two consecutive images; and (2) the error in the depth of the first image of the two sequences is at most the difference between two consecutive images.

Hence, if I_i5^1^1 _׳ and R_i1 _׳sis5 are the inspected and reference images, respectively, the matching procedure detects x, where x is one of -1,0 or 1 such that (I.,R. ) is a pair of comparable images

14* X (see Fig. 29), for 1=1,..,5. Correlation in the depth of focus of two images is measured by computing similarity in the variance of grey levels in the two images. The correlation measure used is the difference between the grey level histograms of the images. The shift x is computed as the one providing the best correlation for all images in the sequence.

Fig. 30 more particularly illustrates the matching procedure. It is composed of the following steps:

(1) Compute the grey level histograms for all the images (blocks 131, 132). The grey level histogram of an image contains the distribution of the grey levels. The histogram H of an image contains in its cell H(j), the number of pixels in the image that has a grey level equal to j.

(2) Compute the distance between the histograms (block 133). The distance is taken as the sum of absolute differences between corresponding cells in the histograms. The distance will be computed as follows:

d(R_k-I₁) = s|H_Rk(i) - H_n(i) |, where are the histograms of R. ,1.

KK 11 Λ A respectively.

(3) Create the distances table (block 134). This table contains the correlation measures computed for each pair of images.

d(R₁ - IJ d(R- - I₉) diR.-I-J d(R2 - 1J) d(R^ ־ φ ^ά&lt;^β2־Φ (4) Find the diagonal in the distance table providing the least means (see Fig. 31) by computing the means of the three main diagonals (block 135), and choosing the least mean (block 136), to produce the depth shift. The shift x corresponds to the diagonal providing the minimal mean, thus minimizing the overall distance between the two sets.

In the preferred embodiment of the invention described below, both the Phase I examination and the Phase II examination are effected, one automatically after the other. It is contemplated, however, that the invention, or features thereof, could also be embodied in apparatus which effects only the first examination or only the second examination. It is also contemplated that the apparatus could be supplied with the capability of effecting both examinations but with means for disabling, e.g., the second examination, if not required for any particular application.

Many other variations, modifications and applications of the invention will be apparent.