Thin film,field effect transistor

The present invention relates to a thin film, field effect transistor, and more specifically to a thin film, field effect transistor of the type formed from an amorphous alloy including at least 5 silicon. In this respect, reference is made to

U.S. Patent No. 4,217,374 Stanford R. Ovshinsky and Masatsugu Izu entitled: AMORPHOUS SEMICONDUCTORS EQUIVALENT TO CRYSTALLINE SEMICONDUCTORS and U.S. Patent No. 4,226,898 Stanford R. Ovshinsky 10 and Arun Madan, of the same title.

Silicon is the basis of the huge crystalline semiconductor industry and is the material which is utilized in substantially all the commercial integrated circuits now produced. When crystal15 line semiconductor technology reached a commercial state, it became the foundation of the present huge semiconductor device manufacturing industry. This was due to the ability of the scientist to grow substantially defect-free germanium and par20 ticularly silicon crystals, and then turn them into extrinsic materials with p-type and n-type conductivity regions therein. This was accomplished by diffusing into such crystalline material parts per million of donor (n) or acceptor 25 (p) dopant materials introduced as substitutional impurities into the substantially pure crystalline materials, to increase their electrical conductivity and to control their being either of a p or n conduction type.

The semiconductor fabrication processes for making p-n junction crystals involve extremely complex, time consuming and expensive procedures as well as high processing temperatures. Thus, these crystalline materials used in transistors and other current control devices are produced under very carefully controlled conditions by growing individual single silicon or germanium crystals, where p-n junctions are required by doping such single crystals with extremely small and critical amounts of dopants. These crystal growing processes produce relatively small crystal wafers upon which the integrated circuits are formed.

In wafer scale integration technology the small area crystal wafer limits the overall size of the integrated circuit which can be formed thereon. In applications requiring large scale areas, such as in the display technology, the crystal wafers cannot be manufactured with as large areas as required or desired. The devices are formed, at least in part, by diffusing p or ntype dopants into the substrate. Further, each device is formed between isolation channels which are diffused into the substrate. Packing density (the number of devices per unit area of wafer surface) is also limited on the silicon wafers, because of the leakage current in each device and the power necessary to operate the devices, each of which generate heat which is undesirable. The silicon wafers do not readily dissipate heat. Also, the leakage current adversely affects the battery or power cell lifetime in portable applications.

In MOS type circuitry the switching speed is related directly to the gate length with the smallest length having the highest speed. The dif-3fusion processes» photolithography and other crystalline manufacturing processes limit how short the gate length can be made.

Further, the packing density is extremely important because the cell size is exponentially related to the cost of each device. For instance, a decrease in die size by a factor of two results in a decrease in cost on the order of a factor of six.

in summary, crystal silicon transistor and integrated circuit parameters which are not variable as desired, require large amounts of material, high processing temperatures, are producible only on relatively small area wafers and are ex15 pensive and time consuming to produce. Devices _ based upon amorphous silicon can eliminate these crystal silicon disadvantages. Amorphous silicon can be made faster, easier, at lower temperatures and in larger areas than can crystal silicon.

Accordingly, a considerable effort has been made to develop processes for readily depositing amorphous semiconductor alloys or films each of which can encompass relatively large areas, if desired, limited only by the size of the deposi25 tion equipment, and which could be doped to form p-type and n-type materials to form p-n junction transistors and devices superior in cost and/or operation to those produced by their crystalline counterparts. For many years such work was sub30 stantially unproductive. Amorphous silicon or germanium (Group IV) films are normally four-fold coordinated and were found to have microvoids and dangling bonds and other defects which produce a high density of localized states in the energy gap thereof. The presence of a high density of localized states in the energy gap of amorphous silicon semiconductor films resulted in such films not being successfully doped or otherwise‘modified to shift the Fermi level close to the conduction or valence bands making them unsuitable for making pn junctions for transistors and other current control device applications.

In an attempt to minimize the aforementioned problems involved with amorphous silicon and germanium, W.E. Spear and P. G. Le Comber of Carnegie Laboratory of Physics, University of Dundee, in Dundee, Scotland did some work on Substitutional Doping of Amorphous Silicon, as reported in a paper published in Solid State Communications, Vol. 17, pp. 1193-1196, 1975, toward the end of reducing the localized states in the energy gap in amorphous silicon or germanium to make the same approximate more closely intrinsic crystalline silicon or germanium and of substitutionally doping the amorphous materials with suitable classic dopants, as in doping crystalline materials, to make them extrinsic and of p or n conduction types.

The reduction of the localized states was accomplished by glow discharge deposition of amorphous silicon films wherein a gas silane (SiH4) was passed through a reaction tube where the gas was decomposed by an r.f. glow discharge and deposited on a substrate at a substrate temperature of about 500-600°K (227-327°C). The material so deposited on the substrate was an intrinsic amorphous material consisting of silicon and hydrogen.

To produce amorphous material a gas of phosphine (PH3) for n-type conduction or a gas of diborane ץ (B2^h6) ^for P־type conduction were premixed with j the silane gas and passed through the glow dis5 charge reaction tube under the same operating conditions. The gaseous concentration of the dopants used was between about 5 x 106־ and 10²־parts per volume. The material so deposited ineluded supposedly substitutional phosphorus or 10 boron dopant and was shown to be extrinsic and of n or p conduction type.

While it was not known by these researchers, it is now known by the work of others that the hydrogen in the silane combines at an optimum temperature with many of the dangling bonds of the silicon during the glow discharge deposition, to substantially reduce the density of the localized states in the energy gap toward the end of making the electronic properties of the amorphous mate20 rial approximate more nearly those of the correspending crystalline material.

D.I. Jones, W.E. Spear, P.G. LeComber, S. Li, and R. Martins also worked on preparing a-Ge:H from GeH4 using similar deposition techniques.

The material obtained gave evidence of a high density of localized states in the energy gap thereof. Although the material could be doped the efficiency was substantially reduced from that obtainable with a-Si:H.

In this work, reported in Philosophical Magazine B. Vol. 39, p. 147 (1979) , the authors conelude that because of the large density of gap states the material obtained is . . a less attractive material than a-Si for doping expertmeats and possible applications.״

The incorporation of hydrogen in the above 5 silane method not only has limitations based upon the fixed ratio of hydrogen to silicon in silane, but, most importantly, various Si:H bonding configurations introduce new antibonding states which can have deleterious consequences in these mate10 rials. Therefore, there are basic limitations in reducing the density of localized states in these materials which are particularly harmful in terms of effective p as well as n doping. The resulting density of states of the silane deposited mate15 rials leads to a narrow depletion width which in turn limits־the efficiencies of devices whose operation depends on the drift of free carriers. The method of making these materials by the use of only silicon and hydrogen also results in a high 20 density of surface states which affects all the above parameters.

After the development of the glow discharge deposition of silicon from silane gas was carried out, work was done on the sputter deposition of 25 amorphous silicon films in the atmosphere of a mixture of argon (required by the sputtering deposition process) and molecular hydrogen, to determine the results of such molecular hydrogen on the characteristics of the deposited amorphous 30 silicon film. This research indicated that the hydrogen acted as a compensating agent which bonded in such a way as to reduce the localized states in the energy gap. However, the degree to which the

-רlocalized states in the energy gap were reduced in the sputter deposition process was much less than that achieved by the silane deposition process described above. The above described p and n dopant materials also were introduced-in the sputtering process to produce p and n doped materials. These materials had a lower doping efficiency than the materials produced in the glow discharge process. Neither process produced efficient p-doped 10 materials with sufficiently high acceptor concentrations for producing commercial p-n junction devices. The n-doping efficiency was below desirable acceptable commercial levels and the p-doping was particularly undesirable since it increased the number of localized states in the band gap.

Various methods of fabrication and construetion of thin film transistors and devices have been proposed wherein the various films of the transistor are made of different materials having 20 different electrical characteristics. For exampie, thin film transistors have been proposed utilizing nickel oxide films, silicon films, amorphous silicon films and amorphous silicon and hydrogen films formed from silane as above men25 tioned. Also, various geometrical configurations have been proposed such as a planar-MOS construetion.

The prior deposition of amorphous silicon, which has been altered by hydrogen from the silane 30 gas in an attempt to make it more closely resemble crystalline silicon and which has been doped in a manner like that of doping crystalline silicon, has characteristics which in all important re-8spects are inferior to those of doped crystalline silicon. As reported by Le Comber and Spear and others referenced above, in the silane based transistor devices the leakage current may be as low 5 as 1011־ amperes, the saturation current appears to be about 5 x 10“θ amperes, the device switching frequency appears to be about 10^ Hz and the stability is poor since the material degrades with time.

It has been proposed to make a solar cell which is essentially a photosensitive rectifier utilizing an amorphous alloy including silicon and fluorine in the aforementioned U.S. Patent No. 4,217,374, issued August 12, 1980 to Stanford R.

Ovshinsky and Masatsugu Izu for Amorphous Semi. conductors Equivalent to Crystalline Semiconductors, and U.S. Patent No. 4,276,898, issued

October 7, 1980 to Stanford R.Ovshinsky and Arun Madan of the same title.

According to the present invention there is provided a thin film, field effect transistor having a source region, a drain region, a gate insulator, a thin film deposited amorphous alloy including at least silicon and fluorine coupled with the source region, the drain region and the gate insulator and a gate electrode in contact with the gate insulator and having a V-MOS-like construction.

Preferably, the amorphous alloy also contains 30 hydrogen, such as an amorphous alloy a-Si_a:Fb:H_cwhere a is between 80 and 98 atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.

The field effect transistor can be deposited on various substrates with an insulator between the active regions of the thin film, field effect transistor and a conducting substrate such as a metal. The transistors can be deposited on an insulator, a semiconductor, an insulated metal or an insulated semiconductor substrate. Because of the capability to be formed on various substrates and the low leakage and operating current, the transistors also can be formed on top of one another, i.e., stacked.

The thin film, field effect transistor can have various desirable characteristics depending upon the particular geometry chosen and thickness of the film of amorphous silicon fluorine material chosen such .as, for example, a DC saturation current as low as 10⁶־ amperes and up to or greater than 104־ amperes, an upper cut off frequency at least above 10 MHz, a high OFF resistance:ON resistance ratio of about 10⁷, and a very low leakage current of about 10“Tl amps or less. Further, the alloy does not degrade with time.

Accordingly, a first object of the invention is to provide a thin film, field effect transistor device characterized by a source region, a drain region, a gate insulator, a thin film deposited semiconductor alloy coupled to said source region, said drain region and said gate insulator, and a gate electrode in contact with said gate insulator having a V-MOS-like construction.

The preferred embodiment of this invention will now be described by way of example, with reference to the drawings accompanying this specification in which:

Fig. 1 is a vertical sectional view of one embodiment of thin film deposited, field effect transistor made in accordance with the teachings of the present invention and having metal source 5 and drain regions similar to a V-MOS-type transistor.

Fig. 2 is a schematic circuit diagram of the transistor shown in Fig. 1.

Fig. 3 is a vertical sectional view through a 10 second embodiment of a thin film deposited, field effect transistor similar to the transistor shown in Fig. 1, having semiconductor source and drain regions.

Fig. 4 is a schematic circuit diagram of the 15 transistor shown in Fig. 3.

Referring now to the figures in greater detail, there is illustrated in Fig. 1 a new V-MOS like construction illustrated in a thin film, field effect transistor 70 made in accordance with 20 the teachings of the present invention. As shown, the transistor 70 is formed on a substrate 72 of insulating material which could be a silicon material, a layer of polymer material or an insulator on top of a metal. On the substrate layer 72 is 25 first deposited a layer or band of drain metal 74 which has a central portion thereof cut or etched away. On top of the drain metal 74 is deposited a thin layer or band of amorphous alloy 76 which has a central portion cut or etched away aligned with 30 the cut away portion of layer 74. In accordance with the teachings of the present invention, an alloy containing silicon and fluorine which can also contain hydrogen and which can be doped to form an N or P type alloy is utilized for forming the amorphous alloy layer 76. This alloy provides the desirable characteristics enumerated before which can be utilized for many different circuits.

The alloy layer 76 is preferably made-of a-Si_a:Fb:H_cwhere a is between 80 and 98 atomic percent, b is between 1 and 10 atomic percent and c is between 1 and 10 atomic percent.

The alloy can be doped with a dopant from

Group V or Group III of the Periodic Table materials in an amount constituting between 10 and 1000 parts per million (ppm). The dopant materials and amount of doping can vary.

The thickness of the alloy layer 76 of amor15 phous material can be between 100 and 5000 Angstroms, one thickness utilized being approximately 1000 Angstroms.

A layer of source metal 78 is deposited on the layer 76 and a corresponding central portion thereof is cut away. Alternately, all the layers can be etched in one step following the deposition of all the layers. Then a gate insulator 80 referred to as a gate oxide is deposited over the source metal 78 and into the resulting central V25 cut space 82 and onto the inclined edges of the layer portions 74, 76 and 78 and over the exposed substrate 72. The source metal 78 and drain metal 74 can be formed of any suitable conductive metal such as aluminum, molybdenum or a high work func30 tion metal such as gold palladium, platinum or chromium. The gate insulator can be a nitride, silicon dioxide or silicon nitride material. The source metal 78 and the drain metal 74 can also have thicknesses ranging from 500 to 20,000 Angstroms with one utilized thickness being of approximately 2000 Angstroms.

A gate conductor 84 which can be of any suit5 able metal such as aluminum or molybdenum is then deposited on the gate insulator 82. The gate conductor 84 can also be made of a doped semiconductor material if desired. Next, a layer 86 of insulating material identified as a field oxide, 10 which can be made of a metal oxide, silicon dioxide or other insulator such as silicon nitride, is deposited over the gate metal conductor 84 as a passivating layer.

This particular V-MOS like construction with 15 the open space 80 has the advantage that a very short distance L is established between the source metal 74 and the drain metal 78 through the alloy layer 76. The layer thickness or distance L resuits in a high operating frequency and a high 20 saturation current.

Depending upon the geometry of the various layers and thicknesses of the various layers, a field effect transistor can be constructed as described above wherein the leakage current is 25 approximately 10^-H amperes thereby to provide a high OFF resistance and a DC saturation current of approximately 10~^ amperes.

In constructing the thin film, field effect transistor 70 shown in Fig. 1, the layers of mate30 rial, and particularly the alloy layer 76, are deposited by various deposition techniques, preferably by glow discharge.

A conventional schematic gate (G), source (S) and drain (D) diagram of the transistor 70 is shown in Fig. 2.

In Fig. 3 is illustrated another V-MOS like 5 thin film, field effect transistor 90.formed on a substrate 92 with alloy layers 94, 96 and 98 having silicon and fluorine (N or P type) deposited on the substrate 92. The respective layers 94, 96 and 98 have a central portion 100 cut or etched 10 away thereof. Then a gate insulator 102 identified as a gate oxide is deposited over the edge of the layer 98 and contacts the exposed edges of the layers 94, 96, and 98 and also the exposed portion of the substrate 92 as shown. A gate conductor 15 104 is deposited over the insulator layer 102 and lastly a layer 106 of insulating material, such as a field oxide, is deposited over the gate conductor 104. The transistor 90 operates utilizing the oppositely biased P-N junctions formed between 20 layers 94 and 96 and between 96 and 98.

The transistor 90 is similar to the transistor 70 as shown in Fig. 1 except that the source region 98 and drain region 94 is made of a semiconductor alloy, such as a-Si:F:H. The V-MOS like 25 construction of the invention illustrated by transistors 70 and 90 is advantageously utilized with any deposited semiconductor material, such as but not only a silicon alloy containing at least hydrogen as deposited from silane.

A conventional schematic circuit diagram of the transistor 90 is illustrated in Fig. 4.

The transistors 70 and 90 can be formed in a matrix so that either the source or drain region extends as a Y axis conductor across the deposited substrate 92. Then, the drain or source region is deposited to form a segregated drain or source region which is then connected to an X axis con5 ductor. Then the gate electrode is deposited so as to extend parallel to the Y axis to form a Y axis gate conductor. In this way, the field effeet transistors 70 and 90 can be utilized in conjunction with PROM devices to form the isolat10 ing device in a memory circuit therefor which comprises a memory region and the isolating device.

The thin film, field effect transistor of the present invention and the various specific embodi15 ments thereof described herein provide a transistor which is very small and yet has very good operating characteristics as enumerated above. The top insulating layer of the transistors, such as 106 in Fig. 3, can be utilized to form the 20 insulating layer for another transistor to be formed thereon to provide a stacked transistor configuration and hence further increase the packing density of the devices. This is possible because the layers are deposited and because of the 25 low operating and leakage current of the devices.

From the foregoing description it will be apparent that a thin film, field effect transistor incorporating an alloy layer of a-Si:F:H therein according to the teachings of the present inven30 tion has a number of advantages.

The gate conductor in a device can be metal, polysilicon or doped semiconductor material with a different metal or semiconductor drain material.

instead of both being of the same metal or semiconductor material.