High power mosfet and method of manufacture

HIGH POWER MOSFET AND METHOD OF MANUFACTURE f

BACKGROUND OF THE INVENTION

This invention relates to MOSFET devices and more specifically relates to a novel, structure for a

MOSFET device which permits it to be used in high power applications with a relatively high reverse voltage and with an exceptionally low on-resistance. The major advantage of the bipolar transistor over the MOSFET transistor is that the bipolar transistor has a very low on-resistance per unit conductive area. The MOSFET transistor has numerous advantages over the bipolar transistor including very high switching speed, very high gain and lack of the secondary breakdown characteristics exhibited by a minority carrier device. However, because the MOSFET transistor has high on-resistance, its use in high power switching applications has been, limited.

BRIEF DESCRIPTION OF THE INVENTION

The present invention provides a novel high power MOSFET device which has a low forward resistance so that the device becomes more competitive with bipolar devices in a switching type application while retaining all of the numerous advantages of the MOSFET over the bipolar device. In particular, with the present invention, the forward resistance per unit area of the י - 3 device has been reduced by at least a factor of two, compared to the limiting resistance per unit area previously existing in a MOSFET-type device.

In one embodiment of the invention, two sources are placed on the same surface of a semiconductor wafer and are laterally spaced from one another. A gate electrode, deposited on a conventional gate oxide, is disposed between the sources. Two p-type conduction channels are disposed beneath the gate.and

1θ are spaced from one another by an n-type bulk region.

Current from each source can flow through its respective channel (after the creation of the inversion layer defining the channel)., so that majority carrier conduction can flow through the bulk region and across the wafer or chip to the drain electrode. The drain electrode may be on the opposite surface of the wafer or on a laterally displaced surface region from the source electrodes. This configuration is made using the desirable manufacturing techniques of the D-MOS device, which 2θ permits precise alignment of the various electrodes and channels and permits use of extremely small channel lengths. While the above configuration device may have been previously described for a MOSFET signal-type device, the structure is not that of the commonly used signal 25 MOSFET.

The device is basically formed in an n(-) substrate which has the relatively high.resistivity which is necessary to obtain the desired reverse voltage capability of the device. For example, for a 400 volt device, the n(.-) region will have a resistivity of about 20 Ohmcentimeters. However, this same necessary high resistivity characteristic has caused the on-resistance of the MOSFET device, when used as a power switch, to be relatively high,

In accordance with the present invention, it has been found that in the upper portion of the central bulk region to which the two inversion layers feed current in the path to the drain electrode, the central region immediately beneath the gate oxide can be a relatively low resistivity material formed, for example, by an n (/)״.,diffusion in that channel region, without affecting the reverse voltage characteristics of the device.

More specifically, and in accordance with the invention, this common channel will have an upper portion beneath the gate oxide and a lower bulk portion extending toward the drain electrode. The lower portion has the high resistivity desired to produce high reverse voltage ability, and will have a depth dependent on the desired reverse voltage for the device, Thus, for a 400 volt device, the lower n(-) region may have a depth of about 35 microns, while for a 9.0. volt device it will have a depth of about 8 microns. Other depths will be selected, depending on the desired reverse voltage of the י - 5 device to provide the necessary thicker depletion region required to prevent punch-through during reverse voltage conditions. The upper portion 0£ the common channel is made highly conductive (n+) to a depth .of from about 3 to about 6 microns. It has been found that this does not interfere with the reverse voltage withstand ability of the device. However, it decreases the on-resistance per unit area of the device by more than a factor of two. The resulting device becomes competitive with conventional high power bipolar switching devices since it retains all of the advantages of the MOSFET device over the bipolar device but now has the relatively low forward resistance which was the major characterizing advantage of the bipolar device.

The present invention also provides a novel high power MOSFET device with 101; forward resistance where, however, a very high packing density is available and which can be made with relatively simple masks. The device further has relatively low capacitance.

Each of the individual spaced source regions, in accordance with a preferred embodiment of the invention, is polygonal in configuration and is preferably hexagonal to ensure a constant spacing along the major lengths • of the sources disposed over the surface of the b'ody.'

An extremely large number of small hexagonal source elements may be formed in the same surface of the semiconductor body for a given device. By way of example, 6,600 hexagonal source regions can be formed in a chip area having a dimension of about 100 by 140 mils to produce an effective channel width of about 22,000 mils, thus permitting very high current capacity for the device.

The space between the adjacent sources may contain a polysilicon gate or any other gate structure where the gate structure is contacted over the surface of the device by elongated gate contact fingers which ensure good.:contact over the full surface of the device.

Each of the polygonal source regions is con10 tacted by a uniform conductive layer which engages the individual polygonal sources through openings in an insulation layer covering the source regions, which openings can be formed by conventional D-MOS photolithographic techniques. A source pad connection region is then provided for the source conductor and a gate pad connection region is provided for the elongated gate fingers and a drain connection region is made to the reverse surface of the semiconductor device.

A plurality of such devices can be formed from 20 a single semiconductor wafer and the individual elements can be separated from one another by scribing or any other suitable.method.

In accordance with another feature of the present invention, the p-type region which defines the channel beneath the gate oxide has a relatively deeply . diffused portion beneath the source so that the p-type diffusion region will have a large radius of curvature in the n(-) epitaxial layer forming the body of the device. This deeper diffusion or deeper junction has been found to improve the voltage gradient at the edge of the device and thus permits the use of the device with higher reverse voltages,

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a plan view of a high power MOSFET chip which incorporates the present invention and particularly illustrates the metalizing patterns of the two sources and the gate.

Figure 2 is a cross-sectional view of Figure!

taken across the section line 2-2 in Figure 1.

Figure 3 is a cross-sectional view similar to

Figure 2 showing the initial step in the process of manufacture of the chip of Figures 1 and 2 and particularly shows the pQ+1 contact implant and diffusion step.

Figure 4 shows the second step in the manufacturing process and shows the n(+) implant and dif20 fusion step.

Figure 5 shows a further step in the process of manufacture of the chip of Figures 1 and 2 and shows the channel implant and diffusion step.

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Figure 6 shows a further step in the process of manufacture and illustrates the source predeposition and diffusion step. This precedes the last step in which the gate oxide is cut for the metalization step which produces the device of Figure 2.

Figure 7 is a plan view of the metalizing pattern of a second embodiment of the invention.

Figure 8 is a cross-sectional view of Figure 7 taken across the section line 88־ in Figure 7.

Figure 8a is a view similar to Figure 2 and shows a modified source contact configuration.

Figure 9. shows the shape of forward-current characteristics of a device like that of Figure 2 where the region 40 beneath the oxide is n(-).

Figure 10. shows the shape of the characteristic of a device identical to that of Figure 2 where the region 40. has high n(+)_ conductivity.

Figure 11 is a plan view of a completed element on a semiconductor wafer prior to the separation of the 20 element away from the remainder of the wafer.

Figure 12 is an enlarged detail of the gate pad to illustrate the relationship of the gate contact and the source polygons in the region of the gate pad.

Figure 13 is a detailed plan view of a small portion of the source region during one stage of the manufacturing process of the device.

Figure 14 is a cross-sectional view of Figure 3 taken across the section line 14-14 in Figure 13.

Figure 15 is similar to Figure 14 and shows the addition of a polysilicon gate, a source electrode means and drain electrode to the wafer.

DETAILED DESCRIPTION OF THE DRAWINGS

A first embodiment of the novel MOSFET device of the present invention is shown in Figures 1 and 2 which show a chip of monocrystalline silicon 20. (or some other suitable material), with the device electrodes following the serpentine path 21 best shown in Figure 1 in order to increase the current-carrying area of the device. Other geometries could be used. The device illustrated has a reverse voltage of about 400 volts and an on-resistance less than about 0.4 ohm with a channel width of 50 centimeters. Devices having reverse voltages of from 9.0 to 40.0. volts have been made. The 400. volt devices have carried pulse currents of 30 amperes. The 90 volt devices have had forward on20 resistances of about 0.1 ohm with a channel width of centimeters and have carried pulse currents up to about 100 amperes. Higher and lower voltage devices can also be made with varying, channel widths.

Presently known MOSFET devices have much higher on-resistances than the above. For example, a 400 volt MOSFET comparable to that described below but made with t

prior art techniques would normally have an on-resistance much greater than about 1.5 ohms, as compared to an onresistance less than about 0.4 ohm in a device made according to this invention. Moreover, the MOSFET switching device of the present invention will exhibit all of the desirable advantages of the MOSFET' device, since it operates as a majority carrier device. These advantages include high switching speed, high gain and avoidance of the secondary breakdown characteristics which exist in minority carrier devices.

The device of Figures 1 and 2 has two source electrodes 22 and 23 which are separated by a metalized gate electrode 24 which is fixed to but spaced from the semiconductor device surface by a silicon dioxide layer

25. The serpentine path followed by gate oxide 24 has a length of 50 centimeters and has 667 undulations, but is shown more simply in Figure 1. Other channel widths can be used. Source electrodes 22 and 23 can be laterally extended as shown to serve as field plates to help spread the depletion region created during reverse voltage conditions. Each of source electrodes 22 and 23 supply current to a common drain electrode 26 which is fixed to the bottom of the wafer. The relative dimensions for the device, particularly in thickness, have been grossly exaggerated in Figure 2 for purposes of clarity. The silicon chip or wafer 20. is formed on an n(+l substrate which may have a thickness of about 14 mils. An n(-). epitaxial layer is deposited on

- t substrate 20 and will have a thickness and resistivity depending on the desired reverse voltage. All junctions are formed in this epitaxial layer which can have a relatively high resistivity. In the embodiment dis5 closed, the epitaxial layer has a thickness of about 35 microns and a resistivity of about 20 ohm-centimeters. For a 90 volt device, epitaxial layer 20 would be about 10 microns thick and would have a resistivity of about

2.5 ohm-centimeters, A channel width of 50 centimeters is also used to provide the desired current carrying capacity for the device.

In a preferred embodiment of the invention, there is an elongated serpentine p(+) conductivity region beneath each of the source electrodes 22 and 23 15 which thus extends around the serpentine path shown in Figure 1. These p (.+1 regions are shown in Figure 2 as the p(+) regions 30 and 31, respectively, and are similar to those of the prior art except that the maximum p( + ) region depthf.is greatly exaggerated in order to form a large radius of curvature. This allows the device to withstand higher reverse voltages. By way of example, the depth of regions 30 and 31 is preferably about- 4 microns at the dimension X in Figure 2 and about 3 microns at the dimension Y in Figure 2.

By using D-MOS fabrication techniques, two n('+l regions 32 and 33 are formed beneath source electrodes 22 and 23, respectively, and define, with the p(+) regions 30 and 31, n־type channel regions 34 and

35, respectively. Channel regions 34 and 35 are disposed beneath the gate oxide 25 and can be inverted by the appropriate application of a biasing signal to the gate 24 in order to permit conduction from the source 22 and the source 23 through the inversion layers into the central region disposed beneath the gate 24 and then to the drain electrode 26. Channels 34 and 35 may each have a length of about 1 micron.

It has previously been thought necessary that the central n(־)_ region between channels 34 and 35 (and between pC+1 regions 30 and 31) should have a high resistivity in order to permit the device to withstand high reverse voltages. However, the relatively high resistivity η(.־), material is also a significant contributing factor to the high, forward on-resistance of the device.

In accordance with the significant feature of the present invention, a significant portion of this central conducting region is made relatively highly conductive and consists of an n(+) region 40 disposed immediately beneath the gate oxide 25. The n(+) region 40 has a depth of about 4 microns and could range from about 3 microns to about 6 microns. While its exact conductivity is not known, and varies with depth, it is high relative to the n(־) region beneath it. More particularly, region 40 has a high conductivity which would be determined by a total ion implanted dose of from about 1 x 1012 to 1 x 101^ phosphorus atoms/cm2 at 50 kV followed by a diffusion drive at from 1150°C to 1250°C for from 30. minutes to 240. minutes. It has been found that by making this region 40 relatively highly conductive n(+). material through a diffusion or other operation, the device characteristics are significantly improved and the forward on-resistance of the device is reduced by a factor greater than two.

Moreover, it has been found that the provision of the high conductivity region 40 does not interfere with the reverse voltage characteristics of the device. Accordingly, by making the region beneath the gate oxide 25 and between channels 34 and 35 more highly conductive, the forward on-resistance of the ultimate high power switching device has been significantly reduced and the MOSFET device becomes far more competitive with an . equivalent junction-type device while still retaining all of the advantages of the MOSFET majority carrier operation.

In the above description of Figures 1 and 2, it has been assumed that the conduction channels 34 and 35 are of p(+). material and are, accordingly, inverted to an n־type conductivity to provide a majority carrier conduction channel from sources 22 and 23 to the central region 40 upon the application of an appropriate gate voltage. Clearly, however, all of these conductivity types could be reversed so that the device could work as a p-channel device rather than an n-channel device as disclosed.

One process by which the device of Figures 1 and 2 could be constructed is shown in Figures 3 to 6. Referring to Figure 3, the base wafer 20 is shown as an n(+). material having an n(.־). epitaxially deposited region on top thereof. A thick oxide layer 50 is formed on wafer 20 and windows 51 and 52 are opened therein. The open windows 51 and 52 are exposed to a beam of boron atoms in an ion implanting apparatus to form p(+) regions. Thereafter the implanted boron atoms are caused to diffuse deeper into the wafer to form the rounded p(+l concentration region shown in

Figure 3 which might have a depth of about 4 microns. During this diffusion operation, shallow oxide layers 53 and 54 grow over the windows 51 and 52.

As is next shown in Figure 4, windows 61 and 62 are cut in the oxide layer 50 and an n(+) implant takes 20 place to implant the n(+). regions 63 and 64 into the n(.־l epitaxial layer. This n(+l implantation can be carried out with a phosphorus beam. Thereafter, the implanted regions are subjected to a diffusion step to cause the regions 63 and 64 to expand and deepen to a depth of about 31/2־ microns with a concentration determined by an implantation dose of 1 x 10 to

2 x 10 phosphorus atoms/cm followed by a drive for minutes to 4 hours at from 1150°C to 1250°C. As will be later seen, regions 63 and 64 produce the novel n(+) region which substantially reduces the on-resistance of the device.

5 It should be noted that the n( + ) regions 63 and 64 could, if desired, be epitaxially deposited and need not be diffused. Similarly, the resulting device being described herein could be manufactured by any desired process as would be apparent to.those skilled .

in the art.

The next step in the process is shown in Figure 5 and is the channel implantation and diffusion step in which the pC+1 regions 71 and .72 are formed through the same windows 61 and 62 that were used for the n(+) implantation for regions 63 and 64,. The p( + ) regions 71 and 72 are formed by implanting with a boron beam to a dose of about 5 x 1013 to 5 x 1014 atoms/cm2 followed by a diffusion drive for 30 to 120 minutes at 1150°C to 1250°C.

Thereafter, and as shown in Figure 6, steps are carried out for the source predeposition and the diffusion of the source regions 32 and 33. , This is carried out by a conventional and non-critical phosphorus diffusion step where the diffusion proceeds through the windows 61 and 62 so that the source regions 32 and 33 are automatically aligned relative to the other preformed regions. Thus, the wafer is placed in a furnace and exposed to POCl^ suspended in a carrier gas for from 10 minutes to 50 minutes at a temperature of from 850°C to

1000°.

When this step is completed, the basic junction configuration required in Figure 2 is formed with short p(+). regions disposed beneath the oxide 50 to serve as the conducting channel for the ultimately constructed device and with an n(+) region filling the area between the channels 34 and 35 and between p(+) regions 30 and 31. The manufacturing process then continues from the step of Figure 6 to the device shown in Figure 2 wherein the oxide surfaces on top of the chip are suitably stripped and the metalizing patterns for contacts 22, 23 and 24 are formed to establish electrical contacts to the device. The drain contact 26 is applied to the device in a subsequent metalizing operation. Thereafter, the entire device may be appropriately coated with a suitable passivation coating and wire leads are connected to the source electrodes 22 and 23 and the gate 24, The device is then mounted within a suitable protective housing, with the drain electrode fixed to the housing or other conductive support which serves as a drain connection.

The device shown in Figures 1 and 2 utilizes a serpentine path for each of the source regions and gate regions and a drain on the surface of the wafer opposite to the source electrodes. Other configurations can be used. Figures 7 and 8 illustrate a planar configuration which is a simple rectangular arrangement having a ring-shaped gate 80 which is disposed between.

5 a first source electrode 81 of ring shape and a central source 82. The device as shown in Figure 8: is contained within a base wafer of p(-j monocrystalline silicon 83 which may have a buried n(+) region 84 to reduce the lateral resistance of the various current paths of the device leading to the laterally displaced drain electrode 85 which surrounds source 81.

A ring-shaped n(+l region 86 is formed within the device as shown in Figure 8 and, in accordance with the present invention, the ring-shaped region 86 is of 15 much higher conductivity than the n(-) epitaxially deposited region 87 which contains all of the junctions of the device. The ring-shaped region 86 extends from the region beneath the gate oxide 88 and adjoins the ends of the two conducting channels formed between the ring-shaped p(+j region 89 and the central p(+). region 9.1 disposed beneath the ring-shaped source 81 and central source 82, respectively.

It will also be noted in Figure 8 that the outer periphery 90 of the p(+) ring 89 has a large 25 radius to assist the device in withstanding high reverse voltages.

An n( + ) region 95 in Figure 8 is provided to ensure good contact to drain electrode 85. Drain electrode 85 is widely laterally spaced from source 81 (by greater than about 90 microns). The drain contact

85 is surrounded by a p(+) isolation diffusion 96 to isolate the device from other devices bn the same chip or wafer.

In the arrangement of Figure 8, like that of Fig. current flow from source 81 and 82 goes through the width 10 - of epitaxial region 87, through the region 86., The current then flows laterally outward and then up to the drain contact 85. As in the embodiment of Figure 2, device resistance is greatly reduced by the relatively highly conductive region 86.

15 In carrying out the above invention, it should be noted that any type of contact material can be used to make the source and gate contacts. By way of example, aluminmn could be used for the source

*׳ ' electrodes while a polysilicon material can be used for 20 the conductive gate 8Q in Figure 8 or the conductive gate 24 in Figure 2.

Numerous other geometries can be used to make the device of the invention, including a plurality of pairs of straight, parallel source elements with 25 respectively interposed gates and the like.

The source electrodes 22 and 23 have been shown as separate electrodes which can be connected to separate leads. Clearly, the sources 22 and 23 could be directly connected as shown in Figure 8a where components similar to those of Figure 2 have been given similar identifying numerals. In Figure 8a, however, the gate electrode is a polysilicon layer 101 (in place of aluminum) deposited atop gate oxide 25. The gate 25 is then covered with oxide layer 102 and a conductive layer 103 connects the two sources 22 and 23 together to form a single source conductor which is insulated from gate 101. Connection is made to the gate at some suitable edge portion of the wafer.

Figures 9 and 10 show the shape of measured curves which demonstrate the reduction in forward resistance when the region 40 is made highly conductive (n+). In Figure 9, the device tested had a region 40 which had then(-) resistivity of the epitaxial region. Thus, the forward resistance is characteristically high at different gate biases as shown in Figure 9.

In the device of the invention where region 40 is of n(+) conductivity, there is a dramatic decrease in the on-resistance as shown in Figure 10 for all gate voltages before velocity saturation of the electrons occurs.

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The polygon configuration 0£ the source regions of the present invention is best shown in Figures 13, 14 and 15 which are first described.

Referring first to Figures 13 and 14, the device 5 is shown prior to the application of the gate, source and drain electrodes. The manufacturing process can be of any desired type including the D-MOS fabrication techniques and ion implantation techniques previously described for the formation of the junction and placement of the 10 electrodes in the most advantageous way.

The device is described as an N channel enhancement type device. It will be apparent that the invention will also apply to P channel devices and to depletion mode devices.

, The device of Figures 13 and 14 has a plurality of polygonal source regions on one surface of the device, where these polygonal regions are preferably hexagonal in shape. Other shapes such as squares could have been used but the hexagonal shape provides better uniformity 20 of spacing between adjacent source region perimeters.

In Figures 13 and 14, the hexagonal source regions are formed in a basic semiconductor body or wafer which can be an N type wafer 120 of monocrystalline silicon which has a thin N(-J epitaxial region 121 deposited 25 thereon as best shown in Figure 14*. All junctions are formed in epitaxial region 121. By using suitable masks, a plurality of P type regions such as regions 122 and 123 in Figures 13 and 14 are formed in one surface of the semiconductor wafer region 121, where these regions are generally polygonal in configuration and, preferably, are hexagonal.

A very large number of such polygonal regions are formed. For example, in a device having a surface dimensions of 100 by 140 mils, approximately 6600 poly- gonal regions are formed to produce a total channel width of about 22,000 mils. Each of the polygonal regions may have a width measured&amp;#1523;perpendicular to two opposing sides of the polygon of about 1 mil or less. The regions are spaced from one another by a distance of about 0.6 mil when measured perpendicularly between the adjacent straight sides of adjacent polygonal regions.

The P+ regions 122 and 123 will have a depth d which is preferably about 5 microns to produce a high and reliable field characteristic. Each of the P regions has an outer shelf region shown as shelf regions 124 and 125 for P regions 122 and 123, respectively, having a depth s of about 1.5 microns. This distance should be as small as possible to reduce the capacitance of the device.

Each of the polygon regions including polygonal regions 122 and 123 receive N+ polygonal ring regions

126 and 127, respectively. Shelves 124 and 125 are located beneath regions 126 and 127, respectively. N+ regions 126 and 127 cooperate with a relatively conductive

N+ region 128 which is the N+ region disposed between adjacent P type polygons to define the various channels between the source regions and a drain contact which will be later described.

The highly conductive N+ regions 128 are formed in the manner described for the preceding embodiments and produce a very low forward resistance for the device.

In Figures 13 and 14, it will be noted that the entire surface of the wafer is covered with an oxide layer or combined conventional oxide and nitride layers which are produced for the formation of the various junctions. This layer is shown as the insulation layer 130, The insulation layer 130 is provided with polygonal Shaped openings such as openings 131 and 132 immediately above polygonal regions 122 and 123. Openings 131 and 132 have boundaries overlying the N+ type source rings 126 and. 1.2.7 for the regions 122 and 123, respectively. The oxide strips 130, which remain after the formation of the polygonal shaped openings, define the gate oxide for the device.

Electrodes may then be applied to the device as shown in Figure 15. These include a polysilicon grid which includes polysilicon sections 140, 141 and 142 which overlie the oxide sections 130.

A silicon dioxide coating is then deposited atop the polysilicon grid 140 shown as coating sections 145, 146 and 147 in Figure 15 which insulates the polysilicon control electrode and the source electrode which is subsequently deposited over the entire upper surface of the wafer. In Figure 15 the source electrode is shown as conductive coating 150. which may be of any desired material, such as aluminum. A drain electrode 151 is also applied to the device.

The resulting device of Figure 15 is an N channel type device wherein channel regions are formed between each of the individual sources and the body of the semiconductor material which ultimately leads to the drain electrode 151. Thus, a channel region 160 is formed between the source ring 126, which is connected to source electrode 150, and the N+ region 128 which ultimately leads to the drain electrode 151. Channel 160 is inverted to the N type conductivity, upon the application of a suitable control voltage to the gate 140. In a similar manner, channels 161 and 162 are formed between the source region 126, which is connected to the conductor 150, and the surrounding N+ region 128 which leads to the drain 151, Thus, upon application of a suitable control voltage to the polysilicon gate (including finger 141 in Figure 15), channels 161 and 162 become conductive to permit majority carrier conduction from the source electrode 150. to the drain 151.

-, 24 Each of the sources form parallel conduction paths where, for example, channels 163 and 164 beneath gate.element 142 permit conduction from the source ring

127 and an N type source strip 170 to the N+ region 128 and then to the drain electrode 151.

It i.s to be noted that Figures 14 and 15 illustrate an' end P type region 171 which encloses the edge of the wafer.

The contact 150 of Figure 15 is preferably an 10 aluminum contact. It will be noted that the contact region for the contact 15Q lies entirely over and in alignment with the deeper portion of the P type region 122. This is done since it was found that aluminum used .for the electrode 150 might spike through very thin regions of the P type material. Thus, one feature of the present invention is to ensure that the contact 150 lies principally over the deeper portions of the P

- regions such as P regions 122 and 123. This then permits the active channel regions defined by the annular 2.0 shelves 124 and 125 to be as thin as desired in order to substantially reduce the device capacitance.

Figure 11 illustrates one completed device using the polygonal source pattern of Figure 15. The completed device shown in Figure 11 is contained within 25 the scribe regions 180, 181, 182 and 183' which enable the breaking out of a plurality of unitary devices each having a dimension of 100 by 140 mils from the body of the wafer.

&amp;#1470; 25 &amp;#1470; .

The polygonal regions described are contained in a plurality of columns and rows. By way of example, the dimension A contains 65 columns of polygonal regions and may be about 83 mils. The dimension B may contain 5 100 rows of polygonal regions and may be about 148 mils. Dimension C, which is disposed between a source connection pad 190 and a gate connection pad 191, may contain 82 rows of polygonal elements.

The source pad 19.0 is a relatively heavy metal section which is directly connected to the aluminum source electrode 150 and permits convenient lead connection for the source.

The gate connection pad 191 is electrically connected to a plurality of extending fingers 192, 19.3, 15 194 and 195 which extend symmetrically over the outer surface of the area containing the polygonal regions and make electrical connection to the polysilicon gate as will be. described in connection with Figure 12.

Finally the outer circumference of the device 20 contains the P+ deep diffusion ring 1.71 which may be connected to a field plate 201 shown in Figure 11.

Figure 12 shows a portion of the gate pad 191 and the gate fingers 194 and 195. It is desirable to make a plurality of contacts to the polysilicon gate in 25 order to reduce the R-C delay constant of the device.

The polysilicon gate has a plurality of regions including regions 210, 211, 212 and the like which extend outwardly

I and receive extensions of the gate pad and the gate pad elements 194 and 195. The polysilicon gate regions may be left exposed during the formation of the oxide coating 145 147 in Figure 15 and are not coated by the source electrode 50. Note that in Figure 12 the axis 220 is the axis of symmetry 220 which is that shown in Figure 11.

Although the present invention has been described in connection with a preferred embodiment . thereof,. many variations and modifications will now become 10 apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.