Synchronous power communicating

!1 The present invention relates in general to communicating !1 . i ?over power lines and more particularly concerns novel techniques j and apparatus for exchanging digital data over distribution power j : lines between .a central control unit and remote meter or control ! Modules. The invention is especially useful in facilitating ! automatically monitoring and controlling the power distribution ן system and reading meters at remote locations with good reliability I It accomplishes this using the existing power distribution system I between a substation where a typical central control unit located and each remote meter or control module not only itransmission path, but also 88 a synchronisation source invention advantageously incorporates fewer components at remote meter and control modules than at the central control unit is as. a

The the ';to help keep system costs down.

I Utility meters are typically read periodically by a 'meter reader at the location of each customer who manually records each meter reading and returns the information concerning the date, I location and reading to a central office. At the central office i >

la keypuncher or other operator manually converts this data into ia form for automatic processing by billing computers.

When meters are inside a building and no one is I !available, to admit the meter reader, the meter reader does not 'record the reading for that period. The meter reader may leave i|a post card addressed to the utility instructing the customer to ijroad the meter himself, write the reading on the postcard and mail the reading to the utility. Alternatively, the utility .i.

׳!may estimate the use for that period based on past history. Both !of these approaches are subject to inaccuracy. Moreover, even i

“in systems where the meter is located outside and me meter .reader always has access to it, manually obtaining and converting 'ij these readings for automatic processing Is costly, time consuming־

I״2־

A GEN P02 land subject to error in each step between initial reading by the CH7c^“ !1 , , , Λ,,, taeter reader and automatic data processing for billing by the • computer.

A number of automatic meter reading systems have been ^proposed. One approach Involves the use of telephone lines to ;carry the data. Mother contemplates transceivers at each !customer location with an aircraft flying over the area to in!terrogate transponders at each customer location through the !transceivers. Still another approach contemplates the use of power lines for communicating data, but with costly links bypassing each distribution transformer. A disadvantage common Ito all these systems is high cost.

' Utilities presently monitor the power flow on distri ׳bution lines at very few locations because of the high cost of !telephone lines or limited radio-frequency channel allocation.

I Control elements such as switches are manually operated while power factor correction capacitors are operated by a clock !rather than in response to load demands. When power outages occur because of.breaks in the distribution line, utilities wait jfor customer telephone complaints to inform them of the affected !area because they have no method of monitoring or controlling the distribution system in real-time.

! Utilities also have to provide generating capacity to ' meet the peak load demands, rather than the average or essential

I load. The present method of peak load shaving is to lower the ' distribution voltage, which is harmful to items such as computers and air conditioners, or in the extreme, to black out sections ;!of their franchised area by interrupting service. It is a far !1 , better practice to shave peak load by interrupting service to non-essential power loads such as hot water heaters. This is presently accomplished by using time clocks, which lose time during power outages and therefore eventually do not remove the

<td> A GEN P02</td><td> .load during periods of maximum power consumption, or by general</td>

<td> CH/ck 579774</td><td> i ^v * )appeals to the public to turn off non-essential loads. Summary of the Invention</td>

<td> 3.0</td><td> An important object of this invention is to provide an. improved power line communication system. ^r:' It is another object of the invention to achieve the preceding object with a relatively economical digital data trans.- ! mission system in which the existing power transmission system is used not only as transmission paths but also as a source of synchronizing signals locally available at each station. It is another object of the invention to achieve one or more of the preceding objects in a system where equipment specifications at the numerous meter or control module locations may be relaxed relative to those at the many fewer central control</td>

units to keep system costs down while maintaining a reliable exchange of data at reasonable transmission rates.

J It is a further object of the invention to achieve one i

!or more of the preceding objects with a system capable of

;)discriminating between desired and un'desired signals.

It is still a further object of the invention to achieve * one or more of the preceding objects with a system incorporating a logic arrangement facilitating reliable communication at relatively low costs.

I It is another object of the invention to achieve one or more of the preceding objects while automatically reading meters at many remote locations and accurately transmitting these readings to a central billing location.

j It is another object of the invention to achieve one or more of the preceding objects while automatically controlling elements of the power distribution system at many locations and accurately transmitting the status of these elements to a central !operations control location.

It is another object of the invention to achieve one or

'.;)&amp;#1492; /&amp;#1523;&amp;#1523;. b &amp;#1524;5&amp;#1497;&amp;#1509;

A GEN P02 more of the preceding objects while providing a means of rapid

CTM ii '

10/7774 'peak load shaving by interrupting service to non-essential loads, j

It is another object of the invention to achieve one or i more of the preceding objects while providing a means for metering ! power consumption during peak demand hours.

Brief Description of the Drawing

Numerous other features, objects and advantages of the I invention will become apparent from the following specification 1 ;1when read in connection with the accompanying drawing in which: ;

' I

FIG. 1 is a block diagram illustrating the logical !

i 1 ^arrangement of a system according to the Invention;

I! FIG. 2 is a block diagram illustrating the logical arrangement of a system according to the invention having a number of central control units at intervals along a power distribution network;

FIGS. 3A-3G graphically represent the composition of messages for transferring data between the data acquisition computer and central control unit and between the central control unit and the transponders;

i ' &amp;#1523;&amp;#1470; .

&amp;#943; FIG. 4 is a block diagram illustrating the logical arrangement of a,central control unit;

J FIG. 5 is a block diagram illustrating the logical i irrangement of a transponder;

FIG. 6 is a block diagram illustrating the logical arrangement of a meter encoder; 1 jl FIG. 7 is a graphical representation of spectral noise as a funcHen of frequency typically encountered on a 120 volt power line;

I FIGS. 8A and 8B are graphical representations of transmission as a function of freauency in an actual installation

* &amp;#1470; 4 according to the Invention;

!'i FIGS. 9Λ and 9B are schematic circuit diagrams of power factor correction capacitors with series and parallel isolation networks, respectively;

FIG. 10 shows the specific interconnections among integrated circuits

<img file="IL48084A_D0001.tif" />

A GEN P02forming the modulator;

CiT/ck *

7774&amp;#1470;107 demodulator and timing control for the central control unit;

I. X. ' &amp;#1503; FIG. 11 is a timing diagram illustrating typical modulator

A and demodulator timing signals provided by the system of FIG. 100;:

FIG. 12 is a timing diagram helpful in understanding how I data transmitted by the data acquisition computer is processed j by the central control unit; | i

FIG. 13 is a timing diagram showing command cycle !

I ' !

j timing signal waveforms of the central control unit;

! , !

FIG. 14 is a timing diagram showing interrogation cycle timing signal waveforms of the central control unit;

FIG. 15 is a timing diagram showing Interrogation cycle signal waveforms related to data transfer from the central unit ito the data acquisition computer;

! FIG. 16 shows central control uiiit demodulator phase !scan timing signal waveforms;

] FIG. 17 shows specific circuit connectiors among !1 integrated circuits forming the input register and sync code register;

FIG. 18 shows specific interconnections among integrated circuits forming the central control unit coiwnand register; ;

FIG. 19 shows the specific Interconnections among : i components forming central control unit status register;

FIG. 20 shows specific circuit interconnections among ! integrated circuits forming the central control unit output !register;

j '.

! FIG. 21 shows specific interconnections among components ]forming the demodulator, modulator and timing control for the ,!transponder;

![ FIG. 22 shows timing signal waveforms of the transponder ! of FIG. 21;'and

FIG. 23 is a schematic circuit diagram of an exemplary&amp;#1523;

A GEN P02,

Cil/ck-379774 transponder;transmitter.

Description of the Preferred Embodiments

With reference now to the drawing and more particularly

FIG. 1 thereof, there is shown a block diagram illustrating the ; logical arrangement of a system according to the invention. Where appropriate, corresponding elements are identified by the same : reference symbol throughout the drawing. A central billing computer 1, which may be an IBM 360/95, prepares a data file ; containing information pertaining to each meter to ba read or i i item to be controlled,’ with the data file sorted in a hierarchy according to data acquisition and control branch identification, j central control unit identification, distribution feeder and 'phase identification, meter module identification, clock polarity :, identification, and meter type identification. The data file :!is then transmitted by.high speed data link 18, which may be an ;'interconnecting cable, to a communication dispatch computer 2, which may be a Data General NOVA 840. The communication dispatch ;computer 2 transmits the pertinent parts of the data file to a multiplicity of data-acquisition and control branches, such as 3A through 3Γ, via high speed data lines, !9τ&amp;#1470; respectively, !which may be telephone lines or microwave links. The data '1 !

!file is loaded into the data-acquisition computer controlling each I ' . ! jbranch, such as item 4 of branch 3A, which may be a Data General ; NOVA 2/10.

The data-acquisition and control branches, such as 3A, interface with a multiplicity of distribution and metering 1 systems, such as 6Λ through 6R, via a multiplicity of central control units, such as 5A through 5R, which receive data from data

I!

^acquisition computer 4 via data links 20A through 20R, respectively. !&amp;#1523;Based on the data file received from communication dispatch ;computer 2, data acquisition computer 4 sends data to a central !control unit, such as 5A, via data link 20Λ, which may be a

<img file="IL48084A_D0002.tif" />

A R7.N P02

WHk-W774 telephone line, microwave link or cable TV cable, identifying j &amp;#943; ' I &amp;#1523;the distribution feeder and phase 21A that central control unit !

j5A should impress its output signal onto. Distribution feeder ; and phase 21A forms part of distribution network 7. Central |control unit 5A signals data acquisition computer 4 when it has ! ! ' ' ! ]completed switching its output signal to the indicated distribution power feeder 21A. Data acquisition computer 4 then sends data to !

central control unit 5A Instructing it which meter module, such j as 11Λ, and meter type, such as 15, to interrogate, the clock ! polarity to be used for interrogation, and at what data rate meter ;module HA should reply. Central control unit 5A impresses a :modulated audio-frequency signal containing meter module address, imeter type and reply data rate information on distribution feeder j21A. The signal travels along power distribution network 7, cornprising power distribution feeder 21A, which may be 3 3-phase, 12,4 1 kilovolt feeder, and a multiplicity of distribution transformers,

10A through 10’!, to a multiplicity of metering groups, 8A through !

M. The multiplicity of all the meter modules, such as 11A i ]through HP, attached to the 240 or 120 volt, 60-Ilz, distribution ! 14 MA transformer secondaries, such as line 24 of distribution transi .1 former 10A, receive the central control unit signal and their transponders, such as 12, demodulate and decode the signal. The ;:ransponder 12 whose locally-stored identification code matches .:hat of the decoded signal obtains the meter reading of the j !designated meter, such as the electric meter 15, from a meter en- ] ^:oder, such as 13, via line 26. The transponder 12 then impresses I !! ’ ' I on power distribution network 7, via line 24 and distribution trans;i . 'i former 10A, a modulated audio-frequency signal identifying the meter module (HA in example) and meter type (15 in the example), 'i ' &amp;#1523; ' ''

Specifying the reply data rate, and giving the meter reading. The

Signal travels along power distribution network 7 to central control

1 &amp;#1470; .1!

(init 5Λ, xiiich demodulates the signal and sends the data to data acquisition

A GEN PQ2 computer 4 via data link 20A. Data acquisition computer 4 checks CiT/cV. ii

579774 ’jthe data for errors and if any are found repeats the interrogation cycle at a lower reply baud rate. If no errors are found, data ; acquisition computer 4 stores the meter reading In a data file. After all assigned meters have been interrogated, it '

I transmits the meter reading data to central billing computer 1 I.

i . I 'via data link 19, communication dispatch computer 2 and cable 18. I . j In a similar manner, the system can also read gas meters, such as

16, and water meters, such as 17, by using meter encoders 10 13' and 13, respectively.

Another feature of the invention is the ability to :

)Control the configuration of distribution network 7 by connecting ' or disconnecting power factor correction capacitors, such as 23, to.

or from distribution feeders, such as 21A, and by connecting or dis;connecting distribution feeder switches, such as part of 9N.

:Operation center 28 signals a data acquisition a!;d control ’ branch, such us 3A, via data link 29, communication dispatch :computer 2 and data link 19A, to connect or disconnect power ; ;factor correction capacitors, such as 23, to or fran distribution feeder 21A. Data acquisition computer 4 selects the proper central ! ! !control unit, such as 5A, and then sends data to it identifying j !the distribution feeder and phase, such as 21A, central control

, ' . 1&amp;#1523;

5A should impress its output signal onto. Data acquisition computer.

then sends data to central control unit 5A instructing it ,which control module, such as 9A, to command, the clock polarity to be used for Interrogation, and at what baud rate control module 9A should reply with switch status. Central control unit

&amp;#1523; . ;

5A impresses a modulated audio frequency signal containing control :;module address, switch command and reply data rate information ton distribution feeder 21A. The signal travels along power '^distribution network 7, through a multiplicity of distribution :transformers, such as 10A through 10M, to a multiplicity of i -9A GEN P02 ’control modules, 9A through 9N, which receive the central Cli/ck

579/74&amp;#1470; 'control unit signal. Their transponders demodulate and decode !the signal and the transponder, such a9 12', whose identification &amp;#943; ;code matches that of the decoded signal commands switch 22, which ! ;may be a General Electric Catalogue #178L793G51, to the desired | !state, thereby connecting or disconnecting power factor correction

I capacitor 23 tc or from distribution feeder 21A. Transponder 12' then 1 impresses a modulated audio-frequency signal containing the i ! ' ' j &amp;#1503; identification code of control nodule. 9A, reply data rate and ;

switch status on power distribution network 7, via line 24 and ;

!distribution transformer 10A. The signal travels along power jdistribution network 7 to central control unit 5Λ which ;demodulates the signal and sends the data to data-acquisition !computer 4 via data link 20A. Data acquisition computer 4 checks the data for errors and, if any are. found, repeats the command cycle at a lower reply: baud rate. If no errors.are found, data ;:acquisition computer 4 transmits the power factor correction !capacitor switch status to operation center 28 via data link 19A, i;

;communication dispatch computer 2 and data link 29.

; Another feature of the invention is the ability to shave !!peak load by disconnecting high -power-consumption devices such as i|electric hot&amp;#1470;water heaters. Operation center 28 signals a data acquisition and control branch, such as 3A, via data link 29, cons&amp;#1524; ! tnunication dispatch computer 2 and data link 19A, to disconnect hot water heaters. Data acquisition computer 4 sends data to central control units 5A through 5R Instructing them to interrogate all meter modules, such as 11A and 11B, by means of !a given clock polarity, hot water heater identification code and ! command code) Central control units 5A through 5R impress a modulated audio&amp;#1470;frequency signal containing the hot water heater ' identification code and command code on distribution networks, ; such as 7. The signal travels along power distribution feeders,

A GEN Ρ02 !such as 21A, through a multinlicity of distribution transformerst CW? J ' 1(177774 such as 10A through 10M, to a multiplicity of meter modules, such as 11A through IIP. All the meter modules receive the central control unit signal, and the transponders, such as 12, using the i same clock polarity as the transmitted signal correctly demodulate and decode the signal. All transponders contain the hot water | identification code and command their associated hot. water heaters!, such as 14, to the state indicated by the command code. No reply is sent to the central control units in response to this message. !

In a similar manner data acquisition computer 4 then interrogates ;the meter modules using the inverse clock polarity. Thus, the !peak load 18 shaved by a considerable amount in a very short period. The high power consumption devices such as hot water heaters, can be reconnected in a like manner. Alternatively, these devices can be reconnected after a preset interval by using a time-delay relay or similar device.

i In a similar manner, the invention can be used for d

) teetering power consumption during the peak demand hours between and 8 P.M. A second meter encoder, or similar device, is provided at each’metering location. At the start of the peak demand period the hot water identification code is transmitted to all meter modules, along with function code indicating the start ; of peak demand metering. The transponders, such as 12, receive Jithe signal and command the peak demand meter encoder to log the power being consumed. At the end of the peak demand period | the hot water identification code is transmitted to all meter| :!&amp;#943; modules, along with a function code indicating the end of peak .

'1&amp;#1523; demand metering. The transponders, such as 12, receive the li

Signal and command the peak demand meter encoders to stop logging the power being consumed. Alternatively, the peak demand peter encoders can be commanded to stop logging power consumption by using a timer, time-delay relay or similar device. Each peak -11A GEN P02 ciT7?k---W7774 demand meter encoder can then be read monthly or bi-monthly as previously described.

Another feature of the invention is the ability to monitor the power distribution system operating parameters, such as current flow, voltage amplitude and switch status. A transducer, such as current transducer 30, produces a digital signal that is proportional to the current flow through distribution feeder 21A. When a measurement of the current flow in distribution feeder 21A is desired, operations center 28 signals data acquisition computer 4 via data link 29, communication dispatch computer 2 and data link 19A. Data acquisition computer 4 sends data to central control unit 5A instructing it j!to impress its output signal onto power distribution feeder 21/¼.

Data acquisition computer 4 then sends data to central control !unit 5A instructing it to interrogate status module 31, the clock polarity to be used for interrogation, and at what baud rate status module 31 should reply. Central control unit 5A impresses a modulated audio-frequency signal containing status .1 i

-!lak Gl'N PD?. CU/ck 5/9774

I , ' &amp;#1470; module address and reply baud rate information on distribution network 7, through a multiplicity of distribution transformers, &amp;#943; :ouch' as 10A through 10M, to status module 31, where transponder

I . &amp;#1470; . i

12” demodulates and decodes the signal. Since the address of j

| &amp;#1497; !

!transponder 12' matches the demodulated and decoded signal, it !obtains the digital signal representing the current flow from &amp;#1503; 'current transducer 30. Transponder 12“ then impresses a modulated' 'audio-frequency signal containing the identification code of the j ;status module 31, reply baud rate and current flow information on

I. ' !

power distribution feeder 21A via line 24’ and distribution i !transformer 10M. The signal travels along power distribution network. 7&amp;#1523; to central control unit 5Λ which demodulates the ,signal and sends the data to data acquisition computer 4 via data link

20A. Data acquisition computer 4 checks the data for errors and, if any are found, repeats the interrogation cycle with a lower reply baud rate. If no errors are found,data acquisition computer 4 transmits the current flow data to operation center 28 via data link 19A, communication dispatch computer 2 and data link 29. ! The substations of the power distribution system are 20 'advantageous locations for central control units 5A through 5R. At this location the central control unit, such as 5A, has :direct access to all distribution feeders and phases, such ' !!

as 21A. through 21R, emanating from transmission transformers, • !1 'such as 27A through 27R, respectively, thereby allowing a single ' j!

‘central control unit, such as 5A, to conciunicate with all meter i modules, such as 11A through IIP, powered by the substation, j With reference to FIG. 2, it is also within the >principles of the invention to locate central control units at j intervals along distribution network 7'. With, this arrangeraent data acquisition computer 4' communicates with all central control !units, such as 5C through 5F, simultaneously on a party line basic via data link 20C, which may be a telephone line. The data ’ -12A GEN ?02 'acquisition computer message contains a central control unit CIi7c£--?710774 address code and only the central control unit that is addressed, &#1523; ipuch as 5C, responds to the message. Each central control j ^junit such as 5C through 5F has to communicate with only one I

' &amp;#1494;&amp;#1503;.

'metering group, such as 8C through 8F, respectively, thereby reducing !the output signal power requirements of the central control units.

&amp;#1503; Communications with a control module, such as 9B, is assigned to a single central control unit, such as 5D.

t

Having briefly described the physical arrangement of the system,its operational techniques will not be described.

!Referring to FIGS. 3A-3G, there is shoxm the composition of the li ]messages used to transfer data between data acquisition computer and central control unit 5, and central control unit 5 and meter transponder 12. Data is transferred between data acquisition ^computer 4 and central control 5 at 285 baud using the 11 bit byte message format of FIG. 3A. Other baud rates and message !formats may be used without departing from the principles of the ;invention. The signal is normally in the stop (logic 1 ) state and die start of a byte is delineated by a start (logic 0) bit. Eight bits of 2θ jdata are then transmitted with the end of a byte denoted by two stop bits.

Data acquisition computer 4 sends command messages to Central control unit 5 controlling its configuration. These Messages consist of three bytes as shown in FIG. 3B. The first ^yte contains the central control unit address bits, A^. and A-^, ;!the message mode indicator bit K, the command execute enable bit ;? and four of the command bits, Cq. Cp C2 and C^. The next 370 bytes contain the remainder of the command bits, through Gjj. The central control unit address bits are used to insure that only the proper central control unit responds to a command message, particularly when using the party line arrangement of FIG. 2. The message mode bit K is used to delineate between I!

command and ,interrogation messages from data acquisition computer

A GEN P02

CH7c£

5710774

4. When the message from data acquisition computer 4 is a conraand, bit P is interpreted as a command execute enable bit. Xf bit P is logic 1, the command message is executed while if bit P is logic 0, the command message is not executed, thereby enabling data acquisition computer 4 to obtain the configuration status of central control unit 5. FIG. 3B illustrates a message wherein bit K is logic 0, and bit P is logic 1; therefore, the message is a command to central control unit 5 and the command bits, Cq through C^. control the central control unit transmitter power and distribution feeder selection relays !according to exemplary Table I.

TABLE

&amp;#906; Command Action :i j Cq Transmitter Power On &amp;#1503; Transmitter Power Off

<td> ! «2</td><td> Feeder</td><td> 1</td><td> Phase</td><td> A Selector Relay</td><td> On</td>

<td> I ^C3</td><td> Feeder</td><td> 1</td><td> Phase</td><td> A Selector Relay</td><td> Off</td>

<td> ‘4</td><td> Feeder</td><td> 1</td><td> Phase</td><td colspan="2"> B Selector Relay.On</td>

<td>^C5</td><td> Feeder</td><td> 1</td><td> Phase</td><td> B Selector Relay</td><td> Off</td>

<td>^C6</td><td> Feeder</td><td> 1</td><td> Phase</td><td> C Selector Relay</td><td> On</td>

<td>^C7</td><td> Feeder</td><td> 1</td><td> Phase</td><td> C Selector Relay</td><td> Off</td>

<td>^C8</td><td> Feeder</td><td> 2</td><td> Phase</td><td> A Selector Relay</td><td> On .</td>

<td>^c9</td><td> Feeder</td><td> 2</td><td> Phase</td><td> A Selector Relay</td><td> Off</td>

<td>^C10</td><td> Feeder</td><td> 2</td><td> Phase</td><td> B Selector Relay</td><td> On</td>

<td>^C11</td><td> Feeder</td><td> 2</td><td> Phase</td><td> B Selector Relay</td><td> Off</td>

<td>^C12</td><td> Feeder</td><td> 2</td><td> Phase</td><td> C Selector Relay</td><td> On</td>

<td>^C13</td><td> Feeder</td><td> 2</td><td> Phase</td><td> C Selector Relay</td><td> Off</td>

<td> I ^c14</td><td> Feeder</td><td> 3</td><td> Phase</td><td> A Selector Relay</td><td> On</td>

<td> II ? . ^C15</td><td> Feeder</td><td> 3</td><td> Phase</td><td> A Selector Relay</td><td> Off</td>

<td>^C16</td><td> Feedbr</td><td> 3</td><td> Phase</td><td> B Selector Relay</td><td> On</td>

<td> ' ^C17</td><td> Feeder</td><td> 3</td><td> Phase</td><td> B Selector Relay</td><td> Off</td>

<td></td><td> Feeder</td><td> 3</td><td> Phase</td><td> C Selector Relay</td><td> On</td>

<td>^C19</td><td> Feeder</td><td> 3</td><td> Phase</td><td> C Selector Relay</td><td> Off</td>

.i ll. &amp;#1509; &amp;#1524;Λ.&amp;#973;.;

A GEM P02I

CliM ' length, with the central control indicator bits appearing at the

When the party line arrangement of FIG. 2 is used»it is advantageous to increase the number of central control unit !!address bits to allow more central control units to be used. | i ' ' &amp;#1497;' &amp;#1497; . !'

[The command bit field can be decreased correspondingly since the ! &amp;#906; ' ’ ' j !central control unit will only be switching among the three J phases of a single distribution feeder.

After accomplishing the desired command central control I unit 5 transmits its status to data acquisition computer 4 using &amp;#1503; j the 8&amp;#1470;byte message shown in FIG. 3C. Byte 1 contains status in- ; dicator bits 3θ through Sy, byte 2 contains status indicator I bits Sg through Sjj, the central control unit address bits A^6 and ;A.&amp;#1491;, the message‘mode indicator bit K,which is logic 0, and jl 1/ ' !command execute bit P, and byte 3 contains the remaining status !indicator bits S12 through S19. Bytes 4 and 7 repeat byte 1, 1bytes 5 and 8 repeat byte 2, and byte 6 repeats byte 3. Thus.

the message is eight bytes in !'unit address and message mode !!end of the eighth byte. This J [command reply message to data ![in byte count with that of an ;!discussed shortly.

i Data acquisition computer 4 sends the three-byte message 'shown in FIG. 3D to central control unit 5 to initiate an i ' !interrogation cycle. The first byte contains the central control [unit address bits A.^ and A^y, the message mode indicator bit K, !’which is a logic 1 denoting an interrogation message, bit P which controls the bit clock phase during an interrogation cycle, *and the transponder function code bits, Γθ through F^. Hie next ';two bytes contain the meter module, control module or hot water ;identification code bits, Αθ through A15. The function code bits [determine the control action and reply data rata. Table II below 'provides an- exemplary meaning of each bit.

&amp;#1470;15&amp;#1470; makes central control unit 5 acquisition computer 4 compatible &amp;#943; interrogation reply which will be j

A GEN.P021I

5710774

<td></td><td> TABLE</td><td colspan="3"> ,11</td><td></td>

<td> Interrogation Type</td><td> Function B</td><td> it ..₈</td><td> Stats</td><td> Control Action</td><td></td>

<td> Meter</td><td>^Fo</td><td></td><td> .1</td><td> Reply at 30 Baud</td><td></td>

<td> Meter</td><td>^F0</td><td></td><td> 0</td><td> Reply at 15 Baud</td><td></td>

<td> Meter</td><td>^F1</td><td></td><td> 1</td><td> Read Electric Meter</td><td></td>

<td> Meter</td><td>^F2</td><td></td><td> 1</td><td> Read Gas Meter</td><td></td>

<td> Meter</td><td>^F3</td><td></td><td> 1</td><td> Read Water Meter</td><td></td>

<td> Hot Water</td><td>^Fo</td><td></td><td> 1</td><td> Time out at 30 Baud</td><td></td>

<td> Hot Water</td><td>^Fo</td><td></td><td> 0</td><td> Time Out at 15 Baud</td><td></td>

<td> Hot. Water</td><td>^F1</td><td></td><td> 1</td><td> Hot Water Heater On</td><td></td>

<td> Hot Water</td><td>^F1</td><td></td><td> 0</td><td colspan="2"> Hot Water Heater Off</td>

<td> Hot Water</td><td>^F2</td><td></td><td> 1</td><td colspan="2"> Start Peak Demand Meter</td>

<td> Hot Water</td><td>^F2</td><td></td><td> 0</td><td colspan="2"> Stop Peak Demand Meter</td>

<td> Control</td><td>^Fo</td><td></td><td> 1</td><td> Reply at 30 Baud</td><td></td>

<td> Control</td><td>^Fo</td><td></td><td> 0</td><td> Reply at 15 Baud</td><td></td>

<td> Control</td><td>^F1</td><td></td><td> 1</td><td> Connect Capacitor</td><td></td>

<td> Control</td><td>^F1</td><td></td><td> 0</td><td colspan="2"> Disconnect Capacitor</td>

<td> ./.-.-./ Central</td><td> control unit 5</td><td colspan="2"> sends the</td><td> message shown in</td><td></td>

FIG. 3E to^eter modules 11A through IIP, or control modules SA through 9N,. at 30 baud. The first eight bits are a fixed synchronization code which the transponders such as 12, detect and use to synchronize their data decoding. The next four bits are the function code, Ρθ through Ρθ and the last sixteen bits are the meter module identification code, Αθ through A.^. The designated meter or control module replies at the rate indicated by function code bit Εθ with the message format of FIG. 3F.

&amp;#943; Synchronization bits are not required since this message starts i immediately after the completion of the central control unit 5 &amp;#1503; message, shown in FIG. 3E. The reply message repeats the four i! function code bits, Ρθ through F^, and the sixteen module identification, code bits, Αθ through A.^, and includes twenty bits of meter data or control status, Μθ through M^g, ant’ twenty

&amp;#1524;16*

A GEN P02:bits of the one's complement of this data. Mn through M,n. Other C1T7cE-----! 0 I9

&amp;#906;λ)Π$77Δ error detecting or correcting codes may be used for the. data fields Μθ through and Μθ through M^g without departing from the principles of the invention. The function coda and module

Identification code bits are repeated to verify that the central control unit message of FIG, 3F was correctly received by the desired module while the meter or status data is repeated for transmission error detection since data accuracy 18 of the utmost importance. '

Central control unit 5 then transmits the module reply to data acquisition computer 4 as eight bytes of data with the central control unit address bits, A^g and Ajj, message mode indicator bit K, which is logic 1 for this message and clocjk phase ibit P added to the end of the message, as shown in FIG. 3G. When .the party line arrangement of FIG. 2 is used, it is advantageous to :increase the number of central control unit address bits. The .number of nodule identification code bits can be correspondingly :reduced since the number of meter and control modules each central

I 'control unit will have to interrogate will be reduced in proportion !to the quantity of central control units that are used.

With reference to FIG. 4, the basic timing signal of

I !the central control unit 5 is the nominal 120 volt, 60-Hz power :line frequency obtained from the distribution feeder such as three • ^hase feeder 21, via transformer 34 and line 62 or relay contacts !63, 63' or 63 and line 61. Initially relay contacts 63, 63'

I ' ;!nd 63 are open and timing control 47 utilizes the nominal 60-Hz power line frequency on line 62 to derive the 285 baud clock for pommunieating with data acquisition computer 4 and other clock -i ' ' and timing signals that will become apparent as the invention is further described. Central control unit 5 interfaces with modem

35, which may be a Bell System 103A data set, for communication with data acquisition computer 4 over 285 baud data link 20. The | &amp;#1470;17A GEN Ρ02&amp;#943; digital data received by modem 35. from data acquisition computer' Cil/cE !] , , . i

5714 ! 0/74&amp;#1470; is sent to data receiver 36, which may be part of asynchronous ;

i data interface THS 6011 by Texas Instruments, which strips out the 8 data bits from the 11-bit byte of FIG. 3A and signals timing !

control 47, via line 66, that a byte has been received. Timing j ; control 47 issues a signal via line 70 that loads the data from j data receiver 36 into ,input register 37 and a reset signal to data receiver 36 via line 65. After timing. control 47 counts three signals from line 66, it interrogates the first five bits of input register 37, via line 69. If the central control unit

I address bits A16 and A17 are correct, message mode indicator bit K ! indicates the contents of input register 37 are a command and 1 bit P indicates the command should be executed,timing control 47 '! issues a signal, via line 78, that loads the command bits CQ i through C1Q of input register 37 into command register 43, which enables the commanded relay driver, part of 46, which in turn energises the commanded relay coil and indicator, part of 45, i thereby closing relay contacts 63, 63' or 63, which automatically switches the 60-nz power line frequency source used by timing control 47 from line 62 to line 61. The status indicators, part ! of 45, send a signal to the status register 44, via line 82, indicating which relay is energized. Bit P is also loaded into status register 44 via line 68. Timing control 47 waits a !

preset interval after strobing the data into command register ) for relay switching and status indication to take place and ) then loads the contents of status register 44 into data transmitter 55 via line 83, using shift mode, shift clock and )j transmit data control signals on lines 81, 99 and 85, respectively. 'I Data transmitter 55 which may be part of asynchronous data ii interface TMS 6011 by Texas Instruments, inserts the start and !! stop bits to form the 11-bit byte, shown in FIG. 3A, which is j then sent to data acquisition computer 4 via modem 35 and data

18A GFN P02Uink 20. If bit P indicates command execution should not take ®Texi

5/TO774 place, command bits Cq through of input register 37 are not ! loaded into command register 43 and the command cycle times out !.1

l.

as previously explained, thereby transmitting the pre-existing configuration of central control unit 5 to data acquisition. ' I i computer 4.I

If the message mode indicator bit K is logic 1, indicating the contents of input register 37 are interrogation data, timing !

I control 47 loads the preset synchronization code into sync code

Ιθ . register 33 using a control signal on line 72, selects the correct clock phase using bit P, and then shifts the contents of sync

&amp;#906;code register 38 and input register 37 to modulator 39 using !&amp;#1497; the shift clock on line 70. The input to modulator 39 modulates :!a carrier received from timing control 47 on line 73. The output of modulator 39 is amplified by power amplifier 40, which oay be a Bogen model NTB-250, and is impressed on 120V, 60-Hz line 61 by ;coupling network 41, which is a series capacitor and inductor &amp;#1523;! tuned to resonate with the impedance of line 61 at the communication .carrier frequency. The transmitted signal then flows through !relay contacts 63, 63', or 63” and distribution trans former 34 !to distribution feeder 21 and then to all the meter and control . ' I modules. 11 and 9, respectively, attached to the distribution .feeder 21. During this interval modulator 39 is enabled, and ^receive switch 51 is inhibited by the transmit enable signal !from timing control 47 on line 75.

&amp;#1503; At the completion of the central control unit 5 &amp;#912; :itransmission period, modulator 39 is inhibited, and receive switch '51 is enabled,by the transrait enable signal from timing control 47 on line 75. The meter or control module reply signal on 30 ‘.distribution feeder 21 flows through distribution transformer 34, ;.relay contacts63, 63’ or 63 , line 62, bandpass filter 50, v?hich .may have a Q of 20, receive switch 51,which may be an RCA CD4066A, I &amp;#1470;19I r &amp;#1497;*&amp;#1523;.&amp;#1470;’. &amp;#1497;

A GEN P02 and video amplifier 52,which may be a Fairchild Semiconductor 741 ch7cR !

5/10774 *operational amplifier,to demodulator 53.

! J Demodulator 53 uses a reference frequency and function code bit FQ received from timing control 47 on lines 73 and 91, respectively, to obtain the data contained in the received signal. Timing control 47 uses the meter or control module reply baud rate information contained in function code bit Γθ to determine the baud rate at which data is being received by ;central control unit 5. At the end of each baud interval the !output of demodulator 53 is shifted into output register 54 i by a shift clock on line 89, generated by timing control 47. After the entire reply message is received, the first eight bits of output register 54 are transferred to data transmitter p

55, and the central control unit address bits A16 and Αχ7,message mode indicator bit K and clock phase bit P are loaded into output register 54 by control signals from timing control 47 on 1lines 85.and 95, respectively. Data transmitter 55 inserts the ;start and stop bits to form the 11 bit byte shown m MG. 3A and ;transmits the byte to data acquisition computer 4 at 285 baud, via imodem 35 and data link 20. Timing control 47 continues to snift the data in output register 54 and transfer the data from output !register 54 into .data transmitter 55 until the entire meter or j ]control module reply message contained in output, register 54 ;!is transmitted to data acquisition computer 4.

The central control units, such as 5, and transponders, &amp;#1503; 60-Hz power distribution frequency to clock However, due to the random phasing of the distribution transformers, such as 10A through 10M, the | 160-llz polarity at any transponder may be inverted with respect the 60-Hz polarity at central control unit 5. The phasing the 60-He signal in each transponder can be adjusted at time installation but this is a time consuming and, therefore,

&amp;#1524;20&amp;#1524; ! such as 12, both use th !their timing control circuits.

to&amp;#1523; ;of of

I

A GEN P02 'prohibitively expensive process to be performed at each transponder

CiT/cE !'

5/15774 iThe preferred method is to install each transponder without adjustment and then use the data acquisition computers, such as 4, to interrogate each transponder while adjusting the 60.-H3 polarity at central control unit 5. When the 60-Jlz polarity j ; . &amp;#1523;. ' I I used for interrogation timing by central control unit 5 is !

I identical with that at the transponder being interrogated, the I transponder will reply correctly. In this manner the correct | 60-Hz polarity to be used for interrogating each transponder can be fo«nd and stored in the master data files at central billing computer 1. The correct 60-Hz polarity is then transmitted to each data acquisition computer, such as 4, as bit P whenever a transponder, such as 12, is to be interrogated.

J With reference to FIG. 5, there is shown a block ;diagram illustrating the logical arrangement of transponder 12. &amp;#1523;The basic timing signal of transponder 12 is the nominal 120 volt, I 60-Hz power distribution frequency obtained from distribution !transformer secondary, line 24. Timing control 110 utilizes the !nominal 60-Hz power distribution frequency on.line 24 to derive &amp;#943; the various clocks and control signals needed to control the flow iof data in transponder 12. The signal from central control unit i 5 flows through bandpass filter 101 wnich. has a Q of about 5, receive switch 102, which may be RCA CD4066A, video amplifier

103, which may be a Fairchild Semiconductor 741 operational (

&amp;#1503; i amplifier, to demodulator 104. Demodulator 104 uses the reference I frequency from timing control 110, on line 119, to obtain the &amp;#1503; : data contained in the signal received from central control unit

5. The demodulator output on line 135 is used by timing &amp;#1503; ! control 110 to control the phase of the reference frequency on ! line 119.

I At the end of each data interval timing control 110 uses the shift clock on line 118 to shift the received data bit from ! -21:N P02 £-3/74 '&amp;#1497;''' &amp;#943; demodulator 104 into data register 106 via data control 105. j j. : 1

At the beginning of each bit period the first eight bits of data j .register 106, carried by part of line 132, are compared to the . preset synchronization code by synchronization code comparator 111;

When these are identical, a signal is sent to timing control 110, : ;via line 121, which starts a bit counter. After twenty more bits i ;have been received and shifted into data register 106, the!' !first sixteen bits of data register, carried by part of line 132, .!

i - '!

:are compared to the preset meter module address and hot water ! !control address by comparators 113 and 112, respectively, the last

: &amp;#1523;1 !:four bits of data register 106, carried by part of line 132, i are transferred to function code register 114, and receive switch ;102 is inhibited. The shift clock on line 113 assumes the frequency indicated by function code bit Γθ on line 124.

&amp;#943; If meter module address comparator 113 detects a match, :function decoder 115, modulator 107 and the meter data input to data control 105 are all enabled via line 126. The meter module !address and function code contents of data register 106 are shifted to distribution transformer secondary 24 via line 128, &amp;#943;.

!modulator 107, transmitter 108 and coupling network 109, while !the contents of the meter encoder that is enabled by function ;decoder 115, such as the electric meter encoder via line 26, :!are shifted into data register 106 via line 129 and data control !i !105. After the twenty meter data bits, are shifted into data ;register 106, its contents are recirculated via line 133 ;and data control 105, which logically inverts the meter data.

Data recirculation through data control 105 is enabled by timing !control 110 enable signal on line 120. After the 60-bit reply !!message has been transmitted, receive switch 102 is enabled via ii &amp;#1523; ;line 117, and sync code and meter module address comparators, 1111 and 113, respectively, are reset via line 123, thereby ;inhibiting modulator 107, meter data inputs to data control 105 -22A GEN P02)and resetting function decoder 115. Transponder 12 then resumes WcE--!

TtT/~8774 !searching the received data for a synchronisation code match. I I . I &amp;#1497; &amp;#1470; &amp;#1503; If hot water control address comparator 112 detects a j ! match after a synchronization code match is detected, the function .: code bits carried by line 127 are strobed into hot water control ) 116, thereby turning the hot water heater on via line 134 or off via line 134', or controlling the peak demand meter via lines 140 and 140*. Modulator 107 is not enabled since no reply message is to be transmitted. After a period of time equal to that needed for a reply at the rate indicated by function code bit Fq on line 124, receive switch 102 is enabled via line 117, and synchronization code .comparator 111 is reset via line 123. Hot water control 116 )is not reset, thereby enabling the control function to be maintained )until a further hot water control instruction is received. Trans!ponder 12 then resumes searching the received data for a synchronization code match.

If neither a meter module address nor hot water control address is detected by comparators 113 and 112, respectively, after

1&amp;#1523; )a synchronization code match is detected by comparator 111, no 20 !control action is initiated nor reply transmitted. Timing control :110 waits a period of time equal to that needed for a reply at the rate indicated by function code bit Ρθ on line 124, then enables )receive switch 102, via line 117, and resets synchronization code ) )comparator 111 via line 123.

An exemplary electric meter 15 and encoder 13 are shown in FIG. 6. The electric watt-hour meter 15, such as General Electric Co. Model ?!0. 150S, drives revolution contactor, such :as General Electric Co. Model R12/125, which drives relay 176, :such as General Electric Co. Model 731X2G6, whose, contacts'close 30 ;for a short period of time after each 100 watt-hours of consumption jias been logged by watt-hour meter 175. The relay contact closure &amp;#943;! u * . ' )increments counter 177, which may consist of 4 binary coded

I &amp;#1497; 'Π

A GEN P02 decimal counter stages, such as Hayden Switch Model 4241010&amp;#1470;. The WdT :!!

19/5774 parallel outputs of counter 177 are connected to the parallel inputs ~ 1' iiof shift register 178, which may consist of parallel input serial I .

jbutput shift register stages, such as R.CA CD4034A. When a meter I transponder xs not being interrogated the meter select signal, line

I

26, inhibits the A bus and serial operation of shift register 178,1 thereby allowing the parallel outputs of counter 177 to continuously update the contents of shift register 178. During a meter trans- | jponder interrogation the meter select signal, line 26, enables the 10 ^A bus and serial mode of operation, thereby allowing the contents !i ;of shift register 178 to be shifted to meter transponder 12, via

&amp;#1503; jline 129, in a serial manner in response to the shift clock trailsitions on line 118. It is preferred that encoder 13 include a non20 !volatile memory element, such as Hayden Switch Model 42410-10, to !avoid the loss of meter data in the event of power failure. Furthermore, while the Hayden Switch Model 42410-10 has 4 BCD stages it is obvious that a fifth stage can be added; that is preferably, !since many utilities are up-grading their meter equipment to 5-dial meters.

When .peak demand metering is desired, another meter en!coder, such ns 13', can be connected to the same power meter with

&amp;#1503; !the signal from watt-hour meter 15 connected to meter encoder 13': .i ’ ' &amp;#1523;!through relav 32 which is controlled by transponder 12. When it. is j! ' '1 ]desired to log power consumption on the peak demand meter encoder; relay 32 contacts are commanded closed via line 140 from trans- ! Ij /Wj&amp;#1470; kk /)££ *7//^/!

!ponder 12. Whenrit-&amp;#1470;ie-dee4^d-to-40g-pwer_CQpsumpiriQ1x--0n-thB&amp;#1470;&amp;#1470;p&amp;#1470;eak &amp;#1503; duman d tie t&amp;#1470;ar -encoder ;&amp;#1470;~rgiay—32—eentiie^e—are-eona-jantled—elosed-'Vla. !

When it is desired to stop logging !&amp;#1523; . &amp;#1497;I ’power consumption on the peak demand meter relay 32,contacts are ;commanded open via line 140' from transponder 12.

!! FIG, 7 illustrates the typical noise that is present on a power distribution feeder, such as 21 of FIG. 1, and shows that

A GEN P02

CH/ck WIi774 ;the amplitude envelope of the 60&amp;#1470;Hz power distribution frequency

I&amp;#1523;'. ritii $1 ;harmonics is about 1000 times larger' thaxi random noise between 1 ’

and 10 kHz. This would suggest a communication carrier frequency selection in the low noise region above 10 kHz.

j . However, most distribution feeders have power factor {correction capacitors connected to them to enable the utility to 1 !meet economic and quality&amp;#1470;of&amp;#1470;service constraints. Furthermore, the distribution feeders have series inductance and stray capaci&amp;#943;tance to ground, the exact values of which depend on distribution : i .

'!feeder construction and length. Therefore, distribution feeders .

have a low pass transmission characteristic aA GEN P02.

Cii/ck W/74 as a result of these reactive components. A network analysis, !confirmed by distribution feeder signal transmission measurements, !shows the half-power cutoff frequency to lie at about 1 kHz when the power factor correction capacitors are connected to a typical distribution feeder; this is illustrated in FIG. 8A. Wien the power factor correction capacitors are disconnected from the distribution feeder, the half-power cutoff frequency is determined by the distribution feeder series inductance and stray capacitance to ground and lies between 10 and 20 kHz as illustrated in FIG. 8B.

! Furthermore, a remote meter reading and control system will consist j of a large quantity of meter and control modules located through&amp;#1507; out a power utility's franchised service area, and it is imi ' !perative that these units be low cost. Economic factors preclude '!the use of high-power, high-frequency transistors and highly !selective filters. Therefore, it is advantageous to select a conanuniqation carrier frequency in the range between 5 and !10 kHz so the system will operate in the region of low harmonic !noise and low signal transmission loss, and to utilize a technique !!

.! for communicating between central control unit 5 and meter module ' 11 or control module 9 that will discriminate against the 60-Hz i

!power distribution frequency harmonics.

! In order to operate the system in range between 5 and ;

i 10 kHz, it is necessary to overcome the deleterious effects of

I the power factor correction capacitors. The preferred method.

is to insert a capacitor isolation network in series with each i ' ! power factor correction capacitor as shown in FIG. 9A, or in parallel with each power factor correction capacitor as show in '1 ' .

| FIG. 9B. With reference to FIG. 9A. the capacitor isolation

I network, consisting of inductor 32 and capacitor 33, is inserted

I

3° !! in series with power factor correction capacitor 23'. Inductor and capacitor 33 are tuned to anti-resonance at the conmunication carrier frequency. Line 21A' is the high voltage distribution &amp;#1470;25A CEH P02 feeder, and line 21Λ is the distribution feeder neutral.

CiI7ci;

57W.4

I With reference to FIG. 9B, the capacitor isolation .

network, consisting of inductor 32' and capacitor 33', is

I. !

!installed in parallel with power factor correction capacitor 23. ; !^inductor 32' is tuned to anti-resonance with the parallel combina-! Ifcion of capacitors 33' and 23 at the communication carrier fre- !

;quency.

An alternative method of overcoming the effects of power factor correction capacitors on signal transmission consists of j !signalling the control modules, such as 9A, to disconnect the ' i &amp;#1497; ' ’ !capacitor.

i!

! An advantageous communication technique is phase shift keying since a unique choice of parameters enables this method to act as a highly-selective filter and discriminate against the 60-Hz power distribution frequency harmonics. This technique j;is incorporated in the preferred embodiment, wherein the :received communication carrier signal is demodulated by a phase !detector whose output is integrated for a period of time T !corresponding to one baud and then reset.

!! The integrator output E at the end of the integration period T represents the received energy detected by the system I&amp;#1524; !!during the period T and can be written as:

Eo 1.nfi'1 dt (1> .fo where the demodulator reference signal ercf(t) can *De written as:

eref(t) “ Ar ’&amp;#1470; ain ωχ&amp;#971; &amp;#1523;The phase detector input e^^t) consists of the communication !carrier signal each power distribution frequency harmoxiic

e. (t) and random noise er1(t) of uniform energy spectral density np n

Kq/2 watts per Hz where each of these can be written as:

A GEN P02 ClTTck 57W74 (2) e_(t) - A sin (ω t+A) V V V k&amp;#1523; &lt;&amp;#1524; &amp;#1470; ^hp“

The demodulator reference frequency is identical to the communication carrier,so the detected energy for this signal is &amp;#1493;! written as :

A AT ’

E » . cos &amp;#974; (4) oc z c

I By phase locking the reference frequency to the received com:munication carrier signal the phase difference between the two !signals {$c can be made arbitrarily small, and the detected energy &amp;#1523;can be made to approach the maximum value of Α^Α^&amp;#912;/2. The de10 .gy in response to a power distribution frequency ! tected :harmonic e. it) can be written as:

:! np.

zhp &amp;#1497; onp 4

Β1η[(ωΓ-%ρ)Τ - + sin ^p sin[)T + ^hpl - sin 6 *‘A/ (5) where « 2Π(60P) and P is an integer defining the power I distribution frequency harmonic under consideration. In the ^preferred embodiment the communication carrier frequency 18 )selected to be an odd multiple of 30-Hz, half the power distri)bution frequency. The demodulator reference frequency can then Lr,ritr.r'.

D6tV’tfxcccn S3.

j “r “ 2n(2m 46) . 30(1 &amp;#1470;)

A GEN Pi Ch/ck 5713/74 ; where m is an integer defining the odd multiple of 30-Hz used fir data communicative, !t 1b also advantageous to select baud rates Jj 1 . ’ that are sub-multiples of the power distribution frequency, such ,as 30 or 15-baud, corresponding to integration periods T of 1/30 !or 1/15 seconds, respectively. For this unique selection of iparameters the detected energy Β0^ρ Is exactly equal to zero for jjany value of P and 0hpl thereby discriminating against the !60-Hz power distribution frequency harmonics. If a 60-baud rate i I is selected, corresponding to an second, the detected energy EQ^p integration period T of 1/60 can be written as:

>-l sin ih Eohp 3&#1470; &#1470;!SRZSTr&#1470; (7) on the communication carrier acts as frequency

60-Hz harmonics to the extent eac the communication carrier’&amp;#1470;, i &amp;#1524;For this case the phase detector-integrator demodulator &amp;#943; ;a bandpass filter centered (discriminating against the (harmonic'is separated from

2P is greater than 2m+l, and can totally discriminate against a harmonic if £-&amp;#1524;p is an integral multiple of' H radians.

( With respect to the random noise. en(t) the integrator ;!acts as a low-pass filter and discrimnates against the random noise components that are outside the signal bandwidth. Therefore, the average detected power due to random noise can be written as:

P on Eon

T

AN r 0

&amp;#1470;&amp;#1494;&amp;#1512; (8) ratio at the integrator output .for data ;;The signal-to-noise !:rates .that are &amp;#1470;&amp;#1470;sub&amp;#1470;multiples ;of 60-baud, such as 30 or 15-baud, is .

]obtained by comparing the signal power to noise power and can be written as:1

AT cos rf

SilR « —-v----&amp;#1470; %

(9) aA GEN P02

57W74 ;which increases as the baud rate decreases, thereby decreasing the probability of bit error. For a 60-baud data rate the 60&amp;#1470; Hz harmonic noise power is much larger than the random noise power and the signal to noise ratio can be written as:

SNR &amp;#1524;

Afi cos dc *&amp;#1470;*u

<td> 1 - .</td><td> » י 2P 1^2־</td><td> 2 </td>

<td></td><td></td><td> a</td>

(10) where P&amp;#1524; and PT are defined by the upper and lower cutoff u 14 frequencies of the frequency selective, filter that precedes the demodulator.

While expression 10 is smaller than expression 9, a 60-baud data rate is advantageous to use in situations where ;a 60-baud data throughput is desired and the resulting bit |l error probabilities are acceptable.

The odd harmonics of the power distribution frequency have been measured to be 10 to 100 times larger in amplitude than the even harmonics, thus, another advantageous selection of ii ,!communication carrier frequency is an even harmonic of the power distribution frequency. The demodulator reference frequency 1I. ' 1 &amp;#1523; :can then be written as:

j wr * 2H(2Q)60 (11) j !i i ,where Q is an integer defining the even multiple of 60-Hz used for lldata communication. The detected energy in response to the

[!communication carrier is identical with expression 4. The power !distribution frequency.harmonic at the communication carrier ;frequency can be written as:

! W« &#1470;41 &#1470; sln (&#1524;,r^hc’ (l2> ;and the detected energy in response to this harmonic can be Written as:

i!

' ‘ ' A AT «&#1470;he ‘ .4s&#1470; &#1470;*he <&#1524;>

- .

A GEN P02iThe detected energy E &amp;#1524;&amp;#1497; in response to any other harmonic of the CH7cTi ] onp

5/10774 power distribution frequency is given by expression (6) and is exactly equal to zero for any value of P and thereby discriminating against these harmonics. Since the signal power r' ' .

of the power distribution harmonic at the communication carrier frequency is much larger than the random noise power, the signal to noise ratio can be written as:

(14)

A cos d &amp;#1470;.l“™&amp;#1470;. « SNR he005 **he* and is independent of baud rate. Expression 14 may be smaller then expression }#, thereby yielding a higher probability of bit error. However, the set of parameters defined by expressions 11 through 14 are advantageous to use in situations where a 60 baud data throughput is desired and the resulting bit error probabilities are acceptable.

4 It is also within the principles of the invention to use other camunication techniques such as frequency shift keying or arrplitude modulation.

In the preferred embodiment of the invention central control unit 5 transmits data to meter module 11 and control module 9 at 30 baud, and the modules reply at 30 or 15 baud. However, in situations where higher bit error probabilities are acceptable and higher data throughputs are desired, it 18 advantageous to have central control unit 5 transmit data to meter module 11 and control module 9 at 60 baud, and the modules reply at 60, 30 or 15 baud. For this situation central control unit 5 transmitter output power may have to be increased to obtain acceptable error rates and an odd harmonic of 30 Hz, defined by expression 6, should be used for the communication carrier frequency, thereby :permitting central control unit 5 demodulator to discriminate !against the power frequency harmonics when the modules are !replying at'30 or 15 baud.

&amp;#1524;30Α (5?&amp;#943; Ρ02 CH / ck T37S774 ! Measurements on power distribution feeders have shown the power line frequency has variations as large as 3% from the nominal $0&amp;#1470;Hz. Therefore, it is advantageous to derive the transmitter comtfiunication carrier, demodulation reference carrier and data bit 1 :. &amp;#1470; I timing from the power distribution frequency so the previously de-: &amp;#1470;ined relationships between parameters remain constant and the de-I modulation results remain valid. Measurements on power distribution feeders have also shown the communication carrier phase can vary | tore than 50° in a six minute period. Therefore, it is advantageous |o phase lock the various demodulator reference oscillators to a j signal obtained from the unit that is transmitting. &amp;#943; il The preferred embodiment incorporates the principles developed above to eliminate the need for costly items, such as highly selective filters and high power transmitters in the transbonders. Referring again to FIG. 1, between interrogations of meter &amp;#912; .

module 11 or control module 9 central control unit 5 transmits a pilot tone, an unmodulated communication carrier, with sufficient Signal strength to be detected by all transponders 12 connected to distribution feeder 21 being driven by.the central control unit 5 transmitter, The transponders 12 connected to distribution feeder

&amp;#1524; &amp;#1497;&amp;#1497;&amp;#1470;

2;1 receive the pilot tone and phase lock their reference carrier oscillators to this central control unit 5 signal, thereby making ! the previously defined phase angle 6 arbitrarily, small. After a ' i , . c j period of time, sufficient for all transponder 12 reference oscilXators to have achieved phase lock, central control unit 5 transmits [ data to transponders 12 at a fixed rate of 30 baud by phase-shift modulating the communication carrier. It i© advantageous to use a modulation deviation of +90 degress to represent a logic one and -90 degrees to represent a logic zero as this deviation provides the 1 least probability of bit error for a given signal-to-nolse ratio. The transponder 12 that is interrogated replies at the instructed data rate, such as 30 or 15 bits per second. Transponders 12 do no&amp;#1523;: transmit 0 pilot tone to central control unit 5, which instead demodulates the transponder transmission by using four parallel phase sensitive demodulators that liave their reference carriers separated in p!1ase

A GEN POP. CH/ck 5/10774

Ly 45 degrees. After receiving the first bit of transmission from transponder 12, central control unit 5 scans the four !demodulator outputs and selects the demodulator output with the maximum absolute amplitude, and therefore, minimum phase angle .J . J ;separation «5. from transponder 12 conanunication carrier. The c demodulator polarity is obtained by comparing the received bit

I polarity with the expected polarity of the first bit, which is function code bit FQ. This demodulator polarity is used for 'detection of the remainder of the transponder transmission.

The ability to use different transponder bit.rates !permits the system to use low-power transponder transmitters and automatically adapt the . transponder transmission cotmmaiica10 tion channel to varying signal-to-noise ratios while obtaining maximum system data throughput.

; Exemplary embodiments of central control unit modulator

39, demodulator 53 and timing control’47 are shown in FIG. 10 jjusing logic elements of the RCA CD4000A series with key timing ;&amp;#1523;relationships presented in FIGS, 11 through 16. Tae central ;control unit communication and reference carriers, and a !synchronous data interface clock are developed in a phase-lock loop using the. 60-Hz power distribution frequency as the source via the utility bus, line 62, or the switched bus, line 61. The sinusoidal signals on lines 61 and 52 are squared using zero !crossing detectors 200 and 201 which are National Semiconductor bll39 voltage comparators. If a signal is present at the output bf zero-crossing detector 201, such as when relay contact 63, '!63' or 63 is closed, retriggerable monos table multivibrator 202, which is a CD4047A, is continuously triggered enabling NAND !*gate 204 and ,inhibiting HAND gate 204', thereby selecting the lj .

30 ‘switched bus signal as the timing reference for the central !!control unit. If no signal is present on the switched bus, line 61t such as when relay contacts 63. 63', and 63'' are all -32A GEN P02 Cii7ciZ 57W74 open, retriggerable monostable multivibrator 202. remains in its i stable state, inhibiting NAUD gate 204 and enabling HAND gate 204' thereby selecting the utility bus signal as the timing reference for the central control unit. The basic 30-Hz baud rate clock is obtained from the 60-Hz output of OR gate 205 via exclusive OR j gate 239 and divider 208. The polarity of the 60-Hz signal used ! to clock divider 208 Is selected by clock phase bit P on line 69'via flip-flop 219 and exclusive OR gate 239.

The communication and reference carriers and asynchronous data interface clock are developed in a phase-locked ! loop oscillator circuit consisting of phase-locked :scillator 206, !which is a CD 4046A, dividers 207, 207' and 207, which are )CD4029A,and various HAND gates, shift register 210 which is a |cD4015A,and inverter 209. The output frequency of phase-locked ;oscillator 206 is 50,160-Hz, which is eight times 6270-Hz, The 50,160-Hz signal is divided down in dividers 207, 207' and 207, in this 4 and 9, respectively. The. output frequency )an odd multiple of 30-Hz.

:by the appropriate factors 'instance the division is by 11, of divider 207, is 4560-Hz, which is sixteen times the 285 baud 20 !data transmission rate between central control unit 5 and data I !acquisition computer 4, while the output of divider 203 is the &amp;#1523;data transmission rate, 285-Hz. This method of developing the &amp;#1503; asynchronous data interface clock avoids the necessity of using a crystal stabilized oscillator in each central control unit. The output of divider 207 is fed back to phase-locked oscillator 206 for comparlsion with the selected 60-Hz power distribution !frequency signal from OR gate 205, thereby closing the phase-locked

&amp;#1497; 1( loop. The output 01 phase-locked oscillator 206 clocks shift ;register 210 to develop four 6270-Hz signals separated in phase :1 . ,

Jby 45 degrees. The timing relationship between the phase-locted loop oscillator output and the four ^hift register output signals is Illustrated in FIGS. 11A through HE, which shows that the

&amp;#1524;33&amp;#1524;

I .vI '

A GEN P02 shift register third stage output, FIG. 11D, lags the first stage Wck i cJ

5/14774 output, FIG. 11B, by 90 degrees. Therefore, the third stage !output is used for the unmodulated communication carrier, and the !first stage output or its inverse t .

[carrier.

is used for the modulated i| . As previously mentioned, after a byte of data £8 received !! ' !

)by data receiver 36, it sets a Data Ready flag, FIG. 12B, to the timing control 47 via line 66. The signal on line 66 is clocked !into shift register 211, which consists of CD4013A flip-flops, by the asynchronous data interface clock on line 64, shown in [*FIG. 12A. The first clock transition on line 64 after the Data ;i )[Ready flag is set changes the state of the first stage of shift register 211, FIG. 12C, which triggers monostable multivibrator ]214,which is a CD4047A, whose output, FIG. 121, was resetting ;shift register 212, which consists of CD4013Aflip-flops, to the 100 state as shown in FIGS. 12Ξ, 12F,&amp;#1523; and 12G. Before the next [clock transition on line 64 the output of the first stage of shift register 212, FIG. 12E enables the A bus of the first eight bits of input register 37 via line 71, thereby transferring [data from data receiver 36 to input register 37.

) The second clock transition on line 64 after the Data &amp;#1523;Ready flag is set changes the state of the second stage of shift il register 211, FIG. 12D, which resets the Data Ready flag via [inverter 213 and line 65, and clocks shift register 212 to the !010 state, thereby clocking the bit P on line 69' into flip-flop

219, which is a GD4013A. The next two clock transitions on line !64 return shift register 211 to its original state, &amp;#1523;fhe second [byte of data from data receiver 36 is loaded into the second !eight bits of input register 37 by the second Data Ready flag !'and the A bus enable signal from the second stage of shift registe

212 via line 71*, FIG. 12F, and the third data bytG ie loaded j into the third eight bits of input register 37 by the third Data

A GEN P02 Wck 57W74 of

Ready flag and the A bus enable signal from the third stage ^shift register. 212 via line 71, FIG. 12G. After the third {byte is loaded into input register 37, MOR gate 215 output, FIG. 1211, enables HAND gates 217 and 217’, thereby permitting second stage of shift register 211 to issue a cycle-initiate strobe signal, FIG. 121, on either line 220 or 221, depending on contents of the command node control bit on line 69 and central control unit addata dress bits A16.and A17 on line 69’. !

If the central control unit address bits from input , u &amp;#1523;'iL.7'&amp;#1523; :register 37 on line 69' match the preselected central^unit ;!address, decoder 216, which is a CD4051A, enables HAND gates 217 )and 217'. If the mode control bit on line 69 is a logic 1, in1 ( dicating a meter transponder interrogation cycle is desired, NAND gate 217 is enabled, thereby yielding an interrogation cycle !initiate strobe on line 220. If the mode control bit on line 69 is a logic 0, indicating a command cycle is desired, HAND gate 217' is enabled via inverter 213, thereby yielding a command cycle ;initiate strobe on line 221.

J At the end of a preset interval, long enough for dyee &amp;#943; ’ / *7'/*&amp;#1523;,&amp;#1500;&amp;#1488; !data bytes to be received from data acquisition computer /, λ** !monostable multivibrator 214 returns to its stable state, )resetting shift register 212 to the 100 state. Thus, monostable . !multivibrator 214 returns the central control unit to a known state at periodic intervals, thereby overcoming the problems associated with false data loading due to a noisy communication line, such as )10, or Data Ready line 66.

If the mode control bit on line 69 is logic 0, indicatirl!

)a command cycle is desired, the cycle initiate strobe from HAND gate 217’ on line 221, FIG. 13A, triggers monostable multi!vibrator 224, which is a CD4047A.

!bit P, stored in flip-flop 219, is logic 1,AND gate 223 is enabled, and the signal from HAND gate 217' ) -35If the command execute enable on line 221 enables the A bus of command register 43 via line 78, thereby loading the command bits from input register 37 into command register 43. If bit 1; , stored in flip-flop 219, is logic 0, AND gate 223 is inhibited &amp;#1503; I!. &amp;#1523;I :and the contents of input register 37 are not loaded into command , register 43. After a period of about 1 second, monostable!

multivibrator 224 returns to its stable state, FIG. 13B. thereby { clocking flip-flop 225, which is a CD4013A. At the next 285-He| clock transition on line 99, FIG. 13D, flip-flop 226, which { is a CD4013A, changes state, thereby removing the reset level j

&amp;#1470; &amp;#1470; &amp;#1523;

[from counters 227, 227'. and flip-flop 232, enabling the status ; :register A bus outputs and serial mode of operation via line 81, FIG. 13E, and enabling HAND gate 229 via line 233. The command cycle is therefore synchronized to the 285-Hz clock on line 99 by the output of flip-flop 225, FIG. 13C, controlling the state {of flip-flop 226. Counters 227 and 227', which are CD4029A, are !incremented by the 285-Hz clock on line 99, and the outputs of ;counter 227 are sampled by decoder 228, which is a CD4028A. When i . ' counter 227 is in the 0 state, decoder 228 enables AND gate 229, ^thereby sending a transmit strobe, FIG. 13F, to data transmitter i . * !55 via OR gate 230, inverter 231 and line 85. Since the 285-Hz [clock on line 99 is also shifting the contents of status register .44 during this period, the status register contents are trans- ' mitted to data-acquisition computer 3 as eight data bytes. After 1 i the sixty-fourth transition of the 285-Hz clock on line 99,the output of counter 227' clocks flip-flop' 232, whicn is a CD4013A, thereby setting flip-flops 225 and 226, via line 234, FIG. 13C>, !to their original state, which inhibits the status register A bus ! li &#1523; &#1470; !

,outputs and returns the status register to the parallel node of ; 1!operation, all via line 81, FIG. 13E, terminating the command cycle. The signal on line 81 also resets counters 227 and 227' !

[ ' ! and flip-flop 232, while the transmit strobe on line 85, FIG. 13Fj, !Is inhibited by the signal from flip-flop 226 on line 233.

V

A GEN P02 &amp;#1503; If the mode control bit on line 69 is a logic 1,

CffZclc------ |.

5/14774 :indicating an interrogation cycle is desired» the cycle Initiate .1.

jStrobe from NAUD gate 217 on line 220, FIG. 14A, clocks function ;

i&amp;#1493; code bit F&amp;#1524; on line 69” into flip-flop 222, which is a CD 4013A, ;

i 0i jand also clocks flip-flop 240, which is a CD4013A, whose output, i Γ 1 jjFIG. 14B, is clocked into flip-flop 241, which is a CD4013A,!

by the next transition of the 30-Hz clock on line 70, FIG. 14D, | thereby synchronizing the interrogation cycle to the 30-Hz clock, j . | ' γ. i :The change in state of flip-flop 241 on line 242, FIG. 14C,| ij.I removes the reset from counter 243 arid the set from flip-flop 244, !inhibits the pilot-tone enable on line 74, FIG. 14G, via line 246 jiand HAND gate 245, and changes input register 37 and sync code 1 register 38 to the serial mode of operation via line 72. The data contained in input register 37 and sync code register 30 is then shifted to modulator 39 at the rate of 30 bits per second by the

30-Hz clock on line 70, FIG. 14D. After the 28 bits of data, representing the sync code, the function code and module address are transmitted to the meter or control modules, counter 243, .’ &amp;#1493;which is CD4029A,and various HAND gates, clocks flip-flop 244 , I ‘ which is a CD 4013A, thereby inhibiting the transmit enable signal and removing the demodulator phase scan reset signal via line 75, FIG. 14E, removing the demodulator integrator reset ! i ' . !

1signal via line 247, OR gate 264 and line 93, enabling the output | * &amp;#1470;! I register clock output from OR gate 248 and A bus enable gate, j ' ‘i line 88, via line 75 and inverter 249, and enabling the demodulate: reset strobe via line 247. The signal on line 75, FIG. 14E, also i serves to synchronize the 15-Hz clock from divider 250, which is a CD4013A, to the 30-Hz clock,since its reset signal on line !1 &amp;#1510;&amp;#1509; changes state on a 30-Hz clock transition. The output register 30 clock frequency is selected by flip-flop 222. If the function code signal on line 69” indicated the module is to reply at 15 baud, HAND ghte 252 is enabled and HAND gate 253 is inhibited.

&amp;#1524;37t

A GEM P02;If the function code signal on line 69” indicated the module &amp;#1470;:Cll/ck ij

5/14/74 is to reply at 30 baud,HAND gate 252 is inhibited and NAND gate

253 is enabled. At this time HAND gates 252 and 253 are also enabled by the signal from flip-flop 254, which is a CD4013A, via; inverter 255 and line 256, while HAND gate 257 i8 inhibited by the signal on line 256. The output register clock from OR gate 248, line 258, FIG. 14F, triggers monostable multivibrator 259. j i The first pulse from monostable multivibrator 259, line 89, (

FIG. 14H, initiates the demodulator phase scan via &amp;#1524;AND gate 261 ! and line 92. The trailing edge of the signal from monostable ' multivibrator 259, line 89, FIG. 14H, increments counter 262, shifts the contents of output register 54 one.bit position, and !triggers monostable multivibrator 263, which is a CD4047A, whose !output resets the demodulator integrator via OR gate 264 and Iline 93. The trailing edge of the signal from monostable 1 .

multivibrator 259 on line 89, FIG. 14H, also clocks flip-flop ;260, thereby inhibiting HAND gate 261 and preventing further i &amp;#1470; . ' !demodulator phase scans during the remainder of this interrogation cycle. The output pulses from monostable multivibrator 259 on line 89, FIG. 14H, shift the contents of output register 54 and ! !reset the demodulator integrator until counter 265, which is a ! I

ICD4029A, overflows, indicating 64 bits of data have been received i j from the interrogated module and loaded in output register 54.

! The overflow signal from counter 265 clocks flip-flop 254 thereby inhibiting the 30-or 15-Hz clock from NAND gates 252 or 253, enabling the 285-Hs clock from NAND gate 257, all via line 256,

I FIG. 14K, enabling NAND gate 266, and strobing the mode control ! and central control unit address bits into output register .54 !via monostable multivibrator 269 and line 95. This corrects the !contents of output register 54, since the last four bits received

II .

!!by the demodulator represent noise rather than data from the !interrogated module. At this point counters 262 and 265 are in -38A GEN P02 ‘the zero count state, so decoder 267, which is a CD4028A, also ! Cff7ck . ' 37IV74 enables HAND gate 266, allowing the next pulse from multivibrator |

259 on line 268 to send a transmit strobe to data transmitter 55 j via HAND 266, OR gate 230, inverter 231 and line 85, FIG. 14L. j io

Counters 262 and 265 are incremented by the trailing edge I jof the pulses from monostable multivibrator 259 on line 89, liFIG. 14H. Each time counter 262 is incremented to the 000 state !

{ &amp;#1523; !

.{a transmit strobe is sent to data transmitter 55. When counter i 265 overflows, indicating eight transmit strobes have been sent, and the 64 bits of data in output register 54 have been transjtnitted to data-acquisition computer 4, flip-flop 270, which is a :;CD4013A, is clocked, FIG. 14M, thereby resetting flip-flops 240 and 241, returning items 243, 244, 262, 265, 254, 270 and 260 ;to their original state and terminating the interrogation cycle.

i When data is not being transmitted to, or received from, .:e. meter or control module, modulator 39 transmits an unmodulated ‘carrier to power amplifier 40. During this period NAUD gate 287 iis enabled by the transmit enable signal on line 75, HAND gate !280 is enabled by the pilot-tone-enable signal on line 74, and :NAND gates 281 and 282 are inhibited by inverter 283 and the ]signal on line 74. Thus, the signal on line 73, the un!modulated 6270-Hz carrier, is sent to power amplifier 40 via HAND ;gates 280 and 287. and OR gate 286. When data is to be transmitted, NAND gate 280 is inhibited by the signal on line 75, and !HAND gates 281 and 282 are enabled by inverter 283 and the signal !on line 75. If the data to be transmitted on line 58 is logic I !1, HAND gate 281 is enabled and HAND gate 282 is inhibited by ]inverter 287, thereby sending the 6270-Hz signal (that leads 'the 6270-Hz signal on line 72 by 90 degrees) on line 73 jto power amplifier 40 via NAND gates 281 and 287 and OR gate 236. Ilf the data to be transmitted on line 58 is logic 0, HAND gate 281 is inhibited and NAND gate 282 13 enabled by inverter 237.,

The signal on line 73, inverted by inverter 284, becomes a 62'70-Hz signal that lags the 6270-Hz signal on line 73 by >

degrees and is sent to power amplifier 40 via HAND gates

282 and 287, and OR gate 286. When data is to be received, the , .1 modulator is inhibited by the transmit enable signal, line 73&amp;#1470;, :

i and HAND gate 287. i

The video signal from video amplifier 52 on line 96 is sampled in parallel by four phase detectors 300, 300’, 300 and 300'/ Each phase detector uses a receive carrier, on line ; 73, 73', 73’’ and 73' , respectively, that is separated by 45 degrees to demodulate the video signal on line 96. Item 300' is a typical phase detector and comprises amplifier 315, which is a Fairchild Semiconductor 741, resistors 316, 316', 316,, 316 ! and 316’&amp;#1523;, switches 314 and 314', which are CD4066A&amp;#1523; and are driven ! 180 degrees out of phase with each other by the 6270-Hz carrier ) on line 73’, and inverter 313. The operation of this phase ; detector is described by J. N. Giles, Linear Integrated Circuits : Applications. Handbook, Library of Congress Catalog 57-27446.

The outputs of the phase detectors are integrated by integrators 301, 301*, 301 and 30Γ . Item 301' is a typical integrator and comprises amplifier 318, which is a Fairchild semiconductor 741, resistor 317, capacitor 319 and switch 320, .

1 1 &amp;#1470; i i which is a CD4066A. At the end of each bit period capacitor 319 &amp;#1523; &amp;#1503; is discharged by switch 320, via the integrator reset signal on line 93. The integrator outputs are connected to signal bus 324 by switches 302, 302', 302 and 302' and to signal bus 325 : by switches 303, 303', 303 and 303’. Switches 302 and 303 1 are CD4066A. Switches 302, 302’, 302 and 302’ are controlled by I shift register 311 via lines 327, 32.7327 ,&amp;#1523; and 327', respec- ; ’ tively, while switches 303, 303' and 303 are controlled by shift | i) register 310&amp;#1470; via lines 326, 326' and 326, respectively. The ' ; I : absolute magnitude of the signals on lines 324 and 325 is produced

'&amp;#1497;' . &amp;#1497;.‘ ! &amp;#1497; ' &amp;#1497; .' . ; -. ‘&amp;#1497;&amp;#1497;' ’ . ' .&amp;#1470; ' &amp;#1497;&amp;#1497;. &amp;#1497; , &amp;#1497;' ., \ i

A GEN P02 by absolute magnitude circuits 304 and 304', respectively. A Cit/&amp;#904;Ε ii

5713774 typical absolute magnitude circuit 304 .comprises amplifier 321, which is a Fairchild Semiconductor 741, diodes 322, which are

GN914, and resistors 323, 323’, 323 and 323'”. While data is j |>eing transmitted from central control unit 5 to a meter trans- j fonder, integrators 301, 301’, 301” and 301'” are reset by line ^3, FIGS. 16W and 141, while shift registers 310 and 311, which l| .

Are CD4034A, are held in the parallel mode and flip-flop 312, which is a CD4013A, is set by line 75,- FIGS. 16A and 14E. This loads 1000 into shift register 310 as shown in FIGS. 161, 16J, I

! . &amp;#1523;' !&amp;#1523;

16K and 16L, and enables the A bus of shift register 311, via ! i!

line 328, FIG. 16G, thereby allowing the contents of shift register 310 to be loaded into shift register 311 via lines 326, | 326’, 326 and 326'. The shift register 311 assumes the 1000 state as shown in FIGS. 16M, 16N, 16P and 16Q.

&amp;#912; After data is transmitted to the meter transponders, the |»hase scan reset on line 95, FIG. 16A, and the integrator reset qn line 93, FIG. 16W, are removed and integrators 301, 301', 301” And 301’ integrate the signals from phase detectors 300, 300',

300 and 300'”, respectively. At the end of the received data j bit period flip-flop 306, which is a CD4013A, is clocked,

I!&amp;#1523;

FIG. 16C, by the phase&amp;#1470;scan&amp;#1470;initi.ate signal on line 92, FIG. 163.

I!. '.

^he next transition of the 6270-ilz clock on line 73', FIG. 16D, |i

Clocks flip-flop 307, which is a 0D4013A thereby synchronizing the ii’ $hase scan.to the 6270-Hz clock. Flip-flop 307 output, FIG. 16E, enables HAND gate 308, whose output clocks shift register 310

Via line 329, FIG. 16F, and flip-flop 312, which is a CD4013A, yia inverter 309. i ! The algorithim used for the phase scan is to load shift register 311 with the contents of shift register 310 if the njagnltude of the. signal on line 324 is less than the magnitude of the signal on line 325 and to freeze the contents of shift register

A GEN P02

CH/ck 57B774

311 if the reverse is true, all the while shifting shift register i

3,10

At the start of the phase scan shift registers 310 and 311 contain 1000, thereby enabling switch 302 via line 327, 16M, and switch 303 via line 326, FIG. 161.

FIG. 16 illustrates the case where the signal magnitude;

I from integrator 301 on line 324 is less than that from integrator; 301', on line 325, thus the output of differential comparator 305, which is a National Semiconductor LM139, is high as shown in

FIG. 16H, and the negative-going transition on line 329, FIG. 16F, clocks an A bus enable signal into flip-flop 312, as shown in each

FIG.

I FIG, 16G, thereby allowing shift register 311 to be loaded from ! shift register 310. ;

! The positive going transition on line 329, FIG. 16F, i ’ !shifts the contents of shift registers 310 and 311 to the 0100 jstate enabling switch 302' via line. 327', FIG. 16N, and switch 303’ via line 326, FIG. 16J. FIG. 16 illustrates the case where I;. |t the signal magnitude from integrator 301' on line 324 is greater j than that from integrator 301 on line 325,so comparator 305 !output, FIG. 161J, is low and the next negative-going transition 'on line 329, FIG. 16F, clocks an A bus inhibit signal into flipi ; flop 312 as shown in FIG. 160, thereby freezing the contents of shift register 311. ;

The positive-going transition on line 329, FIG. 16F, &amp;#1503; shifts the contents of shift register 310 to the 0010 state, while shift register 311 remains in the 0100 state, thus, switch j 302' remains enabled via line 327', FIG. 16N, and switch 303 is 'enabled via line 326, FIG. 16K. FIG. 16 illustrates the case !!

where the signal magnitude from integrator 301' on line 324 is !less than that from integrator 301' on line 325,80 comparator i &amp;#1523;

I 305 output, FIG. 16H, is high and the next negative-going transition on line 329, FIG. 16F, clocks an A bus enable signal into flip-flbp 312 as shown in FIG. 16G, thereby allowing shift register

A GEN P02

CE/ck 5715774 !311 to be loaded from shift register 310.

The positive going transition on line 329, FIG, 16F, ’shifts the contents of shift register 310 and 311 to the 0001 :

! . &amp;#1523; .1

State, thereby enabling switch 3.02’ via line 327'”, FIG. 16Q, J and setting flip-flops 306 and 307 which terminates the phase scan, and triggering monostable multivibrator 330, which is a CD4047A, both via line 326, FIG. 16L. The output of integrator

&amp;#1503;

301’, via switch 302’” and line 324, is compared to ground by j differential comparator 331, which is a National Semiconductor .

i LM139, whose output is logic 0 if the signal on line 324 is negative and logic 1 if the signal on line 324 is positive.

Exclusive OR gate 333 compares the logic level output of differential comparator 331, FIG. 16S, to the logic level of ithe first expected bit, which is function code bit Fq, via line ;91. If the inputs to exclusive OR gate 331 are identical, logic .10 is clocked into flip-flop 332 by monostable multivibrator 330, FIG. 16R. If the inputs .to exclusive OR gate 333 are opposite, i]a logic 1 is clocked into flip-flop 332, which is a CD4013A. ![ The polarity level from flip-flop 332, FIG. 16T, is ]compared to the signal from differential comparator 331 by !exclusive OR gate 334 and sent to output register 54 via line 90, !FIG. 16U. The selected Integrator and polarity level are used to .

!. &amp;#1523; 1 receive the remainder of the interrogated module message until reset by the phase scan reset signal, line 75, FIGS. 16A and 14E, j and polarity clock pulse, FIG. 16R, during the next interrogation | ! cycle. The output register shift clock and demodulator integrator I lines 39 and 93, FIGS. 14H and 141, respectively, are shown for !reference as FIGS. 16V and 16W, respectively.

! Exetplary embodiments of input register 37 and sync

[code register 38, command register 43. status register 44 and [!output register 54 using logic elements of the RCA CD6000A series ![are shown in FIGS. 17, 18, 19 and 20, respectively. With referenda I -43&amp;#1470;

A GEN P02 CH/ck '5715774 :to FIG. 17, the input register and sync code register comprises {'CD4034A eight-bit registers, operated in the asynchronous mode i ‘.

{with A bus data input and 3 bus data output and are normally &amp;#943;operated in the parallel node. The first data byte, on line 56, | from data receiver 36 is loaded ,into register 37 by the A bus enable 'gate signal from timing control •27 on line 71; the second data byte, on line 56', &amp;#1497; is loaded into register 37' by the A bus enable signal on line 71' and the third

I '.

! data byte, an line 36, are loaded into register 37 by the A bus enable signal on line 71. The A bus of sync code register 38 is always enabled, thereby {!continuously loading the preset eight bit synchronization code.

ii 1 {!The contents of registers 37, 37' and 37 are available for trans&amp;#1524; {fer to timing control 47 or command register 43 via the B bus ,i outputs, During an interrogation cycle,registers 37, 37', 37 and

138 are transferred to the serial mode of operation by the serial enable signal on line 72 and the register contents are shifted to modulator 39 by the shift clock on line 70, both signals from ;timing control 47.

&amp;#906; {{ With reference to FIG. 18, the command register comprises ;i.

i! CD4034A eight bit registers operated in the asynchronous, paral20 !lei mode, xdth A bus data input and B bus data output, Data from input register 37 is continuously available on lines 67, 67' and

&amp;#938; 67. Klien the message mode indicator bit K indicates the contents I!&amp;#1523; ':of input register 37 is a command, the data on lines 67, 67 and !

• i* .!

{{67 are loaded into registers 43, 43’ and 43, respectively, by tt!e τi

11A bus enable signal on line 78 from timing control 47. The { !contents of command registers 43, 43' and 43 are available on { ;i!

!3 bus lines 79, 79' and 79, respectively.{ &amp;#1523; ' ’ &amp;#1493; 'i

With reference to FIG. 19, the status register comprises { CD4034A eight-bit registers operated in the asynchronous mode 'with B bus data input and A bus data output. Status eata is ';continuously available on lines 82, 82' and Sz1', while the preset !message mode indicator bit K (preset to logic 0) preset central j ->44**

A GEN Ρ02 CH/clt 5715774 *

[control unit address bits and Ajj, and command execute enable ;&amp;#1523;bit P on line 68 are continuously available as inputs Bl through &amp;#1523;.

iB4 of register 44’. When the status register contents are to be !sent to data transmitter 55 via line 83, the A bus outputs of register 44 are enabled arid registers 44, 44' and 44. are operate^ in the serial mode by the serial enable signal from timing control 47 on line 81, and inverter 80, respectively. The contents of registers 44, 44' and 44 are shifted by the clock on line 99 from timing control 47.

With reference to FIG. 20, the 64-bit output register ;

i - i i comprises eight-bit register 54 and four-bit register 54, which are CD4034A, two 18-bit registers 54' and 54, which are

CD4006A, and a 16-bit register 54’, which is CD4006A. Registers ;54, 54’, 54 and 54' are always operated in the parallel mode, while the Abus of register 54 is used to transfer data, via line 87, to data transmitter ,55. While receiving data from demodulator 53,

[via line 90, data is shifted from register 54 to register 54 by ]the shift clock,'on line 89, from timing control 47. After the [meter module reply message has been received, the 60-bit reply [ . ]message resides in registers 54, 54', 54' and 54 . Timing ]control 47 then enables the A bus output of register 54 via |line 88. Simultaneously, register 54’ is transferred to asyn[chronous parallel mode for a short period of time, via timing !1 .

]control 47 strobe signal on line 95, thereby loading the message !mode indicator bit K, preset to logic 1, preset central control I !!unit address bits, A., and A.,, and clock phase bit P on line 68 !

&amp;#1503; /1 10 1 ]into register 54 via A bus Inputs Al through A4, respectively.

[The contents of registers 54', 54, 54’ and 54&amp;#1523;’ are then ]shifted to register 5.4 for transfer to data transmitter 55 ] Exemplary embodiments of transponder demodulator 104, data control 105, data register 106, modulator 107, timing contra

110, synchronisation code comparator 111, hot water control address

A GEN P02

CH/ck ' * comparator 112, meter module address comparator 113, function code register 114, function decoder 115 and hot water control 116 are shown in FIG. 21, using logic elements of the RCA CD4000A series, with key timing relationships sho^m in FIG. 22.

The transponder 30&amp;#1470;Hz basic timing clock, line 424, !

FIG. 22A, is derived from the nominal 60&amp;#1470;Hz power distribution !.

i frequency via line 24, differential amplifier 401, which is a National Semiconductor 111139, and divider 423, which is a CD4013A. The phasing of the 30&amp;#1470;Hz clock output of exclusive OR gate 431, line 445, FIG. 22C, is controlled by dividers 427 and 428, which are CD4040A and CD4013A, respectively, and monostable multivibrator 426, which is a CD4047A. Each time the synchronization code is received monostable multivibrator 426 is triggered by the sync flag signal, on line 121, FIG. 22F, thereby resetting divider

427. If a synchronization code match is not detected during a duration of 2048 successive 30-Hz clock periods, about 68.3 seconds, divider 423 is toggled, FIG. 22B, thereby inverting the phase of ! the 30-Hz clock on line 445. While interrogating meters or controlling hot water heaters, central control unit 5 will be transmitting a message, including the synchronization code, about i every five seconds. Thus, once 30&amp;#1470;Hz clock phase synchronization is obtained, divider 428 will remain quiescent. The shift clock ;

' &amp;#1503; on line 116, FIG. 22D, is developed from the 30&amp;#1470;Hz clock on line ! 445 via WAND gate 434, which is normally enabled by line 124, OR ! gate 435 and monostable multivibrator 436, which is a CD4047A.

! The reference frequency for demodulator 104 and modulator !07 are developed in a phase-locked loop oscillator which '1 ' , , uses the 60&amp;#1470;Kz power distribution frequency, via differential ; amplifier 401, as the source reference frequency. The output frequency of phase-locked oscillator 402, which, is a CD4046A, ; is 1θθ.320&amp;#1470;ΙΙζ, which is sixteen times the communication carrier : frequency, 6270&amp;#1470;Hz, and is divided by eight in divider 404, which i -46'The phase of the reference frequency on line 119 is

J the data received from demodulator 104 via line 135 '425.

' .

While central control unit 5 transmits an carrier, up/down counters 407 and 408, which are CD

A GEN P02ks a CD4029A, and by 209 in divider 405,which is a CD4029A, to CH/ck------ij .

3/75774 [!produce a 60-IIz signal that is fed back to phase-locked oscillator j402, thereby closing the phase-locked loop;” The 100,320-Hz output of phase-locked oscillator 402 is also divided by sixteen by ! divider 403, which is a CD4029A, to obtain the 6270-llz reference !

' frequency, on line 119, used by demodulator 104 and modulator 107,. controlled by ' and inverter unmodulated

029A, are &amp;#1524;clocked by the 30-Hz signal on line 445, FIG. 22C, via NAND gate 410 and inverter 409. If demodulator 104 output is a logic 0, !counters 407 and 408 are incremented upward. If the signal on ;line 135 is a logic 1, they are decremented downward. The output of counter 407 is compared to the output of divider 404 by digital comparator 406, which is a CD4063A. Wien the outputs match, !divider 403 is reset. Thus, an excess of logic 0's from !

!demodulator 104 will advance the 6270-Πζ reference frequency on line 119, while an excess of logic 1's will retard the phase, !thereby phase locking the 6270-Hz reference frequency on line 119 !to the unmodulated carrier received from central control unit 5. ! Counter 408 has a scale factor of sixteen; therefore, an accumulated excess of sixteen logic l's or logic 0’s is

I required before the phase of the 6270 Hz. reference frequency on jline 119 is advanced or retarded, thereby making die circuit insensitive to short term variations. When the synchronization

' &amp;#1470; ] !code, which has a balanced quantity of logic l'a and 0's, is received and detected, the phase shift circuits are inhibited !via the sync flag signal on line 121, FIG. 22F, and NAND gate 410. :This prevents the phase control circuits from acting on function &amp;#906; . - .

;!bits, Fq through F^, and address bits, Αθ through A15 of the ! -47A GEN P02 interrogation message from central control unit 5. After the ! CH7ci&lt; ’ i - , t)

F7I5T74 );meter transponder interrogation cycle is complete the sync flag ;

!)signal on line 121, FIG. 22F, again enables the phase control | !circuitry.)

Data is obtained from video amplifier 103 signal, on ) '.I line 131, by demodulator 104 which comprises transformerless| phase detector 411 and integrator 416. Phase detector 411 comprises resistors 412, 412&amp;#1523;'412 ,.412 ,412 ,&amp;#1524; and 412’, operational amplifier 413, which is a Fairchild Semiconductor 741, and switches

414 and 414', which are CD4066A, driven 180° out of phase by inverter 415 and the 6270-Hz reference frequency on line 119.

Phase detector 411 output is integrated by integrator 416, which )) comprises resistor 417, operational amplifier 418, which is U Fairchild Semiconductor 741, capacitor 419, switch 420, which is a CD4066A, monostable multivibrator 421, which is a CD4047A, and differential amplifier 422, which is a National Semiconductor !121139&amp;#1470;. When the output of operational amplifier 418 is ljpositive, the output of differential amplifier 422, on lines 130 &amp;#1524;and 135, is logic 1. When the output of amplifier 418 is )!negative, the output of amplifier 422 is logic 0. At the end &amp;#1503; of each bit period the negative-going transition of the shift | clock on line 118, FIG. 22D, triggers monostable multivibrator !421, thereby discharging capacitor 419 via switch 420 and resetting ! I )integrator 416. I

Before the synchronization code is received, the sync flag signal on line 121, FIG. 22F, continuously resets counters ; 437 and 433, which are CD4029A, to the zero state, thereby )developing an enable signal on lines 117 and 120, FIG. 22G, from )!decoder 439, which is a CD4028A. Thus, receive switch 102 18 ’ . !1.

:) enabled and data from demodulator 104 is clocked into data j

) register 106, consisting of shift registers 106 and 106',which ) are CD4034A, and 106, which is a CD4015A, by the 30-lIz shift

A GEN P02 CH/ ck

15774&amp;#1470;57&amp;#1470;

1.0

X

[clock on line 118, FIG. 22D, via OR gate 443 and HAND gate 442, [which is enabled by the control signal on line 120. The data[ register input signal is shown in FIG. 22E. OR gate 443 and[

NAND gate 442 form part of data control 105, the remainder of [ which comprises HAND gates 440 and 441, and inverter 424. The [ first eight bits of data register 106 are compared to the&amp;#912; preset synchronization code by digital comparator 111, which is I two CD4063A, via line 132. When a synchronization code match is [ ; detected, sync flag flip-flop 1111, which is a CD4013A, is!

, clocked,removing the reset from counters 437 and 438, triggering monostable multivibrator 426 and inhibiting NAKD gate 410, via line 121, FIG. 22F.

1 Twenty bit periods after the synchronization code !match is detected, decoder 439 inhibits receive switch 102, via ;line 117, demodulator 104 data flow through data control 105, via [the control signal on line 120, FIG. 22G, triggers monostable multi&#1523;vibrator 449, and clocks function code bit Γθ, on line 132 ' from data register 106, into reply rate register 114 and function code bits Fp F?>, F^, on line 132 from data register 106, into function register 114’, via the control signal on line 122, FIG. 2211, and enables meter data flow through data control 105 ;via the control signal on line 120', FIG. 22H. The reply data ! rate is determined by function code bit Ρθ in reply rate register 1 [114, which is a CD4013A. If the Fq bit is logic 1, the reply rate is 30 baud, and HAND gate 434 is enabled via line 124. If 1the Γθ bit is logic 0, the reply rate is 15 baud and divider !432, which is CD4013A, is enabled by the signal on line 124, thereby ;synchronizing the 15-Hz clock to the 30-Hz clock, while HAND I gate 433 is enabled by the signal on line 124'. Thus, the shift clock frequency on line 118, FIG. 22D, is determined by the &#1523;[contents of reply register 114.

I The preset meter modulo address and hot water control

A GEN P02 CilTcx 57W74 )

address codes are simultaneously compared to address bits Aq through A^r, from data registers 106' and 106 by digital comparators 113 and 112, respectively, which are CD4O63A, via lines 132 and { 132'. Monoatable multivibrator 449, which is a CD4047A, enables comparators 113 and 112 via line 444, FIG. 22K, to detect a meter module address match, a hot water control address match, or no i &amp;#1523;&amp;#1497; j match. I .

If comparator 113 detects a meter module address was i received, meter module address flag flip-flap 113', which is a CD4013A, is clocked, thereby enabling. function decoder 115, via line 126*, and meter data flow through data control 105, and modulator 107, via meter module address flag on line 126, FIG. 22L. Function code bits F^, Fo, Fg are held in function register 114’, !which is a CD4042A, and are decoded by function decoder 115, which ¼9 a CD4028A, via line 127. Only one meter encoder is enabled by function decoder 115, such as electric meter encoder via :line 26.

: During the 20-blt periods immediately following meter ' I ! module address detection, function code and address data is : shifted to modulator 107 from data register 106, via line 128, FIG. 22M, while meter reading data bits Μθ through i!1g from the selected mater encoder are shifted into data register 106 via line 129 and data control 105, which is enabled by decoder 439 control signal on line 120', FIG. 22Π. During the second 20-bit period following meter module address detection the meter reading data contents of data register 106 are shifted to modulator ! 107 via line 128, FIG. 22M, while Inverted meter data bits. 1¾ !!through are shifted into data register 106, FIG. 22Ξ, via line 133 and data control 105, which is enabled by decoder 639 30 control signal on line 120, FIG. 221. During the third 20-bit : period following meter module address detection the inverted I ' ! meter data in data register 106 is shifted to modulator 107 via / '

A.GEN P02!1ine 128, FIG. 22M, and data register 106 is loaded with logic Cll/ck i 0's. as shown in FIG. 22?:, since data control 105 is inhibited by decoder ,439.

At the end of this period decoder 439 control signal on line 123, FIG. 22J, sets sync flag flip-flop 111', meter module

I address flag flip-flop 113', and reply rate register.114 &amp;#1470; and resets ; function register 114', thereby resetting bit counters 437 and ! 438 to the zero state and enabling NAND gate 410 via line 121, i FIG. 22F, inhibiting function decoder 115, via line 126, meter data 10 ; entry to data control 105 and modulator 107, via line 126, FIC. 22L, ' setting the shift clock on line 118 to 30-Hz via line 124, and ! ° I enabling receive switch 102, via line 117, FIG. 22G. The ! transponder now resumes searching the received data for the next i synchronization code transmission from central control unit 5.

! If comparator 112 detects a hot water control address, i function code bits, on line 127, is clocked into hot water &amp;#1503; control register 116, which is a CD4042A, by the strobe from J &amp;#943; comparator 112 on line 125, FIG. 22N. This performs the desired control 'function, such as turning the hot water heater control relay on, via line 134, or ![ * !peak demand meter control relay an, via line 140, FIG. 22P. The meter transponder then idles 'for 60-bit periods, since modulator 107, function decoder 115 and data control 105 are not enabled by meter module address flag signal on line 126. At the end of 60-bit periods, whose ! duration is determined by function code bit Fg of reply rate | register 114, receive sync flag flip-flop 111' and reply rate | register 114 are reset by decoder 439 control signal on line 123, ! FIG. 22J, thereby resetting bit counters 437 and 438 to the zero i state and enabling NAND gate 410 via line 121, FIG. 22F, setting ' the shift clock on line 118 to 30-llz via line .124, and enabling ! receive switch 102, via line 117, FIG. 22G.

If no address match is detected by comparators 112 and ρ 113, transponder 12 performs no control function and idles for 60 -511 &amp;#1470; . , Λ &amp;#1503;

A GEN P02 bit periods, whose duration is determined by finccio:&amp;#1470;: code bit Fn of ! cH/ck“ &amp;#1498;&amp;#1524; ,. u . &amp;#1503;

11/26/74 ' reply rate register 114, and then resets as in the hot water control cyclo.

j The signal from data register 106, on line 128, FIG. 22M and 22Q, modulates the phase of the 6270-IIz reference frequency, on ! line 119, in exclusive OR gate 446, thereby producing the desired : 180&amp;#1470;degree phase shift between communication carrier outputs repro! senting logic 1 and logic 0. The modulated signal, and its inverse • via inverter 447, are enabled in HAND gates 450 and 451 by meter module address flag signal on line 126, FIG. 22L, which drive transmitter 108 via inverters 452 and 453, and lirass 136 and 136’, respectively.

| 'With reference to'FIG. 23, there is shown an exemplary embodiment of transponder transmitter 108. Transformer 500, which is a Stancor P-8605, steps down the 120V, 60-ilz power line voltage !from electric service entrance 24 and 24'. The reduced voltage is !rectified by diodes 501 and 502, which arc Motorola MR751, and filtered.by capacitor 503. Transistors 504 and 505, which are

2&amp;#1523;N2222A,are normally turned off by the modulator signals on lines !136 and 136’, via resistors 506 and 597, respectively. When moduJlator 107 is enabled, transistors 504 and 595 are switched 189 I . l :degrees out of phase. When transistor 504 is switched on, current !flows through resistors 503 and 509, charging capacitor 510, there1 by slowly switching on transistor 511, which is a 2Π2905, whese ! collector current is limited by resistor 523, and transistor 512, which is a 2J6111 whose emitter current is limited by resistor 5131 !This raises the voltage on line 525 to that on line 526, thereby ;charging capacitor 523 through resistor 527. The voltage drop j !across resistor 527 causes triac 529 to conduct. When the modulator . ’ ,. !

[flignal on line 136 switches off transistor 504, capacitor 510 dis-‘ [charges through resistor 508, slowly switching off transistors 511. !! !

30 and 512, while diode 514, which is a Motorola MR751, clips the spike

Ij !

Created by the inductance of electric service entrance 24 and distr!-.

!bution transformer 10. When transistor 595 is switched on by &amp;#1524;52A CKJ P02 C17ck &amp;#938;Τ725/74 • Λ modulator signal 136', transistor 515, which is a 212905, is switched on via resistors 516 and 517. Current then flows through resistor 513, j charging capacitor 519, thereby 01a&amp;#1524;ly turning an transistor 520, which is a 2:16336, whose emitter current is limited by resistor 524. This lowers the voltage on line 525 to that on line 24’, the service entrance neutral, thereby discharging capacitor 523 through resistor 527. The &amp;#1470;voltage drop across resistor 527 causes trlac 529 to conduct. When the modulator signal on line 136' switches off transistor 505, capacitor 519 discharges through resistor 521, slowly switching off transistor 520, while diode 522, which is a Motorola MR751, clips the spike created by the Inductance of electric service entrance 24 aid distribution transforner

10. The voltage trEnsistions on line 525 are cowled to the electric service ! ;entrance, lines 24 and 24', by coupling capacitor 109. I; .

The circuitry just described comprises a source of unipolar !potential ou line 26 derived from the electrical power and having :ripple at the power line frequency, The transistor circuitry comprises means for interrupting the uiipolsr potential at a rate correspending to the carrier frequency in response to the means for moiulacing applied to the bases of transistors 504 and 595 to interrupt them!&amp;#1524; !polar potential at a rate corresponding to the carrier fnYjUincy. The triac

529 comprises means for coupling the interrupted unipolar potential

I to the power lines to provide a carrier signal 01&amp;#1494; the power lines.!

There has been described novel apparatus and techniques j i for effectively communicating over power lines with numerous advarv tages and features described above. It is apparent that those skilled (in the art may naw make numerous uses and loodificatlonr. of and departures :1 !from the specific embodiments described herein without csparting fra?. tie!

!

;inventive concepts. Ccmequently, the invonticn is to be caiatrued as ea!bracing each and every novel feature and novel ccrbination of features

II present in or possessed by the apparatus and techniques herein disclosed find limited solely by the spirit and scope of the appended claims.