System and method for assigning classifications to defects detected on a wafer

SYSTEM AND METHOD FOR ASSIGNING CLASSIFICATIONS TODEFECTS DETECTED ON A WAFER

BACKGROUND OF THE INVENTION 1. Field of the Invention

The present invention generally relates to methods and systems for utilizing design data in combinationwith inspection data. Certain embodiments relate to a computer-implemented method for determining aposition of inspection data in design data space and/or substantially accurately determining the position ofa design space location on a wafer during an inspection process. 2. Description of the Related Art

The following description and examples are not admitted to be prior art by virtue of their inclusion in thissection.

An integrated circuit (IC) design may be developed using a method or system such as electronic designautomation (EDA), computer aided design (CAD), and other IC design software. Such methods andsystems may be used to generate the circuit pattern database from the IC design. The circuit patterndatabase includes data representing a plurality of layouts for various layers of the IC. Data in the circuitpattern database may be used to determine layouts for a plurality of reticles. A layout of a reticlegenerally includes a plurality of polygons that define features in a pattern on the reticle. Each reticle isused to fabricate one of the various layers of the IC. The layers of the IC may include, for example, ajunction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contactpattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.

The term "design data" as used herein generally refers to the physical design (layout) of an IC and dataderived from the physical design through complex simulation or simple geometric and Booleanoperations. A semiconductor device design is verified by different procedures before production of ICs. For example,the semiconductor device design is checked by software simulation to verity that all features will beprinted correctly after lithography in manufacturing. Such checking commonly includes steps such asdesign rule checking (DRC), optical rule checking (ORC), and more sophisticated software basedverification approaches that include process simulation calibrated to a specific fab and process. The 1 output of the physical design verification steps can be used to identify a potentially large number of critical points, sometimes referred to as "hot spots," in the design.

Fabricating semiconductor devices such as logic and memory devices typically includes processing asubstrate such as a semiconductor wafer using a large number of semiconductor fabrication processes toform various features and multiple levels of the semiconductor devices. For example, lithography is asemiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged ona semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are notlimited to, chemical-mechanical polishing (CMP), etch, deposition, and ion implantation. Multiplesemiconductor devices may be fabricated in an arrangement on a single semiconductor wafer and thenseparated into individual semiconductor devices.

Inspection processes are used at various steps during a semiconductor manufacturing process to detectdefects on wafers to promote higher yield in the manufacturing process and thus higher profits. Inspectionhas always been an important part of fabricating semiconductor devices such as ICs. However, as thedimensions of semiconductor devices decrease, inspection becomes even more important to the successfulmanufacture of acceptable semiconductor devices because smaller defects can cause the devices to fail.For instance, as the dimensions of semiconductor devices decrease, detection of defects of decreasing sizehas become necessary since even relatively small defects may cause unwanted aberrations in thesemiconductor devices.

Another important part of manufacturing yield control is determining the cause of defects on the wafer orreticle such that the cause of the defects can be corrected to thereby reduce the number of defects on otherwafers or reticles. Often, determining the cause of defects involves identifying the defect type and otherattributes of the defects such as size, shape, composition, etc. Since inspection typically only involvesdetecting defects on the wafer or reticle and providing limited information about the defects such aslocation on the wafer or reticle, number of defects on the wafer or reticle, and sometimes defect size,defect review is often used to determine more information about individual defects than that which can bedetermined from inspection results. For instance, a defect review tool may be used to revisit defectsdetected on a wafer or reticle and to examine the defects further in some manner either automatically ormanually.

Defect review typically involves generating additional information about defects at a higher resolutionusing either a high magnification optical system or a scanning electron microscope (SEM). The higherresolution data for the defects generated by defect review is more suitable for determining attributes of thedefects such as profile, roughness, more accurate size information, etc. Defect analysis may also be 2 performed using a system such as an electron dispersive x-ray spectroscopy (EDS) system. Such defectanalysis may be performed to determine information such as composition of the defects. Attributes of thedefects determined by inspection, review, analysis, or some combination thereof can be used to identitythe type of the defect (i.e., defect classification) and possibly a root cause of the defects. This informationcan then be used to monitor and alter one or more parameters of one or more semiconductor fabricationprocesses to reduce or eliminate the defects.

As design rules shrink, however, semiconductor manufacturing processes may be operating closer to thelimitations on the performance capability of the processes. In addition, smaller defects can have an impacton the electrical parameters of the device as the design rules shrink, which drives more sensitiveinspections. Therefore, as design rules shrink, the population of potentially yield relevant defects detectedby inspection grows dramatically, and the population of nuisance defects detected by inspection alsoincreases dramatically. Therefore, more and more defects may be detected on the wafers, and correctingthe processes to eliminate all of the defects may be difficult and expensive. As such, determining whichof the defects actually have an effect on the electrical parameters of the devices and the yield may allowprocess control methods to be focused on those defects while largely ignoring others. Furthermore, atsmaller design rules, process induced failures may, in some cases, tend to be systematic. That is, processinduced failures tend to fail at predetermined design patterns often repeated many times within the design.Elimination of spatially systematic, electrically relevant defects is important because eliminating suchdefects can have a significant overall impact on yield. Whether or not defects will affect deviceparameters and yield often cannot be determined from the inspection, review, and analysis processesdescribed above since these processes may not be able to determine the position of the defect with respectto the electrical design.

Some methods and systems for aligning defect information to the electrical design have been developed.For instance, a SEM review system may be used to determine more accurate coordinates of defectlocations for a sample of defects, and the defect coordinates reported by the SEM review system may beused to determine locations of defects in the electrical design. Other methods involve aligning inspectioncare areas (e.g., the areas of the device pattern formed on the wafer in which inspection will beperformed) to the physical location of the pattern printed on the wafer. However, currently, the care areascan be aligned to the pattern printed on the wafer with an accuracy of no better than about 2 .mu.m due tosystem errors and imperfections. For instance, some bright field (BF) inspection systems have coordinateaccuracies of about +/-1 .mu.m. In addition, the inspection care areas in currently used methods arerelatively large and include many non-critical features as well as desired critical features. In trying tomaximize the sensitivity of the inspection system to capture subtle spatially systematic "design-for- 3 manufacturability" (DFM) defects resulting from design and process interdependencies, the system maybe overwhelmed by millions of events in non-critical areas such as CMP fill regions. Detecting suchnuisance defects is disadvantageous for a number of reasons. For example, these nuisance events need tobe filtered out of the inspection results by post-processing of the inspection data. In addition, nuisanceevent detection limits the ultimate achievable sensitivity of the inspection system for DFM applications.A high rate of nuisance defect data may also overload the run time data processing capacity of theinspection system thereby reducing throughput and/or causing the loss of data.

Accordingly, it may be advantageous to develop methods and systems for aligning inspection data todesign data with sub-pixel accuracy (where the size of the pixel may be on the order of the size of thegeometries being inspected) such that substantially highly accurate "context" of the design data can beutilized to perform one or more context-based functions such as, but not limited to, grouping pixels in adefect detection algorithm or method, tailoring detection sensitivity, filtering nuisance defects, classifyingdefects, grouping defects, and sampling defects for review by using design context as part of the samplingscheme.

SUMMARY OF THE INVENTION

The following description of various embodiments of methods and systems is not to be construed in anyway as limiting the subject matter of the appended claims.

One embodiment relates to a computer-implemented method for determining a position of inspection datain design data space. The method includes aligning data acquired by an inspection system for alignmentsites on a wafer with data (e.g., design data) for predetermined alignment sites. The data for thepredetermined alignment sites and the data acquired by the inspection system for the alignment sites onthe wafer are obtained separately. For instance, the data for the predetermined alignment sites is notacquired using the wafer on which the alignment sites are printed. The method also includes determiningpositions of the alignment sites on the wafer in design data space based on positions of the predeterminedalignment sites in the design data space. Determining the positions of the alignment sites on the wafer indesign data space may also be performed based on design layout on the wafer and/or the orientation of thewafer during inspection. In addition, the method includes determining a position of inspection dataacquired for the wafer by the inspection system in the design data space based on the positions of thealignment sites on the wafer in the design data space. The position of the inspection data may be storedand used as described further herein. In one embodiment, the position of the inspection data is determinedwith sub-pixel accuracy. 4

In another embodiment, the data for the predetermined alignment sites includes design data stored in adata structure such as a graphical data stream (GDS) file, any other standard machine-readable file, anyother suitable file known in the art, and a design database. A GDSII file is one of a class of files used forthe representation of design layout data. Other examples of such files include GL1 and OASIS files.Although some embodiments are described herein with respect to GDS or GDSII files, it is to beunderstood that the embodiments are equally applicable to this entire class of files irrespective of datastructure configuration, storage format, or storage mechanism. In a different embodiment, the data for thepredetermined alignment sites includes one or more simulated images illustrating how the predeterminedalignment sites will be printed on the wafer.

In some embodiments, the data for the predetermined alignment sites includes one or more attributes ofthe predetermined alignment sites, the data for the alignment sites includes one or more attributes of thealignment sites, and the aligning step includes aligning the one or more attributes of the predeterminedalignment sites to the one or more attributes of the alignment sites. In one such embodiment, the one ormore attributes of the predetermined alignment sites include centroids of the predetermined alignmentsites, and the one or more attributes of the alignment sites include centroids of the alignment sites.

In an additional embodiment, the data for the predetermined alignment sites includes data, acquired by theinspection system or other image acquisition system, that has been aligned to design data stored in a datastructure such as a GDSII file for the design data. In still another embodiment, the data for thepredetermined alignment sites includes at least a portion of a standard reference die image that has beenaligned to design coordinates in the design data space. The standard reference die image may be areference image that has been acquired, simulated, augmented, or any combination thereof.

In some embodiments, the predetermined alignment sites include at least one alignment feature havingone or more attributes that are unique in the x and y directions. In other embodiments, the predeterminedalignment sites include at least two alignment features. A first of the at least two alignment features hasone or more attributes that are unique in the x direction. A second of the at least two alignment featureshas one or more attributes that are unique in the y direction.

In an additional embodiment, the method includes selecting the predetermined alignment sites using theinspection system. In one such embodiment an imaging mode of the inspection system (or other imageacquisition system) used for selecting the predetermined alignment sites is different than an imagingmode or imaging modes of the inspection system used to acquire the inspection data. In someembodiments, determining the positions of the alignment sites is performed before inspection of the wafer,and determining the position of the inspection data is performed during the inspection of the wafer. In 5 other embodiments, determining the position of the inspection data is performed subsequent to inspectionof the wafer. In one such embodiment, determining the position of the inspection data is performed forportions of the inspection data corresponding to defects detected on the wafer and not for portions of theinspection data that do not correspond to the defects. In this manner, the position of the inspection data indesign data space may be determined only for inspection data (e.g., patch images) acquired at defectivelocations on the wafer.

In another embodiment, the data for the alignment sites is within a swath of the inspection data. In onesuch embodiment, determining the position of the inspection data includes determining the position of theswath in the design data space based on the positions of the alignment sites in the design data space anddetermining the position of an additional swath of the inspection data in the design data space based onthe position of the swath.

In one embodiment, the method includes determining a sensitivity for detecting defects on differentportions of the wafer based on the position of the inspection data in the design data space and one or moreattributes of design data in the design data space. In one such embodiment, the one or more attributes ofthe design data are selected based on one or more attributes of previously acquired inspection data for thewafer, other wafers, or some combination thereof for the design data, different design data, or somecombination thereof for a process layer for which the inspection data for the wafer was acquired, fordifferent process layers, or some combination thereof. In another such embodiment, the one or moreattributes of the design data are selected based on yield criticality of defects previously detected in thedifferent portions, fault probability of the defects previously detected in the different portions, or somecombination thereof.

In another embodiment, the method includes determining a sensitivity for detecting defects on differentportions of the wafer based on the position of the inspection data in the design data space and a contextmap, which includes values for one or more attributes of design data across the design data space. In onesuch embodiment, determining the sensitivity includes determining sensitivity thresholds used with theinspection data to detect the defects on the different portions of the wafer. In another such embodiment,determining the sensitivity is performed by the inspection system during inspection of the wafer. In afurther such embodiment, determining the sensitivity is performed after acquisition of the inspection datafor the wafer has been completed.

In an additional embodiment, the method includes determining a sensitivity for detecting defects ondifferent portions of the wafer based on the position of the inspection data in the design data space, one ormore attributes of design data in the design data space, and one or more attributes of the inspection data. 6

In one such embodiment, the one or more attributes of the inspection data include one or more image noise attributes, if defects were detected in the different portions, or some combination thereof.

In some embodiments, the method includes altering one or more parameters for detecting defects on thewafer based on one or more attributes of schematic data for a design of a device being fabricated on thewafer, one or more attributes of expected electrical behavior of a physical layout for the device, or somecombination thereof. In another embodiment, the method includes altering one or more parameters fordetecting defects on the wafer using the inspection data based on one or more parameters of an electricaltest process to be performed on the wafer. In an additional embodiment, the method includes altering oneor more parameters of an electrical test process to be performed on the wafer based on defects detected onthe wafer using the inspection data.

In a further embodiment, the method includes periodically altering one or more parameters of aninspection process performed by the inspection system based on results of one or more steps of themethod using a feedback control technique. In another embodiment, the method includes automaticallyaltering one or more parameters of an inspection process performed by the inspection system based onresults of one or more steps of the method using a feedback control technique. In yet another embodiment,the method includes generating a knowledge base using results of one or more steps of the method andgenerating an inspection process performed by the inspection system using the knowledge base.

In another embodiment, the method includes classifying defects detected on different portions of thewafer based on the positions of portions of the inspection data corresponding to the defects in the designdata space and a context map, which includes values for one or more attributes of design data across thedesign data space. In one such embodiment, classifying the defects is performed by the inspection systemduring inspection of the wafer. In another such embodiment, classifying the defects is performed afteracquisition of the inspection data for the wafer has been completed.

In another embodiment, the inspection data includes data for a defect or defects on the wafer. In one suchembodiment, the method includes determining positions of the defects in the design data space based onthe position of the inspection data in the design data space and determining if the defects are nuisancedefects based on the positions of the defects in the design data space and one or more attributes of designdata in the design data space. In such an embodiment, the method may include determining if the defectsnot determined to be nuisance defects are systematic or random defects based on the one or moreattributes of the design data in the design data space. Determining if the defects are spatially systematicdefects or random defects may also be performed based on one or more attributes of the design data indesign data space in combination with other information such as historical fab data or other data 7 corresponding to a hot spot in the design data. In such an embodiment, the method may also includedetermining if the defects are systematic or random defects based on the position of the inspection data inthe design data space and one or more statistically determined attributes of the inspection data. In oneembodiment, the inspection data is acquired for process window qualification. In another embodiment,the method includes classifying the defect based on the position of the inspection data in the design dataspace and one or more attributes of design data in the design data space.

In one embodiment, the method includes binning the defects into groups based on the position of theinspection data in the design data space and one or more attributes of design data in the design data space.In some embodiments, the method includes binning the defects into groups based on the position of theinspection data in the design data space, one or more attributes of design data in the design data space,and one or more attributes of reticle inspection data acquired for a reticle on which the design data isprinted. In an additional embodiment, the method includes binning the defects into groups based on theposition of the inspection data in the design data space, one or more attributes of design data in the designdata space, and one or more attributes of the inspection data. In some embodiments, the method includesbinning the defects into groups based on the position of the inspection data in the design data space, oneor more attributes of design data in the design data space, one or more attributes of the inspection data,and one or more attributes of reticle inspection data acquired for a reticle on which the design data isprinted. In a further embodiment, the method includes binning the defects into groups based on theposition of the inspection data in the design data space, one or more attributes of design data in the designdata space, one or more attributes of the inspection data, and one or more attributes of previously acquiredinspection data for the wafer, other wafers, or some combination thereof for the design data, differentdesign data, or some combination thereof for a process layer for which the inspection data for the waferwas acquired, for different process layers, or some combination thereof.

As described above, the inspection data may include data for a defect or defects on the wafer. In one suchembodiment, the method includes selecting at least a portion of the defects for review based on theposition of the inspection data in the design data space and one or more attributes of design data in thedesign data space. In a further such embodiment, the method includes determining a sequence in whichthe defects are to be reviewed based on the position of the inspection data in the design data space andone or more attributes of design data in the design data space. In yet another such embodiment, themethod includes selecting at least a portion of the defects for review, and at least the portion of the defectsincludes at least one defect located within each portion of design data in the design data space havingdifferent values of one or more attributes of the design data. Defect review sampling may also oralternatively be performed based on one or more attributes of groups into which the defects are binned. 8

The defects may be binned as described further herein, and the one or more attributes of the groups maybe determined based on one or more attributes of the design data or in any other manner described herein.

In another embodiment, the method includes extracting one or more predetermined attributes of outputfrom one or more detectors of the inspection system acquired for different portions of the wafer based onthe position of the inspection data in the design data space and one or more attributes of design data in thedesign data space. In one such embodiment, the one or more attributes of the design data are selectedbased on one or more attributes of previously acquired inspection data for the wafer, other wafers, orsome combination thereof for the design data, different design data, or some combination thereof for aprocess layer for which the inspection data for the wafer was acquired, for different process layers, orsome combination thereof.

In another embodiment, the method includes extracting one or more predetermined attributes of outputfrom one or more detectors of the inspection system acquired for different portions of the wafer based onthe position of the inspection data in the design data space, one or more attributes of design data in thedesign data space, and one or more attributes of the inspection data. In one such embodiment, the one ormore attributes of the inspection data include one or more image noise attributes, if one or more defectswere detected in the different portions, or some combination thereof.

In some embodiments, the method includes determining a fault probability value for one or more defectsdetected on the wafer based on the position of the inspection data in the design data space and one ormore attributes of design data in the design data space.

In another embodiment, the method includes determining coordinates of positions of defects detected onthe wafer in the design data space based on the position of the inspection data in the design data space andtranslating the coordinates of the positions of the defects to design cell coordinates based on a floor planfor the design data. In one such embodiment, the method includes determining different regionssurrounding the defects using an overlay tolerance and performing defect repeater analysis using thedifferent regions for one or more cell types to determine if the one or more cell types are systematicallydefective cell types and to determine one or more locations of one or more systematically defectivegeometries within the systematically defective cell types. In one such embodiment, the method includesdetermining if spatially systematic defects occur in the systematically defective cell types based on one ormore attributes of design data for cells, geometries, or some combination thereof located proximate to thesystematically defective cell types. 9

In another embodiment, the method includes determining a position of a defect detected on the wafer inthe design data space based on the position of the inspection data in the design data space and determiningvalues for one or more attributes of design data corresponding to the position of the defect using a datastructure in which predetermined values for the one or more attributes of the design data are stored as aunction of position in the design data space.

In a further embodiment an image of a reticle generated by a reticle inspection system is used as designdata in the design data space. The reticle is used to print the design data on the wafer. In anotherembodiment, a simulated image illustrating how a reticle image would be printed on the wafer is used asdesign data in the design data space. In an additional embodiment, the method includes generating acontext map for design data in the design data space based on reticle inspection data acquired for a reticleused to print the design data on the wafer.

In one embodiment, the method includes optimizing a wafer inspection process for determiningprintability of a reticle defect on the wafer using the position of the inspection data in the design dataspace and a context map. In another embodiment, the method includes detecting defects on the waferusing the inspection data and a standard reference die for standard reference die based inspection. In anadditional embodiment, the method includes detecting defects on the wafer using the inspection data, astandard reference die, and a representation of wafer noise associated with the standard reference die in aperturbation matrix for standard reference die based inspection.

In a further embodiment the wafer and additional wafers are processed using wafer level processparameter modulation, and the method includes detecting defects on the wafer and the additional wafersby comparing inspection data for die on the wafer and the additional wafers to a common standardreference die.

Each of the steps described above may be performed based on the approximate position of the inspectiondata in the design data space, one or more attributes of design data in the design data space, historical fabdata, or other data corresponding to a hot spot in the design data. In some embodiments, the method mayinclude performing statistical process control (SPC) based on the defects, one or more attributes of groupsinto which the defects were binned, or any other results of any of the method embodiment(s) describedherein. Each of the embodiments of the method described above may include any other step(s) of anymethod(s) described herein. Each of the embodiments of the method described above may be performedby any of the system embodiments described herein. 10

Another embodiment relates to a system configured to determine a position of inspection data in designdata space. The system includes a storage medium that includes design data. The system also includes aprocessor coupled to the storage medium. The processor is configured to align data acquired by aninspection system for alignment sites on a wafer with data for predetermined alignment sites. Theprocessor is also configured to determine positions of the alignment sites on the wafer in design dataspace based on positions of the predetermined alignment sites in the design data space. In addition, theprocessor is configured to determine a position of inspection data acquired for the wafer by the inspectionsystem in the design data space based on the positions of the alignment sites on the wafer in the designdata space. This embodiment of the system may be further configured as described herein.

An additional embodiment relates to a system configured to determine a position of inspection data indesign data space. This system includes an inspection system configured to acquire data for alignmentsites on a wafer and inspection data for the wafer. The system also includes a storage medium thatincludes design data. In addition, the system includes a processor coupled to the inspection system andthe storage medium. The processor is configured to align the data for the alignment sites on the waferwith data for predetermined alignment sites. The processor is also configured to determine positions ofthe alignment sites on the wafer in design data space based on positions of the predetermined alignmentsites in the design data space. In addition, the processor is configured to determine a position of theinspection data in the design data space based on the positions of the alignment sites on the wafer in thedesign data space. This embodiment of the system may be further configured as described herein.

An additional embodiment relates to a system configured to determine positions of design data-based careareas (e.g., areas to inspect, areas to be inspected with higher sensitivity, or areas to be inspected withlower sensitivity) in inspection space at run time (e.g., during the inspection process). In addition, thesystem may be configured to substantially accurately assign acquired pixels of data to the correct carearea during the inspection process. The size and frequency of such care areas may approach the size andfrequency of design geometries on the die. This system may be further configured as described herein. A further embodiment relates to a computer-implemented method for binning defects detected on a wafer.The method includes comparing portions of design data proximate positions of the defects in design dataspace. The method also includes determining if the design data in the portions is at least similar based onresults of the comparing step. Determining if the design data in the portions is at least similar may includerotating and/or mirroring one or more of the portions. In addition, the method includes binning the defectsin groups such that the portions of the design data proximate the positions of the defects in each of the 11 groups are at least similar. The method further includes storing results of the binning step in a storage medium.

In one embodiment, dimensions of the portions are determined based, at least in part, on positions of thedefects reported by an inspection system used to detect the defects, coordinate inaccuracy of theinspection system, one or more attributes of the design data, defect size error of the inspection system, orsome combination thereof. In another embodiment, dimensions of at least some of the portions aredifferent.

In one embodiment, the design data in the portions includes design data for more than one design layer. Inthis manner, the design data used in the methods described herein may be design data for one or morelayers of the design. Using design data for one or more layers of the design in the methods describedherein may be useful in instances such as when the defects are detected using bright field (BF) inspection,which may detect defects on more than one layer, and if the criticality of a location may depend on whathappens on previous or following layers of the design. The method described above may include binningsome or all defects of interest into groups with at least similar design data.

In another embodiment, the comparing step includes comparing an entirety of the design data in at leastsome of the portions to the design data in others of the portions. In a different embodiment, the comparingstep includes comparing different regions of the design data in at least some of the portions to the designdata in others of the portions.

In one embodiment, the method includes determining the positions of the defects in the design data spaceby comparing data acquired by an inspection system for alignment sites on the wafer with data forpredetermined alignment sites. In another embodiment, the method includes determining the positions ofthe defects in the design data space by comparing data acquired by an inspection system during detectionof the defects to locations in the design data determined by review.

It is noted that alignment accuracy depends on both coordinate transformation from design to wafer andcoordinate accuracy of the inspection system. Preferably, therefore, the coordinates reported by theinspection system are substantially accurate. In addition, the measurements for alignment sites may beperformed using logical inspection coordinates. (Inspection systems output logical wafer coordinates, butdefect review tools such as scanning electron microscopes (SEMs) measure physical wafer coordinates.Therefore, the physical coordinates on the wafer may be corrected by the inspection system to account fordifference in reticle offset, scaling and slight rotation when compared to the expected wafer layout. As 12 such, these corrections may also be applied to the SEM measurements to reduce errors between the two coordinate systems from reticle to reticle.)

In one embodiment, the binning step includes binning the defects in the groups such that the portions ofthe design data proximate the positions of the defects in each of the groups are at least similar and suchthat one or more attributes of the defects in each of the groups are at least similar. In one suchembodiment, the one or more attributes include one or more attributes of results of inspection in whichthe defects were detected, one or more parameters of the inspection, or some combination thereof.

In some embodiments, the portions of the design data proximate the positions of the defects include thedesign data on which the defects are located. In another embodiment, the portions of the design dataproximate the positions of the defects include the design data around the positions of the defects.

In another embodiment, the binning step includes binning the defects in the groups such that the portionsof the design data proximate the positions of the defects in each of the groups are at least similar and suchthat positions of the defects in each of the groups with respect to polygons in the portions are at leastsimilar.

In a further embodiment, the method includes determining a defect criticality index (DCI) for one or moreof the defects. In another embodiment, the method includes determining a probability that one or more ofthe defects will cause one or more electrical faults in a device fabricated for the design data based on oneor more attributes of the design data proximate the positions of the defects, one or more attributes of thedefects, positions of the defects reported by an inspection system used to detect the defects, coordinateinaccuracy of the inspection system, or some combination thereof. In one such embodiment, the methodalso includes determining a DCI for the one or more of the defects based on the probability.

In some embodiments, the method includes identifying one or more hot spots in the design data based onresults of the binning step. In another embodiment, the method includes selecting at least some of thedefects for review based on results of the binning step. In an additional embodiment, the method includesgenerating a process for sampling the defects for review based on the results of the binning step. In afurther embodiment, the method includes altering a process for inspecting the wafer based on the resultsof the binning step. In some embodiments, the method includes altering a process for inspection of thewafer during the inspection based on results of the inspection. In yet another embodiment, the methodincludes altering a metrology process for the wafer based on the results of the binning step. In a furtherembodiment, the method includes altering a sampling plan for a metrology process for the wafer based onthe results of the binning step. In still another embodiment, the method includes monitoring systematic 13 defects, potential systematic defects, or some combination thereof over time using the results of the binning step.

In yet another embodiment, the defects were detected by an inspection process, and the method includesreviewing locations on the wafer at which one or more patterns of interest (POIs) in the design data areprinted, determining based on results of the reviewing step if defects should have been detected at thelocations of the one or more POIs, and altering the inspection process to improve one or more defectcapture rates.

In some embodiments, the method includes prioritizing one or more POIs in the design data andoptimizing one or more processes to be performed on wafers on which the design data will be printedbased on results of the prioritizing step. In another embodiment, the method includes prioritizing one ormore POIs in the design data and optimizing at least one of the one or more POIs based on results of theprioritizing step. In an additional embodiment, the method includes prioritizing one or more POIs in thedesign data and optimizing one or more resolution enhancement technology (RET) features of the one ormore POIs based on results of the prioritizing step.

In one embodiment, the defects are detected by optical inspection. In some embodiments, the defects aredetected by electron beam inspection. In another embodiment, the defects are detected in a processwindow qualification (PWQ) method.

In some embodiments, the method includes determining if one or more of the groups of defectscorrespond to nuisance defects by reviewing at least some of the defects in the one or more of the groupsand removing the one or more of the groups corresponding to the nuisance defects from results of aninspection process in which the defects were detected to increase signal-to-noise ratio of the results of theinspection process. In another embodiment, the method includes classifying one or more of the groups ofdefects based on results of review of at least some of the defects in the one or more of the groups, one ormore attributes of design data, one or more attributes of the defects, or some combination thereof. In anadditional embodiment, the method includes determining a root cause of one or more of the groups ofdefects based on results of review of at least some of the defects in the one or more of the groups, one ormore attributes of the design data, one or more attributes of the defects, or some combination thereof.

In one embodiment, the method includes determining a root cause of one or more of the groups of defectsby mapping at least some of the defects in the one or more of the groups to experimental process windowresults. In another embodiment, the method includes determining a root cause of one or more of the 14 groups of defects by mapping at least some of the defects in the one or more of the groups to simulated process window results.

In some embodiments, the method includes modeling electrical properties of a device being fabricatedusing the design data about a defect location and determining parametric relevancy of a defect at thedefect location based on results of the modeling step. In another embodiment, the method includesmonitoring a kill probability (KP) value of one or more of the defects based on one or more attributes ofthe design data. In an additional embodiment, the method includes monitoring a KP value for one or morePOIs in the design data and assigning the KP value for the one or more POIs to one or more of the groupsif the portions of the design data proximate the positions of the defects binned into the one or more of thegroups correspond to the one or more POIs.

In some embodiments, one or more of the steps of the methods described herein may be performed by theinspection system (i.e., "on tool") or by a processor physically separate from, but perhaps coupled to theinspection system by a transmission medium (i.e., "off tool"). For instance, in one embodiment, thecomputer-implemented method is performed by an inspection system used to detect the defects. In analternative embodiment, the computer-implemented method is performed by a system other than aninspection system used to detect the defects.

In another embodiment, the determining step includes determining if common patterns in the design datain the portions are at least similar. In an additional embodiment, the determining step includesdetermining if common attributes of the design data in the portions are at least similar. In a furtherembodiment, the determining step includes determining if common attributes in feature space of thedesign data in the portions are at least similar.

In one embodiment, the method includes determining a percentage of a die formed on the wafer impactedby one or more of the groups of defects. In another embodiment, the method includes determining one ormore POIs in the design data corresponding to at least one of the groups and determining a ratio ofnumber of defects binned in the at least one of the groups corresponding to the one or more POIs tonumber of locations of the one or more POIs on the wafer. In an additional embodiment, the methodincludes determining one or more POIs in the design data corresponding to at least one of the groups anddetermining a ratio of number of the defects binned in the at least one of the groups corresponding to theone or more POIs to number of locations of the one or more POIs in the design data.

In a further embodiment, the method includes determining a POI in the design data corresponding to atleast one of the groups, determining a percentage of a die formed on the wafer in which the defects binned 15 in the at least one of the groups are located, and assigning a priority to the POI based on the percentage.In some embodiments, the method includes prioritizing one or more of the groups by number of totaldesign instances on the wafer at which the defects in the one or more of the groups are detected. Inanother embodiment, the method includes prioritizing one or more of the groups by number of designinstances on a reticle, used to print the design data on the wafer, at which the defects in the one or more ofthe groups are detected at least once. In an additional embodiment, the method includes determiningreticle-based marginality for one or more of the groups based on number of locations on a reticle at whichdefects binned into one or more of the groups were detected and total number of portions of the designdata printed on the reticle that are at least similar to the portions of the design data proximate to thepositions of the defects binned into the one or more of the groups.

In one embodiment, the method includes converting the portions of the design data proximate thepositions of the defects in the design data space to bitmaps prior to the comparing step. In one suchembodiment, the comparing step includes comparing the bitmaps to each other.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein.

Another embodiment relates to a method for determining a DCI for a defect detected on a wafer. Themethod includes determining a probability that the defect will alter one or more electrical attributes of adevice being fabricated on the wafer based on one or more attributes of design data, for the device,proximate the position of the defect in design data space. The method also includes determining the DCIfor the defect based on the probability that the defect will alter the one or more electrical attributes. Inaddition, the method includes storing the DCI in a storage medium.

In one embodiment, the defect includes a random defect. In another embodiment, the defect includes asystematic defect. In an additional embodiment, the one or more electrical attributes include functionalityof the device. In a further embodiment, the one or more electrical attributes include one or more electricalparametrics of the device.

In one embodiment, the one or more attributes of the design data include redundancy, net list, or somecombination thereof. In another embodiment, the one or more attributes of the design data includedimensions of features in the design data, density of features in the design data, or some combinationthereof. 16

In one embodiment, determining the probability includes determining the probability using a correlationbetween electrical test results for the design data and the one or more attributes of the design data. Inanother embodiment, determining the probability includes determining the probability based on the one ormore attributes of the design data in combination with a probability of the position of the defect within thedesign data space, a position of the defect reported by an inspection system used to detect the defect,coordinate inaccuracy of the inspection system, a size of the defect, defect size error of the inspectionsystem, or some combination thereof. In one such embodiment, the defect includes a random defect.

In some embodiments, determining the probability includes determining the probability based on the oneor more attributes of the design data in combination with one or more attributes of the defect. In one suchembodiment, the defect includes a systematic defect.

In one embodiment, determining the DCI includes determining the DCI for the defect based on theprobability in combination with a classification assigned to the defect. In another embodiment, the one ormore attributes of the design data include one or more attributes of the design data for more than onedesign layer for the device.

In one embodiment, the method includes determining the design data proximate the position of the defectby determining a position of inspection data in the design data space. In another embodiment, the methodincludes determining the design data proximate the position of the defect by defect alignment. In someembodiments, the method includes determining the design data proximate the position of the defect based,at least in part, on a position of the defect reported by an inspection system used to detect the defect,coordinate inaccuracy of the inspection system, one or more attributes of the design data, defect size,defect size error of the inspection system, or some combination thereof.

In one embodiment, the method includes modifying the DCI based on sensitivity of yield of the designdata to defects. In another embodiment, the method includes altering a process performed on the defectbased on the DCI determined for the defect. In an additional embodiment, the method includes altering aprocess used to detect the defect based on the DCI determined for the defect. In a further embodiment, themethod includes generating a process for inspection of additional wafers on which the device will befabricated based on the DCI for the defect.

In one embodiment, the computer-implemented method is performed by an inspection system used todetect the defect. In another embodiment, the computer-implemented method is performed by a systemother than an inspection system used to detect the defect. 17

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein.

Another embodiment relates to a computer-implemented method for determining a memory repair index(MRI) for a memory bank formed on a wafer. The method includes determining a number of redundantrows and a number of redundant columns required to repair the memory bank based on defects located inan array block area of the memory bank. The method also includes comparing the number of theredundant rows required to repair the memory bank to an amount of available redundant rows for thememory bank. In addition, the method includes comparing the number of the redundant columns requiredto repair the memory bank to an amount of available redundant columns for the memory bank. Themethod further includes determining the MRI for the memory bank based on results of comparing thenumber of the redundant rows and comparing the number of the redundant columns. The MRI indicates ifthe memory bank is repairable. The method also includes storing the MRI in a storage medium.

In one embodiment, the method includes determining which of the defects located in the array block areawill cause bits in the memory bank to fail and determining positions of the bits that will fail based onlocations of the defects that will cause the bits to fail. In one such embodiment, determining the numberof the redundant rows and the number of the redundant columns required to repair the memory bank isperformed using the positions of the bits that will fail.

In another embodiment, the method includes altering one or more parameters of an electrical test processbased on the MRI using a feed forward control technique. In an additional embodiment, the methodincludes altering one or more parameters of an electrical test process based on the MRI using a feedforward control technique such that if the memory bank is not repairable, a die in which the memory bankis located is not tested during the electrical test process. In a further embodiment, the method includesaltering one or more parameters of a repair process based on one or more attributes of the defects locatedin the array block area of the memory bank, the MRI, or some combination thereof.

In one embodiment, the defects include defects detected at a gate layer of the memory bank. In anotherembodiment, the defects include defects detected at a metal layer of the memory bank.

In some embodiments, the method includes predicting bit failure modes of the defects based on locationsof the defects in the memory bank. In another embodiment, the method includes determining a DCI forone or more of the defects located in the array block area. In one such embodiment, determining the 18 number of the redundant rows and the number of the redundant columns required to repair the memory bank is performed using the DCIs for the one or more of the defects.

In one embodiment, comparing the number of the redundant rows is performed separately for each bankof a memory die, and comparing the number of the redundant columns is performed separately for eachbank of the memory die. In some embodiments, the method includes determining the amount of theavailable redundant rows and the amount of the available redundant columns based on defects located inthe redundant rows and the redundant columns of the memory bank.

In one embodiment, the method includes determining the MRI for more than one memory bank formed ina die and predicting a repair yield for the die based on the MRIs for the more than one memory bank. Inanother embodiment, the method includes determining, based on the MRI, if the amount of the availableredundant columns, the amount of the available redundant rows, or some combination thereof in thememory bank should be evaluated by a designer of the memory bank.

In some embodiments, the method includes determining the MRI for each memory bank in one or moredies on the wafer and determining a memory repair yield for the one or more dies based on the MRI is foreach memory bank. In some such embodiments, the method includes performing wafer disposition basedon the one or more memory repair yields for the one or more dies on the wafer.

In one embodiment, comparing the number of the redundant rows includes determining a fraction of theredundant rows needed to repair the memory bank, comparing the number of the redundant columnsincludes determining a fraction of the redundant columns needed to repair the memory bank, anddetermining the MRI for the memory bank includes determining the MRI based on the fraction of theredundant rows and the fraction of the redundant columns. In some such embodiments, the methodincludes determining the MRI for each memory bank in one or more dies on the wafer and determining amemory repair yield for the one or more dies based on the MRIs for each memory bank. In additionalsuch embodiments, the method includes determining a memory repair yield for the wafer based on thememory repair yields for each of the one or more dies.

In one embodiment, the MRI also indicates a probability that the memory repair bank will not berepairable. In one such embodiment, the method includes determining the MRI for each memory bank inone or more dies on the wafer and determining a MRI for the one or more dies based on the MRI for eachof the memory banks in the one or more dies, and the MRIs for the one or more dies indicate a probabilitythat the one or more dies will not be repairable. In one such embodiment, the method includes 19 determining a wafer based yield prediction based on thresholding of the MRIs for the one or more dies onthe wafer.

In one embodiment, the method includes determining a number of non-repairable defects in the memorybank based on a number of defects located in a decoder area of the memory bank, a number of defectslocated in a sense amp area of the memory bank, or some combination thereof.

In some embodiments, determining the number of the redundant rows and the number of the redundantcolumns includes determining a DCI for each of the defects located in the array block area of the memorybank, comparing the DCIs to a predetermined threshold, and determining the number of the redundantrows and the number of the redundant columns required to repair all of the defects having a DCI abovethe predetermined threshold.

In one embodiment, the method includes determining a MRI for failure of the memory bank due to thedefects located in the array block area of the memory bank. In another embodiment, the method includesdetermining a MRI for failure of the memory bank due to defects located in the redundant rows and theredundant columns of the memory bank.

In some embodiments, the method includes generating a stacked map of like memory bank designsillustrating spatial correlations between defects detected in the memory banks. In another embodiment,the method includes determining the MRI on a die basis. In an additional embodiment, the methodincludes determining an index indicating if a die on the wafer will fail due to the defects located in thearray block area.

In one embodiment, the method includes determining the MRI for memory banks in a die on the waferand generating a stacked map of the die illustrating spatial correlations between two or more of thememory banks indicated by the MRIs to not be repairable. In another embodiment, the method includesdetermining the MRI for memory banks in a die on the wafer and generating a stacked map of a reticleused to form the memory banks on the wafer illustrating spatial correlations between two or more of thememory banks indicated by the MRIs to not be repairable.

In some embodiments, the method includes identifying memory banks of a die impacted by defectsdetected in the die and ranking the memory banks based on the impact of the defects on the memorybanks. In another embodiment, the method includes determining a percentage of memory banks formedon the wafer impacted by defects in non-repairable areas of the memory banks. In an additionalembodiment, the method includes generating a stacked wafer map of probable failures in memory banksformed on the wafer illustrating spatial correlations between the probable failures. In a further 20 embodiment, the method includes determining the MRI for more than one die formed on the wafer and ranking the more than one die based on the MRIs.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein.

Another embodiment relates to a different computer-implemented method for binning defects detected ona wafer. The method includes comparing positions of the defects in design data space with positions ofhot spots in design data. Hot spots located proximate to design data that is at least similar are correlatedwith each other. The method also includes associating the defects and the hot spots having positions thatare at least similar. In addition, the method includes binning the defects in groups such that the defects ineach of the groups are associated with only hot spots that are correlated with each other. The methodfurther includes storing results of the binning step in a storage medium.

In one embodiment, the method includes correlating the hot spots by identifying a location of a POI in thedesign data associated with a systematic defect, correlating the POI with similar patterns in the designdata, and correlating the location of the POI and locations of the similar patterns in the design data aspositions of correlated hot spots.

In some embodiments, the method includes assigning a DBC to one or more of the groups. In anotherembodiment, the computer-implemented method is performed by an inspection system used to detect thedefects on the wafer. In a further embodiment, the method includes monitoring the hot spots using resultsof inspection of one or more wafers on which the design data is printed.

In one embodiment, the method includes inspecting the wafer based on correlations between the hot spots.In another embodiment, the method includes monitoring systematic defects, potential systematic defects,or some combination thereof over time using the results of the binning step. In an additional embodiment,the method includes performing review of the defects based on the results of the binning step. In a furtherembodiment, the method includes generating a process for selecting the defects for review based on theresults of the binning step.

In one embodiment, the method includes identifying systematic defects and potential systematic defects inthe design data based on the results of the binning step and monitoring occurrence of the systematicdefects and the potential systematic defects over time. In another embodiment, the method includesgenerating a process for inspecting wafers on which the design data has been printed based on the results 21 of the binning step. In an additional embodiment, the method includes altering a process for inspecting wafers on which the design data has been printed based on the results of the binning step.

In some embodiments, the method includes determining a percentage of a die formed on the waferimpacted by one or more of the groups of defects. In another embodiment, the method includesdetermining a DCI for one or more of the defects. In an additional embodiment, the method includesdetermining a percentage of a die formed on the wafer in which the defects binned in at least one of thegroups are located and assigning a priority to the at least one of the groups based on the percentage.

In one embodiment, the method includes prioritizing one or more of the groups by number of total hotspots correlated with the hot spots associated with the defects in the one or more of the groups andnumber of the defects in the one or more of the groups. In another embodiment, the method includesprioritizing one or more of the groups by number of corresponding hot spot locations on a reticle used toprint the design data on the wafer at which the defects in the one or more of the groups are detected atleast once.

In some embodiments, the method includes determining reticle-based marginality for one or more of thegroups based on number of locations on a reticle at which defects binned into the one or more of thegroups were detected and total number of hot spot locations on the reticle that are correlated with the hotspots associated with the defects in the one or more of the groups.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein.

Another embodiment relates to a different computer-implemented method for binning defects detected ona wafer. The method includes comparing one or more attributes of design data proximate positions of thedefects in design data space. The method also includes determining if the one or more attributes of thedesign data proximate the positions of the defects are at least similar based on results of the comparingstep. In addition, the method includes binning the defects in groups such that the one or more attributes ofthe design data proximate the positions of the defects in each of the groups are at least similar. Themethod further includes storing results of the binning step in a storage medium.

In one embodiment, the one or more attributes include pattern density. In another embodiment, themethod includes determining if the defects are random or systematic defects using the one or moreattributes. In an additional embodiment, the method includes ranking one or more of the groups using theone or more attributes. In a further embodiment, the method includes ranking the defects in at least one of 22 the groups using the one or more attributes. In some embodiments, the one or more attributes include theone or more attributes in feature space.

In one embodiment, the method includes binning the defects within at least one of the groups into sub-groups using the one or more attributes. In another embodiment, the method includes analyzing thedefects within at least one of the groups using the one or more attributes. In an additional embodiment,the method includes determining a yield relevancy of one or more of the defects using the one or moreattributes. In a further embodiment, the method includes determining overall yield relevancy of one ormore of the groups using the one or more attributes. In yet another embodiment, the method includesassigning a DCI to one or more of the defects using the one or more attributes.

In some embodiments, the method includes separating the design data proximate the positions of thedefects into the design data in an area around the defects and the design data in an area on which thedefects are located. In another embodiment, the method includes identifying structures in the design datafor binning or filtering using rules and the one or more attributes.

In one embodiment, the method includes determining locations on the wafer at which review,measurement, test, or some combination thereof is to be performed based on inspection results generatedduring detection of the defects and based on the defects identified as systematic defects. In anotherembodiment, the method includes determining locations on the wafer at which review, measurement, test,or some combination thereof is to be performed based on inspection results generated during detection ofthe defects, the defects identified as systematic defects, and yield relevancy of the defects. In anadditional embodiment the method includes determining locations on the wafer at which review,measurement, test, or some combination thereof is to be performed based on inspection results generatedduring detection of the defects, the defects identified as systematic defects, and process window mapping.

In one embodiment, the method includes performing systematic discovery using the results of the binningstep and user-assisted review. In another embodiment, the method includes prior to the comparing step,separating the defects based on functional blocks in which the defects are located to improve signal-to-noise in the results of the binning step.

In some embodiments, the design data is organized by design into hierarchical cells, and the methodincludes prior to the comparing step, separating the defects based on the hierarchical cells in which thedefects are located to improve signal-to-noise in the results of the binning step. In another embodiment,the design data is organized by design into hierarchical cells, and if a defect could be located in more thanone of the hierarchical cells, the method includes correlating the defect to each of the hierarchical cells 23 based on a probability that the defect is located in each of the hierarchical cells based on area of the hierarchical cells, defect positional probability, or some combination thereof.

In one embodiment, the defects were detected by an inspection process, and the method includesreviewing locations on the wafer at which one or more POIs in the design data are printed, determiningbased on results of the reviewing step if defects should have been detected at the locations of the one ormore POIs, and altering the inspection process to improve one or more defect capture rates.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein.

Another embodiment relates to a computer-implemented method for assigning classifications to defectsdetected on a wafer. The method includes comparing portions of design data proximate positions of thedefects in design data space with design data (e.g., POI design examples) corresponding to differentDBCs (e.g., different DBC bin definitions). The design data corresponding to the different DBCs and thedifferent DBCs are stored in a data structure. The method also includes determining if the design data inthe portions is at least similar to the design data corresponding to the different DBCs based on results ofthe comparing step. In addition, the method includes assigning to the defects the DBCs corresponding tothe design data that is at least similar to the design data in the portions. The method further includesstoring results of the assigning step in a storage medium.

In one embodiment, the computer-implemented method is performed by an inspection system used todetect the defects. In another embodiment, the computer-implemented method is performed by a systemother than an inspection system used to detect the defects.

In one embodiment, the method includes monitoring hot spots in the design data based on the results ofthe assigning step. In another embodiment, the design data corresponding to the different DBCs isidentified by grouping defects detected on one or more other wafers based on portions of the design dataproximate positions of the defects detected on the one or more other wafers in the design data space.

In some embodiments, the defects were detected in an inspection process, and the method includesreviewing locations on the wafer at which one or more POIs in the design data are printed, determiningbased on results of the reviewing step if defects should have been detected at the locations of the one ormore POIs, and altering the inspection process to improve one or more defect capture rates. 24

In one embodiment, the method includes determining if the defects are nuisance defects based on theDBCs assigned to the defects and removing the nuisance defects from results of an inspection process inwhich the defects were detected to increase signal-to-noise ratio of the results of the inspection process.

In another embodiment, the method includes determining a KP value for one or more of the defects. In anadditional embodiment, the method includes determining if the DBCs assigned to the defects correspondto systematic defects that are visible to a review system and sampling the defects for review by selectingonly the defects that are visible to the review system for the review. In a further embodiment, the methodincludes determining one or more POIs in the design data by identifying one or more features in thedesign data indicative of a pattern dependent defect.

In one embodiment, the DBCs identify one or more polygons in the design data on which the defects arelocated or located near the defects. In another embodiment, the DBCs identify locations of the defects inone or more polygons in the design data. In an additional embodiment, the data structure includes alibrary containing examples of the design data (e.g. POI design examples for DBC bin definitions)organized by technology, process, or some combination thereof.

In some embodiments, the method includes separating the design data proximate the positions of thedefects into the design data in areas around the defects and the design data in areas on which the defectsare located. In another embodiment, the method includes monitoring systematic defects, potentialsystematic defects, or some combination thereof over time using the results of the assigning step. In anadditional embodiment, the method includes determining a KP value for one or more of the DBCs basedon one or more attributes of the design data corresponding to the DBCs. The KP value may also bedetermined based on the one or more attributes of the design data and electrical test data corresponding tothe DBCs. In a further embodiment, the method includes determining a KP value for one or more of thedefects based on one or more attributes of the design data corresponding to the DBCs assigned to the oneor more of the defects. In yet another embodiment, the method includes monitoring KP values for one ormore of the DBCs and assigning to the defects the KP values for the DBCs assigned to the defects.

In one embodiment, dimensions of at least some of the portions are different. In another embodiment, thedesign data in the portions includes design data for more than one design layer. In another embodiment,the method includes determining the positions of the defects in the design data space by comparing dataacquired by an inspection system for alignment sites on the wafer with data for predetermined alignmentsites. In an additional embodiment, the method includes determining the positions of the defects in thedesign data space by comparing data acquired by an inspection system during detection of the defects tolocations in the design data determined by review. 25

In one embodiment, the assigning step includes assigning to the defects the DBCs corresponding to thedesign data that is at least similar to the design data in the portions and that has one or more attributes thatare at least similar to one or more attributes of the design data in the portions. In one such embodiment,the one or more attributes include one or more attributes of an inspection in which the defects weredetected, one or more parameters of the inspection, or some combination thereof.

In one embodiment, the design data proximate the positions of the defects include the design data onwhich the defects are located. In another embodiment, the design data proximate the positions of thedefects includes the design data around the positions of the defects. In an additional embodiment, themethod includes binning the defects assigned one or more of the DBCs in groups such that the positionsof the defects in each of the groups with respect to polygons in the portions of the design data proximatethe positions of the defects are at least similar.

In one embodiment, the method includes selecting at least some of the defects for review based on theresults of the assigning step. In another embodiment, the method includes generating a process forsampling the defects for review based on the results of the assigning step. In an additional embodiment,the method includes altering a process for inspecting the wafer based on the results of the assigning step.In some embodiments, the method includes altering a process for inspection of the wafer during theinspection based on results of the inspection. In a further embodiment, the method includes altering ametrology process for the wafer based on the results of the assigning step. In yet another embodiment, themethod includes altering a sampling plan for a metrology process for the wafer based on the results of theassigning step. In addition, the method may include determining locations on the wafer at whichmeasurement, test, review, or some combination thereof is to be performed at run time based on results ofthe assigning step.

In another embodiment the method includes prioritizing one or more of the DBCs and optimizing one ormore processes to be performed on wafers on which the design data will be printed based on results of theprioritizing step.

In one embodiment, the method includes determining a root cause of the defects based on the DBCsassigned to the defects. In another embodiment, the method includes determining a root cause of at leastsome of the defects by mapping the at least some of the defects to experimental process window results.In an additional embodiment, the method includes determining a root cause of at least some of the defectsby mapping the at least some of the defects to simulated process window results. In a further embodiment,the method includes determining a root cause corresponding to one or more of the DBCs and assigning aroot cause to the defects based on the root cause corresponding to the DBCs assigned to the defects. 26

In one embodiment, the method includes determining a percentage of a die formed on the wafer impactedby the defects to which one or more of the DBCs are assigned. In another embodiment, the methodincludes determining a POI in the design data corresponding to at least one of the DBCs and determininga ratio of number of the defects to which the at least one of the DBCs have been assigned to number oflocations of the POI on the wafer.

In some embodiments, the method includes determining one or more POIs in the design datacorresponding to at least one of the DBCs and determining a ratio of number of the defects to which the atleast one of the DBCs have been assigned to number of locations of the one or more POIs in the designdata. In another embodiment, the method includes determining a POI in the design data corresponding toat least one of the DBCs, determining a percentage of a die formed on the wafer in which the defects towhich the at least one of the DBCs have been assigned are located, and assigning a priority to the POTbased on the percentage.

In one embodiment, the method includes prioritizing one or more of the DBCs by number of total designinstances (e.g., of a POI design example from the DBC bin definitions) on the wafer (e.g., on theinspected region of the wafer) at which the defects to which the one or more of the DBCs have beenassigned are detected. In another embodiment the method includes prioritizing one or more of the DBCsby number of design instances on a reticle (e.g., on inspected regions of the reticle), used to print thedesign data on the wafer, at which the defects to which the one or more of the DBCs have been assignedare detected at least once.

In another embodiment, the method includes determining reticle-based marginality for one or more of theDBCs based on number of locations on a reticle (e.g., on inspection regions of the reticle) at which thedefects to which the one or more of the DBCs have been assigned were detected and total number ofportions of the design data (e.g. POI design examples from the DBC bin definitions) printed on the reticlethat are similar to the portions of the design data proximate the positions of the defects to which the oneor more of the DBCs have been assigned.

In some embodiments, the method includes converting the portions of the design data proximate thepositions of the defects to first bitmaps prior to the comparing step and converting the design datacorresponding to the DBCs to second bitmaps prior to the comparing step. In one such embodiment, thecomparing step includes comparing the first bitmaps with the second bitmaps. 27

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein. A further embodiment relates to a method for altering an inspection process for wafers. The methodincludes reviewing locations on the wafer at which one or more POIs in the design data are printed. Themethod also includes determining based on results of the reviewing step if defects should have beendetected at the locations of the one or more POIs. In addition, the method includes altering the inspectionprocess to improve one or more defect capture rates for defects located in at least some of the one or morePOIs.

In one embodiment, the altering step includes altering an optics mode of an inspection system used toperform the inspection process. In another embodiment, the altering step includes determining an opticsmode of an inspection system used to perform the inspection process based on results of the determiningstep. In an additional embodiment, the altering step includes altering the inspection process to suppressnoise in results of the inspection process. In a further embodiment, the altering step includes altering theinspection process to reduce detection of defects not of interest. In yet another embodiment, the alteringstep includes altering an algorithm used in the inspection process. In still another embodiment, thealtering step includes altering one or more parameters of an algorithm used in the inspection process.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein.

An additional embodiment relates to a system configured to display and analyze design and defect data.The system includes a user interface configured for displaying a design layout for a semiconductor device,inline inspection data acquired for a wafer on which at least a portion of the semiconductor device isformed, and electrical test data acquired for the wafer. The user interface may also be configured fordisplaying modeled data for the semiconductor device and/or failure analysis data for the wafer. Thesystem also includes a processor configured for analyzing one or more of the design layout, the inlineinspection data, and the electrical test data upon receiving an instruction to perform the analyzing from auser via the user interface. The processor may also be configured for analyzing the modeled data and/orthe failure analysis data as described above.

In one embodiment, the electrical test data includes logic bitmap data. In another embodiment, the userinterface is configured for displaying overlay of at least two of the design layout, the inline inspection 28 data, and the electrical test data, possibly in combination with any other data described herein. In one suchembodiment the electrical test data includes logic bitmap data. In some embodiments, the processor isconfigured for determining defect density in design data space upon receiving an instruction to performdetermining the defect density from the user via the user interface. In an additional embodiment, theprocessor is configured to perform defect sampling for review upon receiving an instruction to performthe defect sampling from the user via the user interface. In a further embodiment, the processor isconfigured for grouping defects based on similarity of the design layout proximate to positions of thedefects in design data space upon receiving an instruction to perform the grouping from the user via theuser interface. Each of the embodiments of the system described above may be further configured asdescribed herein. A further embodiment relates to a computer-implemented method for determining a root cause ofelectrical defects detected on a wafer. The method includes determining positions of the electrical defectsin design data space. The method also includes determining if the positions of a portion of the electricaldefects define a spatial signature corresponding to one or more process conditions. In addition, if thepositions of the portion of the electrical defects define a spatial signature that corresponds to the one ormore process conditions, the method includes identifying the root cause of the portion of the electricaldefects as the one or more process conditions. In this manner, the method may include performing spatialsignature analysis on electrical test results. The method further includes storing results of the identifyingstep in a storage medium. The embodiment of the method described above may include any other step(s)described herein. The embodiment of the method described above may be performed by any of the systemembodiments described herein.

Yet another embodiment relates to a computer-implemented method for selecting defects detected on awafer for review. The method includes identifying one or more zones on the wafer. The one or morezones are associated with positions of one or more defect types (e.g., possible systematic defects) on thewafer. The method also includes selecting defects detected in only the one or more zones for review. Inaddition, the method includes storing results of the selecting step in a storage medium. This embodimentof the method may include any other step(s) described herein. This embodiment of the method may beperformed by any of the system embodiments described herein.

There are multiple review use cases in which the method described above may be used. For example, themethod described above may be used for systematic defect verification from a list of potentiallysystematic defects, which may be performed during the discovery phase or during maintenance in themonitoring phase. In addition, the method described above may be used for systematic defect capture by 29 reviewing known hot spots or locations with local patterns (i.e., local design data) that are similar toknown hot spots (which may be identified by arbitrary pattern searching, which may be performed duringthe discovery phase or during recipe setup). The method may also be used for verification or classificationof defects detected on or near hot spots, which may be performed during the monitoring phase.

The zonal information described above may be used not only to sample defects from a particular zone, butalso to sample defects in some intelligent manner from all zones of the wafer and/or to correlate criticalareas extracted from the design to particular zones of the wafer in which there is a higher probability offinding or locating particular types of these design-determined critical areas.

Critical areas extracted from the design data may be for a single device, but the probability of finding realinspection defects due to these critical areas may be more pronounced in certain wafer zones than otherzones. In this manner, the method may include extrapolating defect information from the die to the waferusing the zonal analysis described above. This embodiment of the method may include any other step(s)described herein.

Still another embodiment relates to a computer-implemented method for evaluating one or more yieldrelated processes for design data. The method includes identifying potential failures in the design datausing rule checking, a model, or any other appropriate step or method described herein. The method alsoincludes determining one or more attributes of the potential failures. In addition, the method includesdetermining if the potential failures are detectable based on the one or more attributes. The method furtherincludes determining which of a plurality of different inspection systems is most suitable for detecting thepotential failures based on the one or more attributes. Furthermore, the method includes storing results ofdetermining which of the plurality of different inspection systems is most suitable for detecting thepotential failures in a storage medium.

In one embodiment, the method includes selecting one or more parameters of the inspection systemdetermined to be most suitable. The parameters are selected based on the one or more attributes. In thismanner, the best inspection system type may be estimated or selected based on the attribute(s) of thedefects of interest. In another embodiment, the method includes determining an impact of the potentialfailures on yield of devices fabricated with the design data. Each of the embodiments of the methoddescribed above may include any other step(s) described of any method(s) described herein. In addition,each of the embodiments of the method described above may be performed by any of the systemembodiments described herein. 30

Further embodiments relate to a carrier medium that includes program instructions executable on aprocessor to perform any computer-implemented method(s) or method(s) described herein. Additionalembodiments relate to a system configured to perform any computer-implemented method(s) ormethod(s) described herein. The system may include a processor configured to execute programinstructions for performing one or more of the computer-implemented methods or methods describedherein. In one embodiment, the system may be a stand-alone system. In another embodiment, the systemmay be part of or coupled to an inspection system such as a wafer inspection system. In a differentembodiment, the system may be part of or coupled to a defect review system. In yet another embodiment,the system may be coupled to a fab database. The system may be coupled to an inspection system, areview system, and/or a fab database by a transmission medium such as a wire, a cable, a wirelesstransmission path, and/or a network. The transmission medium may include "wired" and "wireless"portions.

BRIEF DESCRIPTION OF THE DRAWINGS

Further advantages of the present invention may become apparent to those skilled in the art with thebenefit of the following detailed description of the preferred embodiments and upon reference to theaccompanying drawings in which: FIG. 1 is a flow chart illustrating one embodiment of a computer-implemented method for determining aposition of inspection data in design data space; FIGS. 2-3 are schematic diagrams illustrating top views of different embodiments of a predeterminedalignment site; FIG. 4 is a hierarchical diagram illustrating various embodiments of a computer-implemented method forperforming a wafer-to-wafer comparison; FIG. 5 is a schematic diagram illustrating one embodiment of a computer-implemented method forperforming a wafer-to-wafer comparison; FIG. 6 is a schematic diagram illustrating a top view of one embodiment of inspection data acquired foran area of a surface of a wafer separated into annular rings; 31 FIG. 7 is a schematic diagram illustrating a top view of one embodiment of inspection data acquired for an area of a surface of a wafer separated into radial sectors; FIG. 8 is a schematic diagram illustrating another embodiment of a computer-implemented method forperforming a wafer-to-wafer comparison; FIG. 9 is a schematic diagram illustrating a top view of one embodiment of an arrangement of diesprinted on a wafer; FIG. 10 is a schematic diagram illustrating a top view of an embodiment of inspection data acquired for adie printed on a wafer separated into frames; FIG. 11 is a schematic diagram illustrating an additional embodiment of a computer-implemented methodfor performing a wafer-to-wafer comparison; FIG. 12 is a schematic diagram illustrating a top view of one embodiment of an arrangement of diesprinted on a wafer and a scan path on the wafer; FIG. 13 is a schematic diagram illustrating a top view of consecutive swaths of inspection data acquiredfor a wafer; FIG. 14 is a schematic diagram illustrating a top view of consecutive swaths of inspection data acquiredfor a wafer and alignment sites selected by the computer-implemented method for determining theposition of swath (N+1) with respect to swath N using data in a swath overlap region; FIG. 14a is a schematic diagram illustrating a top view of one embodiment of different swaths ofinspection data acquired for a wafer on which an alignment site is spaced relatively far away from the firstinspection swath; FIGS. 14b-14d are schematic diagrams illustrating top views of various embodiments of different swathsof inspection data acquired for a wafer; FIG. 15 is a flow chart illustrating another embodiment of a computer-implemented method fordetermining a position of inspection data in design data space; 32 FIG. 16 is a schematic diagram illustrating a side view of various embodiments of a system configured todetermine a position of inspection data in design data space; FIG. 17 is a schematic diagram illustrating one embodiment of a computer-implemented method forbinning defects detected on a wafer; FIG. 18 is schematic diagram illustrating a top view of one embodiment of alignment sites on a wafer inthree different die, which are located on the wafer in a triangular arrangement; FIG. 19 is a schematic diagram illustrating another embodiment of a computer-implemented method forbinning defects detected on a wafer; FIG. 20 is a schematic diagram illustrating one embodiment of input to and output from a moduleconfigured to perform a computer-implemented method for binning defects detected on a wafer accordingto the embodiments described herein. FIGS. 21-22 are schematic diagrams illustrating different embodiments of output of the module of FIG.20; FIG. 23 is a schematic diagram illustrating one embodiment of input and output of the module of FIG. 20; FIG. 24 is a schematic diagram illustrating a top view of one embodiment of output of the module of FIG.20; FIG. 25 is a schematic diagram illustrating a side view of one embodiment of a system configured todisplay and analyze design and defect data; FIG. 26 is a schematic diagram illustrating a top view of one embodiment of one or more zones on awafer associated with positions of one or more defect types on the wafer; and FIG. 27 is a flow chart illustrating one embodiment of a computer-implemented method for evaluatingone or more yield related processes for design data. 33

While the invention is susceptible to various modifications and alternative for ms , specific embodimentsthereof are shown by way of example in the drawings and may herein be described in detail. Thedrawings may not be to scale. It should be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to the particular form disclosed, but on thecontrary, the intention is to cover all modifications, equivalents and alternatives falling within the spiritand scope of the present invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As used herein, the term "wafer" generally refers to substrates formed of a semiconductor or non-semiconductor material. Examples of such a semiconductor or non-semiconductor material include, butare not limited to, monocrystalline silicon, gallium arsenide, and indium phosphide. Such substrates maybe commonly found and/or processed in semiconductor fabrication facilities. A wafer may include one or more layers formed upon a substrate. For example, such layers may include,but are not limited to, a resist, a dielectric material, and a conductive material. Many different types ofsuch layers are known in the art, and the term wafer as used herein is intended to encompass a waferincluding all types of such layers.

One or more layers formed on a wafer may be patterned or unpatterned. For example, a wafer mayinclude a plurality of dies, each having repeatable patterned features. Formation and processing of suchlayers of material may ultimately result in completed devices. Many different types of devices such asintegrated circuits (ICs) may be formed on a wafer, and the term wafer as used herein is intended toencompass a wafer on which any type of device known in the art is being fabricated.

Although embodiments are described herein with respect to wafers, it is to be understood that theembodiments may be used for another specimen such as a reticle, which may also be commonly referredto as a mask or a photomask. Many different types of reticles are known in the art, and the terms "reticle,""mask," and "photomask" as used herein are intended to encompass all types of reticles known in the art.

The term "design data" as used herein generally refers to the physical design (layout) of an IC and dataderived from the physical design through complex simulation or simple geometric and Booleanoperations. In addition, an image of a reticle acquired by a reticle inspection system and/or derivativesthereof can be used as a "proxy" or "proxies" for the design data. Such a reticle image or a derivative 34 thereof can serve as a substitute for the design layout in any embodiments described herein that use design data.

For example, in one embodiment, an image of a reticle generated by a reticle inspection system is used asdesign data in the design data space. The reticle is used to print the design data on the wafer. In thismanner, an image of a reticle generated by a reticle inspection system may be used as a substitute fordesign data. The image of the reticle used in this embodiment may include any suitable image of thereticle generated in any suitable manner by any reticle inspection system known in the art. For example,the image of the reticle may be a high magnification optical or electron beam image of the reticle acquiredby a high magnification optical reticle inspection system or an electron beam based reticle inspectionsystem, respectively. Alternatively, the image of the reticle may be an aerial image of the reticle acquiredby an aerial imaging reticle inspection system. The image of the reticle may be used as a proxy for thedesign data in any of the embodiments described herein that use design data to perform one or more steps.

In an additional embodiment, the method includes generating a context map for design data in the designdata space based on reticle inspection data acquired for a reticle used to print the design data on the wafer.In this manner, reticle inspection data may be included as input to the generation of a context map. Thecontext map may be configured as described further herein (e.g., the context map may include values forone or more attributes of the design data across design data space). The reticle inspection data used togenerate the context map may include any suitable reticle inspection data known in the art such as one ormore of the reticle images described above. In this embodiment, therefore, the reticle inspection data maybe used to determine values for one or more attributes of design data printed on the reticle across thereticle, and these values may be mapped to design data space to generate the context map. Determiningthe values for the one or more attributes of the design data printed on the reticle may be performed asdescribed herein or in any other suitable manner. The one or more attributes of the design data mayinclude any of the attribute(s) described herein. Mapping the values for the one or more attributes fromreticle space to design data space may be performed as described further herein. Such a context map maybe used in any of the embodiments described herein that include using a context map to perform one ormore steps. In addition, such a context map may be further generated as described herein and/or based onany other information described herein.

Images derived from a reticle image can also serve as a "proxy" for the design data. For example, a reticleimage generated by a reticle inspection system or any other suitable imaging system can be used togenerate a simulated image illustrating how the reticle image would be printed on a wafer, which can be 35 used as a "proxy" for the design data. In one embodiment, a simulated image illustrating how a reticleimage would be printed on the wafer is used as design data in the design data space. In this manner, asimulation of how a reticle image would appear on the wafer surface can also serve as a substitute for thedesign data. The simulated image may be generated in any manner using any suitable method or systemknown in the art. The simulated image may be used as a proxy for the design data in any of theembodiments described herein that use design data to perform one or more steps.

In embodiments described herein in which design data is used, at least in part, to perform one or moresteps, the design data may include any of the design data or design data proxies described above or anycombination thereof.

Turning now to the drawings, it is noted that the figures are not drawn to scale. In particulars the scale ofsome of the elements of the figures is greatly exaggerated to emphasize characteristics of the elements. Itis also noted that the figures are not drawn to the same scale. Elements shown in more than one figure thatmay be similarly configured have been indicated using the same reference numerals. FIG. 1 illustrates one embodiment of a computer-implemented method for determining a position ofinspection data in design data space. It is noted that all of the steps show in FIG. 1 are not essential topractice of the method. One or more steps may be omitted from or added to the method illustrated in FIG.1, and the method can still be practiced within the scope of this embodiment.

In general, the method may include a data preparation phase, a recipe setup phase (e.g., wafer inspectionrecipe setup), and the wafer inspection phase itself. The method may also include review and analysisphases. The data preparation phase may include creating or acquiring design data reflecting the physicaldesign layout of a device being fabricated on a wafer or to be fabricated on the wafer (e.g., informationobtained from a data structure such as a graphical data stream (ADS) file, GDSII file, or another standardfile or database). The information from the GDS file, other file, or database may describe the physicaldesign layout pre-decoration (i.e., without optical proximity correction (OPC) features and any otherresolution enhancement technology (RET) features added to the design).

The method shown in FIG. 1 generally includes aligning an inspection data stream to the design data towithin sub-pixel accuracy as described further herein. In this manner, the methods described herein maybe generally referred to as "align to design" methods for inspection (e.g., wafer inspection). The methodutilizes design data and optionally context data for wafer inspection. In this manner, the methods 36 described herein may also be referred to as "context based inspection" (CBI) methods. The device designdata and context data may be used to increase wafer inspection sensitivity, dramatically reduce nuisanceevent detection, increase the precision of classifying defects, and enhance applications for inspectionsystems such as process window qualification (PWQ). Context data can also be used to provideadvantages for defect review processes and systems as described further herein. In addition, examples ofmethods that use design data and context data are illustrated in U.S. Pat. No. 6,886,153 to Bevis and U.S.patent application Ser. No. 10/883,372 filed Jul. 1, 2004 published on Jan. 6, 2005 as U.S. PatentApplication Publication No. 2005/0004774 by Volk et al. The methods described herein may include anystep(s) of any of the method(s) described in this patent and patent application.

The methods described herein may include a hot spot discovery phase. Hot spot discovery may beperformed during technology research and development, product design, RET design, reticle design andmanufacturing, and product ramp. The hot spot discovery phase may include identifying hot spots forreticle design improvement and defect monitoring and classification. The hot spot discovery phase mayalso include generating a data structure containing information about the hot spots such as a hot spotdatabase. In some embodiments, hot spot discovery may be performed using multiple sources. Forinstance, hot spot discovery may be performed using a correlation between any of design space hot spotdiscovery, wafer space hot spot discovery, reticle space hot spot discovery, test space hot spot discovery,and process space hot spot discovery. In one such example, discovery of hot spots may be performed bycorrelating multiple sources of input from design, modeling results, inspection results, metrology results,and test and failure analysis (FA) results. Any of the steps described herein may be used in anycombination to discover hot spots.

In design space, the hot spots may be identified using results of design rule checking (DRC) to produce alist of critical points in the design data. DRC is commonly performed for quality control (QC) of reticlelayout data prior to mask manufacturing (pre-mask). Thus, DRC may not produce hot spots. Instead, theresults of DRC may be used to identify new marginal hot spots that were either in the design manual butnot part of DRC rules or are newly discovered. In addition, the hot spots may be discovered usingelectronic design automation (EDA). In this manner, during the hot spot discovery phase, design rules(DRC used as a marginality checker) and/or EDA design tools may be used as sources of hot spots.Furthermore, the hot spots may be discovered using technology for computer-aided design (TCAD) toolsand proxies. TCAD tools are commercially available from Synopsis, Inc., Mountain View, Calif. Inaddition, or alternatively, DesignScan analysis software that is commercially available from KLA-Tencor,San Jose, Calif., arbitrary pattern searching, and design context (e.g., functional block, design library 37 element, cell, whether a pattern is redundant or not, pattern density, dummy/fill versus active, etc.) may be used as a source of hot spots. In another example, design data based grouping of defects (with or without pareto analysis) may be used to discover and group hot spots, which may be performed as described herein.

In an additional example, in design space, the hot spot discovery phase may include aligning oroverlaying scanning electron microscope (SEM) images, of design data printed on a wafer, to design data(which may be performed as described herein) to identify an actual defect position in design data space,and arbitrary pattern searching based on the design data proximate to the position of the defect in designdata space may be performed to identify similar possible hot spots in the design. Repeater analysisperformed on original inspection results for the wafer may then be used to identify systematic defects andtheir design groups in the design data, which may be performed as described further herein.

One advantage of this approach is that if a target defect is substantially accurately positioned in the designdata space, the pattern search window used for arbitrary pattern searching and/or systematic defectidentification may be adjusted defect by defect.

In wafer space, hot spots may be discovered using one or more of repeater analysis, zonal/spatialsignature analysis of systematic (e.g., process marginal) defects, temporal signature analysis of systematicdefects, stacked die (or reticle) results with design overlay to enhance the signal-to-noise ratio (S/N) fordiscovery in the reticle/die space, and yield (or kill probability (KP)) correlated to defect space as anattribute of defects for prioritizing systematic defects or groups of systematic defects, each of which maybe performed as described further herein.

In reticle/die space, hot spots may be discovered using one or more of repeater analysis, defect densitymapping, design pattern-based grouping analysis, filtering by design context (e.g., functional blocks) toimprove S/N, identifying defects not of interest from reticle inspection to discover cold spots in the design,each of which may be performed as described further herein.

In test space, hot spots may be discovered using one or more of memory bit failure to design mapping andlogic bitmap density to design mapping, both of which may be combined with repeater analysis(performed in wafer space) or design data based grouping (performed in reticle/die space) to identifydefects not of interest (or cold spots in the design). Each of these steps may be performed as describedfurther herein. 38

In process space, hot spots may be discovered using PWQ as a source of hot spots (using die-to-die, standard reference die, or die-to-database methods) and design of experiments (DOE) of processes to determine process window and critical design features as hot spots (using die-to-die, standard reference die, or die-to-database methods), each of which may be performed as described further herein.

In some embodiments, as shown in step 10 of FIG. 1, the method includes selecting predeterminedalignment sites in design data. Selecting the predetermined alignment sites may be performed using aninspection system. The predetermined alignment sites may be selected during setup of an inspectionprocess recipe. A "recipe" may be generally defined as a set of instructions for carrying out a process suchas inspection. Setting up a recipe for wafer inspection as described herein may be performedautomatically, semi-automatically (e.g., user-assisted), or manually.

In one example, during setup of an inspection process performed by an inspection system, informationabout parameters of the inspection system such as wafer swathing information, inspection system modelnumber, optical mode(s) to be used for inspection, and pixel size, in addition to the design data may beused to select the predetermined alignment sites. The predetermined alignment sites may also be selectedbased on one or more attributes of the wafer to be inspected. Data for and/or images of the predeterminedalignment sites (or indices that refer to this data) may be stored in the recipe for the inspection process.For example, information about the predetermined alignment sites for a layer on a wafer may be stored asalignment data in an inspection process recipe for the layer on the wafer, and the alignment data may beused each time the inspection system inspects a wafer of this particular device and layer.

Although some embodiments are described herein as including "wafer scanning" or "scanning a wafer" toacquire data and/or images for the wafer, it is to be understood that such data and/or images may beacquired using any appropriate technique and/or system known in the art. For instance, data and/orimages for the wafer may be acquired by the inspection systems described herein or another inspectionsystem configured to perform field-by-field image acquisition. In this manner, instead of scanning acrossthe wafer, the inspection system may acquire data and/or images in a stepping manner. In anotherexample, data and/or images for the wafer may be acquired by the inspection systems described herein oranother inspection system configured to perform point-by-point inspection, which may be commonlyreferred to as automated process inspection (API). 39

Several methods may be used to select the predetermined alignment sites. In one embodiment, the methodincludes acquiring design data corresponding to the predetermined alignment sites. Data or images for thepredetermined alignment sites that may be used in the methods described herein include rendered GUSclips (the term "clip" as used herein refers to a relatively small portion of the design layout) and imagesgenerated by an inspection system that have been aligned to a rendered GDS clip. Simulating (or"rendering") the design data corresponding to the predetermined alignment sites may be used to generateimages that illustrate how the design data will be printed on the wafer. The method may also includeperforming a cross-correlation of the design data or a GUS clip with simulated ("rendered") images andrecording the position of the simulated images in design data space (i.e., with coordinates in the designdata space). Simulating images that illustrate how the design data corresponding to the predeterminedalignment sites will be printed on the wafer as described above may be performed using any suitablemethod, algorithm, or software known in the art such as PROLITH, which is commercially available fromKLA-Tencor.

In addition, simulated images may be generated as described above that illustrate how the predeterminedalignment sites will be printed on the wafer after one or more processes have been performed on the wafer.The one or more processes may include, for example, lithography, a combination of lithography and etch,different lithography processes, etc. In this manner, the data for the predetermined alignment sites used inthe methods described herein may include one or more simulated images selected or generated based onone or more processes performed on the wafer prior to inspection. Using different data for thepredetermined alignment sites for alignment of inspection data acquired after different processes havebeen performed on the wafer may increase the accuracy of the methods described herein.

Selecting the predetermined alignment sites may include pre-processing design data (e.g., GDS data) toselect predetermined alignment sites that are compatible with the inspection process and system. Forexample, in some instances, rendered GDS clips may be advantageous for use as the data for thepredetermined alignment sites in the methods described herein since GDS clips are insensitive tovariations caused by the wafer fabrication processes (e.g., color variation). However, images of thepredetermined alignment sites acquired by the inspection system that have been aligned to rendered GDSclips "off-line" may be advantageous for use with inspection data generated at later stages of devicefabrication because these images may be more similar to images of the alignment sites on the wafergenerated by the inspection system than the rendered GDS clips thereby providing more accuratealignment. In some embodiments, therefore, the alignment data used in the methods described herein mayinclude both GDS clips and images that have been aligned to the GDS clips to ensure that a suitable 40 match to data for alignment sites on the wafer can be found at inspection run-time. Alternatively, one ormore attributes of the predetermined alignment sites in the design data such as centroids of thepredetermined alignment sites may be determined, and corresponding centroids of images of thealignment sites acquired by the inspection system may be determined and used to align the inspectionpixel data to the design data.

The number of predetermined alignment sites selected per die may vary greatly. For example, a relativelysparse set of predetermined alignment sites may be selected. In addition, the predetermined alignmentsites may be selected at a predetermined frequency across a die. Since the predetermined alignment sitesare contained within the die itself the predetermined alignment sites may be selected to include devicefeatures in the die and/or features located within a device area of the die. In this manner, thepredetermined alignment sites may be selected to include pre-existing features of the design data. Suchpredetermined alignment sites are advantageous since the design data does not have to be modified toinclude alignment features and the alignment features do not increase the size of the die.

The method may also include selecting predetermined alignment sites within the design data that can beuniquely identified (within some misalignment tolerance window) in images or data acquired by theinspection system. For example, the predetermined alignment sites may be selected to include analignment feature (i.e., a target) that is unique within a predetermined search range uncertainty. In thismanner, given a certain positional uncertainty of the location of an alignment site on a wafer within animage or data, a correlation can be performed for the alignment data and the image or data to identify arelatively strong match of the two alignment sites without any ambiguity.

In one embodiment, the predetermined alignment sites include at least one alignment feature having oneor more attributes that are unique in the x and y directions. An embodiment of one such predeterminedalignment site is shown in FIG. 2. As shown in FIG. 2, predetermined alignment site 32 includesalignment feature 34. Alignment feature 34 has one or more attributes that are unique in the x and ydirections. For example, the corner of the alignment feature may render the alignment feature unique inthe x and y directions with respect to other features in the die and proximate the alignment feature. Thepredetermined alignment site may also include more than one such alignment feature that may besimilarly or differently configured. In this manner, the alignment feature or features may be unique inboth the x and y directions. 41

In an alternative embodiment, the predetermined alignment sites include at least two alignment features.A first of the two alignment features has one or more attributes that are unique in the x direction. Asecond of the two alignment features has one or more attributes that are unique in the y direction. Anembodiment of one such predetermined alignment site is shown in FIG. 2. As shown in FIG. 2,predetermined alignment site 32 includes alignment feature 38. Alignment feature 38 has one or moreattributes that are unique in the x direction but provides no information about alignment in the y direction.For example, the vertical edge of alignment feature 38 may render the alignment feature unique in the xdirection with respect to other features in the die and proximate the alignment feature. The predeterminedalignment site may include more than one such feature.

Predetermined alignment site 36 includes alignment feature 40. Alignment feature 40 has one or moreattributes that are unique in the y direction but provides no alignment information in the x direction. Forexample, the horizontal edge of alignment feature 40 may render this alignment feature unique in the ydirection with respect to other features in the die and proximate the alignment feature. The predeterminedalignment site may also include more than one such feature. Furthermore, the predetermined alignmentsite may include more than two alignment features that are unique in the x and/or y directions. In thismanner, a predetermined alignment site may be selected to include a set of alignment features such asfeatures 38 and 40 that in combination provide sufficient x and y alignment information for determiningthe absolute (x, y) offsets between the "live" image or data (e.g., the image or data acquired by theinspection system during inspection) and data for the predetermined alignment sites.

Selection of the predetermined alignment sites may be performed manually, automatically, or somecombination of the two (i.e., semi-automatically or user-assisted). Whether performed manually,automatically, or both, predetermined alignment site selection can be performed using the design data, anoptical or electron beam image of a wafer, or both. In user-assisted selection of the predeterminedalignment sites, the user may examine the computer-aided design (CAD) layout, a live or stored optical orelectron beam image of the wafer, or both to determine one or more predetermined alignment sites thatsatisfy the uniqueness criteria described above.

In automatic or semi-automatic selection of the predetermined alignment sites, the method may includescanning a die row on a wafer using the inspection system and processing each frame of a die (e.g., byexecuting an algorithm) to identify unique alignment sites. The term "frame" is generally defined hereinas data or an image for a portion of a die in a swath of inspection data or images acquired during scanningof the wafer. Processing the frames may include determining the x and y gradients of features in the 42 frames and selecting one or more features that have a relatively strong gradient in the x and/or ydirections for use in the predetermined alignment sites. The method may also include performing a cross-correlation of a frame and a patch image containing such a feature to determine if only one relativelystrong peak of the gradient(s) is located within a predetermined search range. In this manner, alignmentfeatures that are unique within a pattern search window may be identified and selected for thepredetermined alignment sites. The method may also include accessing the design data, rendering one ormore relatively small regions of the design data as one or more images, and performing the above steps toidentify suitable alignment sites. The method may also include displaying one or more potentialalignment sites (e.g., optical or electron beam and CAD image pairs for the potential alignment sites)identified by the method and allowing a user to select one or more suitable alignment sites distributedover the die at a predetermined minimum interval distance.

In another embodiment, an imaging mode of the inspection system or another image acquisition systemused to select the predetermined alignment sites is different than an imaging mode or imaging modes ofthe inspection system used to acquire the inspection data. In this manner, the method may include usingdifferent imaging modes for alignment site selection and wafer inspection. The alignment site selectionstep may also be performed based on the various imaging modes that may be used to inspect the wafer.For instance, the inspection system may be configured to use more than one optical imaging mode forinspection such as bright field (BF) mode, dark field (DF) mode, Edge Contrast (which is a trademark ofKLA-Tencor) mode, various aperture modes, and/or an electron beam imaging mode. Edge Contrast (EC)inspection is generally performed using a circular symmetric illumination aperture with a complementaryimaging aperture. The best imaging mode for inspection of a particular layer on a wafer is the imagingmode that maximizes the defect S/N, and the best imaging mode may vary with the layer type. In addition,the inspection system may be configured to inspect a wafer using more than one imaging modesimultaneously or sequentially. Since alignment site image or data acquisition performed during waferinspection uses the best imaging mode for wafer inspection, the alignment site selection preferably usesthat mode to select appropriate alignment sites and alignment features.

However, to precisely determine the positions of the selected predetermined alignment sites in the designdata space, an optical patch image of the predetermined alignment site (on the wafer) may be aligned witha simulated image derived from the design data as described above or a GDSII clip. Obtaining a simulatedimage having suitable quality for alignment of the simulated image and the optical image may be difficultfor all imaging modes. However, a best match of the simulated image and the optical image may beobtained for a particular imaging mode (e.g., BF mode). Therefore, the method may include scanning the 43 wafer using the best imaging mode for inspection to select suitable predetermined alignment sites. Themethod may also include revisiting the selected predetermined alignment sites on the wafer using theinspection system to acquire optical patch images using the mode that provides an image that can best bematched to the simulated image or GDSII clip.

The images acquired using the best mode for matching with simulated images or GDSII clips may bealigned to simulated images or GDSII clips for the corresponding alignment sites in the design data.Using the (x, y) positions of the selected alignment sites in the design data space determined by aligningthe images acquired using the best mode for matching to the simulated images or GDSII clips, these x andy positions can be associated with the patch images acquired using the best mode for inspection. If thereis some fixed offset between the images gathered for the same site in the different modes (inspectionmode and best mode for matching to simulated images or GDSII clips), this offset can be measured and/orcorrected at the start of (or before) inspection using a suitable calibration target.

In one such embodiment, the method may include off-line alignment of a CAD simulated image or aGDSII clip to optical or electron beam images of the predetermined alignment sites to determine mapping(i.e., to determine the positions of individual pixels of the optical or electron beam image in design dataspace). For example, after selecting the predetermined alignment sites and acquiring images of those siteson the wafer using the imaging mode that can provide the best images for matching with simulatedimages, the design data corresponding to the predetermined alignment sites may be acquired (in anyformat such as a polygonal representation) and then rendered as a simulated image at the appropriate pixelsize using an appropriate transform function. The optical (or electron beam) and simulated images maythen be aligned to each other using any appropriate method and/or algorithm known in the art. Aligningthe optical (or electron beam) and simulated images to each other may be performed using otherinformation about the design data (e.g., in the design database) such as previous layer geometry that maybe a source of noise in the optical images such that the previous layer geometry can be eliminated fromthe optical images or otherwise accounted for to achieve sufficiently accurate alignment.

Results of the process for setting up the recipe for inspection may include one or more optical or electronbeam patch images representing the predetermined alignment sites, the position (e.g., x and y coordinates)of each of the predetermined alignment sites in the design data space, and any additional information thatmay be utilized by the inspection system to perform substantially accurate alignment during subsequentwafer inspections. 44

As shown in step 12 of FIG. 1, the method includes aligning data acquired by an inspection system foralignment sites on a wafer with data for the predetermined alignment sites. The data for the predeterminedalignment sites may include any of the data described above. For example, the data for the predeterminedalignment sites may include design data stored in a data structure such as a GDSII file or other standardmachine-readable file for mats . In another embodiment, the data for the predetermined alignment sitesincludes one or more simulated images illustrating how the predetermined alignment sites will be printedon the wafer. The one or more simulated images may be mapped to design data space as described furtherherein such that the positions of the alignment sites on the wafer in design data space can be determinedas described further herein based on the positions of the predetermined alignment sites in design dataspace.

In an additional embodiment, the data for the predetermined alignment sites includes one or moreattributes of the predetermined alignment sites, the data for the alignment sites on the wafer includes oneor more attributes of the alignment sites, and the aligning step includes aligning the one or more attributesof the predetermined alignment sites to the one or more attributes of the alignment sites. The one or moreattributes of the predetermined alignment sites and the alignment sites on the wafer used in thisembodiment may include any of the attribute(s) described herein. For example, in one embodiment, theone or more attributes of the predetermined alignment sites include centroids of the predeterminedalignment sites, and the one or more attributes of the alignment sites on the wafer include centroids of thealignment sites. The centroids of the predetermined alignment sites and the alignment sites on the wafermay be centroids for one or more alignment features in the sites. In this manner, the method may includematching centroids of the predetermined alignment sites and the alignment sites on the wafer to align thealignment sites on the wafer to the predetermined alignment sites. As such, the data for the predeterminedalignment sites may include some property (or properties) of the predetermined alignment sites such as acentroid that can be aligned to the corresponding property (or properties) of the data for the alignmentsites on the wafer. The one or more attribute(s) such as the centroids of the predetermined alignment sitesand the alignment sites on the wafer may be determined as described herein or in any suitable mannerknown in the art.

In a further embodiment, the data for the predetermined alignment sites includes data acquired by theinspection system that has been aligned to design data stored in a data structure such as a GDSII file. Thedata acquired by the inspection system for the predetermined alignment sites may be aligned to the designdata as described herein. In some embodiments, the data for the predetermined alignment sites includes atleast a portion of a standard reference die image that has been aligned to design coordinates in the design 45 data space. The standard reference die image may include any of the standard reference die images described herein, and the standard reference die image may be aligned to the design coordinates as described herein. For instance, the standard reference die image may be mapped to the design space and then used for alignment.

Aligning the data for the alignment sites to the data for the predetermined alignment sites may beperformed using any suitable alignment method(s) and/or alignment algorithm(s) known in the art.

In one embodiment, step 12 may be performed during the wafer inspection. In addition, this step may beperformed each time a wafer is inspected using the inspection process recipe. For instance, the inspectionprocess may include an initialization phase that may be performed at the start of inspection of a lot ofwafers and at the start of inspection of each wafer in the lot. During the initialization phase, thepredetermined alignment sites and (x, y or two-dimensional) mapping of the predetermined alignmentsites in the design data space may be accessed from the recipe setup results and downloaded into imagecomputer processing nodes that may be used to perform alignment of the stored alignment patch imageswith the live patch images acquired by the inspection system for the wafer being inspected. The imagecomputer and processing nodes may have any suitable configuration known in the art.

During the inspection process, the method may include scanning the wafer using the inspection system toacquire swaths of inspection data. Each swath may be acquired as a stream of pixels of some height. H (iny) as the inspection system scans (in x) across the die in a row or column on the wafer. Each processingnode in the image computer may process some part of the swath. For example, the swath may beseparated into portions or "pages," and each of the portions of the swath may be directed to a differentprocessing node. The processing nodes may be configured to perform defect detection using the pixels inthe portions of the swath received by the processing nodes. The method and image computer may useinformation about the locations of the alignment sites on the wafer (e.g., locations within each die) andpatch images of the predetermined alignment sites acquired from a storage medium of the imagecomputer (e.g., downloaded during the initialization phase) to align the predetermined alignment siteswith the live stream data for the alignment sites on the wafer.

In some embodiments, a context map (e.g., stored in a data structure such as a database) may be accessedand downloaded into the processing nodes. This context data may be stored in any suitable format knownin the art. This context data may be stored and/or used in a compact polygonal representation rather thanin image format. However, the context map may be rendered into an image such that the context map can 46 be used for defect detection purposes. This rendering can be performed either once during initialization oreach time the context map is used during inspection. An advantage of the former approach is thatrendering the context map during initialization reduces the data processing cycles performed during theinspection process. However, a disadvantage of this approach is that storing a rendered image of the entirecontext map may require a relatively large amount of memory.

As shown in step 14 of FIG. 1, the method includes determining positions of the alignment sites on thewafer in design data space based on positions of the predetermined alignment sites in the design dataspace. For instance, since the (x, y) positions of the predetermined alignment sites with respect to thedesign data coordinates (i.e., in the design data space) have been determined and the data for thepredetermined alignment sites has been aligned to the data for the alignment sites, the absolute locationsof the live pixel coordinates of the alignment sites on the wafer can be determined in design data space. Inanother embodiment, determining the positions of the alignment sites on the wafer in design data spacemay include aligning the raw data stream (e.g., live images) to the data (e.g., reference images) for thepredetermined alignment sites. Determining the positions of the alignment sites on the wafer in designdata space may be performed before inspection of the wafer or subsequent to acquisition of the inspectiondata for the wafer.

As shown in step 16 of FIG. 1, the method includes determining a position of inspection data acquired forthe wafer by the inspection system in design data space based on the positions of the alignment sites onthe wafer in the design data space. The inspection data for which the position in design data space isdetermined may include any data (e.g., image data) acquired for the wafer by the inspection systemduring inspection. In addition, the position of the inspection data may be determined for some or all of thedata acquired by the inspection system during inspection of the wafer. For example, the position of theinspection data may be determined only for inspection data acquired for care areas on the wafer.

In one embodiment, after aligning the portions of the raw data stream corresponding to the alignment siteson the wafer to the reference images of the predetermined alignment sites as described above, the methodmay include measuring the coordinate offset between the inspection data stream and the design data towithin sub-pixel accuracy. In addition, the coordinate errors between the live inspection data and thedesign data may be corrected by shifting the raw inspection data image with respect to the referenceimages for the predetermined alignment sites so that the alignment sites on the wafer are substantiallyexactly aligned to the predetermined alignment sites for all points across the die. One significantadvantage of the methods and systems described herein is that the position of the inspection data in the 47 design data space can be determined with sub-pixel accuracy. In this manner, the care and do not careareas on the wafer may be determined as described further herein with relatively high precision at sub-100nm accuracy.

In a different embodiment, the data for the predetermined alignment sites may be used to determine atwo-dimensional mapping transform that can be used to map the live image pixel space to design dataspace. For instance, as described above, the method may include correlating downloaded predeterminedalignment site patch images (acquired during setup of the inspection process) with the live image dataover a predetermined search range and determining the offset between the downloaded and live images.The method may also include determining the correspondence between the live image pixel positions andthe design data coordinates using this offset since the (x, y) positions of the predetermined alignment sitesin design data space were determined during setup. The method may then include determining a two-dimensional function for mapping the live pixel coordinate space to the design data space using thecorrespondence between the live image pixel positions and the design data coordinates.

In one such example, using a suitable polynomial fit of a grid of alignment sites to the absolutecoordinates in design data space, a mapping function may be determined that can be used to map anypixel in the inspection data (e.g., the live pixel stream) to its corresponding position in the design dataspace. In a similar manner, any pixel in the inspection data may be mapped to its corresponding positionin the context space as described further below. Several other corrections may be used to providesubstantially accurate mapping. For instance, corrections may be performed based on data provided by theinspection system such as pixel size in the x direction, which may be acquired by the run time alignment(RTA) subsystem of the inspection system, and stage calibration data. The mapping may be used for thedie-to-die inspection mode. Mapping of the live pixel stream as described above may be performed inrealtime during inspection of the wafer or subsequent to acquisition of the inspection data for the wafer.

In this manner, determining the position of the inspection data in design data space may be performedduring the inspection of the wafer. Alternatively, determining the position of the inspection data in thedesign data space may be performed subsequent to inspection of the wafer.

The position of the inspection data in design data space may be stored and used in any manner describedherein.

In one embodiment, the method includes detecting defects on the wafer using the inspection data and astandard reference die for standard reference die based inspection. In this manner, the method 48 embodiments described herein may include performing standard reference die based inspection. In somesuch embodiments, the method may include applying mapping of a standard reference die image in designdata space to live images acquired by the inspection system for the wafer for standard reference die-to-dieinspection mode. The term "standard reference die" generally refers to a reference die on the wafer that isbeing inspected but does not meet the normal adjacency constraints to the "test" die that are required fordie-to-die inspection. Some commercially available inspection systems are configured to use someversion of the standard reference die-to-die inspection mode. One implementation of the standardreference die-to-die inspection mode involves comparing a die to any die within a die row. In anotherimplementation, the standard reference die image may be a stored image. Therefore, stored standardreference die-to-die inspection mode is much like standard reference die-to-die inspection mode, exceptthat the constraint of using a reference die on the wafer is eliminated. One advantages of this inspectionmode is that the stored standard reference die image can be modified to make the standard reference dieimage "substantially defect free." In addition, this inspection mode enables using standard reference dieimages from a different wafer thereby enabling the most simple implementation of the iPWQ application,which is described further herein.

In one embodiment, which may be used for standard reference die-to-die inspection mode, the live imageacquired for a die being inspected is aligned to and compared with a stored die image obtained from aknown good die (standard reference die) on another wafer. Such alignment and comparison may beperformed as described herein. In this case, mapping of the standard reference die pixels to design datacoordinate space may be performed completely offline. For instance, the alignment sites in the standardreference die may be mapped in the design data space as described above, and the mapped standardreference die pixels may be stored offline and fed into the inspection system during inspection. In thismanner, for the standard reference die-to-die inspection mode, determining the position of the liveinspection data in design data coordinate space may be performed by aligning the live data to the storedstandard reference die image or data which itself has been mapped to design space.

In another embodiment, for standard reference die-to-die inspection, a known good die on a referencewafer is scanned at the selected pixel size and imaging mode, and the entire known good die image maybe stored in an appropriate storage medium (e.g., a disk). During inspection of a wafer, a swath of theappropriate standard reference die image is downloaded into the inspection system image computer, andas each die is scanned, frames of the target die (i.e., the die being inspected) are aligned with thecorresponding standard reference die frames. Misalignment between the frames may be corrected usingsub-pixel interpolation. The standard reference die image may then be compared to an image of the wafer 49 to detect defects on the wafer (e.g., to detect defective pixels). In this manner, the same image can be usedfor aligning inspection data to design data space coordinates and for defect detection.

In a different embodiment, the method includes aligning data for the alignment sites on the wafer in theinspection data stream to rendered GUS clips for the predetermined alignment sites to correct errors inreal-time. For example, the method may include applying mapping of the rendered GUS II clips in designdata space to the data for the alignment sites on the wafer for die-to-die inspection mode. The methodmay include correlating downloaded alignment site patch images (selected during setup of the inspectionprocess) with the live image data over a predetermined search range and determining the offset betweenthe two images. In another example, aligning data for the alignment sites on the wafer in the inspectiondata stream to data for the predetermined alignment sites may be performed by aligning a centroid orother attribute of one or more features in the alignment sites, which may be performed as describedfurther herein.

In one embodiment, for defect detection in die-to-die inspection mode, data for each scanned die frame isaligned with data for the subsequent die frame in the swath. In this case, mapping of the predeterminedalignment sites and the alignment sites on the wafer may not be performed offline since the position of thedata for each die in the inspection data stream is subject to mechanical and other error sources of theinspection system. Therefore, in this case, the method may include identifying the alignment sites in eachdie (e.g., using the image computer) during the acquisition of the inspection data.

In another embodiment, defect detection may be performed in wafer-to-wafer inspection mode. In onesuch embodiment, data for alignment sites on one wafer may be aligned to data for the predeterminedalignment sites, and the data for the alignment sites on this wafer may be aligned to data for the alignmentsites on another wafer. Alternatively, data for alignment sites on both wafers may be aligned to data forthe predetermined alignment sites including any of the data described herein. In this manner, after data forthe alignment sites on the wafers have been aligned to the data for the predetermined alignment sites, theinspection data for the wafers will effectively be aligned to each other and can be overlaid or comparedfor defect detection. In some embodiments, the wafer-to-wafer inspection mode involves using areference die that that exists outside of the wafer being inspected (i.e., an off-wafer reference).Implementation of this method is far from straightforward since it involves separating the runtimefeedback concepts that are currently used to enable inspection systems to accomplish die-to-die leveloverlay tolerances (e.g., 0.1 pixel) to achieve adequate sensitivity results. 50

In one such embodiment, the method includes RTA of the wafer being inspected to an off-wafer referenceimage. RTA to an off-wafer image is an image alignment approach that can be used to enable theextension of scanning inspection technology from wafer "self-referencing" approaches such as die-to-diecomparison and cell-to-cell comparison to wafer-to-wafer inspection for detecting defects on patternedwafers. For example, RTA may include electro-mechanically aligning a live acquired image with apreviously acquired image to obtain sub-pixel accuracy positioning prior to digitizing the signalsproduced by one or more detectors of the inspection system. Examples of how RTA may be performed inthe embodiments described herein are illustrated in U.S. Pat. No. 7,061,625 to Hwang et al.

One currently available inspection approach that involves comparing an image of a wafer to an off-waferimage is the die-to-database inspection mode used by Nanogeometric Research, Japan (NGR). This die-to-database inspection approach entails "step and repeat" image acquisition and stitching followed by acomplex series of edge based image processing, process simulation, and detection algorithm steps.However, this method cannot be used to directly compare images of different wafers. In particular, thedie-to-database inspection mode compares a wafer image to a simulated reference derived from the designlayout database. The simulation step of this approach must be carefully calibrated to the specificmanufacturing process used to produce the wafer under test. The calibration is an expensive and timeconsuming process. The calibration is particularly complex for an integrated process flow with multiplesteps. In addition, "step and repeat" image acquisition inspection processes are typically slow relative toscanning based inspection processes due to the practical limitations of stage inertia, stage vibration, staticimage acquisition, stitching the images, etc.

An alternative die-to-database inspection mode is a logical extension of the inspection mode that uses an"off-wafer" reference die described above. In this case, the "database" is a rendered image generated fromdesign data and process simulation as described above. Therefore, database based inspection may beconsidered a logical extension of "off-wafer" reference inspection modes because wafer-to-waferinspection can be performed using a "standard reference die" that was generated from an acquired image(possibly with statistical augmentation, which may be performed as described herein) and a "standardreference die" that was generated strictly from design data and process modeling. Using the standardreference die generated strictly from design data and process modeling is the most complex waferinspection mode to implement. Many attempts have been made to implement this inspection mode, butthe current performance of the attempted implementations is not adequate due to the computationalintensity (modeling and detection), image acquisition rate, and image quality challenges of thisapplication. However, the methods described herein are more practical to implement since a common 51 absolute reference (e.g., the design data) can be used for alignment of the inspection data for the wafer under test and the off-wafer reference.

The methods described herein can, therefore, be used to enable comparison of wafers to one another,which is a potentially extremely useful application. One motivation for defect inspection using wafer-to-wafer comparison is to discover "systematic defect mechanisms" that may result from the interaction of aspecific circuit layout and the stacked tolerances of the wafer manufacturing process. This discoveryprocess may include comparing wafers on which the same device design was printed but which wereprocessed differently. The most deterministic approach is to modulate process parameters in a single- ormulti-variable experiment (e.g., using a methodical DOE approach). In one embodiment, the wafer andadditional wafers (e.g., two or more wafers) are processed using wafer level process parametermodulation, which may be performed as described above or in any other suitable manner. The processparameters may be modulated to cause the measurable physical and/or electrical attributes of the resultingwafers to approach their allowable limits. In addition, the method may include detecting defects on thewafer and the additional wafers by comparing inspection data for die on the wafer and the additionalwafers to a common standard reference die. Detecting the defects on the wafers in this manner may beperformed as described further herein. In one such embodiment, the method may include determining ifstructural differences between wafers occur as measured by the detection of "defects." Such an approachmay be referred to as integrated PWQ (iPWQ). In this manner, the methods described herein may be usedto enable the implementation of iPWQ (e.g., using the standard reference die approach for iPWQ). Assuch, PWQ methodology may be extended to include wafer level process parameter modulation andcomparison of die on different wafers to a common standard reference die for purposes of implementingthe iPWQ methodology.

In contrast, discovery of lithography induced "systematic defect mechanisms" may be performed usingmethods described in U.S. Pat. No. 6,902,855 to Peterson et al., and the PWQ product commerciallyavailable from KLA-Tencor. PWQ leverages the unique ability of lithography tools to modulatelithography exposure process parameters at the reticle shot level using focus and exposure as variables todetermine design-lithography interactions. This application is often used for OPC verification. However,PWQ is limited to the direct comparison of dies on a wafer that are printed with modulated focus and/orexposure parameters. The impact of other process variables associated with process steps such as etch,deposition, thermal processing, chemical-mechanical polishing (CMP), etc. cannot be directly assessed byPWQ since these variables can only be modulated at the wafer level. However, systematic defectmechanisms associated with or caused by these process variables can be discovered using the methods 52 described herein. In particular, the methods described herein can be used to examine non-lithography process modulation in a PWQ-type application by wafer-to-wafer comparison.

In scanning based defect detection systems, die-to-die image subtraction can be performed by "sub-pixel"image alignment to reduce difference image registration noise thus enabling better sensitivity to defects.Defects are identified by detecting pixels in the difference image that exceed one or more thresholds. Thescanning based image acquisition process includes a feedback mechanism often referred to as RTA. Thismechanism precisely aligns the image being acquired to image(s) acquired from the same wafer sometime prior to the current image. Depending on the configuration of the inspection system, the feedbackmechanism can include a combination of opto-mechanical, electro-mechanical, and electronic/algorithmicapproaches.

In one embodiment, the methods described herein include RTA using a stored image as the referencerather than images acquired for the wafer under test. The stored image may be an image of a "standardreference wafer" or a reference wafer. Each die on the wafer under test may be compared to acorresponding die on the standard reference wafer. Although embodiments are described herein asincluding a comparison of two wafers or images of wafers, it is to be understood that the embodimentsmay include comparing any data acquired by inspection of two or more wafers. FIG. 4 illustrates various embodiments of a computer-implemented method for performing a wafer-to-wafer comparison. It is noted that the steps shown in FIG. 4 are not essential to practice of the method.One or more steps may be omitted from or added to the method illustrated in FIG. 4, and the method canstill be practiced within the scope of this embodiment.

As shown in step 220, the method includes a wafer-to-wafer comparison. In one embodiment, the wafer-to-wafer comparison includes comparing a reference wafer image to a test wafer image, as shown in step222. For instance, the reference wafer image that is used in the methods described herein may be a storedimage of the entire reference wafer. The comparison of the reference wafer image to the test wafer imagemay be performed as described herein. Alternatively, as shown in step 224, the wafer-to-wafercomparison may include comparing a standard reference die image to images of all dies on a wafer (e.g.,a reference or test wafer).

In one embodiment, the method includes detecting defects on the wafer using the inspection data, astandard reference die, and a representation of wafer noise associated with the standard reference die in a 53 perturbation matrix for standard reference die based inspection. In this manner, the method may includeusing a relatively compact representation of wafer noise associated with the standard reference die in theform of a perturbation matrix. For example, an image of a reference die on the reference wafer may bestored in addition to a perturbation matrix or other suitable data structure that shows how the die pixelsvary from die to die on the reference wafer. Storing an image of a reference die in addition to theperturbation matrix instead of an entire reference wafer image allows a more compact representation ofthe reference wafer to be stored. In this manner, a perturbation matrix may be included in therepresentation of a reference wafer to reduce the reference wafer image size to a level that can beimplemented in a practical and affordable manner. As such, the method may include standard referencedie based inspection that includes using a perturbation matrix compression of noise signatures.

Generating a reference wafer image and corresponding perturbation matrix may involve standardreference die based inspection using a standard reference die acquired from the reference wafer (i.e., asort of self-referencing). A single standard reference die image on the reference wafer may be used as anRTA reference at run time to reduce any impact that RTA performance may have on sensitivity as well asthe baseline image that is perturbed with the compressed difference data stored for each die on thereference wafer. The size of the stored difference data may be reduced through compression algorithms aswell as by imposing limitations on the total care area size per die swath. At run time, the perturbationmatrix of difference image data may be loaded for the entire reference wafer by swath for eachcorresponding standard reference die swath that gets loaded. A perturbation matrix data volume for awhole wafer may be on the order of about 1 Gb to about 3 Gb, and a data volume for the standardreference die may be on the order of 1 Gb. All other methods described herein that include a standardreference die comparison may use a perturbation matrix as described above.

The perturbation matrix may be defined by P.sub.1(x, y), D.sub.x(1, 2), D.sub.y(1, 2) Diff.sub.1,2(x, y);P.sub.2(x, y), D.sub.x(2, 3), D.sub.y(2, 3), Diff.sub.2,3(x,y); . . . P.sub.m-1(x, y), D.sub.x(m-1, m),D.sub.y(m-1, m), Diff.sub.m-1,m(x, y) if there are m die in a row, where P.sub.i(x, y) is a pixel value inthe i.sup.th die at location (x, y), D.sub.x(i, i+1) and D.sub.y(i, i+1) are offsets in x and y, respectively, ofdie(i) with respect to die(i+1), and Diff.sub.i,i+1(x, y) is the difference gray level of die (i+1) with respectto die(i) at location x, y after die(i+1) has been shifted by x and y offsets to align it with the frame ofdie(i). However, within interpolation error bounds, P.sub.2(x, y) can be reconstructed from P.sub.i(x, y),D.sub.x(1, 2), D.sub.y(1, 2), and Diff.sub.1,2(x, y). In addition, P.sub.i(x, y) can be reconstructed for anyother die by applying these steps successively to each die. Of course, this may compound the interpolationerror and progressively blur the image from die to die. 54

However, if a standard reference die is stored and all interpolations are performed with respect to this die,then the transitive error accumulation described above does not occur. Rather, the error is simply theinterpolation error associated with reconstructing any die on the wafer from the standard reference die,given its offset and difference image. Therefore, as shown in step 226, the method may include saving adifference image of each die with respect to the standard reference die. FIG. 5 illustrates one embodiment of a method for performing a wafer-to-wafer comparison using such adifference image as the reference for comparison. For instance, reference wafer 250 includes a number ofdies [(0,0), (0,1) . . . (4,2)], one of which (e.g., die (2,2)) is designated as the standard reference die.Reference wafer 252 that is used for comparison to the test wafer is generated by storing a differenceimage [Diff(0,0), Diff(0,1) . . . Diff(4,2)] for each of the dies with respect to standard reference die image254. Test wafer 256 may then be compared with reference wafer 252. For instance, as shown in FIG. 5,defect detection may be performed for test die (1,3) by adding standard reference die image 254 andcorresponding difference image (Diff(1,3)) and then subtracting test die (1,3) to generate difference 258between test die (1,3) and reference die (1,3).

The difference image between any die (under test) and the standard reference die may, therefore, berepresented in a compact manner. A lossy compression algorithm may be employed to achieve a higherdegree of compaction. The information that may be lost by such a compression scheme depends on thescheme itself. For example, as shown in step 228 of FIG. 4, the method may include performing lossycompression for non-critical regions of the difference images and lossless compression for critical regionsof the difference images. In this manner, an "intelligent" compression scheme may be used such that lesscritical device regions are allowed to suffer a higher loss than more critical regions. A similarcompression scheme may be used for a reference wafer image. For example, as shown in step 230, themethod may include performing lossy compression for non-critical regions of the wafer image andlossless compression for critical regions of the wafer image.

Alternatively, the method may include saving per pixel difference statistics with respect to the standardreference die, as shown in step 232. For instance, as shown in step 234, the method may include storingstatistics per die per context type. Each die may be separated into one or more context types, which maybe performed as described further herein. In one such example, the method may include recordingstatistics with respect to the difference at each (x, y) location in the standard reference die with respect todifferent groups of dies. As shown in step 236, the context may be the die region. Alternatively, as shown 55 in step 238, the context may be the background type. The per pixel different statistics may be determinedin any suitable manner.

In another example, the wafer may be separated into N radial sectors and/or M annular rings. For example,as shown in FIG. 6, wafer 260 may be separated into annular rings 1, 2, and 3. Although wafer 260 isshown as being separated into three annular rings, it is to be understood that the wafer may be separatedinto any suitable number of annular rings. In addition, or alternatively, as shown in FIG. 7, wafer 260 maybe separated into wafer sectors A, B, C, D, E, F, G, and H. Although wafer 260 is shown as beingseparated into eight sectors, it is to be understood that the wafer may be separated into any suitablenumber of sectors. The method may include saving statistics per pixel per wafer sector and/or annularring, as shown in step 240 of FIG. 4. In one such example, for each of the (N+M) partitions, the averageand standard deviation of the difference with respect to the standard reference die image at the (x, y)locations may be recorded. Using an 8-bit average and an 8 bit standard deviation involves storing2*(N+M) bytes at each (x, y) location versus storing a byte of the difference per die on the wafer. In thismanner, if there are 100 die on the wafer, using eight sectors and eight annular rings requires 32 bytes per(x, y) location versus 100 bytes per (x, y) location. In a further example, the method may include storingstatistics per wafer sector and/or annulus as described above per context type, as shown in step 242. Thecontext type may be based on die regions, as shown in step 244. Alternatively, the context type may bebased on background type, as shown in step 246. The statistics per context type and the context types maybe determined as described herein. FIG. 8 shows how such a scheme may be performed if statistics are stored for each (x, y) location on thestandard reference die on a per annular ring basis. In particular, FIG. 8 illustrates an embodiment of amethod for performing a wafer-to-wafer comparison using difference statistics by annulus as a reference.For example, as shown in FIG. 8, reference wafer 262 includes a number of dies [(0,0), (0,1) . . . (4,2)],one of which (e.g., die (2,2)) is designated as the standard reference die. Reference wafer 264 that is usedfor comparison to the test wafer is generated by determining an average difference at pixel (x, y) and astandard deviation of the difference at pixel (x, y) with respect to standard reference die image 266 foreach annulus. Test wafer 268 (shown in FIG. 8 with the annuluses overlaid on the test wafer) may becompared with reference wafer 264. For instance, test die (1,3) is subtracted from standard reference dieimage 266 to generate difference 270 between test die (1,3) and standard reference die image 266. Asfurther shown in FIG. 8, test die (1,3) is located within annulus 1 and annulus 2. Therefore, in step 272,difference image 270 is compared to statistics 274 (e.g., average difference +/-k*standard deviation of thedifference) at each (x, y) location in the test die on a per annulus basis. In other words, difference 270 for 56 portions of the test die that are located within annulus 1 are compared to the statistics for annulus 1, and difference 270 for portions of the test die that are located within annulus 2 are compared to the statistics for annulus 2.

More compact storage of the standard reference die may be enabled by storing the standard reference diedata on a statistical basis (e.g., separate the die into frames, frames into different geometries (binnedcontexts) and for each frame/context, save the average/standard deviation of die-to-die differences). Forexample, as shown in step 248 of FIG. 4, the method may include saving per die per frame per contextdifference statistics with respect to the standard reference die. For example, as shown in FIG. 9, anarrangement of die [(0,0), (0,1), . . . (M,N)] 276 may be formed on wafer 278. In addition, as shown inFIG. 10, die 276 may be separated into frames 280. The die may be separated into frames 280, and thepixels of each frame may be separated based on context (not shown in FIG. 10). Difference statistics foreach different context of each frame in each die may be determined as described herein. FIG. 11 illustrates one embodiment of a method for performing a wafer-to-wafer comparison usingdifference frame statistics sorted by context. As shown in FIG. 11, reference wafer 282 includes a numberof dies [(0,0), (0,1) . . . (4,2)], one of which (e.g., die (2,2)) is designated as the standard reference die.Reference 284 that is used for comparison to test wafer 286 includes die 276 separated into frames 280and standard reference die image 288. Frames 280 may be configured as described above. Reference 284may be generated by determining statistics 290 such as an average and standard deviation of thedifference for each frame and each context within each frame for each die. To detect defects on test wafer286, the test wafer is compared to reference 284. For instance, to detect defects in test die (1,3), test die(1,3) is subtracted from standard reference die image 288 to generate difference 292 between the test dieand the standard reference die image. In step 294, difference 292 is compared with statistics 290 (e.g.,average and standard deviation of the difference for each frame and context) for die (1,3) of referencewafer 282 on a per frame per context basis.

If the "standard reference die" is not known to be defect free, single arbitration (in which defect detectioncan be performed using one comparison with a reference die that is truly defect free) can be performedusing a "polishing" scheme. In addition, "polishing" may be performed such that a standard referencewafer reflects image variations expected across the wafer due to "inherent" or expected process variations.Therefore, to generate a "defect free" reference wafer, standard reference die "polishing" may beperformed for every die on the reference wafer. 57

Table 1 below shows the approximate size of the reference data for various wafer-to-wafer comparisonsdescribed above assuming a maximum die size of 40 mm by 40 mm, a smallest inspection pixel size of 90nm, the number of maximum size die on the wafer of 44, the number of pixels in the maximum size die of1.975E+11, a frame size of 512.times.512 pixels, a frames per maximum size die of 7.535E+05, the bytesto store average difference and standard deviation of difference of 2, the pixels per swath of maximumsize die of 0.91 Gpixels, the swaths per maximum size die of 217, and a 2048 pixel high swath. Thestandard reference die includes 197 Gpixels or 0.91 Gpixels per swath assuming a 2K high sensor. Inaddition, the difference image for each die on the reference wafer or some compressed form thereof has tobe stored. TABLE 1

Method Data size (Gbytes) Difference image stored (no compression) 8727.8 Difference image at 0.1% of total pixels 8.7 Per pixel sector-based stats: 8 sectors 3160.5 Per pixel ring-based stats: 8 annular rings 3160.5 Per pixel sector + ring-based stats: 8 sectors, 8 rings 6321.0 Frame-based stats: 512 X 512 frames 0.0666 Frame + context-based stats: 8 contexts/frame 0.5327

Table 1 clearly shows that data size for storing the difference image is much larger than the data size forstoring frame and context-based statistics per die. However, saving a fraction of the difference pixels (e.g.,0.1%) having the largest difference and those in critical areas reduces the data size requirement from8727.8 Gbytes for the difference image to 8.7 Gbytes.

The dies on a test wafer may be scanned a number of times using a serpentine scan path to generate anumber of swaths of inspection data. One embodiment of such a serpentine scan is shown in FIG. 12. Asshown in FIG. 12, test wafer 296 includes an arrangement of dies [(0,0), (0,1) . . . (4,2)]. Test wafer 296 isscanned by serpentine scan 298 and serpentine scan 300. Although two serpentine scans are shown in FIG.12, it is to be understood that the test wafer may be scanned using any suitable number of times.Assuming 217 swaths per die and performing the same serpentine scan in all die rows, one can load thestandard reference die swath and the compressed difference for all dies for swath 1, then swath 2, etc. Inthis case, the memory requirements for storing reference data for a test wafer scan is (197+8.7)/217=0.95Gpixels per swath. 58

One consideration in the implementation of standard reference die-to-die inspection is the diskinput/output (I/O) speed and if the speed will impact throughput. Disk I/O traffic can be reduced byloading each swath of the "standard reference die" once. Such loading can be used with serpentinescanning across the whole wafer with die level stepping between wafer scans (vs. serpentine pattern ofadjacent wafer scans).

Of course, for all of the inspection modes described herein, inspection may be performed using one imagestored on a disk vs. another image stored on the disk or using images in memory that were just acquiredfrom a wafer in real time. All of the data described above may be stored or saved as described furtherherein, and all of the storing or saving steps described herein may be performed in any manner describedherein.

As described above, determining the position of the inspection data in design data space may beperformed subsequent to inspection of the wafer. In one such embodiment, determining the position of theinspection data in design data space is performed for portions of the inspection data corresponding todefects detected on the wafer and not for portions of the inspection data that do not correspond to defectsdetected on the wafer. In this manner, the mapping transformation from pixel or wafer space to designdata space may be applied only to the locations at which defects are found. In other words, the methodmay include post-process mapping of defects detected on a wafer to design data space. In addition, thealignment sites in each die may be identified during inspection although the alignment (e.g., alignmenterror measurements) may be performed after the defect detection is complete in a post-processing phase.The mapping is then applied to find the positions of the defects in the design data space.

Regardless of when or how the determining position of the inspection data in design data space isperformed, if one or more defects are present on the wafer, the inspection data includes data for a defector defects on the wafer. Therefore, the positions of one or more defects in design data space can bedetermined from the position of the inspection data in design data space. In addition, the positions of oneor more defects in design data space can be advantageously determined with the same, substantially high(e.g., sub-pixel) accuracy as the position of the inspection data in design data space.

As described further herein, in some embodiments, the inspection data may be acquired in swaths byscanning the wafer. In one such embodiment, each swath of the inspection data may be individually 59 aligned to the design data space by aligning data for alignment sites in each swath with data for predetermined alignment sites, which may be performed as described above.

In a different embodiment, determining the position of the inspection data includes determining theposition of a swath of the inspection data in the design data space based on positions of the alignmentsites in design data space and determining the position of an additional swath of the inspection data indesign data space based on the position of the swath in the design data space. In this manner, one swath ofinspection data may be aligned to the design data space as described above (e.g., by aligning data for thealignment sites on the wafer in a swath of the inspection data with the data for the predeterminedalignment sites, and additional swaths of inspection data may be aligned to this swath of inspection data.

For example, as shown in FIG. 13, a swath (e.g., swath #N+1) may be aligned to the previous swath (e.g.,swath #N) using inter-swath image alignment. In particular, as shown in FIG. 13, swaths #N+1 and #Npartially overlap with each other in area 41 in wafer space. Therefore, both swaths will contain inspectiondata for the features formed within area 41. As such, the inspection data for these features may be used toalign one swath to another. In one such example, FIG. 14 illustrates features 41a and 41b formed in inter-swath overlap area 41 in wafer space in which inspection data for two successive scans overlap. Features41a and 41b can be used for performing swath-to-swath registration. Features 41a and 41b may be furtherconfigured as described herein with respect to other alignment features.

In this manner, if the first swath for a die row has been aligned to design data space by aligning data foran alignment site (or sites) in the die row to rendered images from the design database or otherpredetermined alignment site data described herein, subsequent swaths of the die row can be alignedusing the technique described herein. In particular, using the position of swath #N with respect to designdata space and the position of the alignment features within the swath, the position of swath #N+1 withrespect to design data space may be determined. For example, determining the position of swath #N+1may be performed by storing the alignment feature image acquired during the swath #N acquisition scan,and then aligning the alignment feature image to the image of the same feature acquired during theacquisition of swath #N+1. By determining the misalignment offset between the two alignment featuresimages, the absolute position of swath #N+1 with respect to design data space may be determined.

During the setup of an inspection recipe, the wafer can be scanned with a relatively large overlap betweenconsecutive swaths (e.g. 50% overlap) to determine suitable alignment sites in the inter-swath overlapregions. Using these site positions, the position of each swath with respect to the corresponding previous 60 swath may be determined. Using the position of the first swath with respect to design data space using theabove-described method for aligning a predetermined alignment site to an alignment site on the wafer andthe shift of the second swath with respect to the first determined using an alignment site in the overlaparea between the first and second swaths, the absolute position of the second swath with respect to thedesign data space may be determined. By repeating this procedure for each subsequent swath, the pixelsfor an entire die may be mapped to design data space.

Then, suitable alignment sites can be selected (using the above described methods) such that there is atleast one such site in each inspection swath (i.e. the swath used during inspection in which the overlapbetween swaths is the minimum overlap to ensure that the die is fully scanned). The positions of thesealignment sites in design data space are saved in the inspection recipe along with patch images of eachalignment site. During inspection, for each swath, the corresponding alignment site is retrieved from therecipe and its position is determined in the pixel stream acquired by the inspection system. Once thealignment site has been located in the pixel stream, using cross-correlation or other image matchingtechniques, positions of pixels in the inspection swath can be determined in the design data coordinatespace to sub-pixel accuracy. One advantage of this method is that the inspection swaths can be acquiredwith relatively small overlap (thus improving speed), while the setup swaths (which are used only forrecipe setup) are acquired with relatively large overlap to perform the swath "stitching" used to mappixels for the entire die to the design data coordinate space and find suitable alignment sites in this spacethat occur in each inspection swath. It should be noted the technique of stitching swaths can be applied toa different scanning pattern, for example, a field by field acquisition using an area sensor. Fields may bestitched together in a manner similar to that described above.

Another advantage of the above-described embodiment over aligning each swath with respect to thedesign data space is that this scheme requires data for fewer alignment sites to be rendered from thedesign data. In addition, rendering data for alignment sites faithfully from design data may posechallenges due to the complexity of the models that can be used to predict how a given feature will beprinted on a wafer, particularly when the wafer has multiple layers formed thereon. However, as notedabove, the data for the predetermined alignment sites may be acquired in a number of different manners,which may be selected based on the layer being inspected thereby providing suitable data for thepredetermined alignment sites regardless of the layer being inspected.

As described above, swath stitching using "short swaths" in coverage mode may be used to aligninspection data to the design data. In some embodiments, however, as shown in FIG. 14a, alignment site 61 302 may be located on the wafer spaced from (e.g., far away from) the area on the wafer corresponding tofirst inspection swath 304a. This situation can occur when the only suitable alignment site is separatedfrom the area of the wafer scanned for the first inspection swath. The location of the first inspection swathmay be determined from the care area definition (e.g., care areas automatically defined or defined by auser). In such a situation, the methods or systems described herein can perform a series of "mini-scans"306 on the wafer, each one die wide as shown in FIG. 14a. The swaths acquired by the mini-scans areused to "stitch" the swath containing the alignment site with the first inspection swath 304a using theinter-swath alignment methods described above. Subsequent inspection swaths 304b and 304c may thenbe aligned to first inspection swath 304a as described further above.

The methods and systems described herein may acquire inspection swaths for a wafer in a number ofdifferent manners. For example, as shown in FIG. 14b, the system may acquire inspection swaths 308 forthe wafer in a 100% inspection mode. In particular, the system scans the wafer back and forth to acquireoverlapping swaths that can be used to inspect 100% of the die area. In another example, as shown in FIG.14c, the system may acquire inspection swaths 310 for the wafer in a standard coverage mode. In thiscoverage mode, the area on the wafer for which the swaths were acquired may be about 25% to about50% of the die area. The swaths shown in FIG. 14c correspond to 50% coverage mode in whichalternating swaths are used for inspection. In a different example, as shown in FIG. 14d, the system mayacquire inspection swaths 312 for the wafer in a "smart scanning" mode. In this mode, about 50% of thedie area may be scanned, and the areas that are scanned may be selected based on information about thedesign or an anticipated interaction between design and process. In addition, the systems described hereinmay be configured to perform any of the various scanning methods described above (e.g., differentscanning methods for different wafers). Furthermore, the methods described herein (or a design analysistool) may include using knowledge of the inspection system (e.g., scanning capability) to determine anoptimum "coverage" scheme for a wafer.

In another embodiment, the method may include aligning inspection data to the design data and thenusing die relative design data space coordinates determined by this aligning step to transform coordinatesof additional inspection data to design data space coordinates. The transformation may be performedbased on user input or by extracting the relevant information from the appropriate design files and/orprocess recipes (stepper recipes). An alternative approach for determining the transformation withoutinput from the user may include aligning (e.g., overlaying) the inspection data to the design data bymanually selecting alignment sites or by using an algorithmic overlay optimization approach. It is notedthat this is a die alignment technique. The wafer alignment technique may not be performed if die relative 62 coordinates are used (i.e., if the inspection system already accurately knows where the alignment site is for each die).

The methods described herein may or may not include acquiring the inspection data by performinginspection of a wafer. In other words, the methods described herein may be performed by a system (suchas a system described further herein) that does not include an optical or electron beam inspectionsubsystem. Instead, the system may be configured as a "stand-alone" system that is configured to receivethe inspection data from the inspection system. In this manner, the stand-alone system may acquire theinspection data from the inspection system. The stand-alone system may acquire the inspection data inany manner known in the art (e.g., via a transmission medium that may include "wired" and/or "wireless"portions). Alternatively, the method may be performed by a system that includes an inspection system. Inthis manner, the inspection system may form part of the system, and the inspection data may be acquiredby the system by performing inspection of the wafer. In addition, regardless of the manner in which theinspection data is acquired, the methods described herein may be performed using any type of inspectiondata known in the art in any format known in the art. The inspection data may include data for a defect ordefects detected on the wafer. In another example, in one embodiment, the inspection data is acquired forPWQ, which is described further herein.

The methods described herein can be advantageously used to correlate inspection space to design dataspace coordinates with relatively high precision, and such a correlation may be used in a number of stepsas described further herein. For example, the position of the inspection data in design data space may beadvantageously used to determine if the inspection data corresponds to care areas or non-care areas on thewafer, and the inspection process may be performed based on the type of area corresponding to theinspection data or different portions of the inspection data. For example, by shifting the raw image datawith respect to the inspection care areas so that the care areas are substantially exactly aligned topredetermined features in the design or CAD database for all points across the die, the methods andsystems described herein may generate substantially precise care areas such that inspection may beperformed only at critical locations on the die such as via locations while non-critical areas such as CMPpattern fill areas can be ignored. These critical locations, or "where to inspect" areas, may be input atrecipe setup and may be determined by "hot spot" analysis performed using results of CAD DRC, DFManalysis such as Design Scan and/or PWQ analysis, electrical test, FA, or some combination thereof.

For example, in some embodiments, the methods described herein include translating design data andinformation about the design data such as care areas stored in standard EDA layout format (e.g., GDSII, 63 OASIS, etc.) generated from layout analysis software tools into a format that can be used by an inspectionsystem. In this manner, the method may include transferring care area information from design tools to aninspection system. For instance, a translator module (not shown) may be configured to generateinspection care areas from a standard design format such as GDS or OASIS. Therefore, files in such adesign format include not the design but the resulting polygons from design analysis performed by EDAtools. The translator module, therefore, allows efficient translation between the two spaces (i.e., designand inspection).

In another embodiment, the method includes determining a position of a defect detected on the wafer inthe design data space based on the position of the inspection data in the design data space, which may beperformed as described herein, and determining values for one or more attributes of design datacorresponding to the position of the defect using a data structure in which predetermined values for theone or more attributes of the design data are stored as a function of position in the design data space. Inthis manner, the values for the one or more attributes of the design data corresponding to the position ofthe defect may be determined from persistent previously extracted design layout attribute data. In otherwords, the values for the design data attribute(s) corresponding to the defect position may be determinedfrom attributes that have been previously calculated based on the geometry of the design, for example, bydetermining values for the one or more attributes from polygons in the geometry (e.g., as a function ofgeometrical operations on the polygons). In this manner, the design can be processed at the polygon level,and values of any attributes at the polygon level that can be determined may be stored in the data structure.As such, the data structure may include "a superset" of data for the values of the one or more attributes ofthe design data stored in a data structure. The predetermined values for the one or more attributes of thedesign data as a function of position in the design data space may be generated using an FDA layoutanalysis tool or any other method or system known in the art. In this manner, the design may be pre-processed to determine values of the one or more attributes of the design data as a function of positionacross the design data space, and the values for the one or more attributes may be determined on a defect-by-defect basis by looking up values of the one or more attributes in the data structure "on the fly" usingthe defect positions in design data space. The data structure in which the predetermined values are storedas a function of design data space position may include any suitable data structure known in the art. In asimilar manner, the data structure may include predetermined values for one or more attributes of a designlayout for the design, one or more attributes of a floor plan of the design, one or more attributes of cells inthe design, any other information about the design, or some combination thereof as a function of positionin the design data space. 64

In one embodiment, the method includes determining a sensitivity for detecting defects on differentportions of the wafer, as shown in step 18 of FIG. 1. In one such embodiment, the method includesdetermining a sensitivity for detecting defects on different portions of the wafer based on the position ofthe inspection data in the design data space and one or more attributes of design data in the design dataspace. In such an embodiment, the method may include performing design based inspection bytransferring care area information from design tools to an inspection system. For example, the care areainformation may be used to identify the different portions on the wafer and the sensitivity to be used todetect defects in the different portions. As such, the one or more attributes of the design data may includethe care area information. However, the one or more attributes of the design data may also or alternativelyinclude any of the attribute(s) of the design data described herein.

The data preparation phase may include creating or acquiring data for one or more attributes of the designdata. The one or more attributes of the design data used to determine the sensitivity for detecting defectson different portions of the wafer may include process or yield information associated with design data.For example, in one embodiment, the one or more attributes of the design data are selected based on oneor more attributes of previously acquired inspection data for the wafer, other wafers, or some combinationthereof for the design data, different design data, or some combination thereof for a process layer forwhich the inspection data for the wafer was acquired, for different process layers, or some combinationthereof. In this manner, the one or more attributes of the design data in the design data space used todetermine the sensitivity for detecting defects on different portions of the wafer may be selected based ona correlation to attributes of previously collected inspection data from the same wafer or different waferson the same or different designs on the same or different process layers. The previously collectedinspection data may be stored in a data structure such as a fab database or any other suitable database, file,etc. or may be included in a knowledge base, which may be configured as described herein. In thismanner, the one or more attributes of the design data may be selected in this embodiment based oncumulative learning, historical data, or a training set of data.

In another embodiment, the one or more attributes of the design data are selected based on yield criticalityof defects previously detected in the different portions, fault probability of the defects previously detectedin the portions, or some combination thereof. In this manner, the sensitivity for detecting the defects maybe based at least in part on one or more attributes of the design data that are selected based on the yieldcriticality and/or fault probability of defects detected in the different portions. The process or yieldcriticality information may include, for example, critical defects determined by PWQ, locations of defectsof interest (DOI) based on hot spots (e.g., determined from inspection), hot spot information determined 65 from logical bitmaps, a KP value determined from test results for a defect detected at a hot spot, any otherprocess or yield information described herein, or some combination thereof. The KP value may bedetermined as described further herein. In addition, the fault probability may be determined in a mannersimilar to that described herein for determining the KP value for defects. The yield criticality value maybe determined in a manner similar to that described further herein for determining the yield relevancy ofdefects.

Data for the one or more attributes of the design data may also be referred to as "context" data that definesgeometrical areas in the device design that have different values of one or more attributes (e.g., type(s) offeatures within the areas such as contact areas or dummy fill areas, "where to inspect" information or"scare areas," "critical" areas in which a process failure is possible, or some combination thereof). Theterm context data is used interchangeably herein with the terms "context information" and "context map."The context information may be acquired from a variety of sources including simulation, modeling,and/or analysis software products that are commercially available from KLA-Tencor, other software suchas DRC software, or some combination thereof. Furthermore, additional context data may be determinedand combined with data for the attribute(s) of the design data, A data structure such as a database or fileincluding the design data and/or the context data may have any suitable format known in the art.

Determining the sensitivity as described above may be performed such that defects detected in differentportions of the wafer corresponding to design data having different values of the one or more attributes ofthe design data are detected with different sensitivity. In this manner, the method may also includedetermining, identifying, and/or selecting the different portions based on the values of the one or moredesign data attributes as a function of design data space position. The dimensions of all, some, or none ofthe different portions may be different and may vary depending on the resolution at which the values ofthe attribute(s) of the design data are available or are acquired. For example, if a context map is used todetermine the sensitivity for the different portions as described further herein, the dimensions of thedifferent portions may vary depending on the resolution of the context map.

In one such embodiment, the sensitivity is determined based on the position of the inspection data in thedesign data space and a context map, which as described further herein may include values for one ormore attributes of design data across the design data space. For example, the method may include usingthe context map to define relatively high sensitivity regions in a die on the wafer for critical regions andvariable sensitivity regions based on criticality of context. In one example, segments of the design datamay be defined to isolate dense arrays and logic, open areas, and grainy metal. A combination of image 66 gray level and context may also be used to define one or more segments in the design data. For example,pixels having an intermediate gray level may be combined in one segment. The image gray levels may bedetermined using a simulated image or an image acquired by the inspection system or other imageacquisition system.

In some embodiments, determining the sensitivity for detecting the defects on different portions of thewafer based on the position of the inspection data in the design data space and a context map is performedby the inspection system during inspection of the wafer. For example, the context map may be used by theinspection system as described herein when inspecting a wafer. In another embodiment, determining thesensitivity for detecting the defects on different portions of the wafer based on the position of theinspection data in the design data space and a context map is performed by the inspection system afteracquisition of the inspection data for the wafer has been completed. For example, the context map may beused by the inspection system as described above after the inspection data is available offline. In both ofthese embodiments, the method may use the context map to automatically define dummy areas (do notinspect regions) of the die on the wafer and to define coarse regions of the die for which differentsensitivity thresholds are to be used. For example, the context map (e.g., a context map that definesdummy fill areas) may be used to automatically define do not care regions which require no inspectionand can therefore be excluded for purposes of defect detection. Such regions are typically less wellcontrolled and therefore produce a relatively large amount of noise (when comparing die-to-die).Therefore, excluding such regions may increase the overall S/N of inspection.

In one embodiment, determining the sensitivity for detecting defects on different portions of the waferbased on the position of the inspection data in design data space and a context map includes determiningsensitivity thresholds used with the inspection data to detect the defects on the different portions of thewafer. In this manner, the sensitivity may be altered from region-to-region by altering one or morethresholds used for defect detection, which is analogous to segmented automatic threshold (SAT) methods.For example, low threshold (high sensitivity) detection can be used for critical regions, and high threshold(low sensitivity) detection can be used for non-critical regions. By segmenting the design data andvarying the threshold(s) used for defect detection based on one or more attributes of the design data, theoverall sensitivity of the inspection process can be increased. Therefore, the methods and systemsdescribed herein provide improved defect detection.

The method may also include using the context map described above to perform a number of differentsteps. For example, the context map (regardless of whether die-to-die inspection mode, standard reference 67 die-to-die inspection mode, etc. is used for defect detection) may be used to perform a variety of stepssuch as, but not limited to, determining sensitivity, filtering nuisance defects, classifying defects, andgenerating a review sample for either online or offline review. To use design or contextual information asdescribed further herein, the absolute location of an image pixel or other inspection data acquired (e.g., byscanning a wafer) during an inspection process is determined in design data space (e.g., design databasecoordinates). Mapping of the inspection data to the design data space to within half of the inspection pixelsize allows for substantially accurate setting of detection thresholds (by substantially accuratelyseparating critical from non-critical areas), filtering of nuisance defects from actual defects, and any othersteps, which may be performed as described further herein.

In addition, relatively high bandwidth, pixel-level context information may be used with the substantiallyhighly precise mapping of inspection space to design space coordinates for a wide range of applications.For example, a relatively high resolution context map may be used to automatically define pixel-levelregions that can be inspected with different sensitivities. Relatively high resolution context as describedherein is generally more accurate than user-defined region based multi-thresholds (RBMT) which arerelatively coarse (e.g., about 50 .mu.m by about 50 .mu.m) and inaccurate due to ambiguity in the carearea border (e.g., a border uncertainty having a spread of about 5 .mu.m or more).

In one embodiment, the context map can be used at the pixel level to control the detection sensitivity ateach pixel. However, a simpler approach (from a system complexity point of view) is to use the contextmap only for post-processing of defects detected using a detection method that does not detect defectsusing context information. In this manner, the mapping of inspection or wafer space to the design dataspace may be applied only to inspection data corresponding to detected defects. As described above fordie-to-die and standard reference die-to-die inspection, the position of a defect is determined in designdata space. Subsequently, a patch image of the design data at the position of the defect in design dataspace can be acquired, and this patch image may be used to determine design context corresponding to thedefect. Alternatively, a context map aligned to the design data may be used to determine the design datacontext corresponding to the defect based on the position of the defect in design data space.

For standard reference die-to-die inspection, determining the context of each pixel in the inspection datamay include determining the context of each standard reference die pixel. Since the standard reference dieimage is acquired during the recipe setup phase, the method may include aligning data for alignment sites(selected as described above) in the standard reference die image with data for the predeterminedalignment sites and performing a mapping transformation to determine the location of each standard 68 reference die pixel in design data space. These steps may also be performed during the recipe setup phase.In addition, the standard reference die may be mapped to the context data based on mapping of thestandard reference die to design data space, and the standard reference die pixels along with the contextcorresponding to each pixel may be stored offline and provided to or acquired by the inspection systemduring inspection. This processing can be performed offline and may be performed only once during therecipe setup phase.

In one such embodiment, each standard reference die pixel may be associated ("tagged") with contextinformation. In this manner, the context information may be "attached" to the standard reference diepixels. In one example, if there are 16 different possible contexts, a 4 bit tag can be attached to each pixel.Alternatively, the context data may be compressed using a suitable compression algorithm or method, orthe context data may be represented in polygonal form. In this manner, during inspection both thestandard reference die pixel data and the mapped (transformed) context data associated with the standardreference die pixel data may be provided to or acquired by the image computer or other process of theinspection system. Therefore, the context corresponding to inspection data pixels may be determinedbased on the context information of the corresponding pixels in the standard reference die image. As such,the context information corresponding to the inspection data pixels will be available for defect detectionand classification (and/or binning) applications, which may be performed as described further herein.

In another embodiment, the method may use the context map at any resolution to assist in waferinspection. For instance, a variable resolution context map may be used to assist in wafer inspection andbinning of defects. The resolution of the context map may vary depending on, for example, the accuracywith which the live pixel stream can be aligned to the design data and the accuracy requirements of theapplication. The context map at different resolutions may be represented in a number of different ways.For example, an absolute (i.e., to many decimal places in microns) representation of the context map in apolygonal format can be rendered internal to the inspection system at the appropriate pixel size to producea pixel level context map. Additionally, or alternatively, a coarse context map may include context forrelatively coarse regions having lateral dimensions of, for example, about 1 .mu.m.times.about 1 .mu.m.The coarse regions may form "Tiles" that separate the design data. Context data such as feature type (e.g.,dummy features, contacts, line ends), feature attributes (e.g., the minimum line widths/spaces betweengeometries, etc.), or some combination thereof may be associated with each tile.

In one embodiment, the method includes generating a relatively high resolution context map using thelocation and attribute information for a design that may be acquired from any software program that can 69 be used to analyze the design for critical regions and possible design rule violations. Such a context mapmay be generated using analysis software that is commercially available from KLA-Tencor (such asDesign Scan) or other software such as DRC software that generates a list of locations and some attributes(or labels) of each location that can be converted into a format for use by inspection, metrology, or reviewsystems.

In another embodiment, the method includes generating a relatively low resolution, coarse context map byextracting feature vectors from a CAD layout and using unsupervised clustering to define equivalentcontext groups. For example, a method for generating a relatively coarse context map (e.g., a mapincluding about 1 .mu.m.times.about 1 .mu.m regions or tiles) may include processing the CAD layoutfile, rendering or analyzing these tiles, and extracting certain attributes or feature vectors for each tile. Foreach region, multiple features may be extracted from a predefined feature set. The value of each feature isits feature vector. The feature vectors for each region can be combined into a series of feature vectors thatcan be used to determine the similarity of the regions by evaluating clustering in feature space. Thesefeature vectors (one or more vectors per tile) can be clustered in feature space using any unsupervisedclustering algorithm and/or method known in the art that can be used to find clusters of vectors (i.e., tilesthat have similar attributes). Examples of such algorithms and methods that can be used in the methodsdescribed herein are illustrated in U.S. Pat. No. 6,104,835 to Han. Each such cluster can then be assigneda unique context code or identity. A map of the die in which each tile is represented by this code oridentity can then be used by the inspection system as described further herein.

In a different embodiment, the method may include generating a relatively low resolution, coarse contextmap by rendering CAD layout patch images and cross-correlating the CAD layout patch images toidentify equivalent context groups (which may be used for binning as described further herein). Anothermethod for generating a context map (e.g., relatively a coarse context map) includes rendering the CADlayout file into patch images, separating the design data into the patch images, and identifying imagecross-correlations between patch images such that the patch images that have a relatively high cross-correlation may be binned into groups of patch images corresponding to the same context type.

In some embodiments, the context data used in the methods described herein may include context data formore than one layer that is or will be formed on the wafer. For example, some defects may not be locatedin critical areas in the layer on which the defects were detected. However, these non-critical defects maybe rendered critical if the defects are located in an area on the wafer in which a critical area in an 70 overlying layer will be formed on the wafer. The context map used in any of the steps described herein may be a context map for multiple layers on the wafer.

In another embodiment, the method includes determining a sensitivity for detecting defects on differentportions of the wafer based on the position of the inspection data in the design data space, one or moreattributes of design data in the design data space, and one or more attributes of the inspection data. Theattribute(s) of the design data used in this step may include any of the attribute(s) described herein. In onesuch embodiment, the one or more attributes of the inspection data include one or more image noiseattributes, if defects were detected in the different portions, or some combination thereof. In this manner,the one or more attributes of the inspection data used in this embodiment may include image noiseattributes and/or the detection or non-detection of defects in different regions of the inspection data. Theattribute(s) of the inspection data used in this step may include any other attributes of the inspection datadescribed herein. Determining the sensitivity in this embodiment may be performed for RBMT setup forthe inspection process based on image noise correlated to design attributes. Determining the sensitivity inthis embodiment may be further performed as described herein.

In another embodiment, the method includes altering one or more parameters for detecting defects on thewafer based on one or more attributes of schematic data for a design of a device being fabricated on thewafer, one or more attributes of expected electrical behavior of a physical layout for the device, or somecombination thereof. In this manner, design schematic data attribute(s) and other electrical descriptions ofthe behavior expected of the physical design (layout) may be used to alter one or more parameters fordetecting defects or any other parameters of the inspection process. For example, information about thecritical and non-critical paths, active and non-active geometries, and other such information about theschematic data or expected electrical behavior of the physical design (layout) may be used to alter thesensitivity for detecting the defects, to determine which portions of the wafer in which defects are to bedetected (e.g., the care areas and non-care areas), determining which portions of the inspection data are tobe used for detecting defects (e.g., based on the correlation from wafer space to design data space), andaltering any other one or more parameters of the inspection process.

In another example, defect capture rate and electrical behavior monitoring may be performed based ondesign/image context. For example, the electrical behavior may be monitored by performing electricaltesting, FA, or any other testing or analysis known in the art or using results of such testing or analysis.The results of the electrical testing, FA, or other testing or analysis may be correlated to contextinformation about the schematic data and the physical layout for the device. The monitored defect capture 71 rate and the electrical behavior may be correlated to the design/image context to determine informationabout the defects detected on the wafers, information about the inspection process used to detect thedefects, and information about the design. For example, results of monitoring the defect capture rate andthe electrical behavior may be used to determine what type of defects are being detected on the wafer,which defects should be detected (e.g., in an online inspection process) but are not being detected, andweak points in the design. Such information may be used to alter the inspection process as describedfurther herein.

In an additional embodiment, the method includes altering one or more parameters for detecting defectson the wafer using the inspection data based on one or more parameters of an electrical test process to beperformed on the wafer. For example, one or more parameters for detecting defects on the wafer or anyother parameters of the inspection process may be altered based on an electrical test definition associatedto the relevant (physical) design data space. In this manner, the inspection process may be altered basedon how electrical testing is performed. In one such example, the areas on the wafer that will be analyzedby the electrical test process may be determined based on the one or more parameters of the electrical testprocess, and the one or more parameters for detecting the defects or any other parameters of theinspection process may be altered such that defects in the areas on the wafer that will not be analyzed inthe electrical test process may be inspected with adequate sensitivity.

In addition, the one or more parameters of the electrical test process and the positions of the defects in thedesign data space or wafer space may be used to identify defects that will not be tested by the electricaltest process (or "electrical test escapes"). In one such example, the areas on the wafer that will be tested inthe electrical test process and the positions of the defects on the wafer may be used to determine whichdefects will not be tested by the electrical test process. In another example, the areas in the design thatwill be tested in the electrical test process and the positions of the defects in design data space may beused to determine which defects will not be tested by the electrical test process. In a similar manner, theone or more parameters of the electrical test process and the positions of the defects in the design dataspace or wafer space may be used to separate or bin defects into different groups depending on whetherthe defects will or will not be tested by the electrical test process.

In wafer space, attributes of the design data and information about hot spots (e.g., information from a hotspot database) may be used to setup an inspection recipe in the monitoring phase. For example, care areasmay be automatically defined in the monitoring phase in wafer space. The automatically defined careareas may include macro and micro care areas. The automatically defined care areas may also include do 72 not care areas. In addition, the inspection recipe may be setup for automatically altering the sensitivity,filtering nuisance defects, enhancing capture of known systematic defects (e.g., enhancing sensitivity forhot spots or hot spot regions), and suppressing defect signals or data corresponding to cold spot regions.Furthermore, attributes of the design data and information about the hot spots may be used to setup theinspection recipe to better group, classify or bin defects and sample defects, which may include designdata based binning using GDS (i.e., GDS pattern grouping) and/or GDS pattern grouping pareto, each ofwhich may be performed as described herein.

In a further embodiment, the method includes periodically altering one or more parameters of aninspection process performed by the inspection system based on results of one or more steps of themethod using a feedback control technique. In another embodiment, the method includes automaticallyaltering one or more parameters of an inspection process performed by the inspection system based onresults of one or more steps of the method using a feedback control technique. For example, themonitoring phase may include automatic process control (APC) for inspection processes that involveschanging the inspection recipe or parameters based on previous metrology results perhaps in combinationwith prior knowledge of process zone differences. APC for metrology processes may be performed basedon systematic defects, which may be identified according to any of the embodiments described herein, todetermine locations at which measurements are to be performed in addition to the measurements that areto be performed in subsequent metrology. APC for test processes may be performed based on systematicdefects, which may be identified according to any of the embodiments described herein, to determinelocations at which testing is to be performed and the electrical parameters that are to be tested insubsequent electrical testing.

In an additional embodiment, the method includes generating a knowledge base using results of one ormore steps of the method and generating an inspection process performed by the inspection system usingthe knowledge base. The knowledge base may be generated by storing one or more image attributesand/or one or more attributes of the design data in a suitable data structure. In addition, the knowledgebase may include cumulative learning acquired by the inspection system that can be used to generate theinspection process. For example, for an inspection process, the knowledge base may be used to determinecumulative results of the inspection such as frequency of defect detection and percentage of detecteddefects that are nuisance defects, and such cumulative results may be used to determine additionalinformation such as the probability that a defect is a nuisance defect. 73

Such a knowledge base may be used to generate the inspection process as described further herein. In thismanner, the knowledge base may be used to generate new inspection recipes. In addition, the knowledgebase may be used to generate the inspection process for recipe setup and/or wafer-less recipe setup.Generating the inspection process may include selecting any one or more parameters of the inspectionprocess. In addition, the knowledge base may be used to alter an inspection process by recipeoptimization and automated recipe optimization. For example, the method may include using a feedbackmechanism for training of the knowledge base for the periodic or automatic optimization of one or moreparameters of an existing inspection process. Altering the inspection process may include altering any oneor more parameters of the inspection process.

In another embodiment, the method includes optimizing a wafer inspection process for determiningprintability of a reticle defect on the wafer using the position of the inspection data in the design dataspace and a context map. In this manner, the method may include optimization of a wafer inspectionprocess for purposes of determining the printability of defects detected on a reticle using CBI incombination with a context map. Optimizing the wafer inspection process may include altering any one ormore parameters of the wafer inspection process, which may include any parameter(s) of any waferinspection process(es) described herein. In general, determining the printability of a reticle defect on awafer may include inspecting the wafer to detect defects on the wafer that may correspond to a defect onthe reticle. In this manner, optimizing the wafer inspection process for determining printability of reticledefect(s) may include optimizing the wafer inspection process for detecting defects on the wafer that maycorrespond to a defect on the reticle.

In one example, the method may include using the position of the inspection data, acquired for the wafer,in design data space and the positions of one or more reticle defects in design data space, which may bedetermined as described herein, to identify portions of the inspection data that can be used to determinethe printability of the reticle defect(s). In this manner, the design data space positions of the reticledefect(s) and the inspection data acquired for the wafer may be used to determine portions of theinspection data that can be used to detect defects on the wafer that may correspond to the reticle defect(s).Any of the attribute(s) of the design data included the context map may be used to select one or moreparameters of the wafer inspection process for determining the printability of the reticle defects. Forexample, the context map may be used to determine one or more attributes of the design datacorresponding to the portions of the inspection data identified as described above. In this manner, one ormore parameters of the wafer inspection process used for different portions of the inspection dataidentified as described above may be selected based on the one or more attributes of the design data 74 corresponding to the different portions. As such, different portions of the inspection data identified asdescribed above, which correspond to design data having different values of the one or more attributes,may be processed with one or more different parameters to detect wafer defects that may correspond tothe reticle defect(s). In one such example, the context map may be used to determine the criticality of thedesign data corresponding to different portions of the inspection data acquired for the wafer, which areidentified as described above, and the criticality may be used to determine the sensitivity for detectingdefects in the different portions of the inspection data. In one such particular example, differentparameters of the wafer inspection process may be selected for different portions of the inspection datasuch that the printability of one or more reticle defects may be determined with higher accuracy in criticalareas of the design data than in non-critical areas of the design data.

The one or more parameters of the wafer inspection process may also be altered and/or optimized basedon the position of the inspection data in design data space, the context map, and any other informationdescribed herein. For example, one or more attributes of different portions of the design data in which oneor more reticle defects were detected may be determined using a context map, and the one or more designdata attributes of the different portions may be used in combination with one or more attributes of reticleinspection data (such as attributes of the one or more reticle defects) to select the wafer inspection processparameters for different portions of the inspection data corresponding to the different portions of thedesign data in which the reticle defect(s) were detected. In one such example, the one or more parametersof the wafer inspection process may be selected such that the printability of different types of reticledefects located in portions of the design data having substantially the same attribute(s) may be determinedwith one or more different parameters of the wafer inspection process. In another example, the one ormore parameters of the wafer inspection process may be selected such that the printability of the sametype of reticle defects located in portions of the design data having different values of the attribute(s) maybe determined with one or more different parameters of the wafer inspection process.

The context map used in the embodiments described above for optimizing the wafer inspection processfor determining printability of reticle defects may be configured as described herein and may include anyof the context maps described herein. In addition, any of the information included in the context map maybe used in the embodiments described above for altering one or more parameters of the wafer inspectionprocess.

In some embodiments, the method includes altering one or more parameters of an electrical test process tobe performed on the wafer based on defects detected on the wafer using the inspection data. For example, 75 in test space, the monitoring phase may include using systematic defects identified according to any of theembodiments described herein to define or modify the test pattern and/or other test parameters. Inaddition, the defects detected on the wafer using the inspection data may be used to determine if one ormore of the defects will not be tested by the electrical test process (or are "electrical test escapes") and toalter one or more parameters that define areas on the wafer at which the electrical test process isperformed such that the one or more defects will be tested by the electrical test process. In this manner,the results of the inspection process may be fed forward to the electrical test process to reduce the numberof defects that are not tested in the electrical test process. In addition, the one or more parameters of theelectrical test process may be altered based on the defects detected on the wafer using the inspection data,positions of the defects in design data space, which may be determined as described herein, or waferspace, one or more attributes of the defects, which may include any attribute(s) of the defects describedherein determined in any manner described herein, one or more attributes of the design data, which mayinclude any attribute(s) of the design data described herein determined in any manner described herein,any other information described herein, or some combination thereof. For instance, the positions of thedefects, the attribute(s) of the defects, and the attribute(s) of the design data may be used to determine afault probability value for one or more of the defects as described herein. If the defects that will not betested by the existing electrical test process have a relatively low fault probability value, then one or moreparameters of the electrical test process may not be altered by the method. In contrast, if the defects thatwill not be tested by the existing electrical test process have a relatively high fault probability value, thenone or more parameters of the electrical test process may be altered such that the defects having therelatively high fault probability value are tested by the electrical test process. In a similar manner, one ormore parameters of a metrology process such as sampling of the metrology process may be selected,determined, or altered as described above.

Aligning the inspection data to the design data enables inspection of "hot spots" on the wafer. A "hotspot" may be generally defined as a location in the design data printed on the wafer at which a killerdefect may be present. In contrast, a "cold spot" may be generally defined as a location in the design dataprinted on the wafer at which a nuisance defect may be present. One example of a nuisance defect is avariation in critical dimension (CD) of a feature that will not substantially affect the yield of the deviceformed on the wafer but causes the inspection system to indicate that there is a defect at that location.Some defects may be killer defects only under certain conditions such as if the defects are contacted by adevice structure formed on another layer of the wafer. Therefore, the locations at which such defects maybe present in the design data printed on the wafer may be generally referred to as "conditional hot spots." 76

In an additional embodiment, the method includes determining if defects detected on the wafer arenuisance defects, as shown in step 20 of FIG. 1. Whether or not a defect is a nuisance defect is determinedbased on the position of the inspection data in the design data space and one or more attributes of thedesign data. For example, in some embodiments, the method includes determining positions of the defectsin the design data space based on the position of the inspection data in the design data space anddetermining if the defects are nuisance defects based on the positions of the defects in the design dataspace and one or more attributes of design data in the design data space. The one or more attributes of thedesign data used to identify nuisance defects in this step may include any of the attribute(s) describedherein. For example, the one or more attributes of the design data may be defined in the context map. Inthis manner, the method may include applying the context map to defect data to filter (e.g., discard)defects considered not important (e.g., nuisance defects) in applications such as, but not limited to, PWQ.As such, portions of the design that are approaching the limits of the capabilities of the fabricationprocesses may be separated into portions that are critical and portions that are not critical based on thecontext. In another example, the attribute(s) of the design data used to identify nuisance defects in thisstep include hot spot information for the design data. In this manner, the positions of the defects in designdata space and the hot spot information may be used to identify defects detected at cold spots in thedesign data as nuisance defects. PWQ applications for lithography generally involve exposing dies on a wafer at different exposuredosages and focus offsets (i.e., at modulated dose and focus) and identifying systematic defects in the diesthat can be used to determine areas of design weakness and to determine the process window. Examplesof PWQ applications for lithography are illustrated in commonly assigned U.S. patent Ser. No. 7,729,529filed Dec. 7, 2004 by Wu et al.,. Many artifacts of focus and exposure modulation can appear as defects(die-to-standard reference die differences), but are in fact nuisance defects. Examples of such artifactsmay include CD variations and line-end pullbacks or shortening in regions in which these artifacts haveno or little impact on yield or performance of the device. However, the position of a defect may bedetermined substantially accurately with respect to the design layout using the methods described herein.In addition, the methods described herein can be used to determine care areas with relatively highaccuracy as described further above. These "micro" care areas can be centered on known hot spots andinspected with relatively high sensitivity or may be centered on known cold-spots (systematic nuisance)as don't care areas or areas inspected with relatively low sensitivity.

As described above, therefore, the method may include determining if a defect is a nuisance defect basedon the position of the defect with respect to the design data space and whether or not that position is 77 located in a care area. The defects may also be filtered depending on context, size, redundancy, PWQ"rules," or some combination thereof. For example, in process space, PWQ analysis and DOE analysismay be performed using hot spots in the monitoring phase. In addition, the methods described herein maybe used to extend PWQ applications below 65 nm design rules at which currently used noise filters faildue to limited resolution. One advantage of the methods described herein is, therefore, that the methodscan be used to extend BF inspection for detecting systematic and DFM defects. In particular, CBI asdescribed herein may enable additional functionality for BF inspection systems such as systematic defectinspection and/or DFM applications at 65 nm design rules and below. The methods also provide or assistin making relatively quick determinations of the root cause of a DFM systematic defect. Determining theroot cause may be performed as described further herein.

In another embodiment, the method includes determining if the defects not determined to be nuisancedefects are systematic or random defects, as shown in step 22, based on one or more attributes of thedesign data in the design data space (which may be defined in the context map as described further above)or by comparing the positions of the defects to positions of hot spots, which may be stored in a datastructure such as a list or database. In addition, all of the defects not of interest may not be nuisancedefects. For instance, systematic defects that have relatively low or no yield impact may be defects not ofinterest and not nuisance defects. Such defects may appear on the active pattern or device area on thewafer. The methods described herein may include identifying such defects. Such defects, or defectslocated at cold spots, may be identified from the design context (e.g., redundant vias), modeling (e.g.,DesignScan), PWQ, inspection and review, and defect correlation with test (e.g., relatively high stackeddefect density at a location with relatively low stacked electrical fault locations, etc.). In addition,monitoring of these defects may be performed by comparing the positions of the defects with thepositions of hot spots and cold spots. These defects may also be binned separately from other systematicdefects using the design data based grouping methods described herein if the pattern in which thesedefects are located is common. Furthermore, discovery of the systematic defects may be performed bycorrelating multiple sources of input from design, modeled results, inspection results, metrology results,and test and FA results.

Systematic DOI may include all pattern dependent defect types. Identifying systematic defects isadvantageous such that the impact that these defects will have on devices can be analyzed. Random DOImay include a statistical sample of critical types of random defects. Identifying random defects isadvantageous since critical types of random defects can be analyzed to determine the impact that thesedefects will have on devices. In addition, by identifying the random defects, one or more inspection 78 process parameters may be altered to suppress the detection of random defects that can be considerednuisance defects. Furthermore, the inspection process parameter(s) may be altered to distinguish nuisancedefects from systematic causes (cold spots).

Determining if defects are nuisance, systematic, or random defects is also advantageous since yield can bepredicted more accurately based on the types of defects that are detected on a wafer or wafers and therelevance to the yield that the different types of defects have. In addition, the results of the methodsdescribed herein, possibly in combination with the yield predictions, may be used to make one or moredecisions regarding the design data and the manufacturing process. For example, the results of themethods described herein may be used to verify the IC design. In another example, the results of themethods described herein may be fed back to the IC design process such that the IC designs generated bythe process may be susceptible to fewer systematic defects and/or fewer types of systematic defects. Inone such example, the results of the methods described herein may be used to alter the design and/oroptical rules used in the IC design process. In yet another example, the results of the methods describedherein may be used to alter one or more parameters of a process or processes used to fabricate the waferlevel being inspected. Preferably, the one or more parameters of the process(es) are altered such thatfewer systematic defects and/or fewer types of systematic defects, and possibly fewer critical randomdefects and/or fewer types of critical random defects, are caused by the process(es).

In some embodiments, the method includes classifying one or more defects, as shown in step 24, based onthe position of the inspection data in the design data space and one or more attributes of the design data inthe design data space. For example, the position of the defect in design data space may be determinedfrom the position of the inspection data in the design data space. In addition, one or more attributes of thedesign data associated with the position of the defect in the design data space may be determined from thecontext map or in any other manner described herein, and the one or more attributes associated with theposition of the defect may be used to classify the defect. In another embodiment, the method includesclassifying defects detected on different portions of the wafer based on the positions of portions of theinspection data corresponding to the defects in design data space and a context map, which as describedfurther herein may include values for one or more attributes of design data across the design data space.In this manner, the method may use the context map to classify the defects by context. Classifying thedefect(s) in this step may also be performed in any other manner described herein.

In one such embodiment, classifying the defects is performed by the inspection system during inspectionof the wafer. For example, the context map may be used by the inspection system to classify defects as 79 described herein when inspecting the wafer. In another such embodiment, classifying the defects isperformed after acquisition of the inspection data for the wafer has been completed. For example, thecontext map may be used by the inspection system to classify defects as described herein subsequentlyafter the inspection data is available offline. In this manner, the method may include using the contextmap to classify defects either online (e.g., using the inspection system) in a second pass high resolutiondefect classification (HRDC) or offline in HRDC (e.g., using a SEM review station). Typically, secondpass defect classification, whether performed online by the inspection system or offline on a reviewsystem (optical or SEM), involves redetection of the defect and classification. Both redetection andclassification may be performed manually by the user or automatically (i.e., automatic defectclassification, ADC). As design rules shrink, the possibility of identifying the wrong object as the defectin the review process increases. The design data and context map can be useful for both redetection andclassification.

For redetection, the context map provides local background information near the defect that allows a useror the system to position the correct defect in the field of view of the review system. For instance, a localimage of a wafer generated by the review system may be aligned to the design data thereby allowing theposition of the defect in design data space to be substantially accurately identified in the aligned localimage. In addition, a simulated image of the design data (e.g., a gray scale image) may be used by thereview system for alignment to the local image, and the position of the defect in the design data spacemay be used to determine the position of the defect in the local image. Such a simulated image may beused for redetection of the defect and fine alignment in the review process. Examples of such simulationsare illustrated in U.S. Pat. No. 6,581,193 to McGhee et al. The methods described herein may include anystep(s) of the methods described in this patent. Therefore, the methods and systems described herein canbe used to perform relatively highly accurate defect detection.

For classification, the context map may provide additional information that can be used (along with dataacquired by review) to determine the class to which the defect belongs. Review may also be performedusing the context map, the data acquired by review, and the inspection data. For example, patch imagesacquired by a time delay integration (TDI) camera of the inspection system and/or high resolution patchimages acquired by the inspection system may be sent to review with the defect sample. The patch imagesmay be used in combination with the context map for optical or SEM review and classification. In thismanner, the coordinate accuracy with which defect positions can be determined as described furtherabove enables the system to substantially accurately classify defects based on design context and/or DRCfailure codes. 80

One or more of the steps described above may be performed in the monitoring phase in which systematicdefects are identified and classified (or binned) using the inspection results and any other resultsdescribed herein. The monitoring phase may include excursion monitoring and baseline improvement.The monitoring phase may be performed during product ramp and production. In multi-source space(which may involve a correlation between any of design, wafer, reticle, test, and process spaces),identifying and classifying systematic defects detected by inspection may use any combination of thesteps described herein. In addition, one or more of the multi-source space steps may be used in anycombination thereof to validate systematic defect identification.

In addition, the position of a defect in design data space may be combined with inspection data, designdata, or classification data to identify systematic defects (e.g., defects located at hot spots or cold spots) inthe monitoring phase. The identified hot spots may also be used to determine design context forinspection results where there is a "hit" at a hot spot location, which may be performed on-tool or off-toolin post-processing. The yield (or KP value) correlated to design data space may also be used as anattribute for monitoring systematic defects. In addition, one or more defect attributes may be used to inferassociation to a hot spot when there are multiple hot spot candidates.

In reticle space, the monitoring phase may include generating information about hot spots (e.g., creationof hot spot list(s)) that can be compared to inspection results to separate known systematic defects fromrandom defects. In addition, one or more hot spot attributes such as context information for the hot spotsmay be used to determine if the hot spots can be shared across multiple technologies, layers, or devices,and if so, which technologies, layers, or devices. Furthermore, systematic defects identified by inspectionmay be used to define or modify one or more parameters of a metrology process such as the metrologysite locations, measurements, or other parameters.

In some embodiments, the method includes determining a fault probability value for one or more defectsdetected on the wafer based on the position of the inspection data in the design data space and one ormore attributes of design data in the design data space. In addition, the method may include determining afault probability attribute value of detected defects on different portions of the wafer based on the positionof the inspection data in design data space and one or more attributes of the design data in the design dataspace. The fault probability value for the defects may be determined based on the design data spaceposition of the inspection data corresponding to the defects and one or more attributes of design data inthe design data space as described further herein. 81

In another embodiment, the method includes determining coordinates of positions of defects detected onthe wafer in the design data space based on the position of the inspection data in the design data space andtranslating the coordinates of the positions of the defects to design cell coordinates based on a floor planfor the design data. In this manner, the defect coordinates may be translated to design cell coordinatesbased on the floor plan of the chip design. In one such embodiment, the method includes determiningdifferent regions surrounding the defects using an overlay tolerance and performing defect repeateranalysis using the regions for one or more cell types to determine if the one or more cell types aresystematically defective cell types and to determine one or more locations of one or more systematicallydefective geometries within the systematically defective cell types. In this manner, the method mayinclude using cell-based coordinates for repeater analysis. In particular, defect repeater analysis may beperformed using an overlay tolerance (e.g., to define a two-dimensional region surrounding each defect)and for each cell type to determine the existence of systematically defective cell types and locations ofsystematically defective geometries within the cells. In addition, the method may include cell-basedbinning of the defects based on cell context. Such binning may be performed as described further herein.In one such embodiment the method includes determining if spatially systematic defects occur in thesystematically defective cell types based on one or more attributes of design data for cells, geometries, orsome combination thereof located proximate to the systematically defective cell types. In this manner, thedesign contexts (surrounding cells or geometries) of the spatially systematically defective cells may beused as attributes to further characterize the occurrence of spatially systematic defects.

In another embodiment, the method includes binning the defects (e.g., all or some of the defects) intogroups, as shown in step 26, based on the position of the inspection data in the design data space and oneor more attributes of the design data in the design data space. For example, the positions of the defects indesign data space may be determined from the position of the inspection data in the design data space asdescribed herein. The one or more attributes of the design data used to bin the defects may then bedetermined based on the positions of the defects in design data space. The one or more attributes of thedesign data used in this embodiment may include any of the attribute(s) of the design data describedherein such as values associated with the design data (e.g., yield impact) perhaps in combination withother inspection results (e.g., integrated defect organizer (iDO) results and integrated automatic defectclassification (iADC) results). In addition, one or more attributes of the design data associated with thepositions of the defects in the design data space may be determined from the context map. In this manner,the method may include applying the context map to defects detected during wafer inspection to sortdefects into contexts. 82

The methods described herein may, therefore, include context-based background binning for waferinspection. For instance, as described above, the method may use the context map to bin the defects bycontext. In one such example, the defects that remain after nuisance filtering may be sorted by context orany other information described above to identify defects that are systematic defects rather than randomdefects. Context may also be used in conjunction with other image-derived attributes associated with thedefects to perform binning and sorting.

Furthermore, the defects may be binned based on the expected electrical parameters of the defects and/orthe expected electrical parameters of the device features proximate the defect position in the design dataspace. The expected electrical parameters of the defects and the device features may be determined basedon prior electrical testing, simulation of the electrical parameters of the defects, review of the defects, orsome combination thereof. In addition, fault simulation for one or more defects may be based on theposition of the defect(s) in the design data space and/or the group in which the defect(s) are binned.

In some embodiments, the method includes binning the defects into groups based on the position of theinspection data in the design data space, one or more attributes of design data in the design data space,and one or more attributes of reticle inspection data acquired for a reticle on which the design data isprinted. In this manner, the reticle inspection data may be used as binning attributes. In particular, reticleinspection data attributes may be used in the binning of defects detected on a wafer. In this embodiment,the one or more attributes of the design data may include any of the attribute(s) of the design datadescribed herein. The one or more attributes of the reticle inspection data may include any attributes ofthe reticle inspection data such as defects detected on the retile, positions of defects detected on the reticlein reticle space, one or more attributes of the defects detected on the reticle, one or more attributes of thedesign data printed on the reticle, or some combination thereof. The one or more attributes of the defectsdetected on the reticle may include any of the defect attribute(s) described herein. In addition, the one ormore attributes of the design data printed on the reticle may include any of the design data attribute(s)described herein.

The attribute(s) of the reticle inspection data may be determined in any suitable manner by the methodand system embodiments described herein (e.g., by using output of a reticle inspection system).Alternatively, or in addition, the attribute(s) of the reticle inspection data may be acquired by the methodand system embodiments described herein from a storage medium in which the attribute(s) are storedand/or from a reticle inspection system that determined the attribute(s). 83

Binning the defects based, at least in part, on the one or more attributes of the reticle inspection data maybe used to separate defects based on whether the defects are caused by defects on the reticle, one or moreattributes of the reticle defects that caused the defects on the wafer, and one or more attributes of thedesign data printed on the reticle, which may have caused defects on the wafer. As such, the binningresults can provide additional information about the cause of the defects and/or how the reticle affects thedefects and/or the design data printed on the wafer. Such binning results may be advantageously used toalter one or more parameters of a reticle manufacturing process, one or more parameters of a reticleinspection process, one or more parameters of a reticle defect review process, one or more parameters of areticle repair process, one or more parameters of any other reticle- or design-related process, one or moreparameters of any other process described herein, or some combination thereof. Binning the defects inthis embodiment may also be performed based on the position of the inspection data in design data space,one or more attributes of the design data in design data space, one or more attributes of the reticleinspection data, and any other information described herein.

In another embodiment, the method includes binning the defects into groups based on the position of theinspection data in the design data space, one or more attributes of design data in the design data space,and one or more attributes of the inspection data. In this manner, one or more attributes derived frominspection data may be used in the binning calculations. In this embodiment, the one or more attributes ofthe design data may include any of the attribute(s) of the design data described herein. In addition, the oneor more attributes of the inspection data used for binning may include any attribute(s) of the inspectiondata described herein. The defects may also be binned in this embodiment using any other informationdescribed herein. Binning in this embodiment may be performed as described further herein.

In an additional embodiment, the method includes binning the defects into groups based on the position ofthe inspection data in the design data space, one or more attributes of design data in the design data space,one or more attributes of the inspection data, and one or more attributes of reticle inspection data acquiredfor a reticle on which the design data is printed. In this manner, the reticle inspection data may be used asbinning attributes. In particular, reticle inspection data attributes may be used in the binning of defectsdetected on a wafer. The one or more attributes of the design data in the design data space used forbinning in this embodiment may include any of the attribute(s) of the design data described herein. Theone or more attributes of the inspection data used for binning in this embodiment may include any of theattribute(s) of the inspection data described herein. The one or more attributes of the reticle inspectiondata used for binning in this embodiment may include any of the attribute(s) of the reticle inspection data 84 described herein. Binning in this embodiment may be performed as described further herein. In addition,the binning results of this embodiment may be used to perform any step(s) of any method(s) describedherein.

In some embodiments, the method includes binning the defects into groups based on the position of theinspection data in the design data space, one or more attributes of design data in the design data space,one or more attributes of the inspection data, and one or more attributes of previously acquired inspectiondata for the wafer, other wafers, or some combination thereof for the design data, different design data, orsome combination thereof for a process layer for which the inspection data for the wafer was acquired, fordifferent process layers, or some combination thereof. In this manner, attributes determined frompreviously collected inspection data for the same or different wafers, the same or different designs, andthe same or different process layers may be included in the binning calculations. The previously collectedinspection data may be stored in a data structure or may be included in a knowledge base, which may beconfigured as described herein. In this manner, the one or more attributes of the previously acquiredinspection data may be determined from cumulative learning data, historical data, or a training set of data.In this embodiment, the one or more attributes of the design data may include any of the attribute(s) of thedesign data described herein. In addition, the one or more attributes of the inspection data used forbinning may include any attribute(s) of the inspection data described herein. The defects may also bebinned in this embodiment using any other information described herein. Binning in this embodimentmay be performed as described further herein.

In any of the embodiments described above, binning may be performed on-tool, off-tool, or somecombination thereof.

In an additional embodiment, the method includes selecting at least a portion of the defects for review, asshown in step 28, based on the position of the inspection data in the design data space and one or moreattributes of the design data in the design data space such as yield impact associated with the design dataperhaps in combination with other inspection results (e.g., iDO results and iADC results). The one ormore attributes of the design data used to select defects for review may include any attribute(s) of thedesign data described herein. In addition, the position of the inspection data in design data space may beused to determine the positions of the defects in design data space as described herein, which can be usedto determine the attribute(s) of the design data corresponding to the defects as described herein. In somesuch embodiments, nuisance defects can be filtered from other defects detected on the wafer as describedherein, and only the DOI (or non-nuisance defects) can be retained for review or further analysis. In 85 another embodiment, the defect list and the identified hot spots, classification of the defects and hot spots,and design context may be used to improve review sampling (which may include sub-sampling) in themonitoring phase, which may be performed on-tool or during post-processing off-tool.

In another embodiment, selecting defects for review is performed as a function of the binning results. Forexample, defects in some groups may be selected for review while defects in other groups may not beselected for review. In another example, some groups of defects may be more heavily sampled than othergroups (i.e., more defects from some groups may be selected for review). The groups of defects that aresampled and the degree to which the groups are sampled may be determined based on, for example, oneor more attributes of the design associated with each of the groups or any other information describedherein that is associated with the groups of defects. Selecting the defects for review may also beperformed as a function of the yield relevance associated with the defects or the defect bins. For example,the population of defects may be split into random defects and systematic defects, and a different sampleplan may be used for each of the different defect types. In this manner, the sampling strategies for thedifferent types of defects may be dramatically different.

In some embodiments, the method includes selecting at least a portion of the defects for review, whichincludes at least one defect located within each portion of the design data in the design data space havingdifferent values of one or more attributes of the design data. In this manner, defects in each differentportion of the design data may be sampled for review. For instance, the context of each defect can be usedto sort defects for review (e.g., by criticality of context) to generate a review sample that ensures that allcontexts in which defects are detected are represented in the review sample.

In a further embodiment, the method includes determining a sequence in which the defects are to bereviewed, as shown in step 30, based on the position of the inspection data in the design data space andone or more attributes of the design data in the design data space. For example, the method may includeusing the context map to sort defects based on priority for offline review (e.g., optical or SEM review).The context of each defect can be used to sort defects for review (e.g., by criticality of context) such thatsystematic defects and potential systematic defects are given a higher priority than other defect types.

Aligning the inspection data stream to predetermined alignment sites (such as rendered images from theGDS database) at sample points across a die pm a wafer to provide sub-pixel alignment of inspection dataat all points on the wafer provides a number of advantages. For instance, since the raw data stream issubstantially precisely aligned to the design data, defect positions in design data space may be determined 86 with sub-pixel accuracy (e.g., sub-100 nm accuracy vs. 1000 nm accuracy currently achievable). Thesubstantially high accuracy defect positions may greatly improve the precision of any subsequent reviewprocess and the speed with which defects can be located, imaged, and analyzed on a defect review systemsuch as a SEM or a FIB system. In addition, the context information associated with defects can be usedin the HRDC phase, which may be performed on the inspection system in a second-pass review or offlineon a SEM or optical review station. Such information may also be provided to or acquired by anothersystem such as an automatic defect location (ADL) system in addition to any other local contextualinformation about a defect that may aid in locating the defect either automatically or manually. Inaddition, the review system may use this information to generate a logical to physical coordinatetranslation appropriate for that system and that wafer under the measurement parameters.

In some embodiments, the method includes extracting one or more predetermined attributes of outputfrom one or more detectors of the inspection system acquired for different portions of the wafer based onthe position of the inspection data in the design data space and one or more attributes of design data in thedesign data space. In this manner, the method may include extracting predetermined signal or imageattributes for inspection data regions (e.g., specific subsets of the area inspected) based on the position ofthe inspection data in design data space and one or more attributes of the design data in deign data space.The extracted attribute(s) of the output from the one or more detectors may include, for example,brightness or standard deviation of the signal or image for pixels in the different portions. In addition, thewafer may be a patterned wafer, on which a pattern corresponding to the design data is printed. Therefore,the attribute(s) of the output may be extracted based on knowledge about the output corresponding to thepattern formed on the wafer. In addition, information about structures in the pattern formed on the wafermay be extracted from the output from the one or more detectors.

The extracted attribute(s) of the output from the detector(s) may be used to generate an image of theattribute(s) across the different portions of the wafer. In this manner, the method may include generating"design aware images" of the surface of the wafer. The images may be used to determine one or moreattributes of the wafer such as attributes of the wafer that can be determined by metrology. In this manner,the inspection system may be used like a metrology tool by extracting attribute(s) of output (such assignals) from the one or more detectors in substantially precisely defined locations based on the designdata or the layout for the design data. The different portions of the wafer may, therefore, be treatedessentially as metrology sites in this embodiment. In addition, the one or more extracted predeterminedattributes of the output from one or more detectors of the inspection system may be used to perform one 87 or more steps such as the steps described in commonly owned U.S. patent Ser. No. 8,284,394 by Kirk etal. filed Feb. 9, 2006.

The one or more attributes of the design data used in this embodiment may include any of the attribute(s)of the design data described herein. In one such embodiment, the one or more attributes of the design dataare selected based on one or more attributes of previously acquired inspection data for the wafer, otherwafers, or some combination thereof for the design data, different design data, or some combinationthereof for a process layer for which the inspection data for the wafer was acquired, for different processlayers, or some combination thereof. In this manner, the one or more attributes of the design data in thedesign data space used in this embodiment may be selected based on a correlation to attributes ofpreviously collected inspection data from the same wafer or different wafers for the same or differentdesigns on the same or different process layers. The previously collected inspection data may be stored ina data structure or may be included in a knowledge base, which may be configured as described herein. Inthis manner, the one or more attributes of the design data may be selected in this embodiment based oncumulative learning, historical data, or a training set of data.

In another embodiment, the method includes extracting one or more predetermined attributes of outputfrom one or more detectors of the inspection system acquired for different portions of the wafer based onthe position of the inspection data in the design data space, one or more attributes of design data in thedesign data space, and one or more attributes of the inspection data. The one or more attributes of thedesign data used in this embodiment may include any of the attribute(s) of the design data describedherein. In addition, the one or more attributes of the inspection data may include any of the attribute(s) ofthe inspection data described herein. For example, in one embodiment, the one or more attributes of theinspection data include one or more image noise attributes, if one or more defects were detected in thedifferent portions, or some combination thereof. In this manner, the one or more attributes of theinspection data may include, but are not limited to, image noise characteristics and/or the detection/non-detection of defects in the inspection data regions. Extracting the one or more predetermined attributes ofthe output may be further performed as described herein. In addition, the extracted attribute(s) of theoutput may be used as described further herein.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of the method described above may be performedby any of the systems described herein. 88 FIG. 15 illustrates another embodiment of a computer-implemented method for determining a position ofinspection data in design data space. It is noted that the steps shown in FIG. 15 are not essential topractice of the method. One or more steps may be omitted from or added to the method illustrated in FIG.15, and the method can still be practiced within the scope of this embodiment.

The method shown in FIG. 15 can be generally used for CBI. In this embodiment, data preparation phase42 includes generating database 44. Database 44 includes the CAD layout for design data and the contextlayer or layers for the design data. Database 44 may have any suitable configuration known in the art andmay include any other data or information described herein. In addition, data in database 44 may bestored in any other suitable data structure. Database 44 may be generated by software 46 using GDSII file48 and context layer(s) 50 as inputs. Software 46 may include any appropriate software known in the art.In general, the software may be configured as program instructions (not shown in FIG. 15) that areexecutable on a processor (not shown in FIG. 15, but which may be configured as described furtherherein) to generate the database using the GDSII file and the context layer(s). Context layer(s) 50 may beacquired or generated in any manner known in the art and may include any context information or datadescribed herein. In addition, GDSII file 48 may be replaced with any other suitable data structure inwhich design data is stored.

The method shown in FIG. 15 also includes recipe setup phase 52. Recipe setup phase 52 includes steps54 that may be performed to determine alignment information 56. Steps 54 may include scanning a die ona wafer, which may be performed by an inspection system configured as described further herein. Steps54 may also include selecting alignment sites on the wafer using the data acquired by scanning the wafer.The alignment sites on the wafer may be selected as described herein. In addition, the alignment sites onthe wafer may be selected based on inspection swath layout information 58 and any other suitableinformation as described further herein. The inspection swath layout information may include any of theswath information described herein and may be determined as described herein. Selection of thealignment sites on the wafer may be performed automatically, semi-automatically (or user-assisted), ormanually as described further herein.

Steps 54 may also include rendering images or acquiring other suitable data corresponding to thealignment sites on the wafer from the CAD layout information in database 44. For example, steps 54 mayinclude using CAD patches 60 corresponding to the selected alignment sites on the wafer to rendersuitable data or images, or compute values of geometric feature attributes, such as the centroids of certainfeatures, that can be aligned to the alignment sites on the wafer. Steps 54 may also include computing the 89 (x, y) mapping of the alignment sites on the wafer to the information obtained from the CAD layoutinformation. Alignment information 56 includes data for the predetermined alignment sites and the (x, y)positions of the predetermined alignment sites in design data space.

The method shown in FIG. 15 also includes wafer inspection phase 62. Wafer inspection phase 62 mayinclude initialization phase 64 and run phase 66. During initialization phase 64 as shown in step 68, themethod may include preloading alignment information 56 including data for the predetermined alignmentsites and the (x, y) locations of the predetermined alignment sites in design data space. As shown in step70, the initialization phase may also include preloading context layer(s) 72 from database 44. Theinitialization phase may also optionally include rendering the data for the predetermined alignment sitesfrom polygons to pixels, as shown in step 74, which may be performed as described herein. Context layer72 may include any of the context information described herein.

During run phase 66, the method includes performing alignment and mapping, as shown in step 76, of theinspection data to the design data space. This step may be performed during inspection of the wafer.Alignment and mapping may be performed as described further herein. The run phase may also includeapplying mapping to the context map, as shown in step 78. The context data may be mapped as describedfurther herein. The run phase may further include applying the context map to the inspection data duringdefect detection, as shown in step 80, which may be performed as described herein. In addition, the runphase may include mapping defect coordinates to the context map, as shown in step 82, which may beperformed as described herein. The run phase may also include additional steps 84, which may includefiltering the detected defects by context, classifying the defects, generating a review sample, any othersteps described herein, or some combination thereof. Each of additional steps 84 may be performed asdescribed further herein. Each of the embodiments of the method shown in FIG. 15 may include any otherstep(s) described herein. In addition, each of the embodiments of the method shown in FIG. 15 may beperformed by any of the systems described herein.

Program instructions implementing methods such as those described herein may be transmitted over orstored on a carrier medium. The carrier medium may be a transmission medium such as a wire, cable, orwireless transmission link. The carrier medium may also be a storage medium such as a read-onlymemory, a random access memory, a magnetic or optical disk, or a magnetic tape. FIG. 16 illustrates various embodiments of a system configured to determine a position of inspection datain design data space. In one embodiment, the system includes storage medium 86 that includes design 90 data (not shown in FIG. 16). Storage medium 86 may also include any other data and informationdescribed herein. The storage medium may include any of the storage media described above or any othersuitable storage medium known in the art. In this embodiment, the system also includes processor 88coupled to storage medium 86. Processor 88 may be coupled to the storage medium in any manner knownin the art. In this embodiment, the system may be configured as a stand-alone system that does not formpart of a process, inspection, metrology, review, or other tool. In such an embodiment, processor 88 maybe configured to receive and/or acquire data from other systems (e.g., inspection data from an inspectionsystem) by a transmission medium that may include "wired" and/or "wireless" portions. In this manner,the transmission medium may serve as a data link between the processor and the other system. In addition,processor 88 may send data to the other system via the transmission medium. Such data may include, forexample, design data, context data, results of the methods described herein, inspection recipes or otherrecipes, or some combination thereof.

Processor 88 may take various forms, including a personal computer system, mainframe computer system,workstation, image computer, parallel processor, or any other device known in the art. In general, theterm "computer system" may be broadly defined to encompass any device having one or more processors,which executes instructions from a memory medium.

In other embodiments, however, the system includes inspection system 90. Inspection system 90 isconfigured to acquire data for alignment sites on wafer 92 and inspection data for the wafer. Inembodiments of the system that include the inspection system, processor 88 may be coupled to theinspection system in any manner known in the art. For example, processor 88 may be coupled to detector94 of inspection system 90 such that the processor can receive data for alignment sites on the wafer andinspection data generated by the detector. In addition, the processor may receive any other output of thedetector such as image data and signals. Furthermore, if the inspection system includes more than onedetector, the processor may be coupled to each detector as described above.

Processor 88 is configured to align data acquired by the inspection system for alignment sites on a waferwith data for predetermined alignment sites. The processor may be configured to align the data accordingto any of the embodiments described herein. Processor 88 is also configured to determine positions of thealignment sites on the wafer in design data space based on positions of the predetermined alignment sitesin the design data space. The processor may be configured to determine the positions of the alignmentsites on the wafer in design data space according to any embodiments described herein. In addition,processor 88 is configured to determine a position of inspection data acquired for the wafer by the 91 inspection system in the design data space based on the positions of the alignment sites on the wafer inthe design data space. The processor may be configured to determine the position of the inspection data indesign data space according to any of the embodiments described herein. The processor may beconfigured to perform any other step(s) of any of the method embodiment(s) described herein.

In one embodiment, inspection system 90 includes light source 96. Light source 96 may include anyappropriate light source known in the art. Light source 96 may be configured to direct light to beamsplitter 98. Beam splitter 98 may be configured to direct light from light source 96 to wafer 92 at asubstantially normal angle of incidence. Beamsplitter 98 may include any appropriate optical componentknown in the art. Light reflected from wafer 92 may pass through beam splitter 98 to detector 94.Detector 94 may include any appropriate detector known in the art. Output generated by detector 94 maybe used to detect defects on wafer 92. For example, processor 88 may be configured to detect defects onwafer 92 using output generated by the detector. The processor may use any method and/or algorithmknown in the art to detect defects on the wafer. During inspection, wafer 92 may be disposed on stage 100.Stage 100 may include any appropriate mechanical and/or robotic assembly known in the art. Theinspection system shown in FIG. 16 may also include any other suitable components (not shown) knownin the art.

As shown in FIG. 16, the inspection system is configured to detect light specularly reflected from thewafer. In this manner, the inspection system shown in FIG. 16 is configured as a BF inspection system.However, the inspection system ma be replaced by an inspection system configured as a DF inspectionsystem, an EC inspection system, an aperture mode inspection system, or any other optical inspectionsystem known in the art. In addition, the inspection system may be configured to perform one or moreinspection modes. For example, the inspection system shown in FIG. 16 may be configured to performDF inspection by altering an angle of incidence at which the light is directed to the wafer and/or an angleat which light is collected from the wafer. In another example, the inspection system may be configuredsuch that one or more optical components (not shown) such as apertures may be positioned in theillumination path and the collection path such that the inspection system can perform EC mode inspectionand/or an aperture mode of inspection.

Furthermore, the optical inspection system shown in FIG. 16 may include a commercially availableinspection system such as the 2360, 2365, 2371, and 23xx systems that are available from KLA-Tencor.In another embodiment, the optical inspection system shown in FIG. 16 may be replaced by an electronbeam inspection system. Examples of commercially available electron beam inspection systems that may 92 be included in the system of FIG. 16 include the eS25, eS30, and eS31 systems from KLA-Tencor. Theembodiments of the system shown in FIG. 16 may be further configured as described herein. In addition,the system may be configured to perform any other step(s) of any of the method embodiment(s) describedherein. The embodiments of the system shown in FIG. 16 have all of the advantages of the methodembodiments described above.

The methods and systems described above generally perform alignment of inspection data with designdata by aligning data acquired for alignment sites on a wafer (e.g., BF patch images) with data forpredetermined alignment sites (e.g., images derived from GDS II files). Additional methods and systemsdescribed herein generally perform alignment between inspection data and design data and determinesimilarity between different defects using techniques such as statistical techniques (e.g., without usingpatch images or SEM images).

The embodiments described herein may be used for context-based setup, inspection, binning, review,measurement, test, analysis, or some combination thereof. The context that is used in the embodimentsmay include design data or information about the design stored in a data structure such as a designdatabase or a file (e.g. GDS file, OASIS file. Open Access file, net-list, etc.); process simulation results;electrical simulation results; patterns of interest (POIs); hot spot information (e.g., OPC, electrical testresults, inspection results); process tool data (work in progress) ; or some combination thereof. In addition,the embodiments may include predicting yield impact of one or more defects and/or one or more groupsof defects based on results produced by the embodiments described herein. Predicting the yield impactmay be performed as described further herein. Furthermore, the embodiments described herein can beadvantageously used to provide actionable, yield relevant information relatively quickly.

The embodiments described herein may be used to group defects detected by an inspection system thatinaccurately determines defect location coordinates (i.e., the real defect is likely to be located near thereported coordinates but not exactly at the reported coordinates). For instance, the methods and systemsdescribed herein can be used to search for patterns that are at least similar to those proximate to a reporteddefect position by attempting to align the patterns to one another thereby allowing improved grouping ofdefects even if the defect coordinates reported by the inspection system are not perfectly accurate. Inanother instance, an inspection image or a review image (e.g. a SEM image) acquired proximate areported defect location may be compared to or overlaid with the design data to determine the actuallocation of the defect in the wafer space (as opposed to the location of the defect reported by inspection)and an exact representation of the design data proximate the defect position. All instances of at least 93 similar patterns may be identified in the design data (including rotated, flipped, or otherwise skewedinstances of the pattern) and binned into a pattern group. The actual defect positions in wafer spacedetermined as described above may then be compared to the locations for a pattern group, and the defectswhich are located at the locations for the pattern group within a predetermined tolerance may be binnedinto a group. Such grouping of defects may be performed on-tool or off-tool and may improve theperformance of the methods described herein (e.g., reducing the search range when there is coordinateinaccuracy in the defect location coordinates reported by inspection). In particular, with coordinateinaccuracy, the source pattern determined based on reported inspection coordinates is an approximatesource pattern (unless the pattern is isolated or the coordinates of the defects happen to be substantiallyaccurate). Of course, the embodiments described herein may be used with inspection results generated bya highly accurate inspection system.

One embodiment relates to a computer-implemented method for binning defects detected on a wafer. Ingeneral, in the methods described herein, a population of defects may be grouped based on design data(e.g., GDS design data) by selecting a source defect, comparing design data proximate the position of thesource defect in design data space ("source design data") to the design data ("target design data")proximate positions in design data space of target defects (e.g., all or part of the defect population), and ifthere is a match or at least similarity between the compared design data, assigning the target defect to thesource defect group. The comparison may be based on a direct comparison of the source and target designdata. In addition, the comparison may be performed after minor coordinate inaccuracies between thepositions in design data space of the source and target defects have been corrected. Furthermore, thecomparison may include searching for the source design data within the target design data to account forcoordinate inaccuracies in the source and target defect positions. Alignment and/or searching may beimproved by using sub-pixel alignment techniques that may be performed as described herein. Moreover,comparing the source and target design data may be performed to determine if there is an exact matchbetween the source and target design data or a similar but not exact match between the source and targetdesign data. Each of the steps described above may be further performed as described herein.

After the target defect population is tested for the source defect, the next source defect may be selected. Adefect that has yet to be grouped is selected as the next source defect. The above steps may be repeateduntil all defects are grouped (or at least tested). The defect population used in the methods describedherein may include all defects detected on a wafer, all defects detected on multiple wafers, or a subset ofdefects detected on one or more wafers (e.g., defects detected on one or more wafers and identified to benear hot spots). In addition, the methods described herein may be performed for the entire defect 94 population or a subset of the defects in the entire defect population (which may be selected based ondesign functional block such as logic, memory, etc.). Binning may be performed as automatic single-passor multi-pass grouping.

The method includes comparing portions of design data proximate positions of the defects in design dataspace. For example, as shown in FIG. 17, the method may include comparing portion 102 of design data(not shown) proximate a position of defect 104 in design data space 106 with portion 108 of design data(not shown) proximate a position of defect 1110 in design data space 106. Defect 104 is referred to hereinas a "source defect," and defect 110 is referred to herein as a "target defect." The design data proximatethe positions of the defects in design data space defines the background pattern data or backgroundinformation for the defects.

As shown in FIG. 17, portion 102 is larger than defect 104. The dimensions (in the x and y directions) ofportion 102 may be selected by a user. In addition, portion 108 is larger than defect 110. The dimensionsof portion 108 may also be selected by a user. The dimensions of portion 108 are typically larger than thedimensions of portion 102 as described further herein. Alternatively, the dimensions of the portions maybe selected by the computer-implemented methods described herein (e.g., automatically).

In one embodiment, the dimensions (in the x and y directions) of the portions are determined based, atleast in part, on positions of the defects reported by an inspection system used to detect the defects,coordinate inaccuracy of the inspection system, one or more attributes of the design data, defect size,defect size error of the inspection system, or some combination thereof. For example, the method mayinclude defining a portion (i.e., a "pattern window") of the design data centered on a reported defectlocation. The pattern window may have a width and height that are larger than the dimensions of thedefect and are selected to account for error in the defect position due to coordinate uncertainty. Forexample, if the coordinates of a defect location reported by the inspection system are accurate to about +/-3 .mu.m, the pattern window may be defined to include at least 3 .mu.m in every direction from the x andy coordinates of the reported defect location for a total minimum size of about 6 .mu.m by about 6 .mu.m.In this manner, the better the coordinate accuracy of the inspection system, the smaller the patternwindow may be, which may result in faster and more accurate grouping. The dimensions of the patternwindow may also be selected such that the pattern window includes a "sufficient" amount of thebackground pattern data such as a sufficient number of features in the design data. In addition, if thedesign data in the pattern window will be compared to a clip, the pattern window dimensions may beselected such that the pattern window includes entire polygons that are only partially contained in the clip. 95

The portions of the design data used in the methods described herein may include a clip of the designtaken around a position of a defect in design data space. The term "clip" is generally defined as the area indesign data around a defect and can be thought of as the neighborhood of the defect. Polygons define thepattern within the clip, but the polygons can partially extend beyond the clip. The clips used in themethods described herein for some of the defects may have one or more different dimensions. However,the portions of the design data used in the methods described herein may include the design data within anextended bounding box (EBB) around a range of positions at which the defect may be located. The EBBmay be selected based on the coordinate accuracy of the inspection system used to detect the defect andthe defect size (and perhaps defect size error of the inspection system). For example, as the coordinateaccuracy of the inspection increases, the dimensions of the EBB may be reduced. Smaller EBBs arepreferable since the position of a defect within a smaller EBB can be more accurately determined than ina larger EBB, and a more accurate position of the defect within the EBB can be used to determine one ormore attributes of the defect (e.g., the position of the defect with respect to polygons in the design, aclassification for the defect, and a root cause of the defect) with higher accuracy. In addition, one or moredimensions of the EBBs used for at least some of the defects may be different. EBBs are generallysmaller than clips and represent what the defect could be location on.

In another embodiment, the dimensions of at least some of the portions are different. For example, asshown in FIG. 17, the difference between the dimensions of portion 108 and defect 110 is larger than thedifference between the dimensions of portion 102 and defect 104. In other words, the area of the targetportion around the target defect is greater than the area of the source portion around the source defect. Inthis manner, the target portion may include more of the design data than the source portion.

The source portion of the design data may be compared with different areas of the target portion of thedesign data. In this manner, the method may include searching for the source portion of the design datawithin the target portion. For example, as shown in overlay 112 of the source and target portions, thesource portion of the design data may be compared with one area of the target portion. After thiscomparison, the position of the source portion with respect to the target portion may be altered such thatthe design data in another area of the target portion may be compared to the source portion of the designdata. In this manner, the method may include "sliding" the source portion of the design data around in thetarget portion until a match is identified or until all areas of the target portion have been compared to thesource portion. 96

Comparing the portions of the design data may be performed with any information that is available for thecomparing step. For instance, the portions of the design data that are compared may be portions of thedesign data contained in a data structure such as a GDS file. In addition, comparing the portions of thedesign data may include comparing polygons in the portions. In another embodiment, the methodincludes converting the portions of the design data proximate the positions of the defects in the designdata space to bitmaps prior to the comparing step. For example, polygons in the portions of the designdata may be converted to bitmaps for faster processing. The portions of the design data may be convertedto bitmaps using any suitable method or system known in the art. For instance, the portions of the designdata may be converted to bitmaps using a method or system described in U.S. Pat. No. 7,030,997 toNeureuther et al., comparing the portions of the design data includes comparing the bitmaps to each other.Comparing the bitmaps to each other may be performed in any suitable manner. In addition, comparingthe portions of the design data may include comparing one or more attributes of the design data in theportions. The one or more attributes that are compared may include any of the attribute(s) of the designdata described herein.

The method also includes determining if the design data in the portions is at least similar (similar orexactly the same) based on results of the comparing step. If one or more attributes of the design data inthe portions are determined, grouping can be based on common pattern similarity, common attribute(s)similarity, common attribute(s) similarity in feature space, or some combination thereof. For example, inone embodiment, determining if the design data in the portions is at least similar includes determining ifcommon patterns in the design data in the portions are at least similar, which may be performed asdescribed further herein. In another embodiment, determining if the design data in the portions is at leastsimilar includes determining if common attributes of the design data in the portions are at least similar,which may be performed as described further herein. In an additional embodiment, determining if thedesign data in the portions is at least similar includes determining if common attributes in feature space ofthe design data in the portions are at least similar, which may be performed as described further herein. Inaddition, the method may include determining how similar different areas in the portions are. Furthermore,although the design data in the portions may be slightly offset from one another or contain slightlydifferent design geometry, if the portions contain significant common geometry, the portions may bedetermined to be similar to each other. The method may include comparing the design data proximate theposition of each defect in design data space with the design data proximate the position of every otherdefect in design data space to determine which defects are similar to each other based on their"background" patterns. 97

Determining if the design data in the portions is at least similar is preferably not performed based onwhether or not the defects are located at the same position within the design data. In other words, defectsthat are binned in a group based on their "background" by the methods described herein may notnecessarily be located at the same position with respect to patterns, features, polygons, or geometries inthe design data. By not relying on matching of the positions of the defects with respect to the design data,the methods may provide more accurate defect binning. For instance, two defects may be located withinthe same type of pattern but at different locations within the pattern. In addition, a systematic defectwithin a POI may be localized, but also may not be localized. However, such defects may be caused by orrelated to the same pattern based issue. Therefore, binning defects without relying on similarity betweenactual defect positions within the design data may allow more accurate binning, which may be used formore accurate assessments of systematic issues and prediction and control of yield based on thesesystematic issues. Determining if the portions of the design data are at least similar may be performedusing any appropriate algorithm. The method may, therefore, be used as a "similarity checker." Asimilarity checker may be advantageously used when there is coordinate inaccuracy in the actual defectpositions within the design data since the target portion can be larger than the source portion beingcompared to the target portion.

In the embodiment shown in FIG. 17, the entire source portion is compared with different areas of thetarget portion. In some embodiments, the method includes comparing an entirety of the design data in atleast some of the portions to the design data in other portions. In addition, the method may includecomparing an entirety of the source portion of the design data to different areas of the target portion of thedesign data. As such, the method may include searching the target portion for design data that is at leastsimilar to the entire source portion of the design data.

The method further includes binning the defects in groups such that the portions of the design dataproximate the positions of the defects in each of the groups are at least similar. In this manner, the methodincludes binning the defects into groups based on the design data and/or the context of the design dataproximate to the positions of the defects in design data space. For example, polygons in the portions ofthe design data that are at least similar or match may be used to bin defects into groups in an unsupervisedmanner. In addition, the binning step may include binning at least two defects in at least one group suchthat the design data proximate the positions of the at least two defects in the at least one group are at leastsimilar. Furthermore, in the rare instance in which none of the portions of the design data proximate thepositions of the defects in design data space are determined to be at least similar, the method will not binany of the defects into groups. 98

The method also includes storing results of the binning step in a storage medium. The results of thebinning step may include any of the results described herein. In addition, the storing step may includestoring results of the binning step in addition to any other results of any steps of any method embodimentsdescribed herein. The results may be stored in any manner known in the art. In addition, the storagemedium may include any storage medium described herein or any other suitable storage medium knownin the art. After the results have been stored, the results can be accessed in the storage medium and usedby any of the method or system embodiments as described herein. Furthermore, the results may be stored"permanently," "semi-permanently," temporarily, or for some period of time. For example, the storagemedium may be random access memory (RAM), and the results of the binning step may not necessarilypersist in the storage medium.

Determining if the portions of the design data are at least similar may include comparing results of thecomparing step with predetermined criteria for similarity. For example, results of the comparing step maybe compared to a threshold value. If the design data in the portions are at least similar by at least thisthreshold value, the method may bin the defects in a group. In another example, results of the comparingstep may be compared to a "percent similar" value. If the design data in the portions are at least similar byat least this percent, then the method may bin the defects in a group.

In any case, when a similarity check is performed between two or more portions of design data (e.g., GDSpattern clips) and a common pattern in the two or more portions is identified, the method includes binningthe defects in a group. The results produced by determining if the design data in the portions is at leastsimilar may include an indication of whether or not the design data in the source portion was found in thetarget portion. In addition, the center point of the common geometry can be considered to be theapproximate design data space position of a systematic defect. The (x, y) coordinates of the design dataspace positions of the defects in each group can, therefore, be adjusted (translated) to the center point ofthe geometry corresponding to each group. A coordinate correction vector (or error vector) may bedetermined for each binned defect based on the design data space coordinates of the defect and the centerpoint of the common geometry corresponding to the group into which the defect was binned. Todetermine the overall systematic uncertainty in the design data space coordinates of the defect positions(wafer space to design data space translation errors plus errors in the reported coordinates), the methodmay include determining the average of these translation or error vectors over a statistically significantnumber of defects. The method may also include determining the standard deviation of all of the errorvectors and determining an average of only those vectors that fall inside of the +/-1 standard deviation or 99 +/-3 standard deviation. In this manner, outliers that may compromise the average value may beeliminated from the computations. The determined average value may also be used as a global correctionvalue. For instance, this global correction value may be applied to additional design data spacecoordinates of defect positions determined by wafer space to design data translations such that moreaccurate overlay can be determined in subsequent data processing steps.

The results of the determining step may also include the x and y offsets between the target portion and theposition of the source portion within the target portion at which the at least similar design data was found.These x and y offsets may be used to optimize the binning method. For instance, when initially comparingthe portions, the source portion may be positioned in the target portion such that center points of the twoportions are aligned. However, if there is determined to be some predictable or repeatable offset (in the xand/or y directions) between the initially used position of the source portion within the target portion andthe position of the source portion within the target portion at which the at least similar design data isfound, this offset may be used to tune the overlay used in the comparison step of the binning method.

In some embodiments, the design data in the portions includes design data for more than one design layer.In this manner, the method may include binning defects by checking one design layer for backgroundsimilarity of the defects or binning defects by checking a set of design layers for background similarity(i.e., multi-layer background similarity) of the defects. For example, during inspection of a polysiliconlayer (e.g., a gate electrode layer) on a wafer, an underlying diffusion layer may be visible to theinspection system and therefore affect the inspection results. As such, the design data that is included inthe portions may include the design data for the polysilicon layer and the diffusion layer to increase theaccuracy of the background based binning. In addition, an underlying design layer may not be visible tothe inspection system. However, by using design data for more than one design layer, defects locatedproximate portions of the design data that are at least similar but are located above dissimilar design dataon an underlying layer may be binned into different groups.

Regardless of whether or not the design data in the source portion was found in the target portion, themethod may include comparing the source portion with other portions of the design data proximatepositions of other defects in the design data space. Comparing the design data in the source portion todesign data in multiple target portions may be performed since more than one target defect locatedproximate to design data that is at least similar to, or the same as, design data in the source portion may bedetected on a wafer. 100

In one such example shown in FIG. 17, portion 102 may be compared with portion 114 of design data(not shown) proximate a position of defect 116 in design data space 106. The dimensions of portion 114may be selected as described above. The source portion of the design data may be compared with thedesign data in different areas of the target portion as described further above. The method also includesdetermining if the design data in the source portion is at least similar to at least some of the design data inthe target portion based on results of the comparison, which may be performed as described further above.Overlay 118 of the portions illustrates the position of the source portion within the target portion at whichat least similar design data was found. Therefore, the method includes binning defects 104 and 116 in agroup since the design data in portion 102 is determined to be at least similar to at least some of thedesign data in portion 114. In addition, defects 104, 110, and 116 are binned into a group since the designdata in the source portion is determined to be at least similar to at least some of the design data in both ofthe target portions.

In another such example, portion 102 may be compared with portion 120 of design data (not shown)proximate a position of defect 122 in design data space 106. The dimensions of portion 120 may beselected as described above. The source portion of the design data may be compared with the design datain different areas of portion 120 as described further above. The method also includes determining if thedesign data in portion 102 is at least similar to at least some of the design data in portion 120 based onresults of the comparison, which may be performed as described further above. Overlay 124 of portions102 and 120 illustrates the position of portion 102 within portion 120 at which at least similar design datawas found. Therefore, the method includes binning the source defect and target defect 112 in a group. Inaddition, the source defect and the three target defects are binned into a group since the design data in thesource portion is determined to be at least similar to at least some of the design data in the three targetportions. The steps described above may be performed until the background information for each defectdetected on a wafer is compared with the background information for every other defect detected on thewafer.

As described above, the method includes binning the defects based on the design data and/or the contextof the design data located proximate to the positions of the defects in design data space, possibly incombination with other information such as one or more attributes of the design data and/or the designlayout. In contrast with other methods for binning defects based on context information, the methodsdescribed herein do not perform binning based on the background information as printed on the wafer.Instead, the methods described herein perform binning based on the background information as defined in 101 the design data. In this manner, the methods described herein can perform background based binning regardless of whether or not or how the design data is printed on the wafer.

Such independence from the design data as printed on the wafer may be particularly advantageous forPWQ methods and focus exposure matrix (FEM) methods in which the design data as printed on thewafer may change (sometimes dramatically) across the process window parameters used for suchmethods thereby decreasing the accuracy of defect binning methods based on images of the design dataprinted on the wafer. In one such application for empirical techniques such as PWQ, the method mayprovide improved background based binning by using a GDS clip or excerpt of the design data at theposition of the defect in the design data space. As such, binning may be performed by common pattern.The defects that are binned may be classified individually or collectively as a group of defects asdescribed further herein. For example, the method may include classifying the defects based on one ormore attributes of the design data (e.g., one or more attributes the design data located proximate the defectpositions in design data space), which may be performed as described further herein.

Since the defects detected on the wafer are binned by design data proximate the design data spacepositions of the defects, the positions of the defects in the design data space may be determined beforebinning is performed. In one embodiment, the method includes acquiring data for x and y coordinates ofpositions of the detected defects in design data space (or to determine a translation function), which maybe performed as described herein. In another embodiment, the method includes determining the positionsof the defects in the design data space by comparing data acquired by an inspection system for alignmentsites with data for predetermined alignment sites. Acquiring the data for the alignment sites on the wafermay include determining approximate wafer space positions of the alignment sites on the wafer usingproduct layout data, optionally reticle frame data, and the stepper recipe (or input to the stepper) andacquiring the data at the approximate positions. Such comparing and determining may be performed asdescribed further above. In addition, the method may include determining the positions of at least some ofthe defects in the design data space by comparing data acquired by an inspection system for alignmentsites on the wafer with data for predetermined alignment sites. The positions determined for at least someof the defects may then be used to determine the positions of other defects in design data space (e.g., bygenerating and using a transformation for translating reported defect positions to defect positions indesign data space). Determining the positions of the defects in the design data space may also beperformed according to any of the embodiments described herein. 102

Sometimes all of the data described above is not available, or the wafer has not been properly aligned tothe design data. In such instances, it may be useful to determine some of the transformation informationempirically from the wafer during inspection or review. In one embodiment, the method includesdetermining the positions of the defects in design data space by comparing data acquired by an inspectionsystem during detection of the defects to data acquired by a review system at locations in design dataspace determined by review. In this manner, the method may include aligning inspection results for one ormore defects to review results acquired at design data space locations determined by review. In addition,the method may include determining the design data space positions of at least some of the defects bycomparing data acquired by an inspection system during detection of the defects to data acquired by areview system at locations in the design data space determined by review. The positions determined for atleast some of the defects may then be used to determine the positions of other defects in design data space(e.g., by generating and using a transformation for translating reported defect positions to defect positionsin design data space). However, this approach provides a wafer scale offset that may be complicated bycoordinate inaccuracy of the inspection system. Therefore, if there are coordinate inaccuracies in thereported locations of the defects, it may be beneficial to base the transformation function on a statisticalsample of measurements.

After the positions of the defects in design data space are determined, portions of the design data aroundthe determined positions may be extracted such that the extracted portions of the design data may be usedfor binning defects and performing other steps described herein. In addition, prior to using the extractedportions of the design data for binning, each of (or one or more of) the extracted portions may be mirrored,rotated, scaled, translated (shifted), or some combination thereof to generate a set of portionscorresponding to and including each of the extracted portions. These sets of portions may be used forbinning to increase the accuracy of the binning method.

The method may also include determining one or more attributes of the detected defects such asdimension in the x direction (e.g., width), dimension in the y direction (e.g., length), and dimension in thez direction (e.g., height), any other attribute(s) described herein, or some combination thereof. The one ormore attributes may be organized and/or stored in any suitable data structure such as a table or list. Inanother embodiment, binning the defects includes binning the defects in the groups such that the portionsof the design data proximate the design data space positions of the defects in each of the groups are atleast similar and such that one or more attributes of the defects in each of the groups are at least similar.In one such embodiment, the one or more attributes of the defects include one or more attributes of theresults of the inspection in which the defects were detected, one or more parameters of the inspection, or 103 some combination thereof. The one or more attributes of the results of the inspection may include, forexample, an optical mode and/or one or more other parameters of the inspection such as polarization,collection angle, incidence angle, etc., at which the defect was preferentially detected. In addition, oralternatively, the one or more attributes may include any other attribute(s) of the defects described herein.In this manner, binning may be performed such that the defects are separated into groups by design dataand defect attribute(s). Such binning may be performed such that different defect types or defects havingdifferent attribute(s) located within at least similar portions of the design data may be separated intodifferent groups.

In some embodiments, the defects that are binned as described herein are detected by optical or electronbeam inspection. Optical and electron beam inspection may be performed by an inspection systemdescribed herein. In another embodiment, the defects that are binned as described herein are detected in aPWQ or FEM method, which may be performed as described herein. The embodiments described hereinmay be particularly useful for defects detected in a PWQ or FEM method. For example, the methodembodiments described herein may be used to filter defects detected in PWQ and FEM methods such thatpotential systematic issues can be more easily and accurately identified, which may be performed asdescribed further herein. In addition, the method embodiments described herein may be used to bindefects detected by PWQ or FEM into useful groups, which may be performed as described further herein.Furthermore, the method embodiments described herein may be used to prioritize the binned PWQ orFEM defects for review, measurement, or test, which may be performed as described further herein. Inaddition, the method may include binning inspection and/or electrical test defects into groups based on atleast similar design/layout patterns.

In one embodiment, the inspection system used to detect the defects, which are binned in theembodiments described herein, may be aligned to three or four alignment sites on the wafer. Thealignment sites may be selected as described further above. In addition, alignment sites that include one ormore alignment features, patterns, and/or geometries visible on the physical wafer and in the design dataor layout may be selected for use in the methods described herein. After the inspection system has beenaligned to the alignment sites, stage positional accuracy, any rotational errors, x and y translational errors,magnification (scaling) errors, or some combination thereof may be corrected. This correction may takeplace during the inspection process or may be performed post-process (i.e. performed after inspectionresults have been produced). The correction may be based, at least in part, on a comparison of thecoordinates for the alignment sites reported by the inspection system and reference coordinates for thesame alignment sites. 104

In some embodiments, the method may include obtaining coordinates for three or four alignment sites inmultiple die on the wafer such as a die on the left side, right side, top, bottom, and center of the wafer. Inanother embodiment, the alignment sites on the wafer are located in three different die on the wafer. Onesuch embodiment is illustrated in FIG. 18. As shown in FIG. 18, wafer 126 includes a plurality of die 128.Alignment sites 130 may be located in die 128a, 128b, and 128c. Although alignment sites are shown inonly three die, it is to be understood that the alignment sites may be located in each die on the wafer. Asubset of the alignment sites in each die or the alignment sites in a subset of the die may be used in themethods described herein.

The method may also include identifying three common alignment sites (i.e. alignment sites that arecommon to the die printed on the wafer and the design data (e.g., the GDS layout)) in a triangulardistribution within the die. For instance, as shown in FIG. 18, alignment sites 130 are arranged in atriangular distribution within die 128a, 128b, and 128c. In one such embodiment, the three different dieare also distributed across the wafer in a predetermined arrangement (e.g., a triangular or otherarrangement). For instance, as shown in FIG. 18, die 128a, 128b, and 128c are located on wafer 126 intriangular arrangement 132. In this manner, the method may include aligning images (e.g., BF and/or DFimages) acquired by the inspection system for the alignment sites on the wafer with data for thepredetermined alignment sites. The method may include mapping the coordinates of the inspection dataacquired by the inspection system with design data coordinates (e.g., GDS coordinates) and developingtransformation matrices. The transformation matrices may be expressed in any suitable manner such as: ( x'^ px 0 ( x Scale: y' = 0 Sy 0 y .0 0 1 ( x'y (cos^ - sin φ 0Λ ( x' Rotate: y' = sin^ cosφ 0 y . 0 01,

( *Ί ( 1 0 txλ (x Ί Translate : yf = 0 1 ty y I00 1 J 105

The coordinates of these alignment sites may also be used to perform (e.g. automatically perform) "toolmatching" to eliminate coordinate differences between inspection systems. One advantage of such amethod is that the coordinates may be determined individually and automatically for every inspectedwafer thereby yielding a per-wafer set of correction factors. Another advantage of such a method is thatthe determined coordinates may be used to determine coordinate drifts in the inspection system or othersystems across the wafers (e.g., coordinate drifts caused by accumulated error, stage movement errors,and errors caused by mechanical, electrical, and thermal noise) that may otherwise reduce the accuracy ofalignment of the inspection data to the design data.

As described above, comparing the design data in the portions may include comparing an entirety of thedesign data in at least some of the portions to the design data in other portions. In this manner, the resultsof such comparing may be used to determine if all of the design data in the source portion is at leastsimilar to at least some of the design data in the target portion. However, in an alternative embodiment,comparing the design data in the portions includes comparing different regions of the design data in atleast some of the portions to the design data in other portions, which may be performed as describedfurther herein. Further, while design data in multiple regions of the source portion may be at least similaror identical to design data in regions of the target portion, the results of such comparing may be used toidentity the largest region of design data in the source portion that is at least similar or identical to asimilarly-sized region of design data in the target portion. In this manner, the method may includedetermining if the design data proximate to the positions of the source defect and the target defect indesign data space "look alike" or are at least similar. Therefore, this method can be much more effectiveat certain design layers for background based binning of defects as described herein.

One such embodiment of the method is illustrated in FIG. 19. For example, as shown in FIG. 19, themethod may include defining portion 134 of design data (not shown) proximate a position of defect 136in design data space 138. Defect 136 is referred to herein as the "source defect." Defining portion 134 ofthe design data may include selecting the dimensions of the portion, which may be performed asdescribed further above. The method may also include separating, segmenting, or partitioning the portionof the design data into one or more different regions. For example, as shown in FIG. 19, portion 134 maybe divided into four different regions 140, 142, 144, and 146. The different regions into which portion134 is separated may be referred to in this instance as "source quadrants." Although portion 134 is shownin FIG. 19 divided into four source quadrants, it is to be understood that the portion may be separated intoany suitable number of regions. All of the regions may have the same size, or all or some of the regionsmay have different sizes. 106

In this example, the method includes comparing design data in source quadrants 140, 142, 144 and 146with portion 148 of design data (not shown) proximate a position of defect 150 in design data space 138.Defect 150 is referred to herein as a "target defect." As shown in FIG. 19, portion 148 is larger than defect150 and at least as large as portion 134. The dimensions of portion 148 may be selected as describedfurther above.

The design data in each of the source quadrants may be compared with design data in different areas ofthe target portion. In this manner, the method may include searching for the design data in each of thesource quadrants within the target portion. In this example, the method also includes determining if thedesign data in the source quadrants is at least similar to the design data in the target portion based onresults of the comparing step. For example, the method may include determining how similar the designdata in each of the source quadrants is to the design data in the target portion. As such, the design data innone, some, or all of the source quadrants may be determined to be at least similar to the design data inthe target portion. As shown in overlay 152, the design data in three of the four source quadrants wasdetermined to be at least similar to the design data in areas of portion 148 at the positions of sourcequadrants 140, 144, and 146 shown in overlay 152.

In this manner, the method may include comparing the design data in the source quadrants to the designdata in the target portion to determine which defects are at least can be binned into groups based on theircorresponding design data. The results of determining if the design data in each of the source quadrantsand the target portion is at least similar may include an indication of how many and which of the sourcequadrants were determined to contain design data that is at least similar to the design data in the targetportion. The results of the determining step may also include the x and y offsets between the targetportion and each of the source quadrants within the target portion at which at least similar design data wasfound. Whether or not the source defect is binned in a group with the target defect may be determinedbased on how many and which of the source quadrants were determined to include design data that is atleast similar to design data in the target portion and the offsets between the target portion and each of thesource quadrants within the target portion at which at least similar design data was found.

In some embodiments, the design data in each of the source quadrants and the target portion includesdesign data for more than one design layer. In this manner, the method may include binning defects bychecking one design layer for at least similar design data or binning defects by checking a set of designlayers (e.g., multi-layer) for at least similar design data. 107

Regardless of whether or not the design data in the source quadrants was determined to be at least similarto the design data in the target portion, the method may include comparing each of the source quadrantswith other portions of the design data proximate positions in the design data space of other defects.

In one such example, the design data in source quadrants 140, 142, 144 and 146 may be compared withportion 154 of design data (not shown) proximate a position of defect 156 in design data space 138.Portion 154 may be configured as described above. The design data in the source quadrants and portion154 may be compared as described above. The method also includes determining if the design data ineach of the source quadrants is at least similar to design data in portion 154, which may be performed asdescribed further above. As shown in overlay 158, two of the four quadrants (e.g., quadrants 144 and 146)were determined to include design data that is at least similar to that in portion 154 at the positions of thequadrants shown in overlay 158. Therefore, the method may determine that the design data proximate thepositions of defects 136 and 156 in design data space is less similar than defects 136 and 150. Whether ornot the design data proximate the positions of defects 136 and 156 in design data space is similar enoughto bin defects 136 and 156 in the same group may be determined as described further above.

In another such example, the design data in source quadrants 140, 142, 144 and 146 may be comparedwith portion 160 of design data (not shown) proximate a position of defect 162 in design data space 138.Portion 160 may be configured as described above. The design data in the source quadrants and portion160 may be compared as described above. The method also includes determining if the design data ineach of the source quadrants is at least similar to design data in portion 160, which may be performed asdescribed further above. As shown in overlay 164, two of the four quadrants (e.g., quadrants 142 and 144)were determined to include design data that is at least similar to portion 160 of the design data at thepositions of the source quadrants shown in overlay 164. Therefore, the method may determine that thedesign data proximate the positions of defects 136 and 162 in design data space is less similar than the design data proximate the positions of defects 136 and 150 in design data space. Whether or not the design data proximate the positions of defects 136 and 162 in design data space is similar enough to bin defects 136 and 162 in the same group may be determined as described further above.

The quadrant information determined as described above may be stored and/or displayed. Thisinformation may be used for setup, verification, and troubleshooting purposes. 108

The method may also include on-tool classification of systematic defects and nuisance defects (e.g.,defects that are not real or are not of interest) by dynamically compiling a table, list, or other datastructure of unique patterns in the design data and comparing the portions of design data proximate thepositions of the defects in design data space with the patterns in the table, list, or other data structure. Thedynamically created set of patterns (or a static set of patterns) may be stored in a data structure such as alibrary along with design based classifications (DBC) associated with each of the patterns. In this manner,the DBCs may define the groups into which the defects may be binned, and the unique patterns mayinclude POI design examples. As such, design data proximate to design data space defect positions is notcompared to design data proximate other design data space defect positions, but to unique patterns in adynamically created set of patterns. Such comparing may be performed as described further herein. Forexample, one embodiment that may utilize such a data structure (which may or may not be dynamicallycreated) is a computer-implemented method for assigning classifications to defects detected on a wafer,which is described in detail below.

In addition, in some embodiments, the computer-implemented method is performed by an inspectionsystem used to detect the defects. In this manner, binning defects may be performed "on-tool." Oneadvantage of performing the method on-tool is that the time to results may be quicker. The method maybe performed on-tool at any time after the defects have been detected (e.g., during inspection either whileor after other defects are being detected, during analysis of the inspection results, during review, etc.). Inaddition, locations of potential systematic defects or systematic defects (hot spots) and data used forbinning may be stored in a data structure (e.g., a hot spot database) and used for inspection comparison(monitoring). Therefore, binning may be performed during inspection to provide better classification(binning for discovery, filtering, or monitoring).

In an alternative embodiment, the computer-implemented method is performed by a system other than aninspection system used to detect the defects. In this manner, the method embodiments described hereinmay be performed "off-tool," The system that performs the method off-tool may include, for example, amicroscope (optical or electron beam), a review system, a system into which the wafer is not loaded (e.g.,a stand-alone computer system), or any other appropriate system known in the art that can be configuredto perform the method. For example, the method may be performed after defect detection during a secondpass of the wafer in which a microscope is used to acquire images of at least some of the detected defects.Such image acquisition may be performed using an optical microscope since an electron beammicroscope may not be able to image some of the defects (e.g., defects that are not visible to the electronbeam microscope such as defects that are located below an upper surface of the wafer). The image 109 acquisition may be performed off-line and used to provide better sampling of the defects for review.

Binning of the defects may also be used for analysis and sampling of the defects as described further herein.

In some embodiments, the method includes identifying hot spots in the design data based on the results ofthe binning step. In this manner, design based binning can be used for discovery of hot spots. In addition,discovery of hot spots can be performed on-tool. The method may also include generating a data structurethat includes the discovered hot spots and one or more attributes of the hot spots such as location, designdata proximate the positions of the hot spots, etc. The data structure may include a list, a database, a file,etc. The hot spots may be used for hot spot management (possibly on-tool). Hot spot management mayinclude discovering hot spots, using on-tool pattern grouping to generate a hot spot data structure, and hotspot monitoring, which may be performed as described further herein. In addition, the hot spotsdiscovered by design based binning can be used as input for DesignScan, PWQ, DOE, and review.Alternatively, the hot spots used in the methods described herein may be discovered using any othermethod or system known in the art such as a reticle inspection system. FIG. 20 illustrates one embodiment of input to and output from module 166 that is configured to performa computer-implemented method for binning defects detected on a wafer according to the embodimentsdescribed herein. Module 166 may be configured to function as a GODS pattern checker (exactnesschecker of the design data or portion of the design data proximate design data space positions of any twodefects) and/or a similarity checker (non-exactness checker). The module may be configured to performone or more of the steps described herein on-tool or off-tool. For example, the module may be configuredto perform one or more of the steps described herein on-tool post-process (e.g., on-tool, post-defectdetection). In addition, the module may be configured to perform one or more of the steps describedherein during defect detection. If the module is configured to perform one or more of the steps describedherein on-tool, the module may be configured to perform other functions described herein such as defectorganizing.

The input to module 166 may include defect list 168. In one embodiment, defect list 168 may includedefect information such as information included in a KLARF file or another standard file that may beproduced by an inspection system. The input to the module may also include coordinate transformationinformation, which may be determined as described above, and design data. In such an embodiment,module 166 may be configured to transform the positions of the defects in defect list 168 as reported bythe inspection system to positions of the defects in the design data space. 110

Alternatively, module 166 may be configured to perform functions in wafer space with access totransformed design data space coordinates provided through another software module (a software moduleconfigured to perform transformation functions). In another alternative, defect list 168 may includepositions of the defects in the design data space. In such embodiments, the defect positions reported bythe inspection system may be transformed to defect positions in design data space by another softwaremodule. Such defect information may be input to module 166 in a suitable data file format or throughprogrammatic means via intra- or inter-process communication either on the same computationalhardware or between a set of networked computational hardware. In this manner, the defect informationmay be provided to module 166 by another system via a transmission medium that couples the module tothe other system. The transmission medium may include any suitable transmission medium known in theart and may include "wired" and "wireless" transmission media or some combination thereof.

Additional input (not shown in FIG. 20) may also be provided to module 166 that may be used by themodule to perform one or more steps of one or more embodiments described herein. The additional inputmay include any other defect and/or design data information that is available such as electrical inspectiondata, defect information for more than one wafer, hot spot or weak spot information ("weak spots" aregenerally defined as locations of potential weak points in the design identified by model-based simulationsuch as, but not limited to, post-OPC verification software, and empirical methods such as, but not limitedto, PWQ), a search window size (e.g., the dimensions of the portions of the design data proximate thepositions of the source and target defects in design data space as described above or the source defectenlargement and the target defect enlargement), some predetermined criteria for similarity (e.g., asimilarity threshold), or some combination thereof.

In addition, the hot spots may be grouped based on design data in advance. For example, hot spots locatedproximate to design data that is at least similar may be correlated with each other, and the method andsystem embodiments described herein may perform such correlating of the hot spots. The correlated hotspots may be used for binning defects as described further herein. In one such embodiment, module 166may be configured to bin defects into groups such that the defects in each group have positions in designdata space that are at least similar to positions of only hot spots that are correlated with each other. In thismanner, the module may be configured to bin defects without using the design data. Furthermore, one ormore attributes of correlated hot spots can be determined for use in later analysis (e.g., yield informationsuch as KP can be determined for correlated hot spots). In this manner, when defects are binned into a 111 group corresponding to correlated hot spots, the module can report the expected yield impact determined for the correlated hot spots for the defect group.

Module 166 may be configured to function as a GDS pattern checker by binning defects in defect list 168by "checking" if the design data proximate to positions of different defects in design data space matches.In this manner, module 166 ma be configured to bin defects in groups such that the defects in each groupare located in design data space proximate to matching design data. In addition, or alternatively, module166 may be configured to function as a similarity checker by binning defects in defect list 168 bychecking the similarity of the design data proximate to the positions of different defects in design dataspace.

Output of module 166 may include output 170. Output 170 may include a list of a variety of informationincluding, but not limited to, the x and y coordinates of the defect positions as reported by the inspectionsystem, the x and y coordinates of the defect positions in design data space, an identity (e.g., 1, 2, 3, a, b,c, etc.) of the group in which the defects were binned (e.g., if the defects are binned in the same group,their identity may be the same), and shift or offset in the x and/or y directions between the center of thetarget portion and the center of the area within the target portion in which design data matching or at leastsimilar to the design data in the source portion is located. The output may include one or more datastructures having any suitable format known in the art (e.g., a plain text file format). In addition, theoutput may be stored in any appropriate storage medium known in the art such that the output may beaccessed and/or analyzed at a later time. The output may be stored and used as described further herein.

In addition, or alternatively, as shown in FIG. 21, the output of module 166 may include a tableillustrating how similar (e.g., % similar) the design data proximate to the position of each defect in designdata space is to the design data proximate to the position of each other defect in design data space. In theexample shown in FIG. 21, the portions of the design data proximate to the positions of defects 1 and 2 indesign data space are 40% similar while the portions of the design data proximate to the positions ofdefects 1 and 3 in design data space are 95% similar. In this manner, the method may use the outputshown in FIG. 21 to determine which defects are to be binned in the same group. For instance, if theportions of the design data proximate the positions of the defects in design data space are more than 90%similar, the defects may be binned in the same group. In addition, as shown in FIG. 21, the portion of thedesign data proximate the position of defect 1 in design data space is more than 90% similar to theportions of the design data proximate to the positions of both defects 3 and 4 in design data space. In thismanner, defects 1, 3, and 4 may be binned in the same group. 112

In another example, as shown in FIG. 22, the output of module 166 may include a graph (e.g., a bargraph) illustrating the number of defects (e.g., defect count or frequency) as a function of different groups.Each of the different groups includes defects located at design data space positions proximate to designdata that is the same or at least similar as described further above. In this manner, the output shown inFIG. 22 provides information about which pattern types in the design are more defective. The chart mayprovide a breakdown of pattern types by various design contexts (e.g., background pattern context byfunctional block). The information in the chart can be further split by annular or angular zone on thewafer as described further herein to provide information about the spatial distribution of defects located indesign data space proximate a common design pattern. This and similar or other information may be usedto perform one or more step(s) of the methods described herein (e.g., defect sampling based onbackground pattern context). Additional information about the defects binned in each group may also bedetermined using any of the step(s) of any of the method(s) described herein.

Module 166 may provide output in only one of the formats shown in FIGS. 20-22. However, the modulemay provide output in more than one of the formats shown in FIGS. 20-22.

An additional example of different inputs and outputs of module 166 are illustrated in FIG. 23. As shownin FIG. 23, one input to module 166 may include wafer map 172 that illustrates the positions of thedetected defects on the wafer. The wafer map may be generated by an inspection system. The wafer mapmay illustrate the positions of the defects on the wafer but not any other information about the defects.For instance, bar graph 174 corresponding to wafer map 172 illustrates all of the detected defects in asingle group corresponding to the layer of the wafer that was inspected.

Output of module 166 may include wafer map 176 that illustrates the positions of the detected defects onthe wafer, and defects that are binned into the same group are indicated in the wafer map with the samecharacteristics (e.g., different colors or symbols for different groups). The defects may be binned asdescribed further herein (e.g., automatic grouping of defects by common GDS layout). In this manner,wafer map 176 indicates the positions of individual defects on the wafer and the group into which theindividual defects were binned. The output may be sent to and used by a spatial signature analysis (SSA)tool such as KLARITY DEFECT SSA, which is commercially available from KLA-Tencor, to enhancemonitoring and root cause determination. 113

The output of the module may also include a stacked die map, a stacked reticle map, or a stacked wafermap in which defects are displayed to represent the pattern groups. The stacked maps can be used toillustrate where systematic defects tend to occur statistically over many die, reticles, or wafers and may beuseful for identifying spatial signatures. Furthermore, any of the output of the module described hereinmay also include one or more GDS clips, one or more SEM images, one or more optical images, or somecombination thereof. The output of the module may be displayed by a user interface such as the userinterface embodiments described further herein.

Bar graph 178 corresponding to wafer map 176 illustrates the number of defects that were binned intoeach group. In addition, the layout pattern signature that corresponds to each group of defects is indicatedin the bar graph. In this manner, the bar graph illustrates the pattern in the design that exhibits (or causes)the most defectivity. For instance, the relatively high number of defects binned into the layout patternsignature 2 group indicates a potential pattern dependent failure mechanism corresponding to this layoutpattern signature. This information may be used to perform one or more step(s) of the methods describedherein (e.g., defect sampling based on design background context). Additional information about thedefects binned in the groups may also be determined using any of the step(s) of any of the method(s)described herein. Module 166 may generate output including wafer map 176 and bar graph 178. Theoutput of the module may be displayed by a user interface such as one of the user interface embodimentsdescribed further herein.

One example of how the output of module 166 may be used in the methods described herein is forcorrelation of different density zones in the device layout with different defectivities. For example, thedevice layout may be partitioned into different zones. The different zones may be determined based onthe design pattern density of different areas of the device, as shown in FIG. 24. In one example, major cellblocks in the device may be partitioned into different zones. In another example, the device layout may beautomatically partitioned based on the density of various device structures (e.g., contacts, vias, metal lines,etc.) across the device layout. In one embodiment, the method embodiments described herein includedetermining a defect density for different portions of the design data. For example, the methods describedherein may use information about the partitioning of the device layout to determine a defect density ofdifferent portions of a cell in the design data. In one such instance, the number of defects detected in eachzone in the design data may be determined. Such information may be plotted in a bar graph or any othersuitable output format. 114

In another embodiment, module 166 splits the design data into "functional blocks" or "cell blocks." Cell blocks are defined in the design data and identify the boundaries of major and minor sub-cells of the design such as an input/output (I/O) block, a digital signal processor (DSP) block, etc. The module may determine the frequency of defects in each cell block. In this manner, it is possible to determine whether a major or minor cell in the design is more or less susceptible to yield issues.

The embodiments described herein may use statistical approaches to determine the design cells in whichthe defects are located. For example, in some embodiments, the method includes determining if thedefects are systematic defects, determining a probability that two or more of the systematic defects arelocated in one or more different portions of the design data, and determining if a correlation existsbetween the systematic defects and the probability. In particular, as described further herein, regioninformation in design data (i.e., the hierarchical design data) may be used in combination with thepositions of the defects in the design data space to determine the hierarchy of the defects in the designdata such as a cell in the design data. As described further herein, the hierarchy of the defects in thedesign data may be used to determine which portions of the design data can or should be altered toimprove yield. One difficulty in determining the hierarchy of the defects is that as cells get smaller, thesizes of the cells approach and become smaller than the coordinate accuracy of inspection systemsthereby decreasing the accuracy with which the cell in which the defects are located can be determined.To overcome this difficulty, statistics may be used to determine the probability that the defects are locatedin various portions of the design data (e.g., the probability that each defect is located in different cells). Inthis manner, for systematic defects, the statistics may be used to determine if a correlation exists betweenthe systematic defects and the probability that the defects are located in various portions of the designdata.

In another embodiment, the input provided to module 166 may include the design data (e.g., GDS layout),inspection data (e.g., physical defect data), and optionally a memory bitmap and/or a logic bitmap. Themodule may use some or all of the input to perform one or more additional steps such as, but not limitedto, discovery, characterization, monitoring, and dispositioning (e.g., making one or more actionabledecisions) of defects that will or may affect yield. The module may be configured to perform the stepsdescribed above in addition to one or more of the following steps: generating a hot spot/weak spot datastructure, grouping of defects (e.g., defects detected by an optical or electron beam inspection systemand/or defects detected by electrical inspection that are displayed in a bitmap) using the design data,generating a review sample plan, optimizing an inspection recipe, altering a review recipe (e.g.,determining where to review), optimizing a review recipe, altering a defect analysis recipe (e.g., where to 115 analyze during an in-line FIB process and/or a FA process may be determined based on design contextpossibly in combination with any other information described herein), optimizing a defect analysis recipe,generating a sampling recipe for a FIB process, an EDX process, or another defect analysis process,generating a sampling recipe for a metrology process, and predicting DOI and possibly one or moreattributes of the DOI such as type and location. In addition, any of the sampling plans or sampling recipesdescribed above may be determined dynamically based on results of the binning. In one such example, themodule may be configured to analyze the design data or to acquire analysis of the design data such asresults from DRC to predict potential DOI that may be detected in inline defect data and bitmap data.

As described above, module 166 may be configured to generate a data structure such as a database. Forexample, in some embodiments, the method includes generating a data structure that includes positions ofsystematic defects and potential systematic defects in the design data space and one or more attributes ofthe systematic defects and the potential systematic defects. Such a database may be generally referred toas a "hot spot" database. The database may also include information about weak spots, conditional hotspots, and cold spots (non-critical areas of the design that can result in systematic defects with little or noyield impact (e.g., dummy structures, dummy fill areas, etc.)). The database may also include locationsand other attribute(s) of potential and real systematic defects (e.g., design context, KP, other yieldproperty, etc.).

The data in the hot spot database may be acquired from a variety of sources. For example, the databasemay be configured as a flexible database that includes data about systematic issues from all (or at leastsome) possible sources. For example, some of the input to the module may be included in the database. Inone such example, inspection results (e.g., PWQ results, defects detected by BF and/or DF inspection, amemory bitmap, a logic bitmap, etc.) may be included in the database. In some embodiments, thedatabase may also include design rules for one or more semiconductor manufacturing processes such aslithography and CMP. In another embodiment, the database may include simulations performed for thedesign data such as results of OPC simulations. In this manner, a multi-source correlation may be used toidentify hot spots and systematic defects.

As described above, the method includes binning defects based on the design data. In one suchembodiment, the method described herein includes determining if the defects are nuisance defects basedon one or more attributes of the design data. In this manner, nuisance defects may be identified based oncontext information. In some embodiments, the method includes removing a portion of the defects fromresults of an inspection process in which the defects were detected based on the design data proximate to 116 the positions of the defects to increase the S/N of the results of the inspection process. In this manner,information about the design located proximate the positions of the defects in design data space can beused to reduce noise in the inspection results thereby increasing the S/N of the inspection results. Forinstance, defects in non-functional areas of the design can be binned in a group and filtered as nuisancefrom the inspection results before the inspection results are used for subsequent analysis. In anotherexample, defects may be separated based on whether the defects are located in a care area or a non-carearea of the wafer. In an additional example, defects that are systematic but are located in a portion of thedesign in which nuisance defects (e.g., non-DOI) are known to occur may be removed from the inspectionresults to increase the S/N of the results for DOI. One or more portions of the design in which nuisancedefects are known to occur may be determined by a user and may be stored in a data structure such as adesign library. For example, portions of the design in which nuisance defects are known to occur mayinclude the polygons that the user has chosen specifically to use for supervised binning. In addition, if thePOIs are defined prior to performing the binning method, then the binning method may performsupervised binning using the defined POIs. Alternatively, the POIs may be determined by a method asdescribed further herein. The methods described herein may include performing supervised binning on theinspection system and excluding nuisance defects from the inspection results.

Removing a portion of the defects as described above thereby increasing the S/N of the inspection resultsmay be advantageous for post-processing of the inspection results. For example, removing the portion ofthe defects (e.g., to remove non-yield impacting defects) may be performed prior to binning of the defectsand may increase the S/N of the binning results for defect types of interest. In addition, analysis of theinspection results or results of the method embodiments described herein may be quicker and moreaccurate when the S/N of the results is higher and includes less noise. In one particularly advantageousexample, in PWQ methods, a major source of noise is line end shortening (LES) that is detected as defects.However, LES generally does not significantly affect yield. Therefore, users generally do not care aboutLES, and because LES can appear in relatively large numbers, detected LES can overwhelm other defectsthat are more relevant to yield. As such, removing detected LES from results of inspection as describedherein is particularly advantageous for further processing of the inspection results. The defects mayinclude defects detected by an optical or electron beam inspection system. In addition, as describedfurther herein, an inspection recipe can be created based on the design context to differentiate thesedefects during the inspection. In this manner, the methods and systems described herein can be used tocreate inspection recipes that can detect more DOI and suppress more nuisance defects and are capable ofclassifying systematic and random defects and pattern based binning of systematic defects. 117

In another embodiment, the method includes determining if one or more groups of defects correspond tonuisance defects by reviewing at least some of the defects in the one or more groups and removing theone or more groups corresponding to the nuisance defects from results of an inspection process in whichthe defects were detected to increase S/N of the results of the inspection process. Reviewing at least someof the defects may be performed as described herein or in any other suitable manner known in the art.Determining if one or more groups of defects correspond to nuisance defects may be performed using anyresults of review in any suitable manner. If one or more groups of defects correspond to nuisance defects,the one or more groups may also be removed from (filtered out of) the inspection results to increase S/Nof DOIs within the inspection results.

As described above, the embodiments described herein advantageously use design data and defectpositions in design data space to bin defects as opposed to defect information and/or backgroundinformation as printed on the wafer. However, the design data in design data space may be used incombination with other information to bin the defects (e.g., to produce finer separation between thedefects binned into different groups). For instance, in one embodiment, binning the defects includesbinning the defects in the groups such that the portions of the design data proximate the positions of thedefects in design data space in each of the groups are at least similar and such that one or more attributesof the defects in each of the groups are at least similar. The attribute(s) of the defects may include any ofthe defect attribute(s) described herein. In addition, the defect attribute(s) may include any defectattribute(s) that can be determined from results of the inspection. As such, binning may be performedusing a combination of design and one or more attributes of the defects. In this manner, the method mayseparate defects into groups based on design data and defect attribute(s). Therefore, different types ofdefects that are located in design data space in portions of the design data that are at least similar may beseparated. Such binning may be advantageously used to identify different defect mechanisms in a regionof the design data and the rate at which the different defect mechanisms occur.

In another embodiment the portions of the design data proximate the positions of the defects include thedesign data on which the defects are located. In other words, the portions of the design data that arecompared for binning may include the design data "behind" the defects. In this manner, binning mayinclude geometry binning by using the geometry in the design data on which the defect is located. Suchbinning may be performed for defects for which defect locations are reported with relatively highcoordinate accuracy such that the probability that the correct geometry is used for binning is relativelyhigh. Using the design data "behind" the defects is possible in embodiments described herein because thedesign data used in the embodiments is not the design data as printed on the wafer. In contrast, defects on 118 a wafer may obscure the design data printed at the same location on the wafer or in an area surroundingthe defect, which may further reduce the accuracy of methods for binning defects based on the design dataas printed on the wafer. In another embodiment, the portions of the design data proximate the positions ofthe defects used in embodiments described herein include the design data around the positions of thedefects. In addition, binning may be performed using the geometry on which the defects are located andthe geometry surrounding or proximate to the positions of the defects in design data space.

As described above, binning may be performed without regard to the positions of the defects within theportions of the design data. Such binning may be particularly advantageous for defects that are detectedby an inspection system that reports defect locations with relatively low accuracy. In addition, suchbinning may produce substantially highly accurate binning results while providing important informationsuch as which portions of the design data exhibit particularly high defectivity and/or particularly highdefectivity rates. However, in an additional embodiment, binning the defects includes binning the defectsin the groups such that the portions of the design data proximate the positions of the defects in each of thegroups are at least similar and such that positions of the defects in each of the groups with respect topolygons in the portions are at least similar. In this manner, binning may be performed using acombination of the portions of the design data proximate the positions of the defects in design data spaceand the positions of the defects with the portions of the design data. As such, binning may be performedbased in part on where in the geometry the defects are located. In other words, binning may be performedbased on the inter-portion positions of the defects in combination with the design data proximate the inter-portion positions. Such binning is preferably performed for defects for which locations are reported withrelatively high coordinate accuracy such that substantially accurate inter-portion positions of the defectsare used for binning. In this manner, defects that are located in the same portions of the design data butimpact the device in different ways due to different inter-portion positions may be separated. For example,using such binning, defects that are located between two features in a portion of the design data andtherefore have a relatively high probability of causing an open in the device may be separated fromdefects that are located entirely within one of the two features and therefore have a much lowerprobability of causing an open in the device. Therefore, such binning may be advantageously used toidentify defects having different yield impacts on a region of the design data and the rate at which thedifferent yield impacting defects occur.

In some embodiments, the binning step includes binning the defects in groups such that the portions ofthe design data proximate the positions of the defects in each of the groups is at least similar and such thathot spot information for the portions of the design data proximate the positions of the defects in each of 119 the groups is at least similar. The hot spot information may include any of the hot spot informationdescribed herein or any other hot spot information known in the art. The hot spot information may bedetermined for the different portions of the design data as described further herein. In this manner, themethod may perform binning using a combination of the design data and the hot spot information. In onesuch example, hot spots in the design data that have similar impacts on yield may be binned as describedabove before the method is performed. Therefore, defects can be binned based on design data similarities,and then the groups of defects resulting from this binning may be separated into sub-groups of defectshaving similar yield impact. In one such example, all portions of design data that are at least similar maynot be associated with the same hot spot information if, for example, some of the positions are locatedabove or below design data that is dissimilar. As such, defects located proximate at least similar portionsof design data may be separated based on the hot spot information for each portion of the design data. Inthis manner, the overall yield of the process that was used to fabricate the wafer can be assessed quicklyand accurately. In addition, the hot spot information may be used for binning to check or verify that thesimilarity of the portions of the design data has been determined correctly. For example, if portions of thedesign data that are determined to be at least similar are not associated with at least similar hot spotinformation, the defects corresponding to the portions of the design data may not be binned into the samegroup.

In another embodiment, the method includes determining if the defects in one or more of the groups aresystematic defects or random defects based on one or more attributes of the design data proximate thepositions of the defects in design data space, one or more attributes of the defects, or some combinationthereof. In this manner, the method may include collectively classifying defects as a group. For instance,the systematic defects may be classified as nuisance defects or defects not of interest as a group. However,such classification may be performed for individual defects. The attribute(s) of the defects that may beused to determine if the defects are systematic or random defects may include, for example, if the defectsare present at approximately the same location in more than one die, if the defects in more than one diehave approximately the same attribute(s), and if the distribution of more than one defect in a die is orderlyand/or clustered. In one example, defects that appear in only one die on a wafer may be classified asrandom defects, and defects that appear in a number of die at approximately the same location may beclassified as systematic defects. The methods described herein may, therefore, be used to determine acause of a defect detected on a wafer by an inspection process (an inline inspection process and/or anelectrical inspection process) using information about the defects. 120

In some embodiments, the method includes classifying one or more groups of defects based on results ofreview of at least some of the defects in the one or more groups, one or more attributes of the design data,one or more attributes of the defects, or some combination thereof. Review of at least some of the defectsin one or more groups may be performed as described herein or in any suitable manner known in the art.The one or more attributes of the design data and the one or more attributes of the defects may includeany of the attribute(s) described herein. In this manner, defects may be classified collectively as a groupbased on a substantial amount of information thereby providing relatively quick and relatively accuratedefect classification.

In another embodiment, the method includes determining if a group into which defects are binned asdescribed herein contains systematic or potential systematic defects. In this manner, the defects may beclassified as systematic or potential systematic defects collectively as a group. However, the defects mayalso be individually classified as systematic or potential systematic defects. For example, the defects maybe classified in these embodiments based on the positions of the defects with respect to polygons in thedesign and whether hot spots, cold spots, etc. are located at approximately the same positions. Themethods described herein may, therefore, be used to determine a cause of a defect detected on a wafer byan inspection process (an inline inspection process and/or an electrical inspection process) usinginformation such as design data.

In some embodiments, the method includes monitoring systematic defects, potential systematic defects, orsome combination thereof over time using the results of the binning step. For example, the results of thebinning step may be used to identify systematic issues in the design data, and the identified systematicissues may be monitored for reoccurrence across wafers and/or across time. Monitoring the systematicand/or potential systematic defects may be performed using any of the results of any of the methodsdescribed herein.

In addition, monitoring the systematic and/or potential systematic defects may be performed in a mannersimilar to statistical process control (SPC) methods. For example, monitoring systematic defects, potentialsystematic defects, random defects, or some combination thereof can be used for yield-based SPC, inwhich different SPC methods and/or algorithms are used for different types of defects. In one suchexample, SPC parameters may be used for monitoring different types of defects, and the SPC parametersmay be determined or selected based on potential yield impact of the different types of defects, whichmay be determined as described herein. In this manner, different types of defects may be monitoredsimultaneously for SPC, but with different SPC parameters. In another embodiment, only a subset of the 121 defects detected by inspection may be used for SPC. For example, only non-nuisance systematic and/orpotential systematic defects may be monitored for SPC purposes such that the process can be monitoredfor design based process marginalities. In an additional example, only systematic defects that aredetermined to have potentially large impacts on yield may be monitored for SPC such that changes in theyield of the fabrication process caused by changes in these defects may be detected relatively early andaccurately. In addition, using different methods for estimating yield impact of systematic defect groupsand random defects may advantageously provide more accurate prediction, monitor, and control of yield-related issues. In this manner, the method may provide information about fabrication of the device (e.g.,increase in systematic defects over time, decrease in systematic defects over time, change in systematicdefects over time, etc.) that can be used to monitor and improve yield of the fabrication.

In one embodiment, the method may include determining the cause of pattern based defects (e.g.,systematic defects). For example, if one or more pattern based defect groups are dominant, the methodmay include acquiring inline inspection data and/or electrical inspection data for a number of other wafersfor the same layer and the same device. For instance, inline inspection data and/or electrical inspectiondata may be acquired for about 100 to about 1000 other wafers. This data may be acquired from a storagemedium such as a defect database or a fab database. If such data is not available, the method may includegenerating such information by inspecting wafers that have already been processed (or processing otherwafers) in the processes which were performed on the wafer on which the systematic defects weredetected and then inspecting the wafers.

The method may also include performing pattern-based binning of the defects detected on the additionalwafers, which may be performed as described herein. The method may include determining if the one ormore pattern based defect groups are dominant for the additional wafers. If the additional wafers exhibitcommonality of dominant pattern based defects, the method may include determining if the wafers wereprocessed through common equipment (or process tools). In this manner, the method may performequipment commonality analysis. The method may include determining if the dominant pattern baseddefect groups are correlated to specific equipment, a specific chamber (e.g., equipment or a chamberwhose parameters may have drifted for some reason), or a specific route-step (e.g., an integration issuebetween equipment and two or more steps). If the dominant pattern based defect groups are correlated tospecific equipment or a specific chamber, then the cause of the pattern based defect groups has beenisolated and possibly identified. The method may include stacking data to determine if there is a spatialsignature for a group of interest. Spatial signatures can be useful for narrowing-down or determining thecause of process-, OPC- or design-related systematic issues, or combinations thereof. 122

If the dominant pattern based defect groups cannot be correlated to specific equipment or a specificchamber, then the method may include performing data mining to attempt to correlate the defects to otherprocess factors. Data mining may be performed in any suitable manner known in the art based on anyinformation about the defects and the design data and any information generated during device fabrication,which may be stored in one or more storage media such as a fab database. If a relatively strong correlationbetween one or more other process factors and the defects is identified, then the process factor(s)correlated to the defects may be identified as the cause of the defects. If a relatively strong correlationbetween one or more other process factors and the defects cannot be identified, then the method mayinclude performing arbitrary pattern searching of the design for the potential POIs and setting up newinline hot spot monitors such that the cause of the pattern dependent defects may be determined. However,if process conditions are ruled out, it is then likely that the process itself or the design itself should beevaluated and, if necessary, adjusted to reduce or remove the problem. In addition, by comparing theattribute(s) of the systematic defects to results of process window mapping, inference may be made as tothe probable sources and/or root cause.

The method may use information about the systematic and/or potential systematic defects to perform datareduction. For instance, there may be 50,000 to more than 200,000 hot spots generated by a full-diepattern-based search for a single POI or from empirical techniques such as electrical functional testingand lithography PWQ results. Therefore, to process and analyze this data in a meaningful and timelymanner, data reduction techniques may be performed on the data. In one such example, for pattern basedhot spots, the method may include binning the hot spots into "looks-like" groups. For example, eachgroup may include hot spots located proximate to at least similar patterns in design data and/or locatedproximate to design data having one or more attribute(s) that are at least similar (e.g., hot spots located inrelatively low pattern density areas of the design may be binned in a group). As such, the method mayinclude binning hot spots based on design context and/or design attribute(s). In an additional example, forempirical techniques such as PWQ, the method may include removing from a defect population on whichreview sampling is performed defects that are proximate to locations of the design with little or no yieldimpact (cold spots). By performing data reduction as described above, a better (e.g., more yield relevant)review sample may be generated using the reduced data as described further herein.

The methods and systems described herein may include CBI in combination with design- and yield-basedpost processing (performed on-tool or off-tool) of inspection results. For example, after the nuisance,systematic, and random defects have been identified, the defects may be organized in some manner (e.g., 123 using a defect organizer (DO) or an inline defect organizer (iDO)). In one example, the results are storedin a data structure such as a database. In another example, as described above, after the defects have beenbinned into groups based on portions of the design data proximate the positions of the defects in designdata space, the defects in the groups may be further separated based on one or more attributes of thedesign data proximate to the positions of the defects in the design data space, one or more attributes of thedefects, or some combination thereof. The defects may be separated based on one or more attributes ofthe design data and/or one or more attributes of the defects using iDO. In this manner, design basedbinning may be used in combination with iDO in the embodiments described herein. In particular, theoutput of design based binning may be input to iDO.

The one or more attributes of the design data, which are used to further separate the defects binned intogroups based on design data, include, but are not limited to, one or more attributes of the patterns orstructures in the design data proximate to the positions of the defects in the design data space, the patterndensity proximate the positions of the defects in the design data space, the functional block in which thedefect is located, and one or more attributes of the device (e.g., n-MOS or p-MOS). The one or moreattributes of the defects, which are used to further separate the binned defects, include, but are not limitedto, size, shape, brightness, contrast, polarity, and texture.

The results of design based binning and iDO may be illustrated in a bar graph. The bar graph mayillustrate the total number of defects versus pattern in the design data in which the defects were detectedand the number of defects within sub-groups as a function of pattern. Using design based binning incombination with iDO as described above may be used to separate random and systematic defects, toprioritize groups into which the defects were binned, and/or to identify and possibly prioritize changesthat should be made to the design data (e.g., using potential yield impact of the defect groups, which maybe determined as described further herein). In particular, the value that design based binning provides forseparation of systematic and random defects may be increased by using iDO for further separation of thesystematic (and possibly random) defects. In addition, the value that design based binning provides forseparation of systematic and random defects may be increased by using yield relevancy possibly incombination with iDO for separation of the systematic (and possibly random) defects.

In this manner, the systematic defect population and the random defect population may be processedseparately (e.g., the systematic defect population and the random defect population may be independentlysampled). The different populations or different information for systematic and random defects may beused to generate separate results for the systematic defects and the random defects. For instance, the 124 systematic and random defects may be illustrated in different bar graphs or other graphical or textual representations that may be processed automatically and/or used by a user. After sampling the defects for review, the systematic defects, and optionally some of the random defects, may be reviewed using a suitable review system (e.g., a relatively high magnification optical review system or a SEM). The results of defect review may be used to normalize the defect density of both the systematic and random defects.

The methods and systems described herein provide a number of advantages for the user. For instance, themethods and systems provide efficient baseline yield improvement, better excursion detection, improvedreview system efficiency, more efficient root cause detection, and improved knowledge retention. Inaddition, the results of the embodiments described herein may include various other types of informationthat are useful for consumers of the results (e.g., customers of the device manufacturers). Such other typesof information may include information such as process tool owner, designer, integration engineer, etc.

Furthermore, it has been estimated that more than 50% of yield loss at 90 nm design rules and beyondwill be caused by systematic issues. As such, systematic yield issues are significant at 90 nm design rulesand are dominant at design rules smaller than 90 nm. Therefore, separating the systematic defects fromnuisance defects and random defects as described above allows for better evaluation, analysis, and controlof these systematic issues. Moreover, the locations of the systematic defects may be compared to thelocations of functional blocks in the design data. In this manner, the systematic defects may be correlatedto one or more functional blocks, and this information may be used to improve the S/N. In particular, themethod may include separating the defects based on functional blocks in which the defects are located toimprove S/N. In a similar manner, the method may include separating the defects based on hierarchicalcells into which the design data is organized by design. Therefore, to improve S/N, the defects binned intogroups and/or the defects to which a DBC has been assigned may be separated based on functional block(or any level of the hierarchy) in which the defect is located (e.g., memory or logic). The portions of thedesign data used in the embodiments described herein may correspond to any cell structure or hierarchyof cells.

The percentage of the defects per functional block may be determined in the methods described herein. Inthis manner, the functional blocks containing design issues may be identified based on the percentage ofthe defects detected in each functional block and/or binned into groups corresponding to the functionalblocks. Additional information about the defects located in the functional blocks may be used to identitythe design issues in each block. The above-described information may also be used to select and/orprioritize design issues for correction based on how many defects can be eliminated by the corrections. 125

For instance, if it is determined that about 70% of the defects are caused by four design issues in fourdifferent functional blocks of the design, only these four design issues may be selected for correction, orthese four design issues may be selected for correction before any others are corrected (e.g., byprioritizing the design issues based on the number or percentage of the defects caused by the designissues). A user (e.g., a chip designer) may have a choice of cell designs to use and may choose to use celldesigns that historically exhibit fewer systematic defects, and such information about the cell designs maybe generated using the embodiments described herein.

In another embodiment, the method includes prioritizing one or more POIs in the design data andoptimizing at least one of the one or more POIs based on results of the prioritizing step. In one suchembodiment, the POI(s) may be prioritized based on the number of defects detected in the POI(s). Thenumber of defects detected in each POI can be determined from the results of the binning step, forexample, by comparing the POI(s) or one or more attributes of the POI(s) to the portions of the designdata corresponding to the groups and assigning to the POI the number of defects in the groupcorresponding to portions of the design data (and/or one or more attributes of the portions of the designdata) that are at least similar to the POI(s) (or the attribute(s) of the POI(s)). In this manner, the POI inwhich the largest number of defects has been detected may be assigned the highest priority, the POI inwhich the next largest number of defects have been detected may be assigned the next highest priority,and so on.

In another embodiment, the method includes prioritizing one or more systematic defects types for yieldoptimization (e.g., by changing the process parameters, the design, OPC, etc., or some combinationthereof). In one such embodiment, the systematic defect types may be classified as POI or groups of POI,and the POIs may be prioritized based on the number of defects detected on or near the POIs, which maybe determined as described above. The priority may be further enhanced by using the criticality of thesystematic defect(s) detected in the POI, the frequency of the POI in the design, and the sensitivity of thePOI to process variation to prioritize the systematic defects.

In addition, or alternatively, the POI(s) may be prioritized based on any other results of any step(s) of anyof the method(s) described herein or any combination thereof. For example, prioritizing the POI(s) mayinclude determining a defect criticality index (DCI) for one or more defects detected in the POI(s) andprioritizing the POI(s) based on the DCI for the one or more defects. The DCI may be determined in thisembodiment as described further herein. In another example, prioritizing the POI(s) may includedetermining a KP value for one or more defects detected in the POI(s) and prioritizing the POI(s) based 126 on the KP values for the one or more defects. In yet another example, the POI(s) may be prioritized based on a combination of number of defects detected in or proximate the POI(s) and a DCI for one or more of the defects detected in or proximate the POI(s). In this manner, prioritizing the POI(s) may include prioritizing the POI(s) based on defectivity exhibited by the POI(s) such that the POI(s) having higher defectivity are assigned higher priorities.

Furthermore, the POI(s) may be identified and/or prioritized based on one or more attributes of the POI(s)possibly in combination with other results described herein. The one or more attributes of the POI(s) mayinclude, for example, dimensions of features in the POI(s), density of features in the POI(s), the type(s) offeatures included in the POI(s), position of the POI(s) within the design, susceptibility of the yield impactof the POI(s) to defects, etc., or some combination thereof. In one such example, POI(s) that are moresusceptible to yield impact by defects may be assigned a higher priority than POI(s) that are lesssusceptible to impact of defects on yield.

Moreover, the POI(s) may be prioritized based on one or more attributes of the design possibly incombination with one or more attributes of the POI(s) and/or other results described herein. The one ormore attributes of the design may include, for example, redundancy, electrical connectivity, electricalattributes, etc., or some combination thereof. In particular, a cell in the design data may have contextbeyond the pattern contained within the cell. Such context may include, for example, hierarchy of cells,redundancy (or not), etc. Therefore, the one or more attributes that are used in the embodiments describedherein may include context of the cells in which the POI(s) are located, which may be determined basedon the positions of the POI(s) in design data space and/or the design data of POI(s) (if the design data isspecific to a cell in the design data). In one such example, POI(s) that are not redundant in the design (e.g.non-array) may be assigned a higher priority than POI(s) that are redundant (e.g. array). The POIs mayalso be prioritized based on redundancy of connections between cells (e.g., routing or redundant vias).Such context of the design may be acquired and/or determined in any manner known in the art.

Optimizing at least one of the POIs based on results of the prioritizing step may include altering any oneor more attributes of the POIs such as dimension(s) of feature(s) of the POI(s), density of feature(s) of thePOI(s), etc., or any combination thereof. The one or more attributes of the POIs may be altered by alteringthe design data corresponding to the POIs. Preferably, the POI(s) are altered to decrease defectivity of thePOI(s) (e.g., number of defects detected in the POI(s)), to alter one or more attributes (e.g., DCI, KP, etc.)of defects detected in the POI(s), and/or to increase yield of devices in which the POI(s) are included. Inaddition, POI(s) having a higher priority as determined by the prioritization step may be altered and 127 optimized before POI(s) having a lower priority as determined by the prioritization step. In this manner,POI(s) exhibiting the largest defectivity and/or defectivity that has the largest impact on yield may bealtered and/or optimized before POI(s) exhibiting lower defectivity and/or defectivity that has less of animpact on yield. As such, the results of the prioritization step indicate which POI(s) can be altered and/oroptimized to produce the largest improvements in yield, and those POI(s) can be altered and/or optimizedbefore other POI(s).

This embodiment is, therefore, advantageous over other previously used methods and systems for alteringdesign data because without timely guidance as to which POI(s) have the largest impact on yield,alterations made to the design data and/or manufacturing processes are delayed resulting in slowerimprovements in yield and increased time to market. Furthermore, although the POI(s) that are altered inthis step may include only the POI(s) that are included in the design printed on the wafer prior todetection of the defects binned in the embodiments described herein, the POI(s) that are altered tooptimize the POI(s) may include POI(s) included in more than one design. For instance, if more than onedesign includes the POI(s), based on the prioritization and/or any other results of the methods describedherein, the POI(s) in different designs may be altered and optimized to thereby increase the yield ofdevices fabricated with each of the different designs.

In an additional embodiment, the method includes prioritizing one or more POIs in the design data andoptimizing one or more RET features of the one or more POIs based on results of the prioritizing step.Prioritizing the POI(s) in this embodiment may be performed as described above. The RET feature(s) thatare optimized in this step may include any RET feature(s) (e.g., OPC features) that are included in thedesign. Optimizing the one or more RET features of the one or more POIs based on results of theprioritizing step may include altering one or more attributes of the RET feature(s) (e.g., dimensions of theRET feature(s), shape of the RET feature(s), position of the RET feature(s) with respect to features in thePOI(s), etc.). The one or more attributes of the RET feature(s) that are altered in this step preferablyinclude any attribute(s) of the RET feature(s) that will decrease the defectivity in the POI(s) and/orincrease yield.

In addition, optimizing the one or more RET features based on the results of the prioritizing step in thisembodiment may include optimizing the RET feature(s) for the POI that has been determined to have thehighest priority before optimizing the RET feature(s) for other POIs. In this manner, RET feature(s) ofPOI(s) having higher priorities may be altered before RET feature(s) of POI(s) having lower priorities arealtered. In this manner, RET feature(s) of POI(s) exhibiting the largest defectivity and/or defectivity that 128 has the largest impact on yield may be altered and/or optimized before RET feature(s) of POI(s) exhibiting lower defectivity and/or defectivity that has less of an impact on yield. As such, the results of the prioritization step indicate which POI(s) can be altered and/or optimized to produce the largest improvements in yield and the RET feature(s) of those POI(s) can be altered and/or optimized before the RET feature(s) of other POI(s).

This embodiment is, therefore, advantageous over other previously used methods and systems for alteringdesign data because without timely guidance as to which POI(s) have the largest impact on yield,alterations to the design are delayed, resulting in slower improvements in yield and increased time tomarket. Furthermore, although the RET feature(s) of the POI(s) that are altered in this step may includeonly the RET feature(s) of the POI(s) that are included in the design printed on the wafer prior todetection of the defects binned in the embodiments described herein, the RET feature(s) of the POI(s) thatare altered and/or optimized may include RET feature(s) of POI(s) included in more than one design. Forinstance, if more than one design includes the POI(s) with the same RET feature(s), based on theprioritization and/or any other results of the methods described herein, the RET feature(s) of the POI(s) indifferent designs may be altered and optimized to thereby increase the yield of devices fabricated witheach of the different designs.

In some embodiments, the method includes modeling electrical properties of a device being fabricatedusing the design data about a defect location and determining parametric relevancy of a defect at thedefect location based on results of the modeling. In this manner, the results of the modeling step may beused to determine parametric relevancy of the defect. For example, the results of the modeling step maybe used to determine how the defect alters one or more electrical parameters of the device beingfabricated using the design. The defect for which the parametric relevancy is determined as describedabove may be a systematic defect. The parametric relevancy may be used in any step(s) of the method(s)described herein. For example, the parametric relevancy, possibly in combination with other informationdescribed herein (e.g., one or more defect attributes, one or more attributes of the design data, etc.) maybe used to determine a DCI of the defect, to prioritize the POI(s) as described herein, etc.

Modeling the electrical properties of the device in this embodiment may be performed using anyappropriate method or system known in the art. The electrical properties of the device that are modeledmay include any one or more electrical properties of the device. The parametric relevancy of the defectmay be determined using the modeled electrical properties and the as-designed electrical properties. Forexample, the modeled electrical properties may be compared to the as-designed electrical properties to 129 determine the degree to which the defect alters the electrical properties. The parametric relevancy maythen be determined based on the degree to which the defect alters the electrical properties (e.g., a defectthat alters the electrical properties to a large degree is more parametrically relevant than a defect thatalters the electrical properties to a lesser degree). The parametric relevancy may be determined in asimilar manner using the modeled electrical properties and a range of suitable electrical properties of thedevice. For example, the modeled electrical properties may be compared to this range, and where themodeled electrical properties fall within or outside of this range may be used to determine parametricrelevancy. In one such example, if the modeled electrical properties are near or outside of the acceptablerange, the defect may be determined to be more parametrically relevant than if the modeled propertieswere inside of the acceptable range. The parametric relevancy may also be determined based, at least inpart, on information from a number of different sources including, but not limited to, simulation, opticalinspection results, defect review results, electrical testing results, or some combination thereof.

In one embodiment, the method includes assigning priorities to systematic defects and potentialsystematic defects based on the parametric relevancy determined for or associated with the systematicdefects and the potential systematic defects. For example, the priority or severity of hot spots may beranked based on the parametric relevancy. The parametric relevancy may define how and how muchdefects at the hot spots will affect the electrical parameters of the device.

The parametric relevancy may also be used to separate or prioritize defects which are more likely to causeparametric issues (e.g. yield loss) for the device. For example, electrical testing results or otherinformation about the electrical properties of the device such as resistance, capacitance, timing, etc. canbe used in combination with one or more attributes of the design data proximate to the positions of thedefects in design data space and/or one or more attributes of the defects to determine which defects willaffect the electrical properties of the device and which defects will not. The electrical testing results orother information about the electrical properties may be determined by the method (e.g., using simulation)or may be acquired from another source (e.g., netlist information). In this manner, defects that are morelikely to cause parametric issues can be separated from defects that are less likely or unlikely to causeparametric issues. As such, defects that affect only the composition of the geometry or the materialattributes of the device may be separated from defects that affect if the device can function according toits intended purpose. In addition, the electrical testing results or other information about the electricalproperties of the device in combination with one or more attributes of the design data and/or one or moreattributes of the defects may be used to separate electrical defects into critical parametric defects (e.g.,electrical defects that may significantly affect the electrical properties of the device) and non-critical 130 parametric defects (e.g., electrical defects that may not significantly affect the electrical properties of the device).

In some embodiments, the method includes determining a DCI for the defects (e.g., one or more of thedefects). The DCI may be determined based on one or more attributes of the design data proximate thepositions of the defects in design data space, one or more attributes of the defects, or some combinationthereof. For example, one or more attributes of the design data proximate the positions of the defects indesign data space, one or more attributes of the defects, or some combination thereof may be used todetermine the design based potential yield impact of the defects thereby increasing the value of the defectdata. In one particular example, DCI can be determined by using defect size and position of the defect inthe design data to determine the likelihood that the defect will cause an electrical fault. The DCI can thenbe used to indicate yield relevance of the defect. In particular, defect size can be used to determine thelikelihood that a defect will kill a die or otherwise alter one or more electrical attributes of a device beingfabricated on the wafer. For instance, as the defect size increases and the pattern complexity increases, thelikelihood that a defect will kill the die or change one or more electrical attributes of the device alsoincreases. Therefore, a relationship describing the likelihood that a defect will kill a die or change one ormore electrical attributes of the device as a function of defect size and pattern complexity may be used todetermine the relative risk of each defect on each wafer. The relative risk of each defect may bedetermined right after inspection thereby allowing better decision making based on the relative risk.

Alternatively, the DCI may be determined using a statistical method that includes determining fordifferent defect sizes and possibly different types of defects (possibly across an entire die) a probabilitythat a defect will kill the die or change the one or more electrical attributes, which can then be used todetermine the DCI for the defects. For example, in one embodiment, the method includes determining aprobability that one or more of the defects will cause one or more electrical faults in a device (or alter oneor more electrical attributes of the device thereby causing a parametric electrical issue) fabricated for thedesign data based on one or more attributes of the design data proximate the positions of the defects indesign data space, one or more attributes of the defects (such as defect size), positions of the defectsreported by an inspection system used to detect the defects, coordinate inaccuracy of the inspectionsystem, or some combination thereof and determining a DCI for the one or more defects based on theprobability. The probability may be determined in this manner using any appropriate statistical methodknown in the art. 131

The DCI for the defects may be used in a number of ways in the embodiments described herein such asfor sampling in which defects are selected for review. In particular, for each defect classification or groupof defects, DCI may be used for sampling the defects with the same classification or binned in the samegroup instead of performing random sampling of commonly classified defects or commonly binneddefects. Using DCI for sampling, the distribution of the DCI may be used to determine which defectshave a higher probability of killing a die or changing the one or more electrical attributes, and defects thathave a higher probability of killing a die or changing the one or more electrical attributes may be moreheavily sampled. As such, defects that are more likely to affect yield may be more heavily sampled forreview, which may, therefore, generate defect review results that are particularly useful for identifyingand classifying defects more likely to impact yield. The DCI may be used to sample not only potentiallysystematic and systematic defects but also random defects.

In some embodiments, the method includes determining high density zones on electrical failure densitymaps. Failure density maps may be produced by generating a "logic bitmap" or physical conversion offailing test chains or failing flip-flops (detected by structural testing, a type of which is scan-basedtesting). Every failing line or region that is found by scan-based testing may be shown as such on agraphical rendering of the die under test (DUT). The terms "logic bitmaps" and "bitmaps" are usedinterchangeably herein. Logic bitmaps for different die of the same layer(s) and design may be stacked(i.e., overlaid) to illustrate the number of failures at each point on the die thereby producing a failuredensity map. Defects that appear in the failure density map at a frequency that is greater than apredetermined value may be considered to be systematic defects. Defects found proximate to hot spots inthe die coordinate space may be considered yield impacting systematic defects or systematic candidates.

In some embodiments, the results of an electrical inspection process (e.g., a bitmap) may be analyzedusing information from inline inspection results to determine if the cause of an electrical defect can bedetermined from the inline inspection results. To correlate the inline inspection results and the electricalinspection results, the different inspection results may be aligned to each other as described herein. Inaddition, the different inspection results may first be aligned to the design data, and then the inspectionresults may be aligned to each other. In either case, the bitmap results may be overlaid with the inlineinspection results.

The method may also include determining the cause of an electrical defect in a bitmap based on the inlineinspection data and the design data. In addition, different fault types and their candidate location or pathscan be analyzed to determined how many of the electrical failures overlap with physical defects. These 132 'hits' provide evidence that the physical defect contributes to the cause of the electrical defect. In thismanner, a hit ratio for a fault type may be determined as the number of faults of that type that correspondto a reported physical defect divided by the number of faults of that type. The hit ratio may be evaluatedto determine if the fault type tends to be correlated with reported physical defects. In addition, the hit ratioand inline inspection results of the physical defects may be used to determine how many of the same typeof physical defects caused an electrical failure. In this manner, the number of defects of the same type thatcaused an electrical failure may be used to determine a statistical prediction of the yield significance ofthe defects.

Additional information about the physical defects may also be used to determine the cause of the bitfailures. Such information may include, but is not limited to, an image of a physical defect correspondingto the location of a bit failure, classification results for the physical defect, binning results for the physicaldefect, or some combination thereof, which may be used in combination with bitmap information such asa bitmap image of the entire die in which the bit failure is located, an image showing stacking (i.e.,overlay) of the bitmap images of multiple die (e.g., to show repeatability of the electrical failures acrossdie), a bitmap pareto diagram, and detailed information about the bitmap results (e.g., data in a table orlist).

In some embodiments, the method may including using defect transition table (DTT) methodology toidentify hot spots at which defects were not detected or at which non-killer or non-significant defectswere detected. In general, rows of a DTT include inspection results for different defects, and differentcolumns of the DTT include inspection results generated by inspections performed at different times. Theinspection results may be arranged in chronological order across the columns. In this manner, the tableillustrates which defects were re-detected at different layers during a semiconductor manufacturingprocess. The table may also include or provide access to (e.g., links to) additional information about thedefects detected at different layers. In this manner, additional information such as images of the defectscan be used to determine if and how the defect changed at different layers.

In an additional embodiment, the method includes determining a KP value for one or more of the defectsbased on one or more attributes of the design data, one or more attributes of the defects, or somecombination thereof. In a similar manner, the method may include determining a KP value for one ormore groups of defects based on one or more attributes of the design data corresponding to the one ormore groups, one or more attributes of the defects in the one or more groups, or some combination thereof.The KP value for systematic defects may be used to determine additional attributes of the systematic 133 defects such as yield ratio. In addition, the KP value may be used to perform additional steps describedherein. For example, the KP values for the systematic defects may be used to determine which defects areselected for review. In particular, systematic defects having a relatively high KP value may be selected forreview. In addition, the method may include monitoring the KP value for the systematic defects andgenerating an output signal if the KP value exceeds a predetermined KP value. The output signal may bean automated report, a visible output signal, an audible output signal, or some other output signal that canbe used to alert a user to a potential problem with the process. In this manner, the output signal may be analarm signal.

As described further herein, one advantage of the methods and systems described herein is thatinformation from a number of different sources may be accessed, correlated, stored, displayed, and/orprocessed together. Such information may include, but is not limited to, information in GDS files,information about the processes performed on the wafer (which may be commonly referred to as WIPdata and which may be acquired from a source such as a fab manufacturing execution system (MES)database), inline inspection results, inline metrology or measurement results, electrical testing results, andend-of-line yield information. Such information may be utilized to determine yield related informationabout the systematic defects. Furthermore, the yield ratio or other yield related information determined forthe systematic defects may be used to assign yield related context to the systematic defects. Both the yieldrelated context information and the design context may be assigned to the systematic defects. In oneembodiment, instead of classifying defects based on design context, the systematic defects may beclassified based on yield limiting context.

As described further herein, hot spot based inspection for systematic defects will produce inspectionresults that include the detected systematic defects and design context corresponding to the systematicdefects. In this manner, marginal features in the design data can be identified and used for SPCapplications. For instance, SPC can be performed by monitoring locations of the marginal features in thedesign data since these features will tend to fail first as the process drifts out of process limits. Therefore,SPC can be performed quicker by monitoring a subset of all features in the design including the mostimportant features in the design instead of all features in the design and can more quickly detect drifts inprocesses since the features in the design that are most sensitive to changes in the process are monitoredduring SPC. In a similar manner, the marginal feature information can be used to generate a recipe for ametrology process such as a CD measurement process. The CD measurement process may include anysuitable CD measurement process known in the art (e.g., CDSEM, scatterometry CD measurements, etc.).Generating the recipe for the CD measurement process may include determining locations on the wafer 134 (e.g., locations at which the marginal features will be printed) at which the CD measurements are to be performed during the process. In addition, results of inspection of the wafer such as BF images acquired at the locations on the wafer at which the CD measurements are to be performed may be provided with the recipe or to the metrology system such that the results can be used by the metrology system to move to the locations on the wafer for the measurements.

However, with the addition of test data, the portions of the design corresponding to the systematic defectscan be related to yield probability of the semiconductor manufacturing process and the KP of thesystematic defects. In one such embodiment, an inspection system or any other system described hereinmay produce yield results for systematic defects such as the probability that each individual die yields andwhich defect or defects are most likely to have an impact on the yield. The KP of the systematic defectsmay also be used for SPC applications. For example, the probability that each die yields and which defector defects are most likely to have an impact on the yield may be used to improve SPC monitoringapplications and review sampling. In this manner, SPC may be performed based on context based yield.In addition, the improved SPC monitoring and review sampling may improve the root cause analysis andbaseline reduction.

In a further embodiment, the method includes monitoring KP values for groups of defects over time anddetermining a significance of the groups of defects based on results of the monitoring. For instance, overtime, as the KP value continues to be updated, hot spots with low KP values can be eliminated ordowngraded to conditional hot spots, weak spots, or cold spots. In this manner, the identified potential hotspots can be assigned a low or zero KP value (i.e., cold spots). In another embodiment, the methodincludes determining a KP value for groups of defects based on an electrical failure density associatedwith the design data. In this manner, hot spots that are determined not to overlay with relatively highfailure density zones on electrical failure density maps can be downgraded in KP and optionally removedfrom the hot spot database and/or their associated inspection recipe.

In one embodiment, the method includes monitoring a KP value for one or more POIs in the design dataand assigning the KP value for the one or more POIs to one or more of the groups if the portions of thedesign data proximate the positions of the defects binned into the one or more groups correspond to theone or more POIs. For example, monitoring the KP value for one or more POIs in the design data may beperformed based on electrical failures, an electrical failure density, any other attribute(s) of the electricalfailures, or some combination thereof determined for the one or more POIs over time and inspectionresults acquired for the one or more POIs over time. The electrical failures, the electrical failure density, 135 and any other attribute of the electrical failures may be determined using any suitable method or systemknown in the art. The inspection results may be acquired as described herein. Although monitoring the KPvalues is performed by the method in this embodiment, monitoring the KP values may be performed by adifferent method or system, and the assigning step described above may be performed by the method. Inaddition, monitoring the KP values may be performed during a setup phase prior to performing thebinning method thereby decreasing the time between inspection and assigning a KP value to one or moregroups of defects. Assigning the KP value for the one or more POIs to one or more of the groups mayinclude comparing the portions of the design data proximate the positions of at least some of the defectsbinned into the one or more groups to portions of the design data corresponding to the one or more POIs.If the portions of the design data proximate the positions of at least some of the defects in a group are atleast similar to the portions of the design data corresponding to a POI, which may be determined based onthe results of the comparing step, the KP value corresponding to the POI may be assigned to the defects(e.g., all of the defects) in the group.

The methods described herein may include generating information for one or more diagnostic or repairprocesses that are sensitive to hot spots (e.g., have high signal and low noise for hot spots). Theinformation may be used to automate or optimize one or more diagnostic or repair processes for hot spots.The one or more processes may be used for hot spot verification and analysis, capturing new learning,optimizing do not care areas and nuisance defect filtering, reporting, and differentiating between designand process marginalities. In this manner, the method may be used to generate recipes for diagnostic andrepair processes such as wafer inspection, reticle inspection, optical inspection, macro-defect inspection,electron beam inspection, optical defect review, SEM defect review, metrology processes such asellipsometry and CDSEM, defect analysis processes, FIB and other FA processes, and defect repairprocesses.

In some embodiments, the method includes prioritizing one or more POIs in the design data andoptimizing one or more processes to be performed on wafers on which the design data will be printedbased on results of the prioritizing step. Prioritizing the one or more POI(s) may be performed asdescribed herein. Optimizing one or more processes in this embodiment may include altering any one ormore parameters of the one or more processes such as focus, dose, exposure tool, resist, post expose bake(PEB) time, PEB temperature, etch time, etch gas composition, etch tool, deposition tool, deposition time,etc. Preferably, the parameter(s) of the process(es) are altered to decrease defectivity of the POI(s) (e.g.,number of defects detected in the POI(s)), to alter one or more attributes (e.g., DCI, KP, etc.) of defectsdetected in the POI(s), and/or to increase yield of devices in which the POI(s) are included. 136

In addition, the one or more parameters of the one or more processes may be optimized for only the POIhaving the highest priority as determined by the prioritization step or the POI(s) having relatively highpriorities as determined by the prioritization step. In this manner, the one or more parameters of the one ormore processes may be altered and/or optimized based on the POI(s) exhibiting the largest defectivityand/or defectivity that has the largest yield impact. As such, the results of the prioritization step indicatewhich POI(s) should be used to alter and/or optimize the one or more parameters of the one or moreprocesses to produce the largest improvements in yield.

This embodiment is, therefore, advantageous over other previously used methods and systems for alteringand/or optimizing processes because without guidance as to which POI(s) have the largest impact on yield,advantageous opportunities to optimize the processes with respect to yield and stability may not beidentified or made in a timely fashion thereby increasing time to market and reducing the efficiency ofprocess optimization.

Furthermore, although the process(es) that are altered and/or optimized in this step may include only theprocesses that were used to print the POI(s) in the design data on the wafer prior to detection of thedefects binned in the embodiments described herein, the one or more processes that are altered and/oroptimized may include any process(es) that are used to print other design data that also includes thePOI(s). For instance, if more than one design includes the POI(s), based on the prioritization and/or anyother results of the methods described herein, one or more processes used to print the more than onedesign may be altered and optimized to thereby increase the yield of devices fabricated with each of thedifferent designs.

In another embodiment, the method includes altering one or more parameters of a process performed onthe wafer or to be performed on the wafer based on the results of the binning step and/or any other resultsof any other step(s) of any method(s) described herein. The process may include any process known in theart such as CMP, deposition (electro-chemical deposition, atomic layer deposition, chemical vapordeposition, physical vapor deposition), lithography, etch, ion implantation, and cleaning. The one or moreparameters may be altered based on the results of the binning such that defects binned in one or moregroups may be reduced on the wafer after subsequent processing of the wafer or may be reduced on otherwafers after processing of the other wafers. 137

For example, if an etch process was performed on the wafer prior to inspection, one or more parametersof the etch process may be altered using a feedback control technique preferably such that other wafersprocessed in the etch process with the altered parameter(s) will exhibit fewer defects in one or more of thegroups, fewer defects with relatively high DCIs, fewer defects with relatively high KP values, etc., orsome combination thereof. Such altering of the parameter(s) may be performed based on prioritization ofthe groups of defects or other information described herein such as DCI and KP value. In this manner, theprocess may be altered based on the groups of defects that have the greatest impact on yield.

In another example, if an etch process was performed on the wafer prior to inspection, one or moreparameters of a post-etch process to be performed on the wafer may be altered using a feed forwardcontrol technique preferably such that after the post-etch process is performed on the wafer with thealtered parameter(s), the wafer will exhibit fewer defects in one or more of the groups, fewer defects withrelatively high DCIs, fewer defects with relatively high KP values, etc., or some combination thereof. Theparameter(s) of the post-etch process or other process(es) may also be altered as described further above.

Altering one or more parameter(s) of a process as described above may include determining how the oneor more parameter(s) should be altered and changing the values of the one or more parameter(s) in arecipe that will be used to perform the process. Such altering may be performed by the methods andsystems described herein, for example, by accessing the recipe in a fab database or in a storage mediumcoupled to a process tool that will perform the process and making the changes directly to the recipe.

Alternatively, altering one or more parameters of a process as described above may include determininghow the one or more parameters should be altered and sending the values of the one or more parametersto another method or system (e.g., a fab database or a processor coupled to a process tool that willperform the process) that can be used to alter the values of the one or more parameters in a recipe that willbe used to perform the process. The values of the one or more parameters that are to be altered may alsobe sent with other information such as the recipe identity, the process tool identity, an instruction to alterthe one or more parameters, etc., such that the process can be altered by the other method or system.

In one embodiment, the method includes altering a process for inspecting the wafer based on the results ofthe binning step. The process for inspecting the wafer may be altered in this embodiment based on any ofthe binning results described herein. In addition, any parameter(s) of the process for inspecting the wafermay be altered in this embodiment. For example, the one or more parameters of the process for inspectingthe wafer that may be altered based on the results of the binning step may include, but are not limited to, 138 the care areas (or alternatively the do not care areas), the sensitivity, the in-line binning process, theinspection area, which wafers are inspected, or some combination thereof. In one particular example, theresults of binning may indicate the number of defects included in one or more of the groups, and the careareas may be altered to include positions on the wafer corresponding to positions in design data space ofthe defects in group(s) including a relatively high number of defects. In another example, the process forinspecting the wafer may be altered to inspect more or differently based on the results of the binning step.The process for inspecting the wafer may also be altered based on any results of any of the step(s) of themethod(s) described herein.

As described herein, the defects may be detected by an inspection process. In one embodiment, themethod includes reviewing locations on the wafer at which one or more POIs in the design data areprinted, determining based on results of the reviewing step if defects should have been detected at thelocations of the one or more POIs, and altering the inspection process to improve one or more defectcapture rates. Reviewing the locations in this embodiment may be performed using any method or systemknown in the art. In this manner, reviewing the locations on the wafer may be performed at the locationsof the POIs to determine if defects were detected at the locations of the POIs. In one such embodiment,the method may include arbitrary pattern searching to identify locations of the one or more POIs in thedesign data and determining the locations of the one or more POI(s) on the wafer from the locations of theone or more POI(s) in the design data. Determining the locations of the POI(s) in this manner ma beperformed as described further herein.

In addition, in some such embodiments, the method may include displaying locations of the POIs withand without hits during the reviewing step to assist in review. As such, the results of the review may beused to determine where defects have occurred but have not been captured by the inspection system.Therefore, the POI(s) may be reviewed to find missed defects (or defects not captured) to know where toperform alteration or optimization of the inspection process.

Based on this information in addition to results of the review (e.g., one or more attributes of the defects,one or more attributes of the design data, etc.), one or more parameters of the inspection process such asoptics mode, collection angle, incident angle, etc. may be altered, preferably such that the defects arecaptured at the locations of the POIs at a higher rate in subsequent inspections. In this manner, the methodmay include setup tuning based on analysis of the defect capture rates in POIs. The one or moreparameters of the inspection process that are altered may be determined in any suitable manner such asusing a rules database. The one or more defect capture rates that may be improved in this embodiment 139 include defect capture rates for one or more defect types within one or more POIs. In a similar manner, the above-described embodiment for improving one or more defect capture rates may be performed by reviewing locations on the wafer corresponding to positions of one or more hot spots in the design instead of reviewing locations on the wafer at which the one or more POIs are printed.

Furthermore, if the above-described method is performed for more than one POI, the POIs may beprioritized as described further herein, and the inspection process may be altered to improve the defectcapture rates for the POIs having the highest priority or higher priorities. In this manner, the inspectionprocess may be optimized for the highest priority POI or the higher priority POIs (although suchoptimization may also result in optimization of the inspection process for lower priority POIs).

In another embodiment, the method includes altering a process for inspection of the wafer during theinspection based on results of the inspection. In this manner, the method may include altering theinspection process using an in-situ process control technique. The results of the inspection that are used toalter the inspection process may include any of the results described herein. In addition, altering theinspection process in this embodiment may include altering any one or more parameters of the inspectionprocess.

As described further above, the method may include optimizing an inspection recipe. The inspectionrecipe that is optimized may include an inline inspection recipe and/or an electrical inspection recipe. Inone embodiment, the method includes altering a process for inspecting the wafer based on hot spotinformation. In another embodiment, the method includes generating a process for inspecting the waferbased on the hot spot information and the design data. In addition, the method may include altering orgenerating a process for inspecting a wafer based on hot spot information and/or predicted POI. Forexample, the inspection recipe may be configured such that only locations of hot spots and POI areinspected and/or such that locations for systematic nuisance defects are not inspected or such that dataacquired at such locations is otherwise suppressed. In another example, as described above, the methodembodiments described herein may include identifying hot spots in a design (e.g., based on systematicdefects). In this manner, the method embodiments may be a source of hot spots, and the locations of thehot spots in the design may be used to alter an inspection process using a feedforward control technique.

The method may also include altering the process for inspecting the wafer based on any other availableinformation. In one such example, the method may include altering the recipe based on hot spotinformation in addition to the design data, the inspection results, and one or more bitmaps. In this manner, 140 any information available to the method may be used to optimize the sensitivity of the inspection recipe for detecting defects that will or may affect yield while reducing the sensitivity of the inspection recipe for detecting defects that will not affect yield. Generating and optimizing an inspection recipe may also be performed as described further herein (e.g., based on the detectability of the DOI).

In some embodiments, the method includes determining a sensitivity for detecting the defects on thewafer based on the design data. In some such embodiments, the sensitivity is different for at least twodifferent portions of the wafer corresponding to at least two different portions of the design data. Inaddition, the method may include identifying "care areas" (or "where to inspect areas") on the wafer.Inspection results may not be acquired in do not care areas, or defect detection may not be performed oninspection results acquired in the do not care areas. However, if data acquisition and defect detection areperformed in the do not care areas, before additional processing of the inspection results such as binningis performed, the method may include determining if the detected defects are located in care areas or donot care areas. If defects are located in do not care areas, then the additional processing may not beperformed for these defects. In this manner, pattern based binning may be restricted to sensitive areas inthe design data to optimize the throughput of the binning process. In another embodiment, after defectshave been grouped by common design data (e.g., pattern grouping or other context data), the groupinginformation may be used for improved counting, binning, monitoring, analysis, sampling, review, test, etc.as described further herein.

This embodiment of the method may or may not utilize hot spot information. For instance, based onknowledge about the design data, the method may include identifying portions of the design data that aremore critical to yield and/or are more susceptible to yield-reducing defects. In this manner, the sensitivityfor detecting defects in these portions of the design data may be higher than the sensitivity for detectingdefects in other portions of the design data. As such, during acquisition of the inspection data, the methodmay include aligning the inspection data to the design data, which may be performed as described furtherherein. The sensitivity of the inspection process may then be altered based on the position of theinspection data in design data space. In such embodiments, the sensitivity of the inspection process maybe altered in real-time. Additional examples of design driven inspection or measurement recipes areillustrated in U.S. Pat. No. 6,886,153 to Bevis and U.S. patent application Ser. No. 10/082,593 filed Feb.22, 2002 published as U.S. Patent Application Publication No. US 2003/0022401 by Hamamatsu et al.The methods described herein may include any step(s) described in this patent and this patent application. 141

In one embodiment, the method includes selecting at least some of the defects for review based on theresults of the binning step. For example, the results of the binning step may be used to determine which ofthe defects are most critical as described herein (e.g., by determining DCIs for the defects), and the mostcritical defects may be selected for review. In another example, the binning results may be used todetermine which of the defects are systematic defects as described further herein. In this manner, themethod may include review sampling from portions of the design data in which DOI tend to occur. Inaddition, information about which defects are systematic as well as information about whether or not thesystematic defects are visible to a review system such as a SEM and/or whether the systematic defects areyield relevant may be used to select at least some of the defects for review (e.g., such that only defectsthat are visible to the SEM are selected for review). Selecting the defects in this manner is particularlyadvantageous since re-locating the defects during review can be difficult and relatively time consumingparticularly if the review system spends a great deal of time looking for defects that are not actuallyvisible to the review system. Results of selecting the defects for review may include locations of theselected defects on the wafer and any other results of any of the step(s) of the method(s) described herein.

In another embodiment, the method includes generating a process for sampling the defects for reviewbased on the results of the binning step. Therefore, instead of or in addition to selecting the defects forreview, the method may include generating a process that can be used (by the method, another method, asystem configured to perform the method, or another system) for sampling the defects for review. Such aprocess may be used for sampling defects detected on multiple wafers for review and/or sampling defectsfor review performed by multiple review systems. The process for sampling may be generated based onthe results of the binning step such that defects detected in a portion of the design data corresponding to agroup of binned defects that includes a relatively large number of defects may be sampled more heavilythan defects detected in portions of the design data corresponding to groups of binned defects that includea relatively small number of defects. The process for sampling the defects for review may be generatedbased on the results of the binning step in combination with any other results of any step(s) of any of themethod(s) described herein such as DCIs for the defects, KP values for the defects, etc.

In another embodiment, the method includes generating a process for selecting defects for review basedon hot spot information. The process for selecting defects for review may be generated based on hot spotinformation as well as any other information available to the method. For example, the process forselecting defects for review may be generated based on the design data, one or more attributes of thedefects, one or more bitmaps, and hot spot information. Preferably, the process for selecting defects forreview is generated such that certain types of defects such as defects detected at hot spots or systematic 142 defects are selected for review while other types of defects such as defects detected at cold spots and nuisance defects are not selected for review. In this manner, the methods described herein may produce a defect sample that largely includes defects that will or may affect yield while increasing the throughput of the review process by largely excluding defects from the review sample that will not affect yield.

In another embodiment, after defects have been binned by at least similar design data as described above,the method may include using the results of binning for the purpose of creating a more "informed" reviewsample for CDSEM, optical, or other forms of physical defect review and classification or verification. Inone such embodiment, the method includes generating a pattern group pareto chart such as that describedabove that illustrates pattern group identities on the x axis and the number of defects detected in eachpattern group on the y axis. In this manner, the chart shows the number of defects detected in differentpatterns. However, any other data that indicates the number of defects detected in different patterns maybe used in the method steps described herein. The embodiments described herein may also includegenerating electrical, systematic, and/or random pareto charts.

The method may include analyzing data for one or more of the different patterns illustrated in this chart todetermine one or more physical defect types that were detected in each pattern type. More than one defecttype may be detected in a pattern group. The method may also include analyzing data for one or more ofthe different spatial signatures illustrated in this chart to determine one or more attributes of the defectsbinned into one or more groups corresponding to the one or more different signatures. The defectattribute(s) may include, but are not limited to, size, die location (or die identity), and any other attributesknown in the art. The die location indicates whether a pattern has a higher frequency of occurrence on aparticular location, zone, or region of the wafer such as the edge, the center, the 3 o'clock position, etc. A defect sampling plan may be determined from the results of the analyzing steps described above. Forinstance, the method may include determining if a strong signal emerges from the analyzing stepsdescribed above. This strong signal indicates which defects (e.g., from which pattern and which defecttype and/or attributes determined by the analyzing steps) should be sampled in a higher proportion or alower proportion. The sampling plans described above may be particularly useful for increasing thethroughput of otherwise relatively slow review systems such as electron beam based review systems andatomic force microscope (AFM) or other scanning probe microscope based review systems.

The methods described herein may also be used to optimize a review recipe. For example, in oneembodiment, the method includes altering a process for reviewing defects on the wafer based on hot spot 143 information and optionally any other information available to the method. The parameters of the reviewrecipe that are altered or selected based on this information may include any data acquisition parametersand any data processing parameters of the review process. The method may also include selectingadditional parameters of the review process such as type of review system (e.g., optical or electron beam)to be used to review the defects and make and model of the review system to be used to review thedefects.

The method may also include providing information to the review system that can be used to assist indetermining the locations on the wafer at which review is to be performed. For instance, the positions ofthe defects to be reviewed may be reported to the review system in design data space, die space, and/orwafer space. In addition, other information about the defects and/or the defect positions may be providedto the review system. For instance, images or overlays of the defects generated by inline inspection inaddition to portions of the design data corresponding to the defect positions may be provided to thereview system. In this manner, the review system may use some or all of this information to find thelocations of the selected defects on the wafer during review. In addition, the results of one or more stepsof one or more methods described herein may be provided to the review system such that the reviewsystem can use the results to perform automatic defect locating (ADL) based on edge placement error.Furthermore, the method may include determining where to measure or test for review based on results ofinspection and systematic identity (perhaps with yield relevancy and/or process window mapping).Review may also include user-assisted review, which may be performed using methods and systems suchas those disclosed by Teh et al., in commonly assigned U.S. patent application Ser. No. 11/249,144 filedOct. 12, 2005 published as U.S. Patent Application Publication No, 2006/0082763 on Apr. 20, 2006.Therefore, a use case for the binning methods (and methods for assigning a classification to a defectdescribed further herein) includes systematic discovery and user-assisted review.

In one embodiment, the method includes altering a metrology process for the wafer based on the results ofthe binning step. For example, the metrology process may be altered such that the most critical defects asdetermined from the results of the binning step are measured during the metrology process. Therefore,altering the metrology process may include altering the locations on the wafer at which the measurementsare performed during the metrology process. In addition, results of inspection and/or review such as BFimages and/or SEM images of the defects selected for measurement may be provided to the metrologysystem such that the results may be used to determine where the measurements are to be performed. Forexample, the metrology process may include generating an image of an approximate location of the defecton the wafer, and this image may be compared to the results of inspection and/or review for the defect 144 such that the metrology system can correct the position on the wafer if necessary such that themeasurements are performed at the correct wafer locations and therefore on the correct defects. In thismanner, the measurements may be performed at substantially accurate locations on the wafer. Altering themetrology process may also include altering any other one or more parameters of the metrology processsuch as the type(s) of measurements performed, wavelength(s) at which the measurements are performed,angle(s) at which the measurements are performed, etc., or some combination thereof. The metrologyprocess may include any suitable metrology process known in the art such as a CD measurementmetrology process.

In another embodiment, the method includes altering a sampling plan for a metrology process for thewafer based on the results of the binning step. Therefore, the method may include adaptive sampling. Forexample, the sampling plan for the metrology process may be altered such that a greater number of themost critical defects as determined from the results of the binning step are measured during the metrologyprocess. In this manner, the most critical defects may be sampled more heavily during the metrologyprocess thereby advantageously producing larger amounts of information about the most critical defects.The metrology process may include any metrology process known in the art. In addition, the metrologyprocess may be performed by any suitable metrology system known in the art such as a SEM.Furthermore, the metrology process may include performing any suitable measurements known in the artof any suitable attributes of defects or features formed on the wafer such as profile, thickness, CD, etc.

In a similar manner, the method may include altering a process for analyzing defects (e.g., metrology orcomposition analysis) or repairing defects on the wafer based on hot spot information and optionally anyother information available to the method. For example, the method may include altering a process suchas electron dispersive x-ray spectroscopy (EDS or EX) for analyzing the composition of defects or a FIBprocess for repairing defects or for FA. The process for analyzing or repairing defects may be altered asdescribed herein with respect to altering other processes. For example, the analysis or repair process maybe altered such that the analysis and/or repair is performed only at the locations of selected defects, whichmay be selected as described herein. In addition, one or more parameters of the analysis or repair processmay be selected and altered based on results of any of the step(s) of any of the method(s) described herein.Such results may include, for example, defect classification, defect root cause, defect size, defectcriticality (which may indicate the accuracy with which analysis and/or repair should be performed), yieldimpact, one or more attributes of the design data proximate the defects (such as dimensions of features,density of features, hierarchy, redundancy, etc.), which may indicate if analysis and/or repair should beperformed and the accuracy with which analysis and/or repair should be performed, etc. Additional 145 examples of methods and systems for generating a recipe for a metrology tool are illustrated in U.S. Pat.

No. 6,581,193 to McGhee et al. The methods and systems described herein may be configured to perform any additional step(s) described in this patent.

In some embodiments, the method includes determining a root cause of the defects based on one or moreattributes of the design data. In another embodiment, the method includes determining a root cause of oneor more groups into which defects were binned. For example, in one embodiment, the method includesdetermining a root cause of one or more of the groups of defects based on results of review of at leastsome of the defects in the one or more groups, one or more attributes of the design data, one or moreattributes of the defects, or some combination thereof. In this manner, the method may includedetermining a root cause of defects individually or collectively as a group. The root cause of a defect or agroup of defects may also be determined based on analysis results from diagnostic systems such as anEDS system that can be used to analyze a defect, for example, by measuring a composition of the defect.One example of such an EDS system is illustrated in U.S. Pat. No. 6,777,676 to Wang et al.

The root cause phase may include identifying the source, the cause, and/or the correction for systematicdefects. The root cause phase may be performed in multi-source space using a correlation between any ofthe design, wafer, reticle, test, and process spaces. For example, in one embodiment, the method includesdetermining a root cause of one or more of the groups of defects by mapping at least some of the defectsin the one or more groups to experimental process window results. The experimental process windowresults may be generated by the method, by another method, by a system configured to perform themethod, or by a system other than a system configured to perform the method. In addition, theexperimental process window results may be acquired using a PWQ method or any other suitableexperiment (e.g., performing an etch process on different wafers with one or more different parameters)and detecting defects on the wafers after the PWQ method or other experiment. The experimental processwindow results may include any results acquired by inspection and/or by review of the defects detectedon the wafers. For example, the experimental process window results may include images of the defects,portions of design data proximate the positions of the defects in design data space, positions of the defectsin design data space, which may be determined as described herein, or any other inspection and/or defectreview results described herein.

Mapping at least some of the defects to the experimental process window results may be performed usingthe results of the inspection process. For instance, if the experimental process window results include theportions of the design data proximate the positions of the defects in design data space and images of the 146 defects on the wafer, mapping the defects to the experimental process window results may includecomparing images of defects binned into one or more of the groups to the images in the experimentalprocess window results for defects detected proximate design data that is at least similar to the design dataproximate to positions of the binned defects in design data space. In another example, if the experimentalprocess window results include positions of the defects in design data space, mapping the binned defectsto the experimental process window results in this embodiment may include comparing the positions ofthe defects in design data space in the experimental process window results to the positions of the binneddefects in design data space.

In this manner, the results of the mapping step may indicate where in process window space a process,which was performed on the wafer prior to detection of the defects, was performed. In particular, if resultsof the mapping indicate that a binned defect and a defect included the experimental process windowresults are at least similar and are located proximate to at least similar design data, the values of one ormore parameters within the process window at which the defect included in the experimental processwindow results was detected may be correlated to the binned defect and may be determined as the rootcause of the binned defect or may be used to determine the root cause of the binned defect.

In another embodiment, the method includes determining a root cause of one or more of the groups ofdefects by mapping at least some of the defects in the one or more groups to simulated process windowresults. The simulated process window results may include results similar to the experimental processwindow results described above. However, the simulated process window results are acquired bysimulating images that illustrate how the design data would be printed on a wafer at various values of oneor more parameters of the process, not by performing an experiment on a physical wafer. The processmay include any process involved in fabrication of a device corresponding to the design data. Forexample, this embodiment may include modeling a patterning process (e.g., lithography or etch) about asystematic defect location, and results of such modeling may be used to determine a root cause of thesystematic defect. The simulated process window results may be generated using any suitable method orsystem known in the art. For example, the simulated process window results may be generated by thePROLITH software that is commercially available from KLA-Tencor. In addition, the simulated processwindow results may be generated by the method, by another method, by a system configured to performthe method, or by a system other than a system configured to perform the method. Determining the rootcause in this embodiment may be performed as described above with respect to the experimental processwindow results. 147

The root cause phase may include determining the source and/or correction for systematic defects. Onepossible source for systematic defects is a process window shift. In addition, knowledge of the hot spotsignature may provide information about where the process is operating within the process window. Theroot cause phase may also include determining the most significant opportunities for improving theprocess to expand the process window. Furthermore, the root cause phase may include determining themost significant systematic issues for improving the reticle design. The root cause phase may furtherinclude determining the most significant systematic issues for improving and/or implementing nextgeneration technology.

In some embodiments, the method includes determining a percentage of a die formed on the waferimpacted by one or more of the groups of defects. For instance, the percentage may be determined bydetermining the number of inspected die on the wafer in which the defects in a group were detected atleast once and dividing the number of inspected die in which the defects in the group were detected atleast once by the total number of inspected die. The number of inspected die on the wafer in which thedefects in a group were detected at least once may be determined based on the design data space positionsof the defects, the design data space positions of the dies printed on the wafer, and information about theinspection process used to detect the defects. The results of these steps may be multiplied by 100 to arriveat the percentage. In one particular example, if there are 300 defects binned into a group, the defects inthis group are located in 5 die on the wafer, and there are 6000 die on the wafer, the percentage may bedetermined as [(5)(100)]/(6000) or 0.083%. The percentage, therefore, reflects the die impact marginalityfor the group of defects. Such a percentage may be determined for more than one group of defects, andeach (or at least some) of the percentages may be displayed in a chart such as a bar chart that may begenerated by the method. Therefore, the chart illustrates die impact marginality as a function of group intowhich defects were binned. Such a chart may be illustrated in a user interface, which may be configuredas described further herein. The method may also include prioritizing one or more groups of the defectsbased on the percentage determined in this embodiment. Such prioritizing may be performed as describedfurther herein, and the results of such prioritizing may be used as described further herein.

In another embodiment, the method includes determining one or more POIs in the design datacorresponding to at least one of the groups and determining a ratio of number of the defects binned in theat least one of the groups corresponding to the one or more POIs to number of locations of the one ormore POIs on the wafer. The one or more POIs in the design data corresponding to at least one of thegroups may be determined as described further herein. If all instances of the one or more POIs on thewafer are not inspected during the inspection process used to detect the defects, the number of locations 148 of the one or more POIs on the wafer used in this embodiment may be the number of inspected locationsof the one or more POIs on the wafer. In this manner, the method may include performing marginalityanalysis by determining the ratio or percentage of the POI in which defects were detected on the wafercompared to the number of the locations of the POI printed on the wafer (or the number of the inspectedlocations of the POI on the wafer). In such embodiments, the number of the locations of the POI on thewafer may be identified by arbitrary pattern searching. In addition, the number of the inspected locationsof the POI on the wafer may be identified by arbitrary pattern searching and using results of the arbitrarypattern searching and information about the inspection process to determine the number of inspectedlocations of the POI on the wafer. In addition, the methods described herein may include arbitrary patternsearching to identify locations of the POI on the wafer and to determine the area of the POI. The area ofthe POI and the number of locations of the POI on the wafer (or the number of inspected locations of thePOI on the wafer) may then be used to determine a defect density by POI. The method may also includeprioritizing the one or more POI(s) based on the ratios determined in this embodiment. Such prioritizingmay be performed as described further herein, and the results of such prioritizing may be used asdescribed herein.

In an additional embodiment, the method includes determining one or more POIs in the design datacorresponding to at least one of the groups and determining a ratio of number of the defects binned in theat least one of the groups corresponding to the one or more POIs to number of locations of the one ormore POIs in the design data (or number of inspected locations of the one or more POIs in the design dataif all locations of the one or more POIs in the design data are not inspected during the inspection processused to detect the defects). In this manner, the method may include performing marginality analysis bydetermining the ratio or percentage of the number of defects in a group corresponding to a POI comparedto the number of locations of the POI in the design (or the number of inspected locations of the POI in thedesign). In such embodiments, the number of locations of the POI in the design data may be identified byarbitrary pattern searching. In addition, the number of inspected locations of the POI in the design datamay be determined as described above. The one or more POIs corresponding to at least one of the groupsmay be determined as described further herein. This method may also include prioritizing one or more ofthe POI(s) based on the ratios determined in this embodiment. Such prioritizing may be performed asdescribed further herein, and results of such prioritizing may be used as described herein.

In a further embodiment, the method includes determining a POI in the design data corresponding to atleast one of the groups, determining a percentage of a die formed on the wafer in which the defects binnedin the at least one of the groups are located, and assigning a priority to the POI based on the percentage. 149

In this manner, the method may include performing marginality analysis based on a percentage of the dieimpacted by the defects. For example, the number of defects binned in a group may be divided by thenumber of design instances of the POI on a reticle used to print the design data on the wafer and thenumber of times the reticle is printed on the wafer. The result of this step may be multiplied by 100 toarrive at the percentage. In one particular example, if there are 300 defects binned in a group, 2000 designinstances of the POI corresponding to the group on the reticle, and the reticle is printed on the wafer 1000times, the percentage of the die formed on the wafer in which the defects binned in the group are locatedis equal to [(300)(100)]/[12000)(1000)] or 0.015%, which is essentially the wafer-based marginality forthis group of defects.

In this manner, the method may include prioritizing systematic defects by number of inspected die on thewafer in which the defects were detected at least once. For instance, a higher priority may be assigned toPOIs if systematic defects appeared on 10% of the design instances of the POI in a die versus 1% of thedesign instances of the POT in the die. In another example, the groups of defects that are detected in alarger number of the die on the wafer may be assigned a higher priority than groups of defects that weredetected in a lower number of die on the wafer. In addition, the method may include generating a chartsuch as a bar chart illustrating the percentage of a die formed on the wafer in which the defects binned indifferent groups are located. Therefore, such a chart graphically illustrates the die-based marginality fordifferent groups of defects. Such a chart may be displayed in a user interface, which may be configured asdescribed herein. The results of such prioritizing may be used as described herein.

In still another embodiment, the method includes prioritizing one or more of the groups by number oftotal design instances on the wafer at which the defects in the one or more of the groups are detected. Thenumber of total design instances on the wafer used in this embodiment may be the number of totalinspected design instances on the wafer if all of the design instances on the wafer are not inspected duringthe inspection process used to detect the defects. In this manner, the method may include prioritizingknown systematic defects by number of total design instances (or number of total inspected designinstances) on the wafer. As such, the method may include prioritizing known systematic defects based onwafer-based marginality. For instance, the groups of defects that are detected at a larger number of thedesign instances on the wafer may be assigned a higher priority than groups of defects that are detected ata lower number of the design instances on the wafer. Such prioritizing may also be performed based onthe percentage of locations of design instances (or inspected design instances) on the wafer at which thedefects were detected. For example, the number of defects detected and binned into a group may bedivided by the total number of design instances (or total number of inspected design instances) on the 150 wafer. The results of this step may be multiplied by 100 to produce the percentage described above. Inaddition, the method may include generating a chart such as a bar chart illustrating the number of designinstances (or the number of inspected design instances) on the wafer at which different groups of defectswere detected. Such a chart may be displayed in a user interface, which may be configured as describedherein. Such prioritizing may be further performed as described herein, and results of such prioritizingmay be used as described herein.

In some embodiments, the method includes prioritizing one or more of the groups by number of designinstances on a reticle, used to print the design data on the wafer, at which the defects in the one or more ofthe groups are detected at least once. The number of design instances on the reticle used in thisembodiment may be the number of inspected design instances. In this manner, the method may includeprioritizing known systematic defects by number of design instances on the reticle at which the defectsare found at least once. For instance, the groups of defects that are detected at a larger number of thedesign instances on the reticle may be assigned a higher priority than groups of defects that were detectedat a lower number of design instances on the reticle. In addition, the method may include generating achart such as a bar chart illustrating the number of design instances on the reticle at which differentgroups of defects were detected. Such a chart may be displayed in a user interface, which may beconfigured as described herein. Such prioritizing may be further performed as described herein. Inaddition, the results of such prioritizing may be used as described herein.

In another embodiment, the method includes determining reticle-based marginality for one or more of thegroups based on number of locations on a reticle at which defects binned into the one or more of thegroups were detected and total number of portions of the design data printed on the reticle that are at leastsimilar to the portions of the design data proximate to the positions of the defects binned into the one ormore of the groups. The number of locations on the reticle used in this embodiment may include thenumber of inspected locations. For example, the reticle-based marginality may be determined by dividingthe number of locations in a stacked reticle map at which at least one defect in a group has been detectedby the total design instances on the reticle. The result of this step may be multiplied by 100 to produce apercentage of the locations of the design instances, corresponding to the group, at which the defects weredetected. In one particular example, if 300 defects are binned into a group, there are 2000 design instancesfor the POI corresponding to that group on the reticle, and the defects binned in the group are detected at50 different locations in the reticle (which may be determined from a stacked reticle map), then the reticlebased marginality for this group of defects would be equal to [(50)(100)]/(2000) or 2.5%. In addition, themethod may include generating a chart such as a bar chart illustrating the reticle-based marginality or 151 percentage of locations at which the defects in the different groups were detected. Such a chart may bedisplayed in a user interface, which may be configured as described further herein. The method may alsoinclude prioritizing one or more of the groups of defects based on the reticle-based marginalitydetermined for one or more of the groups. For instance, groups that exhibit relatively high reticle-basedmarginality may be assigned higher priorities than groups of defects that exhibit lower reticle-basedmarginality. Such prioritizing may be further performed as described herein, and the results of suchprioritizing may be used as described herein.

The steps of the embodiments described above may be performed for groups of defects as describedabove or for individual defects binned into the groups.

Each of the embodiments of the method described above may include any other step(s) of any method(s)described herein. In addition, each of the embodiments of method described above may be performed byany of the systems described herein.

As set forth in detail above, the method embodiments for binning defects may include determining a DCI.In addition, some methods may include determining a DCI for one or more defects detected on a waferand may or may not include binning the defects detected on the wafer. For example, one embodiment of acomputer-implemented method for determining a DCI for a defect detected on a wafer includesdetermining a probability that the defect will alter one or more electrical attributes of a device beingfabricated on the wafer based on one or more attributes of design data, for the device, proximate theposition of the defect in design data space. The probability that the defect will alter the one or moreelectrical attributes of the device may be a probability that the defect will alter one or more electricalparameters of the device and/or will kill a die for the device. The one or more attributes of the design datamay include any design data attribute(s) described herein. The probability may also be determined basedon the one or more attributes of the design data in combination with one or more attributes of the defect(e.g., defect size). In addition, the probability may be determined based on the attribute(s) of the designdata in combination with one or more attributes of the defects, a location of the defect reported by aninspection system used to detect the defect, and coordinate inaccuracy of the inspection system.

In one particular example, determining the probability may include determining one or more attributes ofthe design data such as a critical area for defects in the design data. In this manner, the critical area, thereported defect size, and the reported defect location can be used to determine the probability that thedefect will alter one or more electrical attributes of the device. For instance, as defect size increases and 152 pattern complexity increases, the probability that a defect will alter the one or more electrical attributes of the device also increases. Therefore, a relationship describing likelihood of kill or change in the one or more electrical attributes of the device as a function of defect size and pattern complexity may be used to determine the relative risk of each defect on each wafer.

In another example, the probability may be determined by using the design data proximate to the positionof the defect in design data space, a probability of the position of the defect in the design data, and thedefect size as input to a model to determine if the defect will alter one or more electrical attributes of thedevice. In this manner, the probability is a probability that a defect will alter one or more electricalattributes of the device if the defect is located in a particular spot in the design layout.

The method also includes determining the DCI for the defect based on the probability that the defect willalter the one or more electrical attributes of the device. For instance, the DCI may be an index whichcorrelates, at least roughly, to the probability. In one example, a higher DCI may be determined fordefects for which a relatively high probability has been determined. In other words, the DCI may indicatethat the criticality is higher for defects having a relatively high probability of altering one or moreelectrical attributes of the device. The DCI may be determined from the probability using any suitablemethod, algorithm, data structure, rules, etc., or some combination thereof that describes a relationshipbetween the DCI and the probability. The method described herein may include generating such a method,algorithm, data structure, rules, etc. using experimental results (e.g., results of inspection, metrology,review, test, or some combination thereof), simulation results, empirical data, information about thedesign, historical data, or some combination thereof. In addition, the DCI may have any suitable format(numeric, alphanumeric, text string, etc.). The DCI may be expressed in a manner such that a user caneasily understand the value of the DCI. For example, the DCI may be assigned a value between 1 and 10,with 10 being the highest DCI and 1 being the lowest DCI. The DCI may also or alternatively beexpressed in a manner such that a method or system such as one or more of the embodiments describedherein may utilize the DCI to perform one or more of the steps described herein.

The method further includes storing the DCI in a storage medium. In addition, the storing step mayinclude storing the DCI in addition to any other results of any method embodiments described herein. TheDCI may be stored in any manner known in the art. In addition, the storage medium may include anystorage medium described herein or any other suitable storage medium known in the art. After the DCIhas been stored, the DCI can be accessed in the storage medium and used by any of the method or systemembodiments described herein. Furthermore, it is noted that the DCI may be stored "permanently," "semi- 153 permanently," or temporarily for any period of time. In addition, storing the DCI may be performed in any other manner described herein.

In one embodiment, the defect for which the DCI is determined includes a random defect. In anotherembodiment, the defect for which the DCI is determined includes a systematic defect. In this manner, theDCI may be determined for both random and systematic defects. The defect may be determined as arandom defect or a systematic defect as described further herein. In addition, although the embodiment ofthe method is described above as including determining a DCI for a defect, it is to be understood that themethod may include determining a DCI for one defect, some defects, or all defects detected on a wafer.The defect(s) for which a DCI is determined in the method may be selected by a user. Alternatively, thedefect(s) for which a DCI is determined in the method may be selected by the method (e.g., based on oneor more attributes of the defect(s), one or more attributes of design data proximate to the position(s) of thedefect(s) in design data space, any other information about the defect(s) and/or the design data describedherein, or some combination thereof).

In some embodiments, the one or more electrical attributes include functionality of the device. In thismanner, the DCI may be determined based on a probability that the defect will cause the device to fail ornot function. In another embodiment, the one or more electrical attributes of the device include one ormore electrical parametrics of the device. In this manner, the DCI may be determined based on aprobability that the defect will alter one or more electrical parametrics of the device. As such, theprobability may be a probability that the defect will cause an electrical parametric issue. The electricalparametric issue may not qualify as an electrical defect in electrical testing, but may be an indication thatthe defect alters the electrical performance of the device and may begin to cause electrical defects overtime on other wafers if the defect persists. The electrical parametric(s) may include any electricalparametric(s) known in the art such as speed, drive current, signal integrity, and power distribution of thedevice.

In one embodiment, the one or more attributes of the design data include redundancy, net list, or somecombination thereof. In another embodiment, the one or more attributes of the design data includedimensions of features in the design data, density of features in the design data, or some combinationthereof. Such attributes may be used to determine the probability as described above. In an additionalembodiment, the one or more attributes of the design data include one or more attributes of the designdata for more than one design layer for the device. In this manner, the probability may be determinedbased on multi-layer context information for the defect, which may be advantageous if the defect affects 154 one or more layers of the design by being propagated through the device and since devices formed onwafers typically are formed of many layers. Therefore, a defect may alter the design data printed on morethan one layer of the device, and the alterations to any, some, or all of the layers may alter one or moreelectrical attributes of the device. As such, by using one or more attributes of the design data to determinethe probability, the probability may be determined based on how the defect may affect one or more layersof the device thereby possibly making the probability and the DCI determined therefrom more indicativeof potential parametric issues and more yield relevant.

In some embodiments, determining the probability includes determining the probability using acorrelation between electrical test results for the design data and the one or more attributes of the designdata. For example, the method may include performing data mining to determine if there is a correlationbetween one or more attributes of the design data and electrical test results. In particular, one or moreattributes of the design data such as line width, spacing, etc. printed on a wafer may be measured andelectrical test results for the wafer may be used to determine a correlation between the attribute(s) of thedesign data and the electrical test results. The electrical test results may include measurements of one ormore electrical attributes of one or more devices formed on the wafer or may be used to determine one ormore electrical attributes of the device(s). Therefore, the correlation may be determined as a correlationbetween one or more attributes of the design data and the one or more electrical attributes. The electricaltest results may include any appropriate electrical test results produced using any method or systemknown in the art. The defect may be identified as a random defect according to any of the embodimentsdescribed herein. Such a correlation may be used to determine the probability for both systematic andrandom defects. Using such a correlation to determine the probability may be advantageous since thecorrelation and one or more attributes of the design data located proximate to the position of a defect indesign data space may be used to determine the probability relatively quickly.

In another embodiment, determining the probability includes determining the probability based on the oneor more attributes of the design data in combination with a probability of the position of the defect withinthe design data space, a position of the defect reported by an inspection system used to detect the defect,coordinate inaccuracy of the inspection system, a size of the defect, defect size error of the inspectionsystem, or some combination thereof. In one such embodiment, the defect includes a random defect. Inthis manner, the defect size, the location of the defect reported by the inspection system, and coordinateinaccuracy of the inspection system may be used to determine the DCI for random defects. Using thedefect size, defect size error, reported defect location, and coordinate inaccuracy to determine the DCI asdescribed above may be advantageous since the size and location of random defects may be relatively 155 unpredictable. Therefore, using such information for determining the DCI may increase the accuracy of the DCI.

In an additional embodiment, determining the probability includes determining the probability based onthe one or more attributes of the design data in combination with one or more attributes of the defect. Inone such embodiment, the defect includes a systematic defect. In this manner, the systematic defectattributes may be used to determine the DCI for systematic defects. The defect may be identified as asystematic defect according to any of the embodiments described herein. The one or more attributes of asystematic defect may be used to determine the DCI for the defect since the positions of systematicdefects in design data space may be determined with relatively high accuracy in the embodimentsdescribed herein.

In one embodiment, determining the DCI includes determining the DCI for the defect based on theprobability in combination with a classification assigned to the defect. For example, the DCI may bedetermined based on the probability and then the DCI may be modified based on a defect classification toimprove the DCI. In one such example, if the defect classification indicates that a defect is a bridgingdefect, a DCI for the defect may be altered such that the altered DCI indicates a higher criticality for thedefect than the originally determined DCI. In a different example, if the defect classification indicates thata defect is a partial bridging defect, then the DCI determined for the defect may be altered such that thealtered DCI indicates a lower criticality for the defect than the originally determined DCI. Theclassification of the defect used in this embodiment may be determined or assigned to the defectaccording to any of the embodiments described herein or using any other method or system known in theart for classifying defects. In addition, the DCI may be modified using any other results of any step(s) ofany method(s) described herein (e.g., a KP value for the defect) or any other available information (e.g.,hot spot information).

In some embodiments, the method includes determining the design data proximate the position of thedefect in design data space by determining a position of inspection data in design data space, which maybe performed as described herein. In another embodiment, the method includes determining the designdata proximate the position of the defect in design data space by defect alignment, which may beperformed as described herein. In an additional embodiment, the method includes determining the designdata proximate the position of the defect based, at least in part, on a position of the defect reported by aninspection system used to detect the defect, coordinate inaccuracy of the inspection system, one or moreattributes of the design data, defect size, defect size error of the inspection system, or some combination 156 thereof, which may be performed as described further herein. In this manner, the design data proximate the position of the defect in design data space may be determined based, at least in part, on the reported location of the defect and the location at which the defect could be located within coordinate accuracy of the inspection system. The design data beyond the location at which the defect could be located may be determined in a similar manner.

In one embodiment, the method includes modifying the DCI based on sensitivity of yield of the designdata to defects. In this manner, the DCI may be modified based on sensitivity of yield impact within aregion (e.g., cell or functional block) in the design. For example, the method may include determining theposition of the defect in design data space, which may be performed as described herein, and the yieldsensitivity due to defects located at this position and/or due to defects in the design data proximate to thisposition may be determined. Such yield sensitivity may be determined using any of the embodimentsdescribed herein. For example, the method may include modeling electrical properties of a device beingfabricated using the design data about a position in design data space for different values of one or moreattributes of the design data, which may be selected based on how the one or more attributes may bealtered by defects. Such modeling may be performed as described herein, and the modeled electricalproperties may be used to determine how yield changes as the values of the one or more attributes of thedesign data change, which may be used to determine the yield sensitivity of the design data to defectslocated at the position and/or defects in the design data proximate to this position. In this manner, theposition of a defect in design data space may be used to determine the yield sensitivity of the design datato the defect. If the yield sensitivity of the design data to the defect is relatively high, then the DCI for thedefect may be modified such that the modified DCI indicates a higher criticality than the originallydetermined DCI. Likewise, if the yield sensitivity of the design data to the defect is relatively low, thenthe DCI for the defect may be modified such that the modified DCI indicates a lower criticality than theoriginally determined DCI.

As described further above, the DCI may be used in a number of ways in the embodiments describedherein. For example, in one embodiment, the method includes altering a process performed on the waferbased on the DCI determined for the defect. In one such embodiment, the process is a metrology processor involves one or more measurements on the wafer. In this manner, the method may include adapting ameasurement process based, at least in part, on the DCI. In another example, the process is a defectreview process. As such, the method may include adapting a defect review process based, at least in part,on the DCI. Altering the process as described above may include altering any one or more parameters ofthe process. In addition, such altering may be performed as described further herein. 157

In another embodiment, the method includes altering a process used to detect the defect based on the DCIdetermined for the defect. Altering the process used to detect the defect may include altering any one ormore parameters of the process such as those described further herein. In addition, altering the processused to detect the defect based on the DCI may be performed using a feedback control technique. In onesuch example, if the DCI for the defect indicates that the defect is relatively critical, then the process usedto detect the defect may be altered such that one or more locations on the wafer at which defectscorresponding to the defect for which the DCI was determined may potentially be located may beinspected with a sensitivity that is higher than the sensitivity previously used to inspect these locations.Other parameter(s) of the process may be altered in a similar manner.

In some embodiments, the method includes generating a process for inspection of additional wafers onwhich the device will be fabricated based on the DCI determined for the defect. In this manner, instead ofaltering a previously used process in which the defect was detected, the method may include generatingan entirely new inspection process. The new inspection process may be generated for any one or morelayers of the additional wafers. For example, the process may be generated for the layer on which thedefect for which a DCI was determined was detected. However, such an inspection process may also begenerated for one or more other layers of the additional wafers. For example, if the DCI for the defectindicates that the defect is relatively critical, then a process for inspecting a subsequently formed layer onthe wafer may be generated by selecting one or more parameters of the inspection process such that oneor more locations on the subsequently formed layer at which defects, which may be caused by the defectfor which the DCI was determined, may potentially be located may be inspected with relatively highsensitivity. Other parameter(s) of the process may be selected in a similar manner. Generating the processfor inspecting the additional wafers may also be performed as described further herein.

In one embodiment, the computer-implemented method for determining the DCI is performed by aninspection system used to detect the defect. In this manner, the method may be performed on-tool. Inanother embodiment, the computer-implemented method for determining the DCI is performed by asystem other than an inspection system used to detect the defect. As such, the method may be performedoff-tool. The system used to perform the method of-tool may be configured as described further herein.

The DCI for the defects may be used in a number of ways in the embodiments described herein such asfor sampling in which defects are selected for review. For example, for each group into which defectswere binned, DCI may be used for sampling instead of performing random sampling of the grouped 158 defects. In addition, the DCI determined for the defects may be used to determine which defects have a higher probability of altering the one or more electrical attributes of the device, and defects that have a

higher probability of altering the one or more electrical attributes may be more heavily sampled. The DCI may be used to sample not only systematic defects but also random defects.

Each of the embodiments of the method for determining a DCI described above may include any otherstep(s) of any method(s) described herein. In addition, each of the embodiments of the method fordetermining a DCI described above may be performed by any system embodiments described herein.

Another embodiment relates to a computer-implemented method for determining a memory repair index(MRI) for a memory bank formed on a wafer, A memory die includes memory banks (often manymemory banks). Each memory bank includes an array block area (or a raw area) and a redundancy area.The redundancy area includes a number of rows and a number of columns and is used to repair thememory bank. The numbers of rows and columns included in the memory bank may be user-defined. Thearray block area may be generally square or rectangular in shape. The redundant rows may be formedalong one side of the array block area, and the redundant columns may be formed along another, adjacentside of the array block area. The memory bank may also include row decoders adjacent to the redundantrows, column decoders adjacent to the redundant columns, and sense amps adjacent to the columndecoders. The method may also include determining the locations of redundant rows and columns, senseamps, and decoders for each array block area. Such locations may be determined using any method orsystem known in the art.

The method includes determining a number of redundant rows and a number of redundant columnsrequired to repair the memory bank based on defects located in the array block area of the memory bank.For example, in some embodiments, the method includes determining which of the defects located in thearray block area will cause bits in the memory bank to fail and determining positions of the bits that willfail based on locations of the defects that will cause the bits to fail. Alternatively, the method may includedetermining which defects in the array block area may cause bits in the memory bank to fail anddetermining the positions of the bits that may fail based on the locations of the defects that may cause thebits to fail. Determining which of the defects in the array block area will or may cause bits to fail may beperformed using one or more attributes of the defects, which may include any of the defect attribute(s)described herein, and/or results of one or more other step(s) of any of the method(s) described herein. Forexample, a reported defect location, coordinate accuracy of an inspection system used to detect the defect,defect size, defect size inaccuracy of the inspection system, possibly in combination with a DCI for the 159 defect, which can be determined as described herein, and possibly in further combination with correlated inspection and/or electrical test results for the memory bank may be used to determine if the defect will or may cause a bit failure.

In one such embodiment, determining the number of the redundant rows and the number of the redundantcolumns required to repair the memory bank is performed using the positions of the bits that will fail.This step may alternatively be performed using the positions of the bits that may fail. For example,individual failing bits are not necessarily replaced on a one-to-one basis with redundant rows and columns.Instead, if individual failing bits are "adjacent" to each other along the same logical row or column, thenthat entire row or column becomes a candidate for replacement by an available redundant row or column.Therefore, the positions of the bits that will or may fail may be used to determine which failing bits are"adjacent" to each other along the same logical row or column, which can be used to determine thenumber of redundant rows and columns needed to repair the memory bank. In this manner, the methodmay include predictive bit fail estimation, which can be used to determine and/or monitor the amount ofredundancy that will be consumed by the failed bits.

In addition, although two memory bits may be physically adjacent to each other in the layout, they maybelong to a different logical row or column. In other words, physical adjacency may not correlate withlogical or electrical adjacency. For example, if logical Row 1 includes 256 bits, those 256 bits are notnecessarily next to each other in the physical layout of the bank or segment. As such, physical (ortopological) addresses may be converted to logical (or electrical) addresses through a mapping functionthat may be different for each device. Such mapping may be performed using any suitable method orsystem known in the art. For example, Klarity Bitmap, which is commercially available from KLA-Tencor, provides a graphical or otherwise easy way to create the topological-to-electrical mapping.Therefore, using such a mapping function in this method may allow determination of an MRI thataccurately reflects the repairability of the memory bank.

The defects that are located in the array block area may be identified in or from results of inspection ofthe memory bank. For example, the inspection may detect defects in both the array block area and theredundancy areas (or across the entire memory bank), and the defects may be separated into defects in thearray block area and defects in the redundancy areas based on locations of the defects, which may bedetermined according to any of the embodiments described herein. Separating the defects in the arrayblock area, redundancy areas, decoder areas, and sense amp areas provides enhanced value for theinspection results since such separation can be used to separate the repairable defects from the non- 160 repairable defects. In addition, separation of the defects into defects in the raw, redundancy, decoder, and sense amp areas can be rule-based or region-based.

The method also includes comparing the number of the redundant rows required to repair the memorybank to an amount of available redundant rows for the memory bank. In addition, the method includescomparing the number of the redundant columns required to repair the memory bank to an amount ofavailable redundant columns for the memory bank. In some embodiments, comparing the number of theredundant rows is performed separately for each bank of a memory die, and comparing the number of theredundant columns is performed separately for each bank of the memory die. Comparing the number ofthe redundant rows and comparing the number of the redundant columns may be performed in anysuitable manner.

In another embodiment, the method includes determining the amount of the available redundant rows andthe amount of the available redundant columns based on defects located in the redundant rows and theredundant columns of the memory bank. Defects located in the redundant rows and columns may beidentified as described above. Determining the amount of available redundancy as described above maybe advantageous since if the redundancy is sufficiently defective, then a memory bank failure may occur.In addition, if the redundancy is partially defective, the amount of redundancy available for repair of thememory bank is reduced, and if the number of fails exceeds the amount of non-defective redundancy,then a memory bank may not be repairable. The amount of available redundancy may also be determinedfor individual memory banks within a die since as described further above, each bank has its own set ofredundant rows and columns, and failing bits in each bank can only be replaced by available redundantrows or columns in the same bank.

The amount of available redundancy may also be determined based on the defects located in theredundancy area and one or more attributes of the defects located in the redundancy area. The one ormore attribute(s) used in this step may include any of the defect attribute(s) described herein. Determiningthe available redundancy may also or alternatively be performed using any results of any step(s) of anymethod(s) described herein. For example, a reported defect size of a defect in the redundancy area,coordinate accuracy of an inspection system used to detect the defect, and a classification assigned to thedefect may be used to determine if the defect will cause a failure in the redundancy area, which may beused to determine the amount of available redundancy. 161

The method further includes determining the MRI for the memory bank based on results of comparing thenumber of the redundant rows and comparing the number of the redundant columns. The MRI indicates ifthe memory bank is repairable. For example, if the number of the redundant rows and/or columns neededto repair the failed bits is larger than the number of available redundant rows and/or columns, then thememory bank is not repairable and the die is not repairable. The MRI may be determined based on such acomparison and assigned a value that indicates whether or not the memory bank is repairable. Forexample, the MRI may be assigned a first value if the memory bank is repairable, and the MRI may beassigned a second value if the memory bank is not repairable. The different values for the MRI may beexpressed in any suitable format (e.g., such that the values are easily comprehended by a user and/or suchthat the values can be used by the method embodiments described herein). Suitable formats include, butare not limited to, numeric, alphanumeric, text string, etc.

The method also includes storing the MRI in a storage medium. The storing step may include storing theMRI in addition to any other results of any method embodiment(s) described herein. The MRI may bestored in any manner known in the art. In addition, the storage medium may include any storage mediumdescribed herein or any other suitable storage medium known in the art. After the MRI has been stored,the MRI can be accessed in the storage medium and used by any of the method or system embodiments asdescribed herein. Furthermore, the MRI may be stored "permanently," "semi-permanently," ortemporarily for any period of time. Storing the MRI may also or alternatively be performed as describedherein.

The method embodiments described above, therefore, can be used for early detection of memory lossusing the MRI, which is advantageous for a number of reasons and can be used in a number of manners.For example, in one embodiment, the method includes determining the MRI for more than one memorybank formed in a die and predicting a repair yield for the die based on the MRIs for the more than onememory bank. Predicting the repair yield for a die based on the MRIs determined for the memory banksin the die is advantageous since each bank or segment of the die has a corresponding set of redundantrows and columns available for repair. The bits that fail in a particular bank or segment can only bereplaced by available corresponding redundant rows or columns. Therefore, it is possible for one bank to"run out" of redundancy while other banks in the die have available redundancy. In this case, the die is nolonger fully repairable because at least one bank or segment is not repairable. As such, based on the MRIsfor memory banks in the die, the method may determine yield of a repair process performed on the die. Inaddition, an MRI may be determined for the die, which indicates if the die is repairable, based on theMRIs determined for the memory banks in the die. For example, if the MRIs for the memory banks 162 indicate that any of the memory banks are not repairable, then the MRI may be determined to be a value that indicates that the memory die is not repairable.

In another embodiment, the method includes determining the MRI for each memory bank in one or moredies on the wafer and determining a memory yield for the one or more dies based on the MRIs for eachmemory bank. These steps may be performed as described above. This embodiment of the method may beused to determine the die-to-die memory yield. In addition, the memory yield for the one or more diesmay be used to determine a memory yield for the wafer.

In another embodiment, the method includes combining the memory yield prediction with a yieldprediction outside the memory to determine a total yield prediction.

In an additional embodiment, the method includes performing wafer disposition based, at least in part, onthe one or more memory yields for the one or more dies on the wafer. For example, the methodsdescribed herein can be used to perform in-line disposition of wafers thereby allowing better (e.g., moreefficient) WIP planning and reduction of production costs. For example, the number of dies having amemory yield below some predetermined threshold may be determined and used to determine if repairshould be performed on the wafer, if the wafer should be reworked, if the wafer should be scrapped, etc.

In such an example, the number of dies having a memory yield below the predetermined threshold may becompared to another predetermined threshold, and both thresholds may be selected to represent theminimum wafer-based yield that is needed to determine if repair should be performed on the wafer. Forexample, the thresholds may be selected (e.g., by a user or by one or more embodiments described herein)to correspond to the minimum memory yield at which the estimated value of the wafer does not exceedthe cost of completing the wafer. In another example, the method may include determining a memoryyield for the wafer based on memory yields for one or more dies on the wafer. Therefore, the memoryyield may be the yield after a memory repair process, if that process is performed on the one or more dieson the wafer. The memory yield for the wafer may be used to disposition the wafer as described above.For example, the value of the wafer after the memory repair process may be determined based at least inpart on the memory yield, and this value may be compared to the cost of completing the wafer todetermine if the wafer should be scrapped.

In one embodiment, comparing the number of the redundant rows includes determining a fraction of theredundant rows needed to repair the memory bank, comparing the number of the redundant columnsincludes determining a fraction of the redundant columns needed to repair the memory bank, and 163 determining the MRI for the memory bank includes determining the MRI based on the fraction of the redundant rows and the fraction of the redundant columns.

Methods that include determining the MRI based on the fractions described above may include any othersteps described herein. For example, in one such embodiment, the method includes determining the MRIfor each memory bank in one or more dies on the wafer and determining a memory yield for the one ormore dies based on the MRIs for each memory bank. The steps of this embodiment may be performed asdescribed further herein. In another example, in another such embodiment, the method includesdetermining the MRI for each memory bank in one or more dies on the wafer, determining a memoryyield for the one or more dies based on the MRIs for each memory bank, and determining a memory yieldfor the wafer based on the memory repair yields for each of the one or more dies. The steps of thisembodiment may be performed as described further herein. In this manner, the method may include usingthe MRI to predict memory yield on a wafer to wafer basis. In a similar manner, the MRI may bedetermined for each die on a wafer, and the MRI for each die may be used to determine a wafer-basedmemory yield. For example, the wafer-based memory yield may be determined by dividing a sum of theMRIs for each die on the wafer by the number of die on the wafer to determine the fraction of dies on thewafer that are good or repairable with respect to its memory. The fraction of dies on the wafer that aregood or can be repaired may be used possibly in combination with information about the repair processsuch as historical yield or success rate to better predict the memory yield for the repair process performedon the wafer.

In some embodiments, the MRI also indicates a probability that the memory bank will not be repairable.In this manner, the MRI may indicate whether or not the memory bank is repairable and how likely thattee memory bank is not repairable. The probability that a memory bank is not repairable may bedetermined based on comparing the number of the available redundant rows to the number of redundantrows needed for repair and comparing the number of the available redundant columns to the number ofredundant rows needed for repair, which may be performed as described above, possibly in combinationwith one or more attributes of the defects, one or more attributes of the memory design, and one or moreattributes of the repair process. Such attributes may include, for example, historical success rates of therepair process performed in other memory banks that are at least similar by design to the memory bankfor which the probability is being determined. Such an MRI may be expressed as two values, oneindicating whether or not the memory bank is repairable and another indicating the probability that thememory bank is not repairable. Alternatively, the MRI may be expressed as a single value that indicates ifthe memory bank is repairable and the probability that the memory bank is not repairable. The two values 164 and the single value may be expressed in any of the formats described herein. In one such embodiment,the method includes determining the MRI for each memory bank in one or more dies on the wafer anddetermining a MRI for the one or more dies based on the MRI for each of the memory banks in the one ormore dies. These steps may be performed as described herein. In such an embodiment, the MRIs for theone or more dies indicate a probability that the one or more dies will not be repairable (since the MRI foreach memory bank indicates the probability that the memory banks will not be repairable and since therepairability of the dies are related to the repairability of the memory banks as described further above). Inone such embodiment, the method includes determining a wafer based memory yield prediction based onthresholding of the MRIs for the one or more dies on the wafer. Determining the wafer based memoryyield predication may be performed as described above, but will be the yield of the wafer not the yield ofthe repair process as described above.

In some embodiments, the method includes identifying non-repairable defects in the memory bank (e.g.,in the logic periphery of the memory bank) based on one or more defects located in a decoder area of thememory bank, one or more defects located in a sense amp area of the memory bank, or some combinationthereof. For example, inspection of the memory bank may be performed to detect defects in all areas ofthe memory bank (e.g., including the logic periphery, the decoder area, and the sense amp area), and thelocation of the defects within the memory bank, which may be determined according to any embodimentsdescribed herein, may be used to determine which area of the memory bank each or one or more of thedefects are located. The number of non-repairable defects in the memory bank may be determined based,at least in part, on the number of the defects detected and located in the decoder area and the sense amparea. The method may also include estimating the memory yield based at least in part on the non-repairable defects in the memory bank, which is advantageous since one non-repairable defect may killthe die.

In one embodiment, the method includes altering one or more parameters of an electrical test processbased on the MRI using a feed forward control technique. In another embodiment, the method includesaltering one or more parameters of an electrical test process based on the MRI using a feed forwardcontrol technique such that if the memory bank is not repairable, a die in which the memory bank islocated is not tested during the electrical test process. For example, memory testing takes a relatively longtime. Therefore, based on a prediction that a memory bank or a memory die is not repairable, which maybe determined as described above, that information may be fed to the prober or other memory test systemso that the affected, non-repairable die is skipped during the memory testing. In this manner, the amountof testing may be reduced thereby reducing the cost of memory testing. In addition, memory testing may 165 include open/short testing, functional testing, and electrical parametric testing. If such testing can beeliminated by using the methods described herein to determine which dies can be repaired, then thememory testing process can be performed in a much shorter period of time. Alternatively, the electricaltest process may be altered to collect more relevant test data for further FA on dies that cannot be repaired,and the testing may be focused at specific locations based on the predicted impact of various probablefailure mechanisms. Furthermore, memory repair may include using a laser or electrical means to blowfuses thereby re-routing decoders to the redundant rows and/or columns. Memory testing may beperformed after memory repair to verify the repair and to run further tests such as stress testing. Therefore,by determining which dies can be repaired as described herein, the memory repair and additional memorytesting may be performed for only the repairable dies and therefore in a much shorter period of time.

In some embodiments, the method includes altering one or more parameters of a repair process based onone or more attributes of the defects located in the array block area of the memory bank, the MRI, orsome combination thereof. For example, the memory repair process may be altered such that repair is notattempted on memory die that include memory banks determined to not be repairable. In addition, thememory repair process may be altered to increase the probability that repair will be successful. The one ormore parameters of the repair process that are altered in this embodiment may include any parameter(s) ofthe repair process.

In some embodiments, the defects include defects detected at a gate layer of the memory bank. In otherembodiments, the defects include defects detected at a metal layer of the memory bank. For example, inmemory fabrication, inspection may be performed at the gate layer and the metal layers. The methodsdescribed herein may be performed for defects detected at one or more of these layers. In addition,although most memory fabrication involves inspection at the gate and metal layers and the inspectionresults generated at the gate and metal layers are sufficient to predict the yield, inspection may also beperformed at the capacitor layer for bit repair. Therefore, inspection results generated at the gate, metal,and capacitor layers may be used to predict the yield as well. In addition, the embodiments describedherein may be performed for defects detected at the capacitance layer.

In one embodiment, the method includes predicting bit failure modes of the defects based on locations ofthe defects in the memory bank. In this manner, the locations of the defects can be used to predict bitfailure modes. Such information may be useful for determining the amount of redundancy needed torepair the memory bank. For example, defects in the p-MOS area of the memory bank will cause senseamp failure thereby consuming more redundancy than defects in the n-MOS area. One or more attributes 166 of the design data proximate the defects and/or one or more defect attributes (e.g. size) of the defects mayalso be used to enhance the prediction of bit failure modes. In addition to assisting the prediction ofredundancy needed for repair or if the memory in the die will yield, prediction of the mode of failure mayresult in faster or better identification of the defect(s) causing the bit failure(s). Early prediction mayallow the DOI to be identified and reviewed, which is impossible without FA if the bit failures arediscovered at test. It may also be possible to identify and review defects that may be responsible for latentfailures of the device and to use available redundancy to reduce latent failure rates. In this manner, defectscan be mapped to regions of the memory (e.g., sense amp), and defect and/or design attribute(s) can beused in combination with rules to predict bit failure modes inline.

In some embodiments, the method includes determining, based on the MRI, if the amount of the availableredundant columns, the amount of the available redundant rows, or some combination thereof in thememory bank should be evaluated by a designer of the memory bank. In this manner, the method mayinclude performing "redundancy analysis" to suggest to the designer if adding more rows or columns inthe redundancy area should be performed at certain memory banks. The methods described herein areparticularly advantageous for providing feedback about the design of the die because the methodsdescribed herein can be used for early detection of fatal wafers and allow faster yield learning.

In another embodiment, the method includes determining a DCI for one or more of the defects located inthe array block area. The DCI for the one or more defects may be determined as described herein. In onesuch embodiment, determining the number of the redundant rows and the number of the redundantcolumns required to repair the memory bank is performed using the DCI for the one or more defects. Inanother embodiment, determining the number of the redundant rows and the number of the redundantcolumns required to repair the memory bank includes determining a DCI for each of the defects located inthe array block area of the memory bank, comparing the DCIs to a predetermined threshold, anddetermining the number of the redundant rows and the number of the redundant columns required torepair all of the defects having a DCI above the predetermined threshold. For example, a DCI may bedetermined for every defect located in the array block area. The DCI may be determined for the defectslocated in the array block area as described further herein. In addition, the method may include using theDCI to predict the number of row or column failures caused by the defects. For example, if the number ofdefects having a DCI larger than a predetermined value, which may be user defined, is larger than thenumber of rows or columns in the redundancy area, then the MRI (in this example defined to be the ratioof the redundant rows or columns needed for repair to the available redundant rows or columns) may bedetermined to be greater than 1 (fail). In contrast, if the number of defects having a DCI smaller than a 167 second predetermined value, which may be user defined and may be different than the first predetermined value, is smaller than the number of rows or columns in the redundancy area, then the MRI may be determined to be less than 1 (pass, perhaps with some repair). In addition, the method may include determining a max count or percent of available redundant rows and/or columns that might be needed to repair the memory bank if every defect having a DCI above a threshold requires repair.

Using the DCI to determine if the memory in a die is repairable may be advantageous since the actualyield impact of individual defects may vary depending upon the pattern failure caused by the defects, thelocation of the defects (e.g., on top of a layer, embedded in a layer, etc.), one or more attributes of thedefects such as defect size, etc. The DCI may be determined based on such variations in the defects asdescribed herein thereby reflecting how different defects will actually impact yield. In addition, sincesystematic defects may have more of an actual yield impact, the methods described herein may includedetermining which defects detected in the memory bank are systematic defects and then determining theMRI as described herein based on the criticality of the systematic defects. The systematic defects may beidentified according to any embodiment(s) described herein.

In some embodiments, the method includes determining a MRI for failure of the memory bank due to thedefects located in the array block area of the memory bank. In this manner, the method may includedetermining an index for segment failure due to defects detected in non-redundant areas of the memorybank. In a similar manner, the method may include determining an index for segment failure due todefects detected in redundant areas of the memory bank.

In another embodiment, the method includes determining a MRI for failure of the memory bank due todefects located in the redundant rows and the redundant columns of the memory bank. In this manner, themethod may include determining an index for logical row and/or column failure. Such an index may beused to alter one or more parameters of a test process as described above.

In some embodiments, the method includes generating a stacked map of like memory bank designsillustrating spatial correlations between defects detected in the memory banks. In this manner, the methodmay include generating a stacked map illustrating spatial correlations. Such a stacked map may begenerated in any suitable manner known in the art. 168

In one embodiment, the method includes determining the MRI on a die basis. In a similar manner, the method may include determining the MRI on a wafer basis and/or a lot basis. Determining the MRI on a die basis, a wafer basis, and/or a lot basis may be performed as described herein.

In another embodiment the method includes determining an index or memory yield prediction indicatingif a die on the wafer will fail due to the defects located in the array block area. In this manner, the methodmay include determining an index or a probability that a die will fail due to a bad memory bank. Thisindex may be determined as described further herein.

In an additional embodiment, the method includes determining the MRI for memory banks in a die on thewafer and generating a stacked map of the die illustrating spatial correlations between two or more of thememory banks indicated by the MRIs to not be repairable. Determining the MRI for the memory banks inthe die may be performed as described herein. In addition, the stacked map may be generated in anysuitable manner known in the art.

In a further embodiment, the method includes determining the MRI for memory banks in a die on thewafer and generating a stacked map of a reticle used to form the memory banks on the wafer illustratingspatial correlations between two or more of the memory banks indicated by the MRIs to not be repairable.Determining the memory banks in the die may be performed as described herein. In addition, the stackedmap may be generated in any suitable manner known in the art.

In some embodiments, the method includes identifying memory banks of a die impacted by defectsdetected in the die and ranking the memory banks based on the impact of the defects on the memorybanks. In this manner, the method may include ranking a list of impacted memory banks. The impact ofthe defects on the memory banks may be determined based on any of the information described herein(e.g., one or more attributes of the defects, one or more attributes of the design data for the memory banks,etc.) The impact of the defects on the memory banks that is used to rank the memory banks may includeany impact (e.g., any adverse effect) that the defects have on the memory banks. The memory banks maybe ranked such that memory banks that are most impacted by the defects are assigned the highest rank andthe memory banks that are least impacted by the defects are assigned the lowest rank. Such ranking of thememory banks may be used, for example, to determine a relationship between the location of the memorybanks in the die and the degree to which the defects impact the memory banks. In addition, such arelationship may be used to predict the cause of at least some of the defects, which may be used to reducethese defects on additional wafers and/or to reduce the number of defects that have the largest impact on 169 the memory banks first (e.g., using one or more of the altering steps described herein such as altering the process performed on the memory banks prior to detection of the defects and/or altering the design of the memory banks) before defects having smaller impacts on the memory banks are reduced (e.g., using one or more of the altering steps described above).

In another embodiment, the method includes determining a percentage of memory banks formed on thewafer impacted by defects in non-repairable areas of the memory banks. The memory banks impacted bydefects in non-repairable areas of the memory banks may be determined as described herein. Thepercentage may be determined based on the number of such memory banks and the total number ofmemory banks formed on the wafer. In addition, the method may include determining a percent of dieimpacted by probable redundancy failures and/or impacted by non-repairable failures. The probableredundancy failures and the non-repairable failures may be identified as described herein. In addition, thedie impacted by the probable redundancy failures and/or the non-repairable failures may be identified asdescribed herein. The number of impacted die and the total number of die formed on the wafer may beused to determine the percent of the die impacted by the probable redundancy failures and/or the non-repairable failures.

In some embodiments, the method includes generating a stacked wafer map of probable failures inmemory banks formed on the wafer illustrating spatial correlations between the probable failures. In thismanner, the method may include generating a stacked wafer map of probable failures or binned indexes(for spatial correlations). The probable failures may be identified as described herein, and the stackedwafer map may be generated in any suitable manner. The stacked map may alternatively display oroverlay the probability that a die will have memory failures by a method such as color coding probabilitybins.

In another embodiment, the method includes determining the MRI for more than one die formed on thewafer and ranking the more than one die based on the MRIs. In this manner, the method may includegenerating a ranked list of impacted die on the wafer. The MRI for the more than one die may bedetermined as described herein. In addition, ranking the more than one die based on the MRIs may beperformed as described herein, and results of such ranking may be used as described herein.

Each of the embodiments of the method for determining the MRI described above may include any otherstep(s) of any method(s) described herein. In addition, each of the embodiments of the method for 170 determining the MRI described above may be performed by any of the system embodiments described herein.

Another embodiment relates to a different method for binning defects detected on a wafer. This methodincludes comparing positions of the defects in design data space with positions of hot spots in design data.Comparing the positions of the defects and the hot spots may be performed in any suitable manner. Hotspots located proximate to design data that is at least similar are correlated with each other. The hot spotsmay be correlated with each other by another method or system. Alternatively, the hot spots may becorrelated with each other by an embodiment of the method. For example, in one embodiment, themethod includes correlating the hot spots by identifying a location of a POI in the design data associatedwith a systematic defect, correlating the POI with similar patterns in the design data, and correlating thelocation of the POI and locations of the similar patterns in the design data as positions of the correlatedhot spots. In one such embodiment, the systematic defects may be included in a data structure such as alist, database, or file of systematic defects for the design data, which may be generated by another methodor system. In another such embodiment, the method includes identifying the systematic defects and/ordetermining the POI in the design data for a systematic defect. For example, a systematic defect may beidentified by binning defects detected on a wafer based on portions of design data proximate to thepositions of the defects in design data space, which may be performed as described above. The POI maybe determined by extracting the pattern in the portion of the design data corresponding to a group intowhich the defects were binned. In this manner, the hot spots may be correlated to each other using designbackground based grouping, which may be performed as described further herein. Furthermore, the hotspots may be correlated to each other by binning the hot spots, which may be performed as describedfurther herein. Correlating the hot spots with each other may be performed on-tool. The positions of thecorrelated hot spots may be stored in a "hot spot list" or other suitable data structure that includes someindication of which hot spots are correlated with each other, an identity for the hot spots in the list, andlocations of the hot spots in the list. This list may then be used essentially as reference data in the binningmethod.

The method also includes associating the defects and the hot spots having positions that are at leastsimilar. In particular, defects and hot spots that have at least similar positions in design data space may bedetermined based on results of the comparing step described above. The defects and the hot spots havingpositions in design data space may be associated with each other in any suitable manner. In addition, themethod includes binning the defects in groups such that the defects in each of the groups are associated 171 with only hot spots that are correlated with each other. In this manner, each group of defects may correspond to a group of correlated hot spots.

The method further includes storing results of the binning step in a storage medium. The storing step mayinclude storing the results of the binning step in addition to any other results of any method embodimentsdescribed herein. The results of the binning step may be stored in any manner known in the art. Inaddition, the storage medium may include any storage media described herein or any other suitablestorage media known in the art. After the results of the binning step have been stored, the results of thebinning step can be accessed in the storage medium and used by any of the method or systemembodiments as described herein. Furthermore, it is noted that the results of the binning step may bestored "permanently," semi-permanently, temporarily, or momentarily for any period of time. Storing theresults of the binning step may be further performed according to any other embodiments describedherein.

In one embodiment, the method includes assigning a DBC to one or more of the groups. Assigning theDBC to one or more of the groups may be performed according to any of the embodiments describedherein. In another embodiment, the method includes determining a DCI for one or more of the defects.Determining a DCI for one or more of the defects in this embodiment may be performed according to anyof the embodiments described herein.

In another embodiment, the computer-implemented method is performed by an inspection system used todetect the defects on the wafer. In this manner, the computer-implemented method may be performed on-tool. In addition, the method may include performing hot spot management on-tool. Hot spot managementmay include, for example, hot spot discovery, hot spot monitoring, hot spot revision, or somecombination thereof each of which may be performed as described further herein. For example, in someembodiments, the hot spots are identified by an inspection system used to detect the defects on the wafer.In this manner, the hot spots may be identified or discovered on-tool. Such identification or discovery ofthe hot spots may be performed as described herein (e.g., by performing design background basedgrouping of defects detected on a wafer).

In another embodiment, the method includes monitoring the hot spots using results of inspection of one ormore wafers on which the design data is printed. Monitoring the hot spots based on the results of theinspection may be performed as described herein. Such monitoring of the hot spots may be performed on-tool. Monitoring the hot spots may also or alternatively be performed using the results of the inspection 172 described above, results of one of the binning methods described herein, results of assigning one or more DBCs to one or more defects, which may be performed as described herein, any other results of any of the methods described herein, or some combination thereof.

In another embodiment, the method includes inspecting the wafer based on correlations between the hotspots. For example, positions on the wafer corresponding to different groups of correlated hot spots maybe inspected differently. Inspecting the wafer based on the correlations between the hot spots may also beperformed based on the correlations and one or more attributes of the design data corresponding to groupsof correlated hot spots. For example, positions of a group of correlated hot spots that correspond to designdata that has a particularly high yield sensitivity to defects may be used to determine positions on thewafer that are to be inspected with higher than normal sensitivity, the one or more attributes of the designdata used in this embodiment may include any of the design data attribute(s) described herein. In addition,any one or more parameters of the inspection process may be altered such that positions on the wafercorresponding to different groups of correlated hot spots may be inspected differently. The one or moreparameters of the inspection may include any of the parameter(s) described herein.

In some embodiments, the method includes monitoring systematic defects, potential systematic defects, orsome combination thereof over time using the results of the binning step, which may be performedaccording to any of the embodiments described herein. In another embodiment, the method includesidentifying systematic defects and potential systematic defects in the design data based on the results ofthe binning step and monitoring occurrence of the systematic defects and the potential systematic defectsover time. The steps of this method embodiment may be performed as described herein.

In an additional embodiment, the method includes performing review of the defects based on the resultsof the binning step. For example, review of the defects may be performed such that groups of defects thatcorrespond to different groups of correlated hot spots are reviewed different (e.g., using at least onedifferent value of one or more parameters of the review process). Reviewing the wafer based on results ofthe binning step may also be performed based on the binning results and one or more attributes of thedesign data corresponding to the groups of correlated hot spots. In this manner, reviewing the defectsbased on results of the binning step may be performed as described above with respect to inspecting thewafer based on correlations between the hot spots.

In a further embodiment, the method includes generating a process for selecting the defects for reviewbased on the results of the binning step. Generating the process for selecting the defects for review in this 173 embodiment may be performed according to any of the embodiments described herein. In addition, theprocess for selecting the defects for review may be generated based on the results of the binning step incombination with information about the correlated hot spots associated with the groups of defects, andpossibly in combination with the results of any other step(s) of any method(s) described herein and anyother information described herein (e.g., one or more attributes of the design data, one or more attributesof the defects, etc.). Furthermore, generating the process for selecting the defects may include selectingvalues for any one or more parameters of the process to be used for selecting the defects.

In another embodiment, the method includes generating a process for inspecting wafers on which thedesign data has been printed based on the results of the binning step. Generating the process forinspecting wafers in this embodiment may be performed according to any of the embodiments describedherein. In addition, the process for inspecting the wafers may be generated based on the results of thebinning step in combination with information about the correlated hot spots associated with the groups ofdefects, and possibly in combination with the results of any other step(s) of any method(s) describedherein and any other information described herein (e.g., one or more attributes of the design data, one ormore attributes of the defects, etc.). Furthermore, generating the process for inspecting the wafers mayinclude selecting values for any one or more parameters of the process to be used for inspecting thewafers.

In a further embodiment, the method includes altering a process for inspecting wafers on which the designdata has been printed based on the results of the binning step. Altering the process for inspecting thewafers in this embodiment may be performed according to any of the embodiments described herein. Inaddition, the process for inspecting the wafers may be altered based on the results of the binning step incombination with information about the correlated hot spots associated with the groups of defects, andpossibly in combination with the results of any other step(s) of any method(s) described herein and anyother information described herein (e.g., one or more attributes of the design data, one or more attributesof the defects, etc.). Furthermore, altering the process for inspecting the wafers may include selectingvalues for any one or more parameters of the altered process to be used for inspecting the wafers.

In some embodiments, the method includes determining a percentage of a die formed on the waferimpacted by one or more of the groups of defects. In this embodiment, the percentage of the die may bedetermined according to any of the embodiments described herein. 174

In another embodiment, the method includes determining a percentage of a die formed on the wafer in which the defects binned in at least one of the groups are located and assigning a priority to the at least one group based on the percentage. Determining the percentage and assigning the priority may be performed according to any of the embodiments described herein.

In an additional embodiment, the method includes prioritizing one or more of the groups by number oftotal hot spots correlated with the hot spots associated with the defects in the one or more of the groupsand number of the defects in the one or more of the groups. For example, the number of hot spots in agroup of correlated hot spots may be compared to the number of defects in the group corresponding to thehot spot group. As such, the defectivity of a group of correlated hot spots may be determined (e.g., bydetermining the fraction of correlated hot spots at which a defect has been detected and/or by determiningthe percentage of correlated hot spots at which a defect has been detected). Therefore, the groups ofdefects may be prioritized by the defectivity of the correlated hot spots. For example, defects in a groupthat are detected at a larger number, a larger fraction, or a larger percentage of the corresponding hot spotsmay be assigned a higher priority than a group of defects that are detected at a smaller number, a smallerfraction, or a smaller percentage of the corresponding hot spots. The groups of defects may be prioritized,therefore, based on across wafer hot spot defectivity.

In a further embodiment, the method includes prioritizing one or more of the groups by number ofcorresponding hot spot locations on a reticle used to print the design data on the wafer at which thedefects in the one or more of the groups are detected at least once. For example, a group of defectscorresponding to a larger number of hot spot locations on the reticle may be assigned a higher prioritythan a group of defects corresponding to a smaller number of hot spot locations on the reticle. Therefore,the groups of defects may be prioritized based on the across wafer potential defectivity. In addition, if thenumber of times the reticle will be printed on a wafer is known or determined, the across-reticle potentialdefectivity of the groups may be used to determine or extrapolate the across wafer potential for defectivityof one or more of the groups. Results of this prioritizing step may be used to perform one or more othersteps as described herein.

In some embodiments, the method includes determining reticle-based marginality for one or more of thegroups based on number of locations on a reticle at which defects binned into the one or more of thegroups were detected and total number of hot spot locations on the reticle that are correlated with the hotspots associated with the defects in the one or more of the groups. For example, the number of locationsof hot spots in a group of correlated hot spots on a reticle may be compared to the number of these 175 locations at which defects in a group corresponding to the group of correlated hot spots were detected.

Therefore, the reticle-based marginality may be based on such a comparison and as such may be a measure of the defectivity across locations of correlated hot spots across a reticle. Such reticle-based marginality may be used in one or more steps as described herein.

Each of the embodiments of the method for binning defects described above may include any otherstep(s) of any method(s) described herein. In addition, each of the embodiments of the method for binningdefects described above may be performed by any of the system embodiments described herein.

Another embodiment relates to a different method for binning defects detected on a wafer. In thisembodiment, the method includes comparing one or more attributes of design data proximate positions ofthe defects in design data space. In one embodiment, the one or more attributes include pattern density. Inanother embodiment, the one or more attributes include the one or more attributes in feature space.Feature space may contain one or many feature vectors derived from design data. Unlike design space,feature space has the capability of efficiently considering many attributes which may be useful todetermine groups of defects in a supervised manner (e.g. nearest neighbor binning techniques) or anunsupervised manner (e.g. natural grouping techniques). The one or more attributes of the design dataused in this step may also or alternatively include any other attribute(s) of design data, defect data, hotspots or POI described herein.

The method also includes determining if the one or more attributes of the design data proximate thepositions of the defects are at least similar based on results of the comparing step. Determining if the oneor more attributes are at least similar may be performed in a manner similar to other steps for determiningsimilarity described herein. In addition, the method includes binning the defects in groups such that theone or more attributes of the design data proximate the positions of the defects in each of the groups are atleast similar. This binning step may be performed in a manner similar to other binning steps describedherein. The method further includes storing results of the binning step in a storage medium, which may beperformed as described herein.

In some embodiments, the method includes determining if the defects are random or systematic defectsusing the attribute(s). In addition, the attribute(s) can be used directly for random or systematic defects.The one or more attributes can be used to determine if defects that are binned and/or defects that are notbinned are random or systematic defects. The one or more attributes of the design data may also be usedin combination with any other results described herein and/or any other information described herein (e.g., 176 one or more attributes of the defects and hot spot information) to determine if the defects are random orsystematic defects. In one example of the embodiment described above, the one or more attributes of thedesign data that are used to determine if defects are systematic or random may include one or moreattributes of features in the design data at the position of the defects with respect to the features. Forexample, if the one or more attributes of the design data proximate to a position of a defect in design dataspace include relatively high pattern density and relatively small feature dimensions and design datahaving such attributes is known to be prone to systematic defects (which may be determinedexperimentally, by simulation, or any other suitable method or system), the defects may be determined tobe a systematic defect.

In another embodiment, the method includes ranking one or more of the groups using the attribute(s). Theone or more attributes that are used for ranking one or more groups of binned defects may include any ofthe attribute(s) described herein. In one example, the groups of binned defects may be ranked based onpattern density such that groups of defects associated with higher pattern density are ranked higher thangroups of defects associated with lower pattern density because defects located in high pattern densityareas of the design may have a larger detrimental impact on yield. Results of such ranking may be used asdescribed herein (e.g., the results may be used in steps involving prioritization results in place of theprioritization results).

The attribute(s) can also be used to rank defects within a group. For example, in an additionalembodiment, the method includes ranking the defects in at least one of the group using the one or moreattributes. The attribute(s) of the design data used to rank the defects in a group may include any of theattribute(s) described herein. In addition, the attribute(s) used to bin the defects may or may not be thesame attributes used to rank the defects in the group. Binning and ranking the defects in this embodimentmay advantageously provide finer separation of the defects by group and rank, which may provide moreinformation about the impact of the defects on yield. Ranking the defects within a group may beperformed as described herein. In addition, the defects in more than one group may be ranked separatelywithin their groups. Results of ranking the defects in a group described above may be used in one or moresteps described herein.

The attribute(s) can also be used to bin defects within a group. For example, in a further embodiment, themethod includes binning the defects within at least one of the groups into sub-groups using the one ormore attributes. The attribute(s) of the design data used to bin defects in a group into sub-groups mayinclude any of the attribute(s) described herein. In addition, the attribute(s) used to bin the defects in the 177 group may or may not be the same attributes used to bin the defects into sub-groups. Binning the defectsinto groups and sub-groups in this embodiment may advantageously provide finer separation of thedefects by group and sub-group, which may provide more information about the impact of the defects onyield. Binning the defects within a group into sub-groups may be performed as described herein. Inaddition, the defects in more than one group may be binned separately within one or more sub-groups.Results of binning the defects into groups and sub-groups described above may be used in one or moresteps described herein.

In some embodiments, the method includes analyzing the defects within at least one of the groups usingthe one or more attributes. In this manner, the attribute(s) can be used to analyze defects within a group.DCI determination is one example of this type of analysis. For example, in a further embodiment, themethod includes assigning a DCI to one or more of the defects using the attribute(s). The attribute(s) ofthe design data used to analyze the defects may include any of the attributes described herein. Theanalysis may also or alternatively include any other analysis described herein.

In another embodiment, the method includes determining a yield relevancy of one or more of the defectsusing the one or more attributes. In this manner, the attribute(s) can be used to estimate yield relevancy ofan individual defect. The one or more attributes used to determine the yield relevancy may include any ofthe attribute(s) described herein. In one such example, defects that are located proximate to design datathat has a relatively high pattern density may be determined to be more yield relevant than defects locatedproximate to design data that has a relatively low pattern density. In addition, the yield relevancy may bedetermined based on the one or more attributes of the design data and how likely the defect will affectyield based on those one or more attributes. The defects for which the yield relevancy is determined mayor may not include binned defects.

In an additional embodiment, the method includes determining overall yield relevancy of one or more ofthe groups using the attribute(s). Therefore, the attribute(s) can be used to estimate overall yield relevancy.The overall yield relevancy may be determined as described above.

In some embodiments, the method includes separating the design data proximate the positions of thedefects into the design data in an area around the defects and the design data in an area on which thedefects are located, which may be performed as described herein. In addition, the attribute(s) can be usedto differentiate the neighborhood around a defect from the area the defect may have landed on. 178

In another embodiment, the method includes identifying structures in the design data for binning orfiltering using rules and the attribute(s). For example, the method may include using rules and one ormore attributes of the design data to identify structures such as structures susceptible to LES, large polyblock, etc., and defects located proximate to such structures may be binned in a group and/or filtered fromthe results. The rules may be generated by the method described herein using experimental and/orsimulation results or using any suitable method.

In another embodiment, the method includes determining locations on the wafer at which review,measurement, test, or some combination thereof is to be performed based on inspection results generatedduring detection of the defects and based on the defects identified as systematic defects, which may beperformed according to any of the embodiments described herein. In some embodiments, the methodincludes determining locations on the wafer at which review, measurement, test, or some combinationthereof is to be performed based on inspection results generated during detection of the defects, thedefects identified as systematic defects, and yield relevancy of the defects, which may be performed asdescribed herein. In an additional embodiment, the method includes determining locations on the wafer atwhich review, measurement, test, or some combination thereof is to be performed based on inspectionresults generated during detection of the defects, the defects identified as systematic defects, and processwindow mapping, which may be performed as described herein.

In some embodiments, the method includes performing systematic discovery using the results of thebinning step and user-assisted review. For example, the results of the binning step may be used to assist auser in review (e.g., to determine where to review, how to review, etc.). Review may include generatingreview results (e.g., high magnification images) for at least one defects in one or more of the groups anddisplaying the results to the user such that the user can identify one or more defects or one or more groupsof defects as systematic defects.

In another embodiment, the method includes prior to the comparing step, separating the defects based onfunctional blocks in which the defects are located to improve S/N in the results of the binning step. Thefunctional blocks in which the defects are located may be determined as described herein. By separatingthe defects by functional block prior to the comparing step, defects in some (e.g., non-yield relevant)functional blocks may be eliminated from use in other steps of the method, which will increase S/N in thebinning results. In addition, the binning may be performed based on the one or more attributes of thedesign data in combination with the functional blocks in which the defects are located thereby providingbetter separation in the binning results and higher S/N. Furthermore, binning may be performed separately 179 for each functional block or for one or more different functional blocks thereby increasing the S/N for the binning results.

In another embodiment, the design data is organized into hierarchical cells, and the method includes priorto the comparing step, separating the defects based on the hierarchical cells in which the defects arelocated to improve S/N in the results of the binning step. The design data may be organized intohierarchical cells as described further herein. Separating the defects based on the hierarchical cells may beperformed as described above with respect to functional block based separation. Separating the defectsbased on hierarchical cells may be used to improve S/N of results of the binning step as described above.

In an additional embodiment, the design data is organized by design into hierarchical cells, and if a defectcould be located in more than one of the hierarchical cells, the method includes correlating the defect toeach of the hierarchical cells based on a probability that the defect is located in each of the hierarchicalcells based on area of the hierarchical cells, defect positional probability, or some combination thereof. Inthis manner, if a defect could be located in multiple cells, the defect can be correlated to the cells based ona probability that the defect is located in different cells, which may be determined based on area of defectpositional probability. The probabilities may be determined in any manner known in the art.

In some embodiments, the defects were detected by an inspection process, and the method includesreviewing locations on the wafer at which one or more POIs in the design data are printed, determiningbased on results of the reviewing step if defects should have been detected at the locations of the one ormore POIs, and altering the inspection process to improve one or more defect capture rates, which may beperformed as described further herein.

Each of the embodiments of the method for binning defects described above may include any otherstep(s) of any method(s) described herein. In addition, each of the embodiments of the method for binningdefects described above may be performed by any of the system embodiments described herein.

As described above, the portions of the design data proximate the positions of the defects may becompared to design data (e.g., POI design examples) corresponding to different DBCs (e.g., DBC bindefinitions) stored in a library or other data structure. One embodiment that may utilize such a library ordata structure is a computer-implemented method for assigning classifications to defects detected on awafer. This method includes comparing portions of design data proximate positions of the defects indesign data space with design data corresponding to different DBCs. Comparing the portions of the 180 design data (or the "source portions" of the design data) with the design data corresponding to thedifferent DBCs (or the "target portions" or "reference patterns" of the design data) may be performed asdescribed herein. In some embodiments, the method includes comparing one or more attributes of theportions of the design data with one or more attributes of the design data corresponding to the differentDBCs. The one or more attributes of the design data in the portions and the one or more attributes of thedesign data corresponding to the different DBCs that are compared in this step may include any of theattribute(s) described herein. In addition, the one or more attributes that are used for the comparing stepmay include one or more attributes in feature space. Furthermore, the comparing step may includecomparing the portions of the design data to the reference patterns to determine if there is an exact matchor similarity between the source and reference patterns. Moreover, the comparing step may be performedusing rules, which may include any of the rules described herein or rules based on any methods forperforming the comparing step described herein. Furthermore, the comparing step may include comparingpositions of the defects in design data space to positions of hot spots in design data space, which may beperformed as described herein.

Dimensions of at least some of the portions are different in some embodiments, and the dimensions maybe selected and/or determined as described further herein. In another embodiment, the design data in theportions includes design data for more than one design layer. Such portions of the design data may beconfigured and used in the method as described further herein. The design data in the portions mayinclude any other design data described herein. For example, the design data proximate the positions ofthe defects includes the design data on which the defects are located in one embodiment. In this manner,the design data used in this method may include the design data under or behind the defect or the designdata on which the defect may have landed. In another embodiment, the design data proximate thepositions of the defects includes the design data around the positions of the defects.

In an additional embodiment, the method includes converting the portions of the design data proximatethe positions of the defects to first bitmaps prior to the comparing step, which may be performed asdescribed herein, and converting the design data corresponding to the DBCs to second bitmaps prior tothe comparing step, which may be performed as described herein. In one such embodiment, thecomparing step includes comparing the first bitmaps with the second bitmaps. Such comparing may beperformed as described further herein. The embodiment of the method for assigning classifications to thedefects may include determining the positions of the defects in the design data space according to any ofthe embodiments described herein. 181

In one embodiment, the DBCs identify one or more polygons in the design data on which the defects arelocated or located near the defects. In this manner, the one or more polygons on which the defects arelocated or the one or more polygons located near the defects may be identified by the DBCs assigned tothe defects. As such, the one or more polygons that are or may be affected by the defects may bedetermined. In addition, the one or more polygons on which the defects are located or the one or morepolygons located near the defects may be identified, and information about these polygon(s) may be usedto determine a position of the defects with respect to the polygon(s) in the design data. In someembodiments, the DBCs identify locations of the defects in one or more polygons in the design data.Therefore, the method may include determining where in the polygons the defect is located or near basedon the DBCs assigned to the defects.

In another embodiment, the method includes separating the design data proximate the positions of thedefects into the design data in areas around the defects and the design data in areas on which the defectsare located. In this manner, the method may include differentiating the neighborhood around a defectfrom an area on which the defect may have landed. Such separating may be performed as describedfurther herein. In addition, results of such separating may be used in the computer-implemented methodfor assigning classifications to defects as described further herein.

The design data corresponding to the different DBCs and the different DBCs are stored in a data structure.In addition, the design data corresponding to the different DBCs and the different DBCs may be stored ina data structure as described above. In particular, the design data corresponding to the different DBCs andthe different DBCs may be stored as a DBC library file in the data structure. In addition, in oneembodiment, the data structure includes a library containing examples of the design data organized bytechnology, process, or some combination thereof. In this manner, the data structure may be configured asa design library that includes a set of POI design examples that may be used for classifying defects on-tool, and the POI design examples may be organized by technology, process step, or any other suitableinformation. The data structure may include any suitable data structure known in the art and may bestored on a storage medium such as one of the storage media described herein or any other suitablestorage medium known in the art.

The method also includes determining if the design data in the portions is at least similar to the designdata corresponding to the different DBCs based on results of the comparing step. This determining stepmay be performed according to any of the embodiments described herein. In some embodiments, thisdetermining step includes determining if the design data in the portions is at least similar to the design 182 data corresponding to the different DBCs and determining if the design data in the portions has one ormore attributes that are at least similar to one or more attributes of the design data corresponding to thedifferent DBCs based on results of the comparing step. The one or more attributes may include any of theattribute(s) described herein. For example, the one or more attributes may include information about theinspection system used to detect the defects (e.g., inspection system type, one or more parameters of theinspection system at which the inspection system was operating at the time the defects were detected, etc.)and/or attributes about the defects (e.g. size, rough bin, polarity, etc.).

In addition, the method includes assigning to the defects the DBCs corresponding to the design data thatis at least similar to the design data in the portions. The assigning step may be performed in any suitablemanner. In some embodiments, the assigning step includes assigning to the defects the DBCscorresponding to the design data that is at least similar to the design data in the portions and that has oneor more attributes that are at least similar to one or more attributes of the design data in the portions. Inone embodiment, the one or more attributes may include one or more attributes of results of an inspectionin which the defects were detected, one or more parameters of the inspection, or some combinationthereof. The one or more attributes may also or alternatively include any other attribute(s) describedherein.

The method further includes storing results of the assigning step in a storage medium. The results may bestored in the storage medium in any suitable manner or as described herein. The storage medium mayinclude any of the storage media described herein or any other suitable storage medium known in the art.

The computer-implemented method described above is performed by an inspection system used to detectthe defects in one embodiment. In this manner, assigning classifications to the defects as described hereinmay be performed on-tool. In another embodiment, the computer-implemented method is performed by asystem other than an inspection system used to detect the defects. In this manner, assigning classificationsto the defects as described herein may be performed off-tool.

In one embodiment, the method includes binning the defects assigned one or more of the DBCs in groupssuch that positions of the defects in each of the groups with respect to polygons in the portions of thedesign data proximate the positions of the defects are at least similar. In this manner, the method mayinclude separating the defects into groups based on the DBCs and the positions of the defects within theportions. The positions of the defects with respect to the polygons may be determined as described herein.In addition, such binning may be further performed as described herein. 183

In some embodiments, the method includes monitoring hot spots in the design data based on results of theassigning step. For example, the DBCs or the design data corresponding to the different DBCs may beassociated with hot spots in the design data. The hot spots may be identified in the design data asdescribed herein. Monitoring hot spots in the design data as described above may include determining ifthe number of defects assigned to the DBCs associated with the hot spots or the design datacorresponding to the different DBCs and associated with the hot spots changes over time. In addition,monitoring the hot spots in the design data based on results of the assigning step may be performed basedon the results of the assigning step in combination with any other data described herein such as one ormore attributes of the defects to which the different DBCs have been assigned. In addition, the methodmay include monitoring hot spots based on location (e.g., approximate location). In another embodiment,the method includes binning hot spots based on the design data corresponding to the DBCs. Such binningof the hot spots may be performed as described further herein. Binning the hot spots may includegenerating one or more data structures (e.g., lists, databases, files, etc.) of hot spots that includes locationsof hot spots and indicates which hot spots are at least similar. Such binning of the hot spots may beperformed on-tool.

In another embodiment, the method includes monitoring systematic defects, potential systematic defects,or some combination thereof over time using the results of the assigning step. For example, the results ofthe assigning step may be used to identify systematic issues in the design data, and the identifiedsystematic issues may be monitored across wafers and/or across time. The systematic issues may bedetermined based on the results of the assigning step as described further herein. In addition, monitoringthe systematic defects, the potential systematic defects, or some combination thereof may be furtherperformed as described herein.

In one embodiment, the design data corresponding to the different DBCs is identified by grouping defectsdetected on one or more other wafers based on portions of the design data proximate positions of thedefects detected on the one or more other wafers in the design data space. Such grouping of the defectsmay be performed as described herein. The results of grouping may be used to identify design data thatcorresponds to different DBCs. For example, the design data corresponding to each group of defects maybe identified as design data corresponding to different DBCs. In addition, the different DBCscorresponding to the design data may be determined by classifying the defects in the groups, which maybe performed as described herein, one or more attributes of the design data, one or more attributes of thedefects, any other information described herein, or some combination thereof. 184

In another embodiment, the method includes determining if the defects are nuisance defects based on theDBCs assigned to the defects and removing the nuisance defects from results of an inspection process inwhich the defects were detected to increase S/N of the results of the inspection process. In this manner,the method may include nuisance filtering. The defects determined as nuisance defects may be defectsassigned a nuisance DBC (e.g., a DBC of LES), defects not assigned a DBC, or defects assigned a DBCthat indicates that the defects are not yield relevant defects or that the defects are defects not of interest.Increasing the S/N of the inspection results may be advantageous particularly if the inspection results areused to perform one or more other steps thereby increasing the S/N of the results of the other steps.

In some embodiments, the method includes determining one or more POIs in the design data byidentifying one or more features in the design data indicative of a pattern dependent defect. In this manner,the method may include identifying POI(s) in the design data. The one or more features in the design dataindicative of a pattern dependent defect may be determined based on experimental results, simulationresults, binning results, other results described herein, or some combination thereof. Such results may begenerated as described herein. The one or more POIs may be determined using the identified features toperform arbitrary pattern searching of the design data. Patterns in the design data determined by arbitrarypattern searching to be at least similar to the identified features may be identified as POIs. One or morePOIs may be determined in this manner for more than one pattern dependent defect.

The defects to which DBCs are assigned in the methods described herein were detected in an inspectionprocess. In one embodiment, the method includes reviewing locations on the wafer at which one or morePOIs in the design data are printed, determining based on results of the reviewing step if the defectsshould have been detected at the locations of the one or more POIs, and altering the inspection process toimprove one or more defect capture rates. Each step of this embodiment may be performed as describedherein.

In another embodiment, the method includes determining a KP value for one or more of the defects. In anadditional embodiment, the method includes determining a KP value for one or more of the DBCs basedon one or more attributes of the design data corresponding to the DBCs. In a further embodiment, themethod includes determining a KP value for one or more of the defects based on one or more attributes ofthe design data corresponding to the DBCs assigned to the one or more defects. Each of these steps maybe performed as described herein. In some embodiments, the method includes monitoring KP values forone or more of the DBCs and assigning to the defects the KP values for the DBCs assigned to the defects. 185

The KP values for the one or more DBCs may be monitored as described herein. In this manner, KP values of one or more DBCs may be revised over time and/or wafer such that at the time the defects were detected, a KP value for the DBC assigned to the defect may also be assigned to the defect with relatively high accuracy. Assigning the KP value to a defect based on the DBC assigned to the defect may be further performed as described herein.

In some embodiments, the method includes selecting at least some of the defects for review based onresults of the assigning step. For example, the results of the assigning step may be used to determinewhich of the defects are most critical as described herein (e.g., based on one or more attributes of theDBCs assigned to the defects), and the most critical defects may be selected for review. In anotherexample, the assigning results may be used to determine which of the defects are systematic defects asdescribed further herein. In this manner, the method may include review sampling from regions in thedesign data at which DOI tend to occur.

In one embodiment, the method includes determining if the DBCs assigned to the defects correspond tosystematic defects that are visible to a review system and sampling the defects for review by selectingonly the defects that are visible to the review system for the review. The DBCs corresponding tosystematic defects that are or are not visible to a review system may be determined in any manner knownin the art. The DBCs corresponding to systematic defects that are visible to a review system may bedetermined prior to the method, and the DBCs may be assigned some identity that indicates if the DBCscorrespond to visible or not visible defects. In this manner, the defects may be selected for review basedon this identity. Selecting only the defects that are visible to the review system may be performed suchthat defects that are not visible to a review system such as a SEM are not selected for review. Selectingthe defects in this manner is particularly advantageous since re-locating the defects during review can bedifficult and relatively time consuming particularly if the review system spends a great deal of timelooking for defects that are not actually visible to the review system. Results of selecting the defects forreview may include locations of the defects selected for review on the wafer and any other results of anyof the step(s) of the method(s) described herein.

The method may include adapting a process, measurement, or test based on the results of the assigningstep. For example, in another embodiment, the method includes generating a process for sampling thedefects for review based on the results of the assigning step. Therefore, instead of or in addition toselecting the defects for review, the method may include generating a process that can be used, by themethod, another method, a system configured to perform the method, or another system, for sampling the 186 defects for review. Such a process may be used for sampling defects for review of defects detected onmultiple wafers and/or sampling defects for review performed by multiple review systems. The processfor sampling may be generated based on the results of the assigning step such that a relatively largenumber of defects assigned the same DBC may be sampled more heavily than a relatively small numberof defects assigned the same DBC. The process for sampling the defects for review may be generatedbased on the results of the assigning step in combination with any other results of any step(s) of any of themethod(s) described herein such as DCIs for the defects, KP values for the defects, etc.

In an additional embodiment, the method includes altering a process for inspecting the wafer based on theresults of the assigning step. Any parameter(s) of the process for inspecting the wafer may be altered inthis embodiment. For example, the one or more parameters of the process for inspecting the wafer thatmay be altered based on the results of the assigning step may include, but are not limited to, the care areas(or alternatively the do not care areas), the sensitivity, the in-line binning process, the inspection area,which wafers are inspected, or some combination thereof. In one particular example, the results of theassigning step may indicate the number of defects assigned the different DBCs, and the care areas may bealtered to include positions on the wafer corresponding to additional positions in design data space whichalso contain the design data corresponding to DBCs to which a relatively high number of defects havebeen assigned. In another example, the process for inspecting the wafer may be altered to inspect more ordifferently based on the results of the assigning step. The process for inspecting the wafer may also bealtered based on any results of any of the step(s) of the method(s) described herein.

In some embodiments, the method includes altering a process for inspection of the wafer during theinspection based on results of the inspection. Altering the process for inspection in this embodiment maybe performed as described further herein.

In a further embodiment, the method includes altering a metrology process for the wafer based on theresults of the assigning step. For example, the metrology process may be altered such that the mostcritical defects as determined from the results of the assigning step are measured during the metrologyprocess. Therefore, altering the metrology process may include altering the locations on the wafer atwhich the measurements are performed during the metrology process. In addition, results of inspectionand/or review such as BF images and/or SEM images of the defects selected for measurement may beprovided to the metrology process such that the results may be used to determine where the measurementsare to be performed. For example, the metrology process may include generating an image of anapproximate location of the defect on the wafer, and this image may be compared to the results of 187 inspection and/or review for the defect such that the metrology system can correct the position on thewafer if necessary such that the measurements are performed at the correct wafer locations and thereforeon the correct defects. In this manner, the measurements may be performed at substantially accuratelocations on the wafer. Altering the metrology process may also include altering any other one or moreparameters of the metrology process such as the type of measurements performed, wavelength at whichthe measurements are performed, angles at which the measurements are performed, etc. or somecombination thereof. The metrology process may include any suitable metrology process known in the artsuch as a CD measurement metrology process.

In some embodiments, the method includes altering a sampling plan for a metrology process for the waferbased on the results of the assigning step. Therefore, the method may include adaptive sampling. Forexample, the sampling plan for the metrology process may be altered such that a greater number of themost critical defects as determined from the results of the assigning step are measured during themetrology process. In this manner, the most critical defects may be sampled more heavily during themetrology process thereby advantageously producing larger amounts of information about the mostcritical defects. The metrology process may include any metrology process known in the art. In addition,the metrology process may be performed by any suitable metrology system known in the art such as aSEM. Furthermore, the metrology process may include performing any suitable measurements known inthe art of any suitable attributes of defects or features formed on the wafer known in the art such as profile,thickness, CD, etc.

In another embodiment, the method includes prioritizing one or more of the DBCs (e.g., DBCs assignedto defects) and optimizing one or more processes to be performed on wafers on which the design data willbe printed based on results of the prioritizing step. In one such embodiment, the DBC(s) may beprioritized based on the number of defects to which the DBCs have been assigned. The number of defectsto which each DBC has been assigned can be determined from the results of the assigning step. In onesuch example, the DBC assigned to the largest number of defects may be assigned the highest priority, theDBC assigned to the next largest number of defects may be assigned the next highest priority, and so on.

In addition, or alternatively, the DBC(s) may be prioritized based on any other results of any step(s) ofany method(s) described herein or any combination of results of any step(s) of any method(s) describedherein. For example, prioritizing the DBC(s) may include determining a DCI for one or more defects towhich the DBC(s) have been assigned and prioritizing the DBC(s) based on the DCI for the one or moredefects. The DCI may be determined in this embodiment as described further herein. In another example, 188 prioritizing the DBC(s) may include determining a KP value for one or more defects to which the DBC(s)have been assigned and prioritizing the DBC(s) based on the KP values for the one or more defects. In yetanother example, the DBC(s) may be prioritized based on a combination of number of defects to whichthe DBC(s) have been assigned and a DCI for one or more of the defects to which the DBC(s) have beenassigned. In this manner, prioritizing the DBC(s) may include prioritizing the DBC(s) based ondefectivity detected in design data corresponding to the DBC(s) such that the DBC(s) corresponding tohigher defectivity are assigned higher priorities.

Furthermore, the DBC(s) may be prioritized based on one or more attributes of the design datacorresponding to the DBC(s) possibly in combination with other results described herein. The one ormore attributes of the design data may include, for example, dimensions of features in the design data,density of features in the design data, the type of features included in the design data, positions of thedesign data corresponding to the DBC(s) within the design, susceptibility of the yield impact of the designdata to defects, etc., or some combination thereof. In one such example, DBC(s) corresponding to designdata that is more susceptible to yield impact by defects may be assigned a higher priority than DBC(s)corresponding to design data that is less susceptible to impact of defects on yield.

Moreover, the DBC(s) may be prioritized based on one or more attributes of the design possibly incombination with one or more attributes of the design data corresponding to the DBC(s) and/or otherresults described herein. The one or more attributes of the design may include, for example, redundancy,net list, etc., or some combination thereof. In particular, a POI in the design data may have contextbeyond the pattern contained within the POI. Such context may include, for example, the label of the cellcontaining the POI, the hierarchy of cells above the cell containing the POI, the impact of redundancy (ornot) of a systematic defect on the POI, etc. Therefore, the one or more attributes that are used in theembodiments described herein may include context of the POI in which the design data corresponding tothe DBC(s) is located, which may be determined based on the positions of the design data correspondingto the DBC(s) in design data space and/or based on the design data corresponding to the DBC(s) (if thedesign data corresponding to the DBC(s) is specific to a cell in the design data). In one such example,DBC(s) corresponding to design data that has redundancy such that a systematic defect may not have ayield impact in the design may be assigned a lower priority than DBC(s) corresponding to design data thatdoes not have redundancy such that a systematic defect may have a significant yield impact. Such contextof the cells may be acquired and/or determined in any manner known in the art. 189

Optimizing one or more processes in this embodiment may include altering any one or more parametersof the one or more processes such as focus, dose, exposure tool, resist, PEB time, PEB temperature, etchtime, etch gas composition, etch tool, deposition tool, deposition time, CMP tool, one or more parametersof a CMP process, etc. Preferably, the parameter(s) of the process(es) are altered to decrease defectivityof the design data corresponding to the DBC(s) (e.g., number of defects detected in the design datacorresponding to the DBC(s)), to alter one or more attributes (e.g., DCI, KP, etc.) of defects detected inthe design data corresponding to the DBC(s), and/or to increase yield of devices in which the design datacorresponding to the DBC(s) are included.

In addition, the one or more parameters of the one or more processes may be optimized for only the DBChaving the highest priority as determined by the prioritization step or the DBC(s) having relatively highpriorities as determined by the prioritization step. In this manner, the one or more parameters of the one ormore processes may be altered and/or optimized based on the design data corresponding to the DBC(s)exhibiting the largest defectivity and/or defectivity that has the largest yield impact. As such, the resultsof the prioritization step indicate which DBC(s) should be used to alter and/or optimize the one or moreparameters of the one or more processes to produce the largest improvements in yield.

This embodiment is, therefore, advantageous over other previously used methods and systems for alteringand/or optimizing processes because without guidance as to which DBC(s) have the largest impact onyield, many alterations may be made to the processes without producing large or any improvements inyield thereby increasing the turn around time for and cost of process optimization.

Furthermore, although the process(es) that are altered and/or optimized in this step may include only theprocesses that were used to print the design data corresponding to the DBC(s) on the wafer prior todetection of the defects assigned DBCs in the embodiments described herein, the one or more processesthat are altered and/or optimized may include any process(es) that are used to print other designs that alsoinclude the design data corresponding to the DBC(s). For instance, if more than one design includes thedesign data corresponding to the DBC(s), based on the prioritization and/or any other results of themethods described herein, one or more processes used to print the more than one design may be alteredand optimized to thereby increase the yield of devices fabricated with each of the different designs.

In an additional embodiment, the method includes determining a root cause of the defects based on theDBCs assigned to the defects. For example, the root cause may be determined based on one or moreattributes of the design data corresponding to the DBCs assigned to the defects. The one or more 190 attributes may be used to determine the root cause as described further herein. The attribute(s) of the design data used to determine the root cause may include any of the design data attribute(s) described herein. In addition, any other information and/or results of any step(s) of any method(s) described herein may be used in combination with the attribute(s) of the design data to determine the root cause of the defects.

In a further embodiment, the method includes determining a root cause of at least some of the defects bymapping the at least some of the defects to experimental process window results, which may beperformed as described herein. In another embodiment, the method includes determining a root cause ofat least some of the defects by mapping the at least some of the defects to simulated process windowresults, which may be performed as described herein.

In another embodiments, the method includes determining a root cause corresponding to one or more ofthe DBCs and assigning a root cause to the defects based on the root cause corresponding to the DBCsassigned to the defects. For example, a root cause of defects previously detected in design datacorresponding to the DBCs may be associated with the DBCs. The root cause of the previously detecteddefects may be determined in any manner described herein or in any other suitable manner known in theart. In this manner, the root cause of the defects may be determined as the root cause associated with theDBCs assigned to the defects.

In a further embodiment, the method includes determining a percentage of a die formed on the waferimpacted by the defects to which one or more of the DBCs are assigned. For instance, the percentage maybe determined by the number of die across the wafer in which the defects assigned the same DBC weredetected at least once. Such a percentage may be determined by dividing the number of die in which atleast one defect assigned the same DBC is detected by the total number of inspected die. The results ofthis step may be multiplied by 100 to arrive at the percentage. The percentage, therefore, reflects the dieimpact marginality for defects assigned the same DBC. Such a percentage may be determined for morethan one DBC assigned to the defects, and each or at least some of the percentages may be displayed in achart such as a bar chart that may be generated by the method. Therefore, the chart illustrates die impactmarginality as a function of DBCs assigned to the defects. Such a chart may be illustrated in a userinterface, which may be configured as described further herein. The method may also include prioritizingdefects assigned one or more of the DBCs based on the percentage determined in this embodiment. 191

In some embodiments, the method includes determining a POI in the design data corresponding to at leastone of the DBCs and determining a ratio of number of the defects to which the at least one of the DBCshave been assigned to number of locations of the POI on the wafer. In this manner, the method mayinclude performing marginality analysis by determining the ratio or percentage of number of defectsassigned a DBC compared to the number of locations of the POI corresponding to the DBC printed on thewafer. In such embodiments, the locations of the POI on the wafer may be identified by arbitrary patternsearching. In addition, the methods described herein may include arbitrary pattern searching to identifylocations of the POI in the inspected region of the design and determining the cumulative area of the POIin the inspected regions of the design. The ratio of the number of defects to which the DBC has beenassigned to the cumulative area of the POI in the inspected regions of the design may then be used todetermine a defect density of the DBC corresponding to the POI. The method may also includeprioritizing the one or more DBC(s) based on the ratios determined in this embodiment.

In another embodiment, the method includes determining one or more POIs in the design datacorresponding to at least one of the DBCs and determining a ratio of number of the defects to which atleast one of the DBCs have been assigned to number of locations of the one or more POIs in the designdata (e.g., with respect to the inspected region of the wafer). In this manner, the method may includeperforming marginality analysis by determining the ratio or percentage of the number of defects assigneda DBC corresponding to a POI found on the wafer compared to number of locations of the POI in thedesign across the inspected area of the wafer. In such embodiments, the locations of the POI on the wafermay be identified by arbitrary pattern searching. This method may also include prioritizing one or more ofthe DBC(s) based on the ratios determined in this embodiment.

In an additional embodiment, the method includes determining a POI in the design data corresponding toat least one of the DBCs, determining a percentage of a die formed on the wafer in which the defects towhich the at least one of the DBCs have been assigned are located, and assigning a priority to the POIbased on the percentage. In this manner, the method may include performing marginality analysis basedon a percentage of the die impacted by the defects. For example, the number of defects assigned the sameDBC may be divided by the number of design instances of the POI in a reticle used to print the designdata on the inspected region of the wafer and the number of times the reticle is printed and inspected onthe wafer. The result of this step may be multiplied by 100 to arrive at the percentage. In this manner, themethod may include prioritizing known systematic defects by number of die across the wafer in which thedefects were detected at least once. For instance, a higher priority may be assigned to POIs in whichsystematic defects were detected if the POIs appeared on 10% of the die versus 1% of the die. In another 192 example, defects assigned the same DBC that are detected in a larger number of the die on the wafer maybe assigned a higher priority than defects assigned a different DBC that were detected in a lower numberof die on the wafer. In addition, the method may include generating a chart such as a bar chart illustratingthe percentage of a die formed on the wafer in which the defects assigned different DBCs are located.Therefore, such a chart graphically illustrates the die-based marginality for different DBCs. Such a chartmay be displayed in a user interface, which may be configured as described herein.

In a further embodiment, the method includes prioritizing one or more of the DBCs by number of defectsto which the one or more of the DBCs have been assigned are detected. In this manner, the method mayinclude prioritizing known systematic defects by number of total number of defects to which the DBCswere assigned. As such, the method may include prioritizing known systematic defects based on wafer-based marginality. For instance, a DBC assigned to defects detected at a larger number of the designinstances on the wafer may be assigned a higher priority than a DBC assigned to defects detected at alower number of design instances on the wafer. Such prioritizing may also be performed based on thepercentage of locations of design instances across the wafer at which the defects were detected. Forexample, the number of defects detected and assigned a DBC may be divided by the total inspecteddesign instances corresponding to the DBC across the wafer. The results of this step may be multiplied by100 to produce the percentage described above. In addition, the method may include generating a chartsuch as a bar chart illustrating the number of design instances across the reticle at which defects assigneddifferent DBCs were detected. Such a chart may be displayed in a user interface, which may beconfigured as described herein.

In some embodiments, the method includes prioritizing one or more of the DBCs by number of designinstances on a reticle, used to print the design data on the wafer, at which the defects to which the one ormore of the DBCs have been assigned are detected at least once. In this manner, the method may includeprioritizing known systematic defects by number of design instances across the reticle at which thedefects are found at least once. For instance, DBCs assigned to defects detected at a larger number of thedesign instances on the reticle may be assigned a higher priority than DBCs assigned to defects detectedat a lower number of design instances on the reticle. In addition, the method may include generating achart such as a bar chart illustrating the number of design instances across the reticle at which defectsassigned different DBCs were detected. Such a chart may be displayed in a user interface, which may beconfigured as described herein. 193

In another embodiment, the method includes determining reticle-based marginality for one or more of theDBCs based on number of locations on a reticle at which the defects to which the one or more of theDBCs have been assigned were detected and total number of portions of the design data printed on thereticle that are at least similar to the portions of the design data proximate the positions of the defects towhich the one or more of the DBCs have been assigned. For example, the reticle-based marginality maybe determined by dividing the number of locations in a stacked reticle map at which at least one defectassigned a DBC has been detected by the total inspected design instances across the reticle. The result ofthis step may be multiplied by 100 to produce a percentage of the locations of the design instances,corresponding to the DBC, at which the defects to which the DBC was assigned were detected. Inaddition, the method may include generating a chart such as a bar chart illustrating the reticle-basedmarginality or percentage of locations at which defects assigned different DBCs were detected. Such achart may be displayed in a user interface, which may be configured as described further herein. Themethod may also include prioritizing one or more of the DBCs based on the reticle-based marginalitydetermined for one or more of the DBCs. For instance, DBCs that exhibit relatively high reticle-basedmarginality may be assigned higher priorities than DBCs that exhibit lower reticle-based marginality. Thesteps of the embodiments described above may be performed for groups of defects to which the sameDBC have been assigned or for individual defects to which a DBC has been assigned.

Each of the embodiments of the method for assigning a classification to a defect described above mayinclude any other step(s) of any method embodiment(s) described herein. In addition, each of theembodiments of the method for assigning a classification to a defect described above may be performedby any of the system embodiments described herein.

Another embodiment relates to a method for altering an inspection process for wafers. This methodincludes reviewing locations on the wafer at which one or more POIs in the design data are printed. Themethod also includes determining based on results of the reviewing step if defects should have beendetected at the locations of the one or more POIs. In addition, the method includes altering the inspectionprocess to improve one or more defect capture rates and/or improving the S/N for defects located in atleast some of the one or more POIs. Each of these steps may be performed as described further herein.For example, one or more parameters of the inspection process may be altered based on prioritization ofthe POIs, which may be determined as described herein.

One use case for the above-described method is optics sensitivity applications. For example, in oneembodiment, altering the inspection process includes altering an optics mode of an inspection system 194 used to perform the inspection process. In this manner, the optics mode used for inspection may be altered to improve the S/N of detecting one or more defects corresponding to at least some of the one or more POIs. The optics mode may include any optics mode known in the art.

In another embodiment, the method includes determining an optics mode of an inspection system used toperform the inspection process based on results of determining if the defects should have been detected atthe locations of the one or more POIs. In this manner, the optics mode with the highest S/N for the defectsthat should have been detected may be determined. The optics mode may include any optics mode knownin the art. In addition, the determined optics mode and/or the defects that should have been detected maybe used to select other parameters of the altered inspection process such as type of inspection system usedto perform the inspection process.

In some embodiments, altering the inspection process includes altering the inspection process to increasecapture of DOI associated with one or more POI. Altering the inspection process to increase capture mayinclude altering any one or more parameters of the inspection process. The detection enhanced by alteringthe parameters of the inspection process may include detection of DOI associated with POI in inspectionresults (e.g., increasing the defect count for a yield critical systematic DOI, etc.). The one or moreparameters altered to increase the capture may be selected based on any results of the inspection processand/or any results of the reviewing step (e.g., not just results of reviewing the locations on the wafers atwhich the one or more POIs are printed).

In some embodiments, altering the inspection process includes altering the inspection process to suppressnoise in results of the inspection process. Altering the inspection process to suppress the noise mayinclude altering any one or more parameters of the inspection process. The noise that is suppressed byaltering the parameters of the inspection process may include any noise in inspection results (e.g.,background noise, nuisance defects, etc.). The one or more parameters altered to suppress the noise maybe selected based on any results of the inspection process and/or any results of the reviewing step (e.g.,not just results of reviewing the locations on the wafers at which the one or more POIs are printed).

In a further embodiment, altering the inspection process includes altering the inspection process to reducedetection of defects not of interest or to improve binning of defects not of interest. Altering the inspectionprocess to reduce detection of defects not of interest may include altering any one or more parameters ofthe inspection process. The defects not of interest that are detected less by altering the parameters of theinspection process may include any defects not of interest (e.g., non-yield relevant systematic defects, 195 defects at cold spots, etc.). The one or more parameters altered to reduce detection of the defects not of interest may be selected based on any results of the inspection process and/or any results of the reviewing step (e.g., not just results of reviewing the locations on the wafers at which the one or more POIs are printed).

Altering the inspection process to improve one or more defect capture rates may include altering any oneor more parameters of the inspection process. For example, in one embodiment, altering the inspectionprocess includes altering an algorithm used in the inspection process. The algorithm that is altered may bea defect detection algorithm or any other algorithm used in the inspection process. The altered algorithmmay include any suitable algorithm known in the art. In addition, altering the inspection process mayinclude altering more than one algorithm used in the inspection process.

In an additional embodiment, altering the inspection process includes altering one or more parameters ofan algorithm used in the inspection process. The algorithm for which one or more parameters are alteredmay include a defect detection algorithm or any other algorithm used in the inspection process. Inaddition, altering the inspection process may include altering one or more parameters of more than onealgorithm used in the inspection process. The one or more parameters in the algorithm(s) may include anyparameters of the algorithms, preferably parameter(s) that affect the defect capture rates.

Each of the embodiments of the method for altering an inspection process for wafers described above mayinclude any other step(s) of any method embodiment(s) described herein. In addition, each of theembodiments of the method for altering an inspection process for wafers described above may beperformed by any of the system embodiments described herein.

An additional embodiment relates to a system configured to display and analyze design and defect data.One embodiment of such a system is shown in FIG. 25. As shown in FIG. 25, the system includes userinterface 182. User interface 182 is configured for displaying one or more of design layout 184 for asemiconductor device, inline inspection data 186 acquired for a wafer on which at least a portion of thesemiconductor device is formed, and electrical test data 188 acquired for the wafer. In one embodiment,the electrical test data includes logic bitmap data. Design, inspection (or metrology), test, and overlay datamay be represented in design, device, reticle, or wafer space. The user interface may also be configuredfor displaying modeled data for the semiconductor device and/or FA data for the wafer. In addition, theuser interface may be configured to display information for specific hot spots or DOI based on input fromthe user (e.g., a selection of a hot spot or DOI by the user). In this manner, the user interface may be 196 configured for displaying information about different hot spots or DOI at different times. However, theuser interface may be configured for displaying information about different hot spots or DOIsimultaneously (e.g., in a wafer map or a bar graph) using one or more different indicia (e.g., color,symbol, etc.) to indicate the different hot spots or DOI. The user interface may also be configured todisplay information in the hot spot database. Using the display of the information in the hot spot database,a user may create one or more hot spot lists by selecting subset(s) of hot spots of interest with a givenanalysis or inspection recipe. The user interface may be displayed on display device 190. Display device190 may include any suitable display device known in the art.

The system also includes processor 192. Processor 192 is configured for analyzing one or more of thedesign layout, the inline inspection data, and the electrical test data upon receiving an instruction toperform the analysis from a user via the user interface. The processor may also be configured foranalyzing the modeled data and/or the FA data as described above. For instance, user interface 182 maybe configured for displaying one or more icons 194. Each of the icons may correspond to a differentfunction that may be performed by the processor. In this manner, although five icons are shown in FIG.25, the user interface may be configured for displaying any number of icons corresponding to the numberof possible functions. The user may then instruct the processor to perform one or more functions byselecting (e.g., clicking on) one or more of the icons. In addition, the user interface may display thevarious functions that are available to the user in any other manner known in the art (e.g., a drop downmenu). In this manner, the user interface may be configured as a single integrated user interface thatcombines design/layout visualization and analysis operations with inline process data visualization andanalysis operations and functional/structural electrical test data visualization and analysis operations.

The system may be configured to process the data at increased resolution, which may be commonlyreferred to as "drill down capabilities." For instance, the system may be configured to use input such as awafer map illustrating defects detected on the wafer to select two or more dies for stacking, to selectdefects illustrated in the die stacking results, and to perform some function on the defects. The systemmay also be configured to use the data from more than one of the domains together, which may becommonly referred to as "drill across capabilities."

In one embodiment, the user interface is also configured for displaying overlay 196 of at least two of thedesign layout, the inline inspection data, the electrical test data, and any other information describedherein. In one such embodiment, the electrical test data includes logic bitmap data. In such embodiments,the processor may be configured for overlaying the different data according to any of the embodiments 197 described herein. In this manner, the system may be configured to generate and display overlay of data from two or more of the three domains (e.g., design, inspection, and electrical test). Such overlay of the data may be used to map physical to logical positions of defects and using electrical test results (e.g., electrical failures) and the mapping to identify defects that impact the electrical test results (e.g., causing the electrical failures).

In one embodiment, the processor is also configured for determining a defect density in design data spaceupon receiving an instruction to perform this determination from the user via the user interface. In thismanner, the system may be configured to perform fault density calculations as described further herein.The user interface may also be configured for displaying results of the fault density calculations.

In an additional embodiment, the processor is configured to perform defect sampling for review uponreceiving an instruction to perform the defect sampling from the user via the user interface. In a furtherembodiment, the processor is configured for grouping defects based on similarity of the design layoutproximate to positions of the defects in design data space upon receiving an instruction to perform thegrouping from the user via the user interface. In this manner, the system may be configured to performsampling and data reduction (e.g., data reduction by pattern dependent binning) techniques. Thesetechniques may be performed as described further herein.

In some embodiments, the processor is configured for monitoring KP values for groups of defects overtime and determining a significance of the groups of defects based on the KP values over time. In thismanner, the system may be configured for defect tracking (e.g., using DTT methodology and/or usingimages). The user interface may also be configured for displaying results of monitoring the KP values andthe significance of the groups of defects over time. The processor and the system shown in FIG. 25 maybe further configured as described herein. For example, the processor and the system may be configuredto perform any other step(s) of any other methods described herein. In addition, the system shown in FIG.25 may include other components described herein such as an inspection system, which may beconfigured as described further above. The system shown in FIG. 25 has all of the advantages of themethods described herein. A further embodiment relates to a computer-implemented method for determining a root cause ofelectrical defects detected on a wafer. In one such embodiment, the results of the inspection of the waferfor the electrical defects may include a bitmap for a logic device. The method includes determining 198 positions of the electrical defects in design data space. The positions of the electrical defects in design data space may be determined as described herein.

In some embodiments, the method includes correlating spatial signatures of defects such as systematicdefects to process conditions. For example, after converting scan-based and structural test results to waferspace coordinates, particular spatial signatures may be correlated to one or more process conditions.Methods and systems for performing spatial signature analysis of defect data are illustrated in U.S. Pat.Nos. 5,991,699 to Kulkarni et al., 6,445,199 to Satya et al., and 6,718,526 to Eldredge et al. The methodsand systems described herein may be configured to perform any step(s) of any of the methods describedin these patents.

The method also includes determining if the positions of a portion of the electrical defects define a spatialsignature corresponding to one or more process conditions. This step may be performed by comparing aspatial signature for the portion of the electrical defects to a set of spatial signatures corresponding to theprocess conditions, by applying rules to the positions of the portion of the electrical defects, or in anyother suitable manner. In addition, if the positions of the portion of the electrical defects define a spatialsignature that corresponds to the one or more process conditions, the method includes identifying the rootcause of the portion of the electrical defects as the one or more process conditions. In this manner, themethod described above may include performing spatial signature analysis on logic bitmap data. Themethod further includes storing results of the identifying step in a storage medium. The results of theidentifying step may include any results described herein. In addition, this method may perform thestoring step as described further herein. The storage medium may include any of the storage mediadescribed herein.

Each of the embodiments of the method for determining a root cause of electrical defects described abovemay include any other step(s) of any method embodiment(s) described herein. In addition, each of theembodiments of the method for determining a root cause of electrical defects described above may beperformed by any of the system embodiments described herein.

The root cause of other defects may also be determined in the methods described herein. For example,wafer based or reticle based spatial signature by pattern group (and combination of such) mapped across aprocess window may be particularly useful in determining correlations to aid in root cause determination.In one example, at one edge of a process window, defect x and y are marginal and tend to fail first fromthe outside of the wafer. At the other edge of the process window, defect z tends to fail in the edge of the 199 wafer first. Thus, a possible root cause could be determined by observing which systematic defects fail most often (and perhaps with respect to the outer annular ring) on the wafer.

Another embodiment relates to a computer-implemented method for selecting defects detected on a waferfor review, discovery for classification/investigation, and monitoring for verification/root cause analysisincluding on-tool, off-tool, and on-SEM. The method includes identifying one or more zones of the wafer.The one or more zones are associated with positions of one or more defect types on the wafer. Oneembodiment of one or more such zones is illustrated in FIG. 26. As shown in FIG. 26, zone 198 on wafer200 may be identified as being associated with positions of one or more defect types on the wafer. Forinstance, this zone may be associated with defect types that are caused by focus errors proximate the outeredge of the wafer during a lithography process or etch variation from the wafer center to the wafer edge.

The method also includes selecting defects detected in only the one or more zones for review. Forinstance, as shown in FIG. 26, wafer map 202 may be overlaid with the layout of zone 198. In this manner,defects illustrated in wafer map 202 may be selected for review based on the zone in which they arelocated and the one or more defect types associated with the zone. In one such example, if the zone shownin FIG. 26 is associated with de-focus errors proximate the outer edge of the wafer, the method may selectdefects (only, primarily, or heavily) in zone 198. Alternatively, the defects may be selected from zones onthe wafer other than zone 198.

Although only one zone is shown in FIG. 26, it is to be understood that the wafer may be separated intoany number of suitable zones. In addition, the zones may be defined on the wafer as annular zones asshown in FIG. 26, angular zones, angular and radial zones, or rectangular zones. However, the zones mayhave irregular (e.g., polygonal) shapes. In addition, all, some, or none of the zones may have the samecharacteristics such as shape and/or size.

The method described above may be used to provide a defect sample such that results of review of thedefect sample can be interpolated from the die to the wafer. In contrast, a typical review sample planincludes 100 to 200 defects for recipe optimization and 25 to 100 defects for monitoring spread over theentire wafer. However, there may be tens of thousands of hot spots on one die alone. Hot spots may bereviewed for discovery. Systematic defects may be reviewed for monitoring and verification. Therefore,even after selecting 100 or 200 defects from this population, one preferably does not review them all onthe same die. Instead, the selected defects are preferably spread out across multiple die. The methoddescribed above uses zonal analysis results to identify a correlation between certain defect types and 200 certain zones on the wafer. As such, the methods described herein may be used to identify wafer positionspecific defects. In this manner, the method may include biasing the sampling plan toward these zones toprovide results suitable for use in die-to-wafer interpolation. The method further includes storing resultsof the selecting step in a storage medium. The results of the selecting step may include any resultsdescribed herein. In addition, this method may perform the storing step as described further herein. Thestorage medium may include any of the storage media described herein.

Each of the embodiments of the method for selecting defects for review described above may include anyother step(s) of any method embodiment(s) described herein. In addition, each of the embodiments of themethod for selecting defects for review described above may be performed by any of the systemembodiments described herein.

Another embodiment relates to a computer-implemented method for evaluating one or more yield relatedprocesses for design data. One such embodiment is shown in FIG. 27. It is noted that the steps shown inFIG. 27 are not essential to practice of the method. One or more steps may be omitted from or added tothe method illustrated in FIG. 27, and the method can still be practiced within the scope of thisembodiment.

As shown in FIG. 27, the method includes identifying potential failures in the design data using rulechecking, as shown in step 204. Alternatively, the potential failures in the design data may be identifiedusing observed potential hot spots from repeater analysis or a defect density map. The potential failuresthat are identified in this step may include one or more different types of DOI. In some embodiments, thepotential failures that are identified in this step may include post-pattern potential failures (e.g., post-etchpotential failures). In addition, once a potential failure has been identified, it may be propagatedthroughout the design, which may be detected by searching for common patterns in the design (e.g., viaarbitrary pattern searching). In some embodiments, the method includes arbitrary pattern searching toidentify the locations of all similar POI. The common patterns may be identified by searching for thepattern rotated or flipped to find all of the potential failures. Furthermore, the potential failures in thedesign data may be identified in step 204 using any other suitable method (e.g., modeling), software,and/or algorithm known in the art. In addition, the potential failures may include areas or patterns in thedesign data that may cause failure of a device fabricated for the design data or that may alter one or moreelectrical parameters of the device in an undesirable manner without actually causing failure of the device. 201

As shown in step 206, the method also includes determining one or more attributes of the potentialfailures. The attribute(s) of the potential failures that are determined may include, for example, type. Theattribute(s) of the potential failures may be acquired by experimental testing, simulation results, designdata, or any other method. Since the method includes identifying potential failures as described above, themethod may include altering the design data prior to fabrication to eliminate as many of the potentialfailures as possible. Such altering of the design data may be performed as described herein. However, it isconceivable that not all potential failures can be eliminated prior to fabrication. In addition, the potentialfailures identified in the method described herein may or may not actually produce failures or impactyield during fabrication. Therefore, while some of the potential failures may be eliminated prior tofabrication (and therefore inspection), the method described herein can provide important informationabout where in the design inspection should be performed such that if potential failures actually fail theycan be detected as soon as possible. In addition, the method described herein can provide importantinformation about how different areas of the design should be inspected such that inspection of areas onwafers at which portions of the design data containing the potential failures in the design can beperformed with the most suitable inspection parameters thereby increasing the probability that if apotential failure should actually cause a failure, it will be detected by inspection.

As shown in step 208, the method includes determining if the potential failures are detectable based onthe one or more attributes of the potential failures. Whether or not the potential failures are detectablemay be determined based on the attribute(s) of the potential failures in combination with the knowncapabilities of various inspection systems. As shown in step 210, the method includes determining whichof a plurality of different inspection systems (e.g., BF, DF, voltage contrast, EC, electron beam, etc.) ismost suitable for detecting the potential failures based on the one or more attributes.

In some embodiments, the method includes selecting one or more parameters of the inspection systemdetermined to be most suitable, as shown in step 212. In one such embodiment, the parameter(s) areselected based on the one or more attributes of the potential defects. The parameter(s) may be selected asdescribed further herein. In addition, the parameter(s) that are selected in this step may include anyparameter(s) of the inspection system that can be varied and/or are controllable. One example of such aparameter is optical mode or inspection mode. Preferably, the parameters) are selected to optimizeinspection of wafers for the potential failures (e.g., to increase defect capture rates of defects at thelocations of the potential failures, to increase sensitivity to defects at the locations of the potential failures,etc.). 202

In some embodiments, the method includes prioritizing one or more of the potential failures based on oneor more attributes of the design data proximate the positions of the potential failures possibly incombination with any other information described herein (e.g., susceptibility of the design data to defects,susceptibility of the electrical parameters of the device corresponding to the design data to defects, etc.).Such prioritizing may be performed as described further herein. In addition, the most suitable inspectionsystem and the parameters of the inspection system may be selected based on results of such prioritizingas described further herein. For example, in such embodiments, the most suitable inspection system andthe parameters of the inspection system may be selected to optimize the inspection for potential failuresthat have the highest priority or priorities such that the most important defects are detected in theinspection process. Such determination of the most suitable inspection system and selection of theparameters may or may not result in optimization of the inspection for potential failures that have thelowest priority or priorities.

In another embodiment, the method includes determining an impact of the potential failures on yield ofdevices fabricated with the design data, as shown in step 214. In this manner, the method may be used forrecipe optimization and monitoring. In a further embodiment, the method may include determining theimpact of potential failures that were determined to be undetectable but impact yield. In this manner, themethod may include determining a percentage of yield loss that is undetectable by inspection. Oneexample of a method for predicting yield that may be used in the methods described herein is illustrated inU.S. Pat. No. 6,813,572 to Satya et al.

The methods described above may, therefore, be used for completely automated prediction, tracking, andvalidation of hot spots (after some initial manual setup is performed). The method described above furtherincludes storing results of determining which of the plurality of different inspection systems is mostsuitable for detecting the potential failures in a storage medium. The results of this step may include anyresults described herein. In addition, this method may perform the storing step as described further herein.The storage medium may include any of the storage media described herein.

Each of the embodiments of the method for evaluating one or more yield related processes describedabove may include any other step(s) of any method(s) described herein. In addition, each of theembodiments of the method for evaluating one or more yield related processes described above may beperformed by any of the systems described herein. 203

The method and system embodiments described herein can be used to provide a total design, defect, and yield solution. For instance, as described above, the method may include separating defects (detected by inline inspection and/or electrical inspection) into systematic defects and random defects. The method and system embodiments described herein can also be used to manage hot spots.

Defects related to parametric yield losses may be used as input for a simulation such as a simulation thatdetermines electrical parameters of devices based on parameters of semiconductor manufacturingprocesses. In this manner, the defects related to parametric yield losses may be used in combination withinformation about the processes performed on the wafer to tune or optimize the simulation. In addition,the simulation results may be used to identify parameters of the process performed on the wafer that canbe altered to reduce the defects related to parametric yield losses. Furthermore, the simulation and theresults of the methods described herein may be used to identify which parameters of the process orprocesses are critical to reducing parametric yield losses.

The defects related to systematic patterning losses may be used to identify pattern defects that are relatedto the interaction between the design of the device and the process. In this manner, the information aboutthese defects can be used to alter the process, alter the design, or alter the process and the design to reducethese defects.

The steps described above may be performed during the design feedback phase that is performed toimprove future designs by considering the lessons learned. In other words, knowledge transfer from thehot spot database and monitoring phase may be provided to the design phase (e.g., technology researchand development, product design, RET design, etc.). This phase may be performed in multi-source space(e.g., using a correlation between any of design, wafer, test, and process spaces). This phase may alsoinclude improving the design based on hot spots that have a strong correlation to a particular cell design.In addition, this phase may include improving the design using hot spots that have a strong correlation toproposed design rules.

Information about the random defects may be used to determine the defect limited yield (i.e., the maximum possible yield attainable if all systematic and repeater defects were eliminated). Such information may also be used for online and offline monitoring in combination with simulations that determine the effect of the random defects on the device to identify the random defects that are top yield killers. 204

The methods described herein may include monitoring semiconductor fabrication processes using theresults of the methods. The results that are used to monitor the semiconductor fabrication processes mayinclude any of the results described herein (e.g., inline inspection data, systematic defect information,random defect information, failure density maps, binning results, etc.) or any combination of the resultsdescribed herein. The methods described herein may also include altering one or more parameters of oneor more semiconductor fabrication processes based on the results of any of the methods described herein.The parameter(s) of the semiconductor fabrication process(es) may be controlled using a feedbacktechnique, a feedforward technique, an in situ technique, or some combination thereof. In this manner, themethods described herein and the results generated by the methods may be used for SPC applications.

As described further herein, the methods and systems described herein can be used for on-tool yieldprediction based on design data for improved binning, review sampling, inspection setup, and any otheranalysis described herein. The methods and systems described herein have a number of advantages overother currently used methods and systems. For example, currently used methods and systems for KPanalysis use historical yield data for total random yield loss predictions by considering the defect densityby size distribution and/or classification. One disadvantage of such methods and systems is that otherdefect groupings (e.g., size bins, class bins, layers) are not considered when calculating the probabilitythat one or more defects will kill a die. In addition, these methods and systems require statisticallysignificant historical data for setup. In another example, currently used methods and systems for KPanalysis use historical yield data and yield loss prediction per defect by considering size and/orclassification within a region (e.g., similar pattern density) to better predict the KP of detected defects.One disadvantage of such methods and systems is that statistically significant historical data is requiredfor setup. In a further example, currently used methods and systems for critical area analysis (CAA)determines a yield loss prediction by defect and relies on pre-calculation of critical areas across the fulldie by geometry (line width, spacing) for various defect sizes. The approach is relatively computationallyintensive, but once calculated, defects with an area greater than the critical area based on location arepredicted to be killer. One disadvantage of such methods and systems is that statistically significanthistorical data is required for setup. In addition, such methods and systems involve computationallyintensive pre-processing, and the accuracy of the methods and systems is limited by defect coordinateaccuracy.

In contrast, the methods and systems described herein utilize highly accurate coordinates, which results inimproved yield prediction accuracy for CAA and methods described herein. The methods and systemsdescribed herein may also be used for active CAA. For instance, rather than pre-processing data to 205 generate a look up table across many sizes and locations, this approach calculates the yield based on theimproved location and size. This requires design data to be available to the inspection system and has thepotential to be more computationally efficient. In addition, the methods and systems described hereininvolve saving the analysis for systematic defects or by pattern grouping, which may result in furtherimproved computational efficiency. Furthermore, the methods and systems described herein can be usedto predict yield of on-tool results, which allows the results to be used for prioritizing defects for review(e.g., manual review for recipe optimization, high resolution image grab, etc.) while the wafer is on thechuck. 206