Image sensor with tolerance optimizing interconnects

WO 2012/155143 PCT/US2012/037825

IMAGE SENSOR WITH TOLERANCE OPTIMIZING INTERCONNECTS

BACKGROUND

The disclosure relates generally to electromagnetic sensing and sensors and also 5 relates to low energy electromagnetic input conditions as well as low energy electromagnetic throughput conditions. The disclosure relates more particularly, but not necessarily entirely, to optimizing the tolerances desired for using a stacking scheme for a hybrid image sensor with minimal vertical interconnects between substrates and associated systems, methods and features. 10 There has been a popularization of the number of electronic devices that utilize and include the use of imaging/camera technology in general. For example, smartphones, tablet computers, and other handheld computing devices all include and utilize imaging/camera technology. The use of imaging/camera technology is not limited to the consumer electronics industry. Various other fields of use also utilize imaging/camera 15 technology, including various industrial applications, medical applications, home and business security/surveillance applications, and many more, In fact, imaging/camera technology is utilized in nearly all industries.

Due to such popularization, the demand for smaller and smaller high definition imaging sensors has increased dramatically in the marketplace. High resolution and high 20 definition means that more data and must be moved in a relatively smaller space. The device, system and methods of the disclosure may be utilized in any imaging application where size and form factor are considerations. Several different types of imaging sensors may be utilized by the disclosure, such as a charged-couple device (CCD), or a complementary metal-oxide semiconductor (CMOS), or any other image sensor currently 25 known or that may become known in the future. CMOS image sensors typically mount the entire pixel array and related circuitry, such as analog-digital converters and/or amplifiers, on a single chip. The size limitations of a CMOS image sensor often require that increasing more data is being moved within increasingly smaller confines. The contact pads between circuits can be manufactured 30 smaller and smaller between the sensor and other important functions, such as signal processing, due to the number of considerations that must be accounted for in the design and manufacture of a CMOS image sensor. Thus, for example, increasing the pixel array area may come with a trade-off in other areas, such as A/D conversion or other signal processing functions, because of the decreased area in which the related circuitry may 35 occupy. WO 2012/155143 PCT/US2012/037825

The disclosure optimizes and maximizes the pixel array without sacrificing quality of the signal processing by optimizing and maximizing the pixel array on a first substrate and stacking related circuitry on subsequent substrates. The disclosure utilizes advancements in back-side illumination and other areas to take advantage of optimizing 5 the area of the pixel array on a substrate. The stacking scheme and structure allow highly functional, large-scale circuits to be utilized while maintaining a small chip size.

The features and advantages of the disclosure will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by the practice of the disclosure without undue experimentation. The features and advantages of 10 the disclosure may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the disclosure will become apparent from a 15 consideration of the subsequent detailed description presented in connection with the accompanying drawings in which: FIG. la is a schematic view of an embodiment of an imaging sensor constructed on a single substrate; FIG. lb is a schematic view of an embodiment of an imaging sensor, 20 demonstrating the remote placement of processing circuits relative to a pixel array in accordance with the teachings and principles of the disclosure; FIG. 2 illustrates a schematic view of an embodiment of an imaging sensor built on a plurality of substrates in accordance with the teachings and principles of the disclosure; FIG. 3a illustrates a perspective view of an embodiment of an imaging sensor 25 made on a monolithic and illustrating a plurality of columns comprising pixels and supporting circuitry, where the supporting circuitry is one pixel in width; FIG. 3b illustrates a top view of an embodiment of an imaging sensor made on a monolithic and illustrating a plurality of columns comprising pixels and supporting circuitry, where the supporting circuitry is one pixel in width; 30 FIG. 3c illustrates a perspective view of a single column comprising pixels and supporting circuitry taken from FIG. 3a; FIG. 3d illustrates a top view of a single column comprising pixels and supporting circuitry taken from FIG. 3b; WO 2012/155143 PCT/US2012/037825 FIG. 3e illustrates a perspective view of an embodiment of an imaging sensor made on a monolithic and illustrating a plurality of columns comprising pixels and supporting circuitry, where the supporting circuitry is two pixels in width; FIG. 3f illustrates a top view of an embodiment of an imaging sensor made on a 5 monolithic and illustrating a plurality of columns comprising pixels and supporting circuitry, where the supporting circuitry is two pixels in width; FIG. 3g illustrates a perspective view of an embodiment of an imaging sensor built on a plurality of substrates with a pixel array on the first substrate and supporting circuitry located on a second or subsequent substrate with interconnects and vias being shown 10 connecting the plurality of substrates in accordance with the teachings and principles of the disclosure; FIG. 3h illustrates a front view of the embodiment of an imaging sensor built on a plurality of substrates of FIG. 3g; FIG. 3i illustrates a perspective view of an embodiment of an imaging sensor built 15 on a plurality of substrates wherein a plurality of pixel columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second substrate and showing an electrical connection and communication between one column of pixels to its associated or corresponding column of circuitry; FIG. 3j illustrates a perspective view of a single column of pixels and a single 20 column of circuitry taken from FIG. 3i showing an electrical connection therebetween; FIG. 3k illustrates a front view of the single column of pixels and the single column of circuitry taken from FIGS. 3i and 3j showing an electrical connection therebetween; FIG. 31 illustrates a side view of the single column of pixels and the single column 25 of circuitry taken from FIGS. 3i and 3j showing an electrical connection therebetween; FIG. 3m illustrates a perspective view of an embodiment of an imaging sensor built on a plurality of substrates wherein a plurality of pixel columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second substrate and showing a plurality of electrical connections and communication 30 between the plurality of pixel columns and associated or corresponding columns of circuitry; FIG. 3n illustrates a perspective view of an embodiment of an imaging sensor built on a plurality of substrates wherein a plurality of pixel columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second 35 substrate, wherein the circuit columns are two pixels in width and half of the length of the WO 2012/155143 PCT/US2012/037825 pixel column, and showing a plurality of electrical connections and communication between the plurality of pixel columns and associated or corresponding columns of circuitry; FIG. 3o illustrates a perspective view of a single column of pixels and a single 5 column of circuitry taken from the right most column of FIG. 3n showing an electrical connection therebetween; FIG. 3p illustrates a front view of the single column of pixels and the single column of circuitry taken from FIGS. 3n and 3o showing an electrical connection therebetween; 10 FIG. 3q illustrates a side view of the single column of pixels and the single column of circuitry taken from FIGS. 3n and 3o showing an electrical connection therebetween; FIG. 3r illustrates a perspective view of a single column of pixels and a single column of circuitry taken from the left most column of FIG. 3n showing an electrical connection therebetween: 15 FIG. 3s illustrates a front view of the single column of pixels and the single column of circuitry taken from FIGS. 3n and 3r showing an electrical connection therebetween; FIG. 3t illustrates a side view of the single column of pixels and the single column of circuitry taken from FIGS.3nand3r showing an electrical connection therebetween; 20 FIG. 3u illustrates a perspective view of an embodiment of an imaging sensor built on a plurality of substrates wherein a plurality of pixel columns forming the pixel array are located on the first substrate and a plurality of circuit columns are located on a second substrate, wherein the circuit columns are four pixels in width, and showing a plurality of electrical connections and communication between the plurality of pixel columns and 25 associated or corresponding columns of circuitry; FIG. 3v illustrates a perspective view of a single column of pixels and a single column of circuitry taken from the right most column of FIG. 3u showing an electrical connection therebetween; FIG. 3w illustrates a front view of the single column of pixels and the single 30 column of circuitry taken from FIGS. 3u and 3v showing an electrical connection therebetween; FIG. 3x illustrates a side view of the single column of pixels and the single column of circuitry taken from FIGS. 3u and 3v showing an electrical connection therebetween; WO 2012/155143 PCT/US2012/037S25 FIG. 3y illustrates a perspective view of a single column of pixels and a single column of circuitry taken from the column to the left of adjacent to the right most column of FIG. 3u showing an electrical connection therebetween; FIG. 3z illustrates a front view of the single column of pixels and the single 5 column of circuitry taken from FIGS. 3u and 3y showing an electrical connection therebetween; FIG. 3aa illustrates a side view of the single column of pixels and the single column of circuitry taken from FIGS. 3u and 3y showing an electrical connection therebetween; 10 FIG. 4 illustrates an embodiment of an imaging sensor built on a plurality of substrates and also illustrating an embodiment of the specific placement of support circuits in accordance with the teachings and principles of the disclosure; FIG. 5 illustrates an embodiment of an imaging sensor built on a plurality of substrates and also illustrating an embodiment of the specific placement of support circuits 15 wherein some of the circuits are relatively remotely placed in accordance with the teachings and principles of the disclosure; FIG. 6 illustrates an embodiment of a first substrate having various percentages of coverage by differing pixel arrays in accordance with the teachings and principles of the disclosure; 20 FIG. 7 illustrates an embodiment having a plurality of pixel arrays in accordance with the teachings and principles of the disclosure; FIG. 8 illustrates an embodiment of an image sensor with an optimized pixel array and related or supporting circuitry being stacked and illustrating a light source in accordance with the teachings and principles of the disclosure; 25 FIG. 9 illustrates a backside illuminated embodiment of an image sensor with an optimized pixel array and related or supporting circuitry being stacked in accordance with the teachings and principles of the disclosure; FIG. 10 illustrates an embodiment of an image sensor wherein the pixel array is more remotely located from all said supporting circuits in accordance with the teachings 30 and principles of the disclosure; FIG. 11 illustrates an embodiment of an image sensor having stacked substrates of differing size in accordance with the teachings and principles of the disclosure; FIG. 12 illustrates an embodiment of pixel architecture, where each pixel column does not share a read bus with another pixel column; WO 2012/155143 PCT/US2012/037825 FIG. 13 illustrates an embodiment of pixel architecture, where there is a horizontal 2-way share of pixel columns with respect to a read bus, such that there is one read bus per two pixel columns; FIG. 14 illustrates an embodiment of an imaging sensor built on a plurality of 5 substrates having a front illuminated pixel array in accordance with the teachings and principles of the disclosure; FIG. 15 illustrates an embodiment of an imaging sensor having pixel array divided into read areas containing a plurality of pixels; FIG. 16 illustrates an embodiment of an imaging sensor having a plurality of 10 substrates and the connection of a plurality of buses for accessing data from a pixel array divided into read areas containing a plurality of pixels; FIG. 17a illustrates an embodiment of a pixel array wherein interconnects arc spaced relative to pixels within the pixel array in accordance with the teachings and principles of the disclosure; 15 FIG. 17b illustrates an embodiment of a pixel array wherein interconnects are spaced relative to columns within the pixel array in accordance with the teachings and principles of the disclosure; FIG. 17c illustrates an embodiment of a pixel array wherein a interconnects are spaced relative to areas within the pixel array in accordance with the teachings and 20 principles of the disclosure; FIGS. 18a-18f illustrate embodiments of a pixel array, wherein interconnects may be spaced relative to defined pixel areas within the pixel array in accordance with the teachings and principles of the disclosure; FIG. 19 illustrates a method of spacing interconnects/bumps in accordance with the 25 principles and teachings of the disclosure; FIG. 20 illustrates an embodiment wherein pixel area dedicated support circuits may be used such that each pixel area may have at least a support circuit dedicated to processing only the data produced by pixels within the pixel area to which it is dedicated; FIG. 21 illustrates an embodiment of a schematically large image sensor showing 30 the scalability of the principles and teaching of the disclosure; and FIG. 22 illustrates an. embodiment of a schematically large image sensor showing the scalability of the principles and teaching of the disclosure. 2012/155143 PCT/US2012/037825

DETAILED DESCRIPTION

For the purposes of promoting an understanding of the principles in accordance with the disclosure, reference will now be made to the embodiments illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Any alterations and further modifications of the inventive features illustrated herein, and any additional applications of the principles of the disclosure as illustrated herein, which would normally occur to one skilled in the relevant art and having possession of this disclosure, arc to be considered within the scope of the disclosure claimed.

Before the devices, systems, methods and processes for staggering ADC or column circuit bumps in a column or sub-column hybrid image sensor using vertical interconnects are disclosed and described, it is to be understood that this disclosure is not limited to the particular structures, configurations, process steps, and materials disclosed herein as such structures, configurations, process steps, and materials may vary somewhat. It is also to be understood that the terminology employed herein is used for the purpose of describing particular embodiments only and is not intended to be limiting since the scope of the disclosure will be limited only by the appended claims and equivalents thereof.

It must be noted that, as used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise:

In describing and claiming the subject matter of the disclosure, the following terminology will be used in accordance with the definitions set out below.

As used herein, the terms “comprising,” “including," “containing,” "characterized by,” and grammatical equivalents thereof are inclusive or open-ended terms that do not exclude additional, unrecited elements or method steps.

As used herein, the phrase “consisting of’ and grammatical equivalents thereof exclude any element or step not specified in the claim.

As used herein, the phrase “consisting essentially of and grammatical equivalents thereof limit the scope of a claim to the specified materials or steps and those that do not materially affect the basic and novel characteristic or characteristics of the claimed disclosure.

As used herein, the term “proximal" shall refer broadly to the concept of a portion nearest an origin. WO 2012/155143 PCT/US2012/037825

As used herein, the term “distal” shall generally refer to the opposite of proximal, and thus to the concept of a portion farther from an origin, or a furthest portion, depending upon the context.

Digital imaging, whether still or movie, has many constraints placed upon it with 5 regard to the devices used to record the image data. As discussed herein, an imaging sensor may include a pixel array and supporting circuits that are disposed on at least one substrate. Devices usually have practical and optimal constraints on the form factor of the imaging sensor depending upon the application. With most applications, especially for commercial use, size is usually a constraint. Even in outer space applications where size 10 would seemingly be the least constrained, size is still an issue because the imaging device needs to be orbitally launched and overcome the force of gravity. Additionally, and especially in consumer electronics, any bulk added by the imaging device/camera, takes away from possible other functional hardware or battery capacity/life. Thus, size is nearly always a constraint that must be addressed in any application using an imaging sensor. 15 In many cases, the form factor of an imaging device is constrained. There may be unlimited area or real estate laterally/horizontally, relative to the pixel array, or there may be an abundance of space directly behind a pixel array vertically. Often it is not the pixel array that is the only consideration for fitment, but it is the supporting circuitry that needs to be accommodated. The supporting circuits may be, but are not necessarily limited to, 20 analog to digital converters, power circuits, power harvesters, amplifier circuits, dedicated signal processors and filters, serializers for data transmission, etc. In addition to circuits, physical property elements may be required, such as light filters and lenses. All of the above must be considered when deciding on and designing the form factor of an imaging device and traditionally the industry has chosen lateral or horizontal placement of 25 supporting circuits when designing the image sensors of the day. Yet, there are many applications that would benefit from a more vertical rather than lateral or horizontal form factor.

An example of an application that would benefit from an imaging device having a relatively vertical (relative to the pixel array) form factor would be in the fields of use 3.0. requiring the use of a scope. For example, industrial scopes and medical endoscopes would benefit from an image sensor that could be housed within a lumen of the device. In such a scope application, an image sensor that could be disposed in the lumen of the scope may be advantageous. The inside diameter (if round) of the lumen would then define maximum diameter (round) of the image sensor. With a popular lumen size range of 3mm 35 to 15mm, it will be appreciated that the image sensor will be greatly limited in form factor WO 2012/155143 PCT/US2012/037825 considerations in the lateral direction due to the inside diameter constraints. Accordingly, a more vertical configuration may be advantageous.

Although size is an issue as stated above, pixel count numbers continue to climb industry wide no matter the specific application, and often eclipse the mediums that are 5 used to actually view the images after they have been recorded, such as a computer monitor or television. However, it should be understood that all pixels are not created equal. In the example above, a scope configuration may be used in a limited light application. As such, a scope based image sensor that functions well in low light situations may be advantageous. Large pixels have the ability to collect more light than 10 small pixels simply because of their different sizes. However, the trend in the marketplace has been to increase the number of pixels in a given form factor. Logically more pixels in a given area generally mean smaller pixel size. Smaller pixels have the shortfalls of not working well in lower light and creating noise because of the electronic crowding. Additionally, more pixels equates to more boundary space relative to light gathering 15 space. Larger pixels tend to produce better images and higher image quality because they simply have a larger ratio of light sensing portion to border portion. Both of those issues lend to the poor image quality of today small image sensors.

As pixel counts continue to grow in a given space pixel pitch decreases thereby requiring greater precision for interconnect electrical contact. Accordingly, the cost of 20 image sensor production can increase as the need for greater precision in data handling is required for the increased pixel pitch. Current technologies may be used to achieve image sensors with increased capabilities but at increased cost as yields fall during manufacture.

The techniques and structures disclosed herein with respect to a ratio of the pixel pitch to bump pitch will allow for the following: 25 « Improved manufacturing reliability due to increased ability to provided alternate interconnects, i.e., interconnect redundancy; • Maximize bump pitch size in a cost effective manner per application or field of use; • Allows for more economical CMOS process due to the ability to use larger 30 pixel pitch; e Allows for more efficient bump technology access, i.e., read data from multiple buses or directly off of a pixel array; • Allows for redundancy in CMOS process to improve yield; WO 2012/155143 PCT/US2012/037825 * Use of localized ADC in a pre-determined or defined pixel area; and » Allows for multiple pixel array geometries, plurality of buses, and column bump configurations to be utilized.

The above-identified issues describe the current state of the art relative to a few 5 needs within the industry. What is needed is an image sensor having adequate resolution by way of pixel count, a vertical architecture and form factor, and as large as possible pixel size, all while constrained in a limited space. The disclosure contemplates and will discuss embodiments and methods of design that address these and potentially other issues by optimizing the size of the pixel array on a substrate/chip and remotely locating 10 supporting circuits in a generally vertical configuration on one or more supporting substrates/chips.

High performance image sensors that use on-chip analog to digital convertors (ADC), on-chip digital and analog algorithms, on-chip complex timings, and on-chip complex analog functions provide high quality images because of the following reasons 15 (the list below is not a complete list, but is given merely for exemplary purposes):

No pick-up noise due to long off-chip analog data lines (if no on-chip ADC, then analog signals need to be sent off-chip);

Lower temporal noise because digital conversion is carried out early in the data path (no extra amplifier, buffer that will add extra noise); 20 Local timing optimization using complex on-chip timing generator. Because of pad count limitation, only simple timing can be performed using external system;

Lower noise generated by I/O. On-chip systems allow for reduced pad count; and

Faster operation can be achieved (more serial on-chip operation, reduced stray capacitances and resistances). 25 However the elaborated functions and processes used to provide such high quality images occupy a very large area around the pixel array and significantly lower the ratio of the pixel array size to die size. It is common to have a ratio of pixel array size to die size below 25% in an imaging system that uses on-chip processes and circuitry, including ADCs and the other elaborated functions noted above. Thus, there is a trade-off between 30 ratio of pixel array size to die size and on-chip functions. 10 WO 2012/155143 PCT/US2012/037825

Therefore, most of the applications of the technology that need to use an optimized ratio of pixel array size to die size use customized image sensors without digital conversion (analog out) or with reduced analog/digital functionality and lower grade analog to digital conversion. Even in that case, the ratios of pixel array size to die size that 5 are greater than 50% are difficult to achieve.

The disclosure demonstrates and contemplates a system and method of increasing the ratio of pixel array size to die size without sacrificing image quality. The disclosure contemplates imaging applications using a given die size and where maximized pixel array size is required or imaging applications using a given pixel array size, but where smaller 10 die size is required.

One of the key issues of the three dimensional stacking technology is the bump pitch. Current technologies achieve a bump pitch of around 50μηι to lOOpm. In the next three to ten years, it is expected that developing technologies will permit the bump pitch to be decreased in size in a range that is equal or nearly the same size as pixel pitch. 15 Moreover stacked substrates/chips yield depends directly upon the bump pitch. The most frequent failure in stacked substrates/chips is an electrical short between two interconnects or bumps. As bump pitch decreases in size and becomes smaller, the planarization specification of the wafers has to be tighter. In order to absorb the wafer planarization errors, the interconnects or bumps are made or grown taller. However, 20 excess metal in taller interconnect s/bumps tends to move to the side(s) during the wafer bonding process, which may short neighboring or adjacent bumps. Higher yield and lower costs due to a relaxed wafer alignment process can be achieved by relaxing the interconnect or bump pitch.

The disclosure proposes a device, system, method of relaxing the bump pitch while 25 working on a tighter pixel pitch.

The disclosure also contemplates an image sensor that might otherwise be manufactured with its pixel array and supporting circuitry on a single, monolithic substrate/chip and separating the pixel array from all or a majority of the supporting circuitry. The disclosure may use at least two substrates/chips, which will be stacked 30 together using three-dimensional stacking technology. The first of the two substrates/chips may be processed using an image CMOS process. The first substrate/chip may be comprised either of a pixel array exclusively or a pixel array surrounded by limited circuitry. The second or subsequent substrate/chip may be processed using any process, and does not have to be from an image CMOS process. The second substrate/chip may be, 35 but is not limited to, a highly dense digital process in order to integrate a variety and 11 WO 2012/155143 PCT/US2012/037825 number of functions in a very limited space or area on the substrate/chip, or a mixed-mode or analog process in order to integrate for example precise analog functions, or a RF process in order to implement wireless capability, or MEMS (Micro-Electro-Mechanical Systems) in order to integrate MEMS devices. The image CMOS substrate/chip may be 5 stacked with the second or subsequent substrate/chip using any three-dimensional technique. The second substrate/chip may support most, or a majority, of the circuitry that would have otherwise been implemented in the first image CMOS chip (if implemented on a monolithic substrate/chip) as peripheral circuits and therefore have increased the overall system area while keeping the pixel array size constant and optimized to the fullest extent 10 possible. The electrical connection between the two substrates/chips may be done through interconnects, which may be wirebonds, pbump and/or TSV (Through Silicon Via).

Referring now to FIG. la and lb, FIG. la an example of an imaging sensor of monolithic design wherein a single substrate is used as the basis of chip construction. As can be seen in FIG. la, a substrate 100a may comprise a pixel array 150a that is 15 configured to receive electromagnetic energy, convert it to data, and then pass that data on to supporting circuits 110a, 120a, 130a for processing that will ultimately result inadigital image or video. The supporting circuits may include signal processing circuits such analog to digital converters 110a, amplifier circuits 130a, filter circuits, power supplying and harvesting circuits 120a, and serial processors to name only a few. Some of the 20 supporting circuits may be located nearer to the pixel array than other circuits and connected to each pixel of the pixel array via buses. For example, amplification circuits and digital conversion circuits may be preferred to be located closer to the pixel array because that architecture may increase the clarity of the data stream and introduce minimal noise to the system. As can be seen in FIG. la, image sensor 100a is a schematic 25 illustration of what is typically available in the marketplace with regard to image sensors. FIG. la illustrates a generally lateral placement of the supporting circuits relative to the pixel array 150a, which dominates the marketplace today because of cost and manufacture limitations. Lateral placement of the supporting circuits on the same substrate as, and with respect to, the pixel array 150a simplifies the architecture and reduces the cost of 30 production. However, the use of a single substrate has some drawbacks and limitations, such as form factor issues, because not all applications lend themselves to a lateral or horizontal circuit placement as discussed above. As is illustrated in FIG. lb, when the support circuits, such as 110a, 120a, 130a, are removed from the first substrate 160 there remains considerable room for a larger pixel array 150a to be located on the first substrate 35 160, which means more or larger pixels can be used. Given the same physical limitations 12 WO 2012/155143 PCT/US2012/037825 in an electronic device using an imaging sensor, using the techniques and combination of features disclosed herein allows either increased pixel resolution or increased pixel size to be used. In such cases, the image sensor substrates can be reduced in size and used in more devices where size is of primary concern and yet a high quality image is desired. 5 Specifically, the figure (lb) illustrates the design concept of remotely locating support circuits 110b, 120b and 130b relative to the pixel array.

Referring primarily to FIG. 2, the use of supporting substrates to carry supporting circuits will be discussed. In an embodiment of an exemplary image sensor 200, a pixel array 205, which may comprise a plurality of pixels that are formed into a plurality of 10 pixel columns, are positioned on a surface of a first substrate 210. Each of the plurality of pixel columns located on the first substrate 210 may be electrically connected to a read bus 240. Signal processing and image enhancement may be performed by supporting circuits located on a second substrate 220. The circuits may include signal processing circuits, such as analog to digital converters 228, amplifier circuits 226, filter circuits 224, power 15 supplying and harvesting circuits 222, which may be formed into a plurality of circuit columns that correspond with the plurality of pixel columns on the first substrate 210.

Each circuit column may be comprised of a plurality of supporting circuits that is in electronic communication with a read bus 230 or plurality of read buses corresponding to each circuit column. In other words, the signal processing circuits may be located on a 20 second substrate or supporting substrate 220. Each of the plurality of circuit columns on the second substrate 220 may then be electronically connected to a corresponding pixel column located on the first substrate 210 through an interconnect, such as a solder bump, solder ball or via, which may be located anywhere along the physical path where the read buses 230, 240 are superimposed or overlap. It is also within the scope of this disclosure 25 to contemplate the use of a plurality of secondary substrates, each substrate housing any needed circuits for an image sensor and in any order or combination of supporting circuits depending upon the desired function of the image sensor.

As illustrated in FIGS. 3athrough 3f, an image sensor 300a may generally comprise a pixel array 350a and supporting circuitry 370a, which may comprise an analog 30 to digital converter 317a, an amplifier 315a, a filter 314a and a clock 316a all of which may be disposed on a monolithic substrate 310a. In FIGS. 3a and 3b, a monolithic image sensor is illustrated in a perspective view and a top view, respectively. The pixel array 350a may be comprised of a plurality of pixel columns, wherein each of the plurality of pixel columns 352a comprises a plurality of individual pixels. The supporting circuitry 35 370a may comprise a plurality of circuit columns 356a, wherein each of the circuit 13 WO 2012/155143 PCT/US2012/037825 columns 356a comprises circuitry to support a corresponding pixel column 352a. As illustrated in the figures, the monolithic circuit columns 356a are each one pixel in width and are locally located relative to a pixel column to which they correspond. The figures illustrate a pixel array of unshared pixels with one read bus per pixel column electrically 5 connected to the corresponding column circuitry on one side of the image sensor only. It will be appreciated that the corresponding circuitry is one pixel wide in the embodiment, however, other configurations of support circuitry as discussed below are contemplated within the scope of this disclosure and may be used to increase the image sensor design options, 10 Referring now to FIGS. 3c and 3d, a single pixel column 352a comprising a plurality of pixels and a single circuit column 356a are illustrated in a perspective view and a top view, respectively. It will be appreciated that the single pixel column 352a and the corresponding circuit column 356a illustrated in the figures are taken from the image sensor 300a illustrated in FIGS. 3a and 3b and simply denote a single pixel column 352a 15 electrically connected to a single circuit column 356a. FIGS. 3e and 3f illustrate a perspective view and a top view of an embodiment of an imaging sensor 300a made on a monolithic substrate and illustrating a plurality of columns comprising pixels and supporting circuitry. In contrast to FIGS. 3a and 3b, FIGS. 3e and 3f illustrate the supporting circuitry as being two pixels in width. In the figures it 20 can be seen that alternating pixel columns 352a read to corresponding circuitry located at opposing ends of the pixel columns 352a. Such a configuration offers variations in aspect ratios of corresponding circuit column 356a areas. Because the buses 330a read to alternating ends of the pixel array 350a, the circuit column 356a can be two pixels wide. Contrasting the sensors illustrated in FIGS. 3b and 3f, the pixel column 352a illustrated in 25 FIG. 3b has an aspect ratio of six pixels (units) long by one pixel wide (6/1) and the circuit column 356a has a similar aspect ratio. Conversely, the image sensor illustrated in FIG. 3f has a pixel column 352a that has an aspect ratio of six pixels (units) long by one pixel wide (6/1) and the circuit column 356a has an aspect ratio of two pixels wide and three pixels long (2/3). 30 In contrast, the same functionality of an imaging sensor 300a built on a monolithic substrate (shown in FIGS. 3a-3f) can be provided and supplied in an imaging sensor 300 that has a much smaller dimension (in at least the lateral direction and having a much smaller area and form factor) than a monolithic substrate or chip. Referring now to FIGS. 3g through 3aa, an imaging sensor 300 will be discussed that may comprise a pixel array 35 350 that may be disposed on a first substrate 310, while all of the supporting circuits 370 14 WO 2012/155143 PCT/US2012/037825 may be remotely located (with respect to the pixel array 350 and first substrate 310) to one or more supporting substrates, such as a second substrate 311 and a third substrate 312.

It should be noted that the image sensor may be built and manufactured on a plurality of substrates. Each of the plurality of substrates may be located with respect to 5 each other in a stacked configuration or formation, where all of the supporting substrates are stacked or aligned behind the first substrate 310, which comprises the pixel array 350, and relative to an object to be imaged. Each of the substrates in the stack may be electrically connected through interconnects 321, such as solder bumps or solder balls, vias or other forms of electrical communication. It will be appreciated that the 10 interconnects 321 may include any known means or method for conducting electrical signals to various circuits on the same or different substrates without departing from the scope of the disclosure.

In FIGS. 3g, 3 i, 3m, 3n, and 3u, each of the plurality of substrates comprising the pixel array 350 and the various supporting circuits 370 of the image sensor 300 may be of 15 similar size in the stack, such that the plurality of substrates may be substantially aligned within the stack. In an embodiment, the first substrate 310 and the plurality of subsequent supporting substrates 311 may be stacked in substantial alignment so that a plurality of communication columns are formed in a multi-layer stack of substantially the same length and width. 20 It should be noted that in other embodiments, where the form factor will allow it, different sized substrates having different lengths and widths may be used and may be preferred in the stack. Considerations such as heat dissipation and noise, along with many more considerations, may be accounted for when designing a stacked configuration. For example, in an embodiment, a high heat circuit, such as an amplifying circuif may be 25 placed on a protruding portion of one of the supporting substrates within a stack (illustrated best in FIG. 11).

It should be noted that a pixel array 350 may be formed in a plurality of rows of pixels and a plurality of columns of pixels. Each pixel column 352 may comprise a plurality of pixels in a linear form factor, which is one pixel wide and “N" pixels long. It 30 should be further noted that each pixel column 352 will have an area value that is generally as wide as the pixel pitch and as long as is predetermined by sensor design.

Conversely, a circuit column 356, as referred to herein, is an allocated space on a substrate, other than a first substrate 310 comprising the pixel array 350, which comprises at least one support circuit 370 that is dedicated and electrically connected to, or in 35 electrical communication with, a corresponding pixel column 352. It will be appreciated 15 WO 2012/155143 PCT/US2012/037S25 that the space occupied by the pixel column 352 may be the same as, or substantially the same as, the space occupied by the circuit column 356 that corresponds with that pixel column 352. Thus, the second or supporting substrate 311 may comprise a plurality of circuit columns 356, wherein each circuit column 356 comprises substantially the same or 5 similar real estate area on the second substrate 311 as a corresponding pixel column 352 has area on the first substrate 310.

Additionally, each pixel column 352 is or may be in electronic communication with a read bus 330 on the first substrate 310, while the circuit column 356 is or may be in electronic communication with a read bus 340 on the second substrate 311. The two 10 aforementioned buses 330, 340 may be electrically connected by at least one interconnect 321 that is located anywhere along the path created by, or within, the superimposition of or between the two buses 330, 340 as illustrated in FIGS. 3g through 3aa. In an embodiment, a plurality of interconnects 321 may be used to connect a single pixel column 352 to a single corresponding circuit column 356. In such an embodiment, the redundancy in the 15 number of interconnects 321 used may provide for increased production yield or increased functionality.

As referred to herein, aspect ratio will be used to refer to the general shape of an area on a substrate. For example, an area defined as being 4 pixel units wide and 5 pixel units long will have an aspect ratio of 4/5 or 5/4. The term aspect ratio may be used 20 generically to denote a situation where the shape of an area is considered important. For example, the concept of aspect ratio may be used to denote differences in the aspect ratios of two corresponding areas that are located on differing substrates. It should be noted that the aspect ratios of the pixel columns 352 and the circuit columns 356 illustrated in FIGS. 3g-3aa may be the same or may be different, the area of the footprint of the pixel column 25 352 and its corresponding circuit column 356 may be substantially the same or equal.

Several examples of different aspect ratios are illustrated in FIGS. 3g through 3aa, but it should be noted that the principles of this disclosure may be applied to any number of aspect ratio configurations. However, as illustrated in the figures, the area of the circuit column 356 footprint or real estate is substantially the same as or equal to the area of the 30 footprint or real estate of the pixel column 352. As manufacturing techniques improve or design parameters change more or less area may be needed for the supporting circuits 370 of foe circuit column 356.

Referring specifically to FIGS. 3g and 3h, the supporting circuitry 370, which may include an amplifier, a filter, a clock or other circuitry needed to support an image sensor, 35 may all be disposed on one or more supporting substrates, such as a second substrate 311. 16 WO 2012/155143 PCT/US2012/037825

However, it will be appreciated that such circuits may be dispersed on one or more substrates, such as the second substrate 311, or a third substrate. Additionally, an analog to digital converter may be remotely located on one of the supporting substrates. It will be appreciated that the order and location of the supporting circuits 370 may be changed and 5 may be located on any of the supporting substrates as desired.

As can be seen in the figures, each pixel column 352 may be associated and electrically connected to one read bus 330 on the first substrate 310, while each of the circuit columns 356 may be associated and electrically connected to one read bus 340 on the supporting substrate 311 by one or more interconnects 321, which may include both 10 ubumps 321a and vias 321b (illustrated best in FIG. 3h). At least one interconnect 321 may be used to connect a pixel column bus 330 on the first substrate 310 to a circuit column bus 340 on the supporting substrate 311 as illustrated. The dashed arrows in FIGS. 3i, 3j, 31, 3o, 3q, 3r, 3t, 3v, 3x, 3y and 3aa illustrate that the interconnects 321 may be located anywhere along the superimposition path of the two read buses 330 and 340 per 15 corresponding pixel column 352 and circuit column 356.

Referring now to FIGS. 3i through 3m, there is illustrated various views of an embodiment of an imaging sensor 300 built on a plurality of substrates. FIGS. 3i and 3m illustrate a plurality of pixel columns 352 forming the pixel array 350 on the first substrate 310 and a plurality of circuit columns 356 (that represent the supporting circuitry 370) on 20 the second substrate 311. As illustrated, the circuit columns 356 may be one pixel in width and (fN” number of pixels long to correspond directly with the pixel column 352 to which the circuit column 356 is associated. The figures show an example of a connection between each pixel column 352 to its associated circuitry 370 in a circuit column 356.

The figures also show one read bus 330 per pixel column 352 and one read bus 340 per 25 circuit column 356, where the associated circuitry 370 in a circuit column 356 is one pixel column wide.

As noted herein above, each pixel column 352 may be electrically associated or connected to one pixel column bus 330, and each circuit column 356 may be electrically associated or connected to one circuit column bus 340. FIGS. 3j through 31 illustrate a 30 perspective view, a front view and a side view, respectively, of a single pixel column 352 and a single circuit column 356 separated from the plurality of pixel columns 352 and plurality of circuit columns 356 illustrated in FIG. 31. FIGS. 3j through 31 further illustrate the electrical connection between the buses 330 and 340 of the pixel column 352 and the circuit column 356 using one or more interconnects 321. While the buses 330 and 340 35 may be electrically connected using one or more interconnects 321, the figures illustrate 17 WO 2012/155143 PCT/US2012/037825 that the interconnect 321 may be located anywhere along the superimposed path of the buses 330 and 340 without departing from the spirit or scope of the disclosure.

Referring now to FIG. 3n through 3t, there is illustrated various views of an embodiment of an imaging sensor 300 built on a plurality of substrates, wherein a plurality 5 of pixel columns 352 forming the pixel array 350 are located on the first substrate 310 and a plurality of circuit columns 356 are located on a second substrate 311.. In this embodiment, the circuit columns 356 may be two pixels or two pixel columns in width. In this example, the connection between each pixel column 352 to its associated circuitry 370 in a corresponding circuit column 356 may be one read bus 330, 340 per pixel column 352 10 and circuit column 356. As can be seen in the figure, the area consumed by the pixel column 352 on the first substrate 310 corresponds to an area consumed by a corresponding circuit column 356. Such correspondence allows for direct overlay of the substrates, for example 310 and 311, such that support circuits 370 in a circuit column 356 are directly stacked with the pixel column 352 they support. 15 It should also be noted that in such a configuration, the aspect ratio of the pixel column 352 will be substantially equal to the aspect ratio of the circuit column 356, however such aspect ratio equality is not required as discussed further below. As can be seen in FIG. 3m the pixel column is one pixel column wide and six pixels long, so the aspect ratio is 1/6, The circuit column also has the same aspect ratio of 1/6. In contrast, 20 FIG. 3n illustrates a design wherein the circuit column aspect ratio is twice as wide as the pixel column aspect ratio, but is only half as long, thereby providing a possibly more usable footprint in which to place supporting circuits. In both FIGS. 3m and 3n, the area of the footprint of both the pixel column 352 and the circuit column 356 is substantially equal to each other even though the aspect ratios are different. 25 FIG. 3n also illustrates how differing aspect ratios between the substrates can allow for flexibility in bus contact points. In the embodiment, the column circuit bus 340 has been designed with a general “u” shape that so as to occupy the area of the circuit column 356 more evenly, thereby providing options for connecting the interconnect 32 lthroughout the entire circuit column 356. Note that the pixel column bus 330 is not generally u- 30 shaped, but the circuit column bus 340 may be generally u-shaped, so that the same column circuit 356 may be used with the two different pixel column configurations of FIGS. 3o and 3r. The first leg of the u-shaped circuit column bus 340 may be superimposed to the read bus 330 of the first pixel column 352 (as illustrated in FIG. 3o) and the second leg of the u-shaped circuit column bus 340 may be superimposed to the 35 read bus 330 of the next, adjacent pixel column 352 (as illustrated in FIG. 3r). FIG. 3o 18 WO 2012/155143 PCT/US2012/037825 and FIG. 3r illustrate pixel columns 352 taken from the pixel array 350 of FIG. 3n. FIG. 3o and FIG. 3r illustrate three options for interconnect 321 positioning within the circuit column 356 footprint. In should be noted, as illustrated in FIG. 3q, that because the aspect ratio of the circuit column 356 is illustrated as being twice as wide, but one half the length 5 ofthe corresponding pixel column 352, the interconnect 321 location options are only available for a portion of the pixel column 352 length. FIG. 3p illustrates that for a complex bus shape there may be two interconnect location path options along a bus 340 in a circuit column 356 having twice the width of the pixel column 352 it supports. FIG. 3p illustrates a front view of the superimposition of the first leg of the u-shaped circuit 10 column bus 340 to the read bus 330 of the first pixel column 352 and uses the outer most portion of the bus 340 for locating the interconnect 321 as opposed to the innermost portion of the bus 340 as illustrated in FIGS. 3r and 3s for locating the interconnect 321 to the next, adjacent pixel column 352. FIG. 3r illustrates the next pixel column 352 located to the left of and relative to the first pixel column illustrated in FIGS. 3n (right most pixel 15 column) and 3o. The bus 330 of the second pixel column 352 illustrated in FIG. 3r may be electrically connected to the second leg of the bus 340 as illustrated. It should be noted that because the footprint ofthe circuit column 356 has an aspect ratio of 2/3, the superimposition ofthe pixel column bus 330 to the circuit column bus 340 requires the second leg of the circuit column bus 340 to be generally u-shaped to thereby allow a 20 natural match or super imposition ofthe buses 330 and 340 with respect to the next pixel column 352 illustrated in FIGS. 3r and 3s. FIG. 3u illustrates a perspective view of an embodiment of an imaging sensor 300 built on a plurality of substrates wherein a plurality of pixel columns 352 forming the pixel array 350 are located on die first substrate 310 and a plurality of circuit columns 356 are 25 located on a second substrate 311, wherei n the circuit columns 3 5 6 are four pixels in width, but are also one fourth the length. The figure also illustrates a plurality of electrical connections and communication paths between the plurality of pixel columns 352 and associated or corresponding columns 356 of circuitry. FIG. 3v illustrates a perspective view of a single column of pixels 352 and a single 30 column of circuitry 356 taken from the right most column of FIG. 3u showing an electrical connection therebetween and an illustrative bus configuration to accommodate the architecture. As can be seen in the figure, an embodiment may comprise a pixel column 352 (and associated bus 330) that has a minimal portion of overlay with a corresponding circuit column 356 (and associated bus 340). in other words, very little bus 19 WO 2012/155143 PCT/US2012/037825 superimposition is required between substrates. However, as illustrated in FIG. 3u, there may be superimposition on the substrate level. FIG. 3w illustrates a front view of the single column of pixels 352 and the single column of circuitry 356 taken from FIG. 3v showing an electrical connection 5 therebetween. As can be seen in the figure, only a small lateral portion of bus superimposition is needed to connect the pixel column 352 to the circuit column 356. FIG. 3x illustrates a side view of the single column of pixels 352 and the single column of circuitry 356 taken from FIG. 3v showing an electrical connection therebetween. As can be seen in the figure, one or more interconnects 321 can be used in 10 some embodiments and the figure also illustrates that the placement of the interconnects 321 may be anywhere along the superimposition of the buses 330 and 340. FIG. 3y illustrates a perspective view of a single column of pixels 352 and a single column of circuitry 356 taken from the column to the left of, and adjacent to, the right most column 356 of FIG. 3u showing an electrical connection therebetween. FIG. 3z 15 illustrates a front view of the single column of pixels 352 and the single column of circuitry 356 taken from FIG. 3y showing an electrical connection therebetween. FIG. 3v and FIG. 3y illustrate pixel columns 352 taken from the pixel array 350 of FIG. 3u. FIG. 3v and FIG. 3y illustrate two options for interconnect 321 positioning within the circuit column 356 footprint. It should be noted, as illustrated in FIG. 3aa, that because the 20 aspect ratio of the circuit column is wider, but shorter than that of the corresponding pixel column 352, the interconnect location options are only available for a portion of the pixel column 352 length. FIG. 3z illustrates that for a complex bus shape there may be four interconnect location path options along a bus 340 in a circuit column 356 having four times the width and one fourth the length of the pixel column 352 it supports. Thus, it can 25 be seen that while the aspect ratio of the circuit column 356 is different than the aspect ratio of the-pixel column 352, the areas of the respective footprints are substantially the same or equal. As manufacturing techniques improve or design parameters change more or less area may be needed for the supporting circuits of the circuit column 356. FIGS. 3v and 3w illustrate the superimposition of the first pixel column read bus 30 330 with the first leg of the circuit column read bus 340. FIG. 3y illustrates the next, adjacent pixel column relative to the pixel column illustrated in FIG. 3v. It should be noted that because the footprint of the circuit column 356 has an aspect ratio of 4/2, the superimposition of the pixel column bus 330 to the circuit column bus 340 requires the second leg of the circuit column bus 340 to be shaped accordingly to thereby allow a 35 natural match or superimposition of the buses 330 and 340 with respect to the next pixel 20 WO 2012/155143 PCT/US2012/037825 column 352 illustrated in FIGS. 3y and 3z FIG. 3aa illustrates a side view of the single column of pixels and the single column of circuitry taken from FIG. 3y showing an electrical connection therebetween.

It will be appreciated that each of the pixel columns may be shared or unshared 5 with respect to a read bus, depending upon the conditions present that may affect pixel design and architecture. Illustrated in FIGS. 12 and 13 are two examples of pixel architecture. FIG. 12 illustrates a pixel architecture where each pixel column does not share a read bus with another pixel column. This example, when there is only one read bus per pixel column, illustrates an unshared pixel architecture. Conversely, illustrated in 10 FIG. 13 is a horizontal 2-way pixel share. In FIG. 13, there is only one read bus per two pixel columns. Note that the number of read buses per pixel column may be an important consideration in embodiments where the pixel array 350 is optimized on a first substrate and separated from the majority of the supporting circuitry located on a second or supporting substrate in a three dimensional stacking embodiment as discussed herein. 15 It should be noted that it is within the scope of the disclosure to allow for a plurality of pixel columns to correspond to a set of support circuits in a circuit column.

For example, because the processing power of some support circuits may be greater than what is required by the data generated by a pixel column, a plurality of pixel columns may correspond to a circuit column. The converse is also contemplated herein, wherein certain 20 embodiments a plurality of circuit columns may correspond to a single pixel column in a pixel array.

In an embodiment of the specific process and implementation described above, the connection may be done though an interconnect, such as a ubump, located between the two substrates/ehips. Both metal layers of the two substrates/chips may face each other, 25 therefore back side illumination may be needed on the CMOS image sensor chip comprising the pixel array (front-side of the first chip may be bonded to front-side of the second chip). In an embodiment, there may be only one interconnect used per column 352, 356 between the first substrate/chip and the second substrate/chip. In an embodiment, two or more interconnects may be used per column 352, 356 and may be 30 used for redundancy purposes (process yield), Compared to conventional technology (monolithic CMOS image sensor as shown in FIGS. 3a through 3f), the read bus may be broken at the edge of the pixel array and may be replicated in the second substrate/chip, A bump may then connect the two buses anywhere within the column. It will be appreciated that more interconnects, such as ubumps, may be needed for power distribution between 35 the two or more substrates/chips or for other signals (e.g., vertical decoder). 21 WO 2012/155143 PCT/US2012/037825

Referring now to FIG. 4, an embodiment of an image sensor with its pixel array and supporting circuitry built on a plurality of substrates is illustrated using backside illumination. As can be seen in the figure, a pixel array 450 may be disposed on a first substrate 452. The first substrate 452 may be made of silicon or of another material in 5 order to control light transmission characteristics. Solder balls, bumps or vias 421 may be used to electrically connect one substrate to another. An embodiment of a stacked image sensor may comprise a pixel array 450 on a first substrate 452. The pixel array 450 may cover at least forty percent of a first surface 451 of the first substrate 452. In a backside illuminated configuration, a pixel array 950 may be disposed on the backside of said first 10 substrate 952 as illustrated best in FIG. 9. Further, in a back side illumination configuration the substrate 452 may be thinned for controlling light transmission therethough. In an embodiment utilizing backside illumination, the first substrate may be made of primarily silicon material, or the first substrate may be made of primarily of “High-Z” semiconductor material (Cadmium Telluride e.g.), or the first substrate may be 15 made primarily of III-V semiconductor materials (Gallium Arsenide e.g.).

In an embodiment, a pixel array 450 may cover a majority of the first surface 451 of a first substrate 452. In such an embodiment the pixel array 450 may be situated or located on any portion of said first surface 451. The remaining space on the first surface 451 may be used for secondary circuit placement if desired. Situations may arise where a 20 secondary circuit may be sized such that central placement of the pixel array is not practical.

Referring now to FIG. 5, an embodiment will be discussed wherein at least some of the supporting circuitry and components are remotely located from other supporting . circuitry and components in order to work for a predetermined purpose. For some 25 applications, it may be desirous for certain secondary processors to be more remotely located from the pixel array. For example, in a medical scope such as an endoscope there may not be enough room around the pixel array to contain all of the needed support circuitry, In such cases, the pixel array containing substrate 510 may be remotely located a distance away from other supporting substrates within the image sensor 500. 30 In an embodiment, the pixel array containing substrate 510 may be adjacent to or near a support substrate 520 that is located remotely with respect to the pixel array containing substrate. The support substrate 520 may comprise an amplifier circuit thereon, while other supporting circuits may be more remotely located on another substrate 530 a distance that is farther away from the pixel array substrate 510 than the distance support 35 substrate 520 is located away from the pixel array substrate 510. In an embodiment the 22 WO 2012/155143 PCT/US2012/037825 more remotely located substrate 530 may be connected to the other substrates in the image sensor 500 by wire vias 522 or may communicate wirelessly with the other substrates and circuits. Adjacent substrates may be connected to each other by way of bumps or solder balls 521. As pixel arrays and other circuits become more efficient over time, it is within 5 the scope of this disclosure to provide an image sensor wherein the pixel array containing substrate is more remote from all other support circuits. Such a circuit is pictured in FIG. 10, wherein a pixel array containing substrate 1010 is more remotely located by way of vias 1022 from support substrates 1020, 1030, 1040 each comprising support circuits such as signal processing circuits and power circuits. 10 In an embodiment, the pixel array of an image sensor may dominate a large percentage of the available surface area of a first substrate 570. As can be seen in FIG. 6, various sized pixel arrays 572, 574, 576 (shown in dashed lines) are contemplated by the disclosure and fall within the scope of the design disclosed. Pixel array 576 schematically represents a configuration wherein the pixel array 576 covers a large percentage of a first 15 substrate 570, but yet may not cover a majority of the substrate 570. Pixel array 576 may cover such a large percentage of the available area, even though not a majority of the area, such that at least some of the supporting circuitry may not be located on the first substrate 570.

Pixel array 574 schematically illustrates a separate configuration from pixel array 20 576 and 572, wherein the pixel array 574 covers approximately half of a first substrate 570. Pixel array 572 schematically illustrates a separate configuration from pixel array 576 and 574, wherein the pixel array covers a clear majority of the first substrate 570. It should be apparent from the discussion above that the optimization process may allow for finding a pixel array size that provides the best possible image and image quality while 25 working within constraints dictated by an application, function or purpose. Accordingly, even in an application having an imaging sensor with a fixed first substrate size, the percentage of the surface area occupied by the pixel array located on the first substrate may differ and cover many different percentages of the total surface area available on the first substrate. 30 Thus, it will be appreciated that the surface area that the pixel array may occupy may fall within a range that is about 25% to about 99% of the total surface area of one of the surfaces of the first substrate, or may be within a range of about 40% to about 99% of the total surface area of one of the surfaces of the first substrate, or may be within a range of about 50% to about 99% of the total surface area of one of the surfaces of the first 35 substrate, or may be within a range of about 60% to about 99% of the total surface area of 23 WO 2012/155143 PCT/US2012/037825 one of the surfaces of the first substrate, or may be within a range of about 70% to about 99% of the total surface area of one of the surfaces of the first substrate, or may be within a range of about 80% to about 99% of the total surface area of one of the surfaces of the first substrate, or may be within a range of about 90% to about 99% of the total surface 5 area of one of the surfaces of the first substrate. It will be appreciated that all percentages that fail within the stated ranges are intended to fall within the scope of the disclosure. It will further be appreciated that all sub-ranges falling within the range of about 25% to about 99% of the total surface area of one of the surfaces of the first substrate are intended to fail within the scope of the disclosure. 10 Because of the nature of a backside illuminated pixel array, the substrate surfaces discussed above may be extraneous to an image sensor comprising a backside illuminated pixel array. Thus, in backside illuminated applications, the substrate surface may be eliminated or formed integrally with the pixel array.

Pixel array coverage or surface area may be within a range of about 40% to about 15 70% of the total surface area of the substrate upon which the pixel array resides, and in such cases it may be possible to place some support circuitry thereon without diminishing from the design of the image sensor. In an embodiment, a light emitting circuit may occupy some space on the first substrate to provide light during use. For many applications, where dimensions are extremely tight and are the most tightly constrained, an 20 optimized imaging sensor may cover 90% or more, up to substantially all of a surface area of a first substrate. It should be noted that it is within the scope of this disclosure to contemplate a pixel array having an integrated substrate therein rather than being added to a substrate.

Illustrated in FIG. 7 is an embodiment of an imaging sensor having a plurality of 25 pixel arrays. As can be seen in the figure, an image sensor 700 may comprise a first image sensor 710 and a second image sensor 711, which are in electrical communication with a substrate 715 or a plurality of substrates that may be stacked vertically or otherwise with respect to an object to be imaged. In an embodiment, supporting circuits may be remotely located on subsequent or supporting substrates as discussed above. Such a configuration 30 may be desirable for three dimensional image capture, wherein the two pixel arrays may be off set during use. In another embodiment, a first pixel array and a second pixel array may be dedicated to receiving a predetermined range of wave lengths of electromagnetic radiation, wherein the first pixel array is dedicated to a different range of wave length electromagnetic radiation than the second pixel array. 24 WO 2012/155143 PCT/US2012/037825

Illustrated in FIGS. 14 and 15 is an embodiment for retrieving data from a pixel array 1510 that has been optimized on a first substrate 1552 (see FIG. 15) with supporting circuitry 1520 for an image sensor 1500 located on one or more second, or supporting, substrates 1554 (sec FIG. 14), which may be configured in a stacked configuration (FIGS. 5 14 and 15 combined). As can be seen in the figures, a pixel array 1510 may be located on the first substrate 1552 and may be electrically connected to support circuits 1520 that may reside on one or more subsequent or supporting substrates 1554 (FIG. 14) with one or more interconnects 1521. In the embodiment illustrated in FIGS. 14 and 15, the pixel array 1510 may be comprised of a plurality of pixel columns 1550a-f. Each of the pixel 10 columns 1550a-f may be comprised of a plurality of individual pixels and the pixel columns 1550a-f may be read through corresponding pixel column buses 1551. It will be appreciated that there may be one read bus 1551 per pixel column 1550 within the entire pixel array 1510. It should be noted that the plurality of individual pixels 1526 may be formed in columns (y axis) and rows (x-axis) that denote or define the position of the 15 individual pixel 1526 within the pixel array 1510.

As illustrated in the figures, each of the plurality of pixel column read buses 1551 may provide an electrical connection for a predetermined or defined pixel column 1550, such as 1550a, 1550b, 1550c, 1550d, 1550e, and 1550f in FIG. 15. In such an embodiment, data collected from, the pixels 1526 within the predetermined or defined 20 pixel column, for example 1550a, may be transmitted to support circuits 1520 located on one or more second, subsequent or supporting substrates 1554 via the circuit column read bus 1516 (see FIG. 14) and/or through one or more interconnects 1521. Circuits 1520 may be located on either side of the support substrate 1554 and electrical contact may be facilitated through vias disposed in the substrate material and running through the 25 substrate. The subsequent substrate 1554 may comprise a plurality of circuit columns, each circuit column comprising a plurality of circuits 1520 and a bus 1516 for electrically connecting the various circuits 1520 within the circuit column within the image sensor 1500. It should be noted that the spacing between interconnects 1521, which may be used to connect the pixel column buses 1551 to the circuit column buses 1516, has been 30 increased in the figure by staggering the interconnects 1521 relative to the pixel columns 1550a-f. The dashed lines illustrated on substrate 1554 illustrate an area on the substrate that corresponds to the area consumed by the pixel column 1550 on the first substrate 1552.

In an embodiment, it may be desirable to design an image sensor 1500 where 35 support circuits 1520 for any given pixel column 1550 are placed within a corresponding 25 WO 2012/155143 PCT/US2012/037825 area located on a second substrate. It should be noted that in an embodiment, one or more dedicated support circuits 1520 may be used per pixel column or area 1550, such that each pixel area 1550a- 1550f has at least one support circuit 1520 dedicated to processing only the data produced by the pixels 1526 within that predetermined or defined pixel column 5 represented by pixel columns 1550a-1550f to which the support circuit is dedicated. For example, each pixel column area 1550a- 1550f may have a dedicated analog-to-digital conversion circuit dedicated to converting the analog data read from the associated pixels 1526 from within the associated pixel column 1550. This close and direct association of dedicated circuits can be used to simplify the digital signal processing within the image 10 sensor 1500 thereby greatly simplifying the timing and serializing processes within the image sensor 1500. Such a feature can also be used to control heat production and energy consumption within the image sensor 1500.

Referring primarily to FIG. 16, a multi-substrate image sensor 1600 having a read bus configuration therein is illustrated· As can be seen in the figure, a substrate 1652 may 15 contain a pixel array 1610 and may be electrically connected to support substrates 1654 and 1656 through a plurality of pixel column read buses. Image sensor architecture can be greatly simplified by locating the support circuits on one or more subsequent substrates 1654 and 1656. The subsequent substrates 1654 and 1656 may be in close proximity to, but behind, the first substrate 1652. Support circuits 1622 and 1663 may be placed on the 20 subsequent substrates 1654 and 1656 in order to allow for the stacking of the substrates in a vertical configuration as illustrated. Through substrate vias may be used to enable front to back communication through any of the substrates. The second substrate 1654 in the stack may comprise secondary circuits that are dedicated to pixel columns 1650 located on the first substrate 1652 and electrically connected therewith. The third substrate 1654 may 25 comprise additional data processing circuits 1663 that may be dedicated to support circuits 1622 on the second substrate, and may be purposed to process data from a plurality of support circuits from the second substrate. It should be noted that circuits 1663 on the third substrate 1656 may be dedicated to a specific pixel column 1650 on the first substrate 1652, or may be dedicated to process data from a plurality of pixel columns 1650. In other 30 words, circuits 1663 located on the third substrate 1656 may directly correspond to specific circuits 1622 on the second substrate 1654 or specific pixel columns 1650 on the first substrate 1652. It should be noted that each substrate may comprise at least one bus that electronically connects circuitry on all of the substrates. Accordingly, the buses 1623a-1623c of each of the substrates may be superimposed such that interconnects 1621 26 WO 2012/155143 PCT/US2012/037825 disposed between the substrates cause electrical connection between the buses 1623a-1623c.

As can be seen in the figure, a column of pixels 1650 located on the first substrate 1652 may be electrically connected to support circuits located on one or more supporting 5 substrates 1654, 1656 through direct pixel column reading by placement of one or more strategically located interconnects 1621 within the pixel column 1650 ortho bus system 1623a-1623c. Each of the plurality of substrates 1652, 1654, and 1656 that make up the image sensor 1600 may comprise its own bus or bus system 1623a, 1623b, and 1623c, respectively. Accordingly, it may be advantageous to connect each of the buses 1623 10 together to form a bus skeletal system 1630 from one layer of substrate to the next. For example, the first substrate 1652 comprising the optimized pixel array 1610 as disclosed herein may be connected to support circuits 1622, which reside on the second, subsequent substrate 1654 through the use of interconnects 1621 located within the predetermined or defined pixel column 1650 and interconnect 1621, which may be located anywhere along 15 the path of the superimposed bus system 1623,

As illustrated, the first interconnect 1621a may be used to connect the first pixel column 1650 and pixel column bus 1623a directly to the second bus or bus system 1623b and support circuits 1622 located on the second substrate 1654, while the second interconnect 1621b may be used to connect the second bus or bus system 1623b residing 20 on the second substrate 1654 to a third bus 1623c residing on the third substrate 1656, Additionally as illustrated in FIG, 16, the bus skeletal system 1630 may be extended beyond the first and second substrates 1652 and 1654 and may continue and electrically connect the second substrate 1654 to the third substrate 1656 and so on until all substrates have been electrically connected through the bus skeletal system 1630. The bus 1623b 25 located on the second substrate 1654 may be connected to the third bus 1623c that may be located on the third substrate 1.656 and so on until all substrates have been electrically connected together. Thus, the predetermined or defined pixel column 1650 may be in electrical communication with a support circuit 1622 that may reside remote!}' on the second substrate 1654 or a support circuit 1663 that may reside remotely on the third 30 substrate 1656 through the respective buses 1623a-1623c located on the plurality of substrates.

It should be noted that because a single interconnect 1621 may be used to read a column 1650 containing a plurality of pixels, the interconnect spacing or pitch may be considerably larger than the pixel pitch of the pixel array 1610. 27 WO 2012/155143 PCT/US2012/037825

During use, data created by individual pixels on the pixel array must be processed by supporting circuitry, as such each pixel 1726 must be electronically connected to the supporting circuits 1770 on the second substrate 1754. Ideally each pixel could be read simultaneously thereby creating a global shutter. Referring now to FIG. 17a, it will be 5 appreciated that the ability to read data from an imaging device as a global shutter requires that there be one interconnect 1724 per pixel 1726, which is very difficult to achieve in practice because of the bumping pitch in manufacturing tolerances. FIG. 17b illustrates a situation where the pixels 1726 have been formed in columns 1728, where the bump pitch requirements remain the same in the horizontal direction. A bump pitch of about 5pm is 10 required for pixels near that size, whereas utilizing three dimensional stacking technology and interconnect staggering disclosed herein may allow for a bump pitch of about 20pm to about 200 pm in actual production. Therefore, a very high frame rate rolling type shutter that also uses the stacking technology in three dimensions may be considered a substantial improvement. In the case of a rolling shutter, only one interconnect/bump 1724 per pixel 15 column 1728 is required instead of one interconnect/bump 1724 per pixel 1726. FIG. 17a illustrates a bumping configuration or scheme using one bump 1724 per pixel 1726, which approximates a global shutter operation. In this configuration, the bump pitch equals or substantially equals the pixel pitch in both the X and Y axes or directions. 20 FIG. 17b illustrates a bumping configuration or scheme using one interconnect/bump 1724 per pixel column 1728. This configuration may be used in a rolling shutter operation. This bump pitch configuration or scheme is more relaxed as compared to the bump pitch of FIG. 17a in the vertical direction only. However, it should be noted that in this configuration the bump pitch is still required to be at least the same in 25 one direction or dimension as the pixel pitch. FIG. 17b illustrates a plurality of columns 1728, where each column 1728 is comprised of a plurality of pixels 1726. Each column of pixels may run in the Y direction (y-axis) for a distance and may be one pixel in width as illustrated. Each column of pixels may be read through a single connection point at one end of each column 1728. Although such a configuration simplifies chip architecture, 30 tight tolerances must still be maintained because the distance between pixels laterally (horizontally) continues to limit bump (interconnect) pitch because the interconnect must not make contact with a neighboring interconnect and must be sized accordingly. FIG. 17c, illustrates a bumping configuration that is even further relaxed than that shown in FIG. 17a or 17b. In this figure, the bump pitch is relaxed and half of the 35 interconneets/bumps 1724 can be processed at each side of the pixel array 1710 by adding 28 WO 2012/155143 PCT/US2012/037825 or introducing a second set of interconnects 1724 at alternating and opposing ends of the columns 1728. As can be seen in FIG. 17c, the second set of interconnects may be used in combination with the first set of interconnects and may be employed to allow half of the data to be processed or read at each side of the pixel array 1710. Such a configuration 5 may allow for nearly double the size of bump pitch (interconnect) as compared to the pixel pitch in at least one dimension, which would greatly decrease the cost of producing image sensors 1700. In an embodiment, more than one interconnect or bump 1724 per pixel column 1728 may be utilized, such that data may be read from either end of the pixel column 1728. 10 FIGS. 18a-18f illustrate embodiments and configurations of a pixel array 1810 having staggered interconnect or bump 1824 positioning on a substrate/chip. As noted above, because there is one read bus per pixel column 1828 and one read bus per circuit column, and because the read buses run from the top of the column to the bottom of the column, the interconnect/bump 1824 may be placed anywhere along the superimposed 15 path of the buses within the column. In order to relax the bumping pitch, the bump distance may be increased from column to column by shifting the next column bump 1824 either up or down (in the Y direction) in the next column.

By way of example, it will be appreciated that pixel pitch may be about 5 pm and pixel column may be any length, for example between about 2mm and about 15mm long. 20 It should be noted that bump pitch is a function of pixel pitch, such that the pixel pitch will be determinative of an ideal bump pitch. For example, assuming there is a desired bump pitch of approximately 100pm, placing a first interconnect or bump 1824 may then be accomplished by starting at the top of the first column and shifting down the next column interconnect or bump by 100pm. All other bumps are similarly positioned until the 25 interconnect or bump in the 20th column of the line will be located at the bottom of the pixel column. At that point, the interconnect or bump in the 21st column may again be placed at the top of the pixel column. This same pattern may then be repeated until the end of the pixel array. Horizontally, the interconnects or bumps may be separated by 20 columns x 5pm = 100pm. In this example, all bumps will then be separated by more than 30 100pm, even though the pixel pitch is about 5pm. Redundancy can then be introduced in the pixel column for yield purposes. For example, bumps in all columns can be doubled (i.e., the two read buses are attached by 2 interconnects or bumps). This technique would significantly increase stacking yield and lower the cost of the overall process. 29 WO 2012/155143 PCT/US2012/037825

As can be seen in FIG. 18a, a first column 1828 of pixels 1826 may be electrically accessed via a first interconnect 1824a. In the embodiment, a second pixel column 1830 may be electrically accessed through a second interconnect 1824b, which has been positioned during manufacture in a staggered configuration relative to said first 5 interconnect 1824a. As illustrated, the location or position of the second interconnect 1824b may be at least two pixel widths away from the position of the first interconnect 1824b (and from any other interconnect 1824) in both the X and Y dimensions or directions. A third interconnect . 1824c may then be positioned in like manner in a third pixel column and so on for N-number of interconnects 1824 across the pixel array 1810. 10 Such a configuration provides for an interconnect pitch that is at least three times that of the pixel pitch. It will be appreciated that the gain in interconnect pitch may be much greater than three times that of the pixel pitch under standard conditions. However, it will be appreciated that the gain in interconnect pitch may be at least three times the pixel pitch as noted above. 15 Likewise, greater interconnect gains may be made with area based spacing rather than column-by-column based connectivity (see figures and discussion relating to FIGS. 3m, 3n and 3u, which illustrate a pixel column aspect ratio of 6/1 and circuit column aspect ratio of 6/1 (for FIG. 3m) and 3/2 (for FIG. 3n), and a pixel column aspect ratio of 8/1 and circuit column aspect ratio of 2/4 (for FIG. 3u)). This can be accomplished with 20 the addition of more bus structures or use of direct reading to a subsequent substrate. In either configuration, the interconnect pitch may be described thusly:

Interconnect _ Pitch = A * PixelPitch^y + (Af * PixelPitchy'}2 whereN is the number of pixels between two adjacent interconnects in the X-direction and M is the number of pixels between two adjacent interconnects in the Y-direction. It will be appreciated that 25 each of the plurality of interconnects may be a bump where the bump to bump distance may be greater than two pixels in width, or greater than four pixels in width, or greater than eight pixels in width.

In many applications, the N x Pixel Pitch in the X direction will be equal to M x Pixel Pitch in the Y direction. As illustrated in FIGS. 18b-18fi larger pixel arrays 1810 30 may be accommodated or designed by extrapolating the above described process through additional iterations. FIG. 18b illustrates a superimposed silicon substrate stack. In the figure, a first substrate 1852 consisting of a pixel array is shown overlaid on top of a support substrate 1854 that comprises support circuits. The area available for locating support circuits for a first pixel column 1881 is outlined in dashed lines and labeled for the 30 WO 2012/155143 PCT/US2012/037825 sake of simplicity and discussion. It will be appreciated that the actual area of the circuit column is not represented by the dashed lines, but may be greater than, less than or the same as the area of the pixel column. As discussed above, the support circuit area directly correlates to the area of a pixel column to which they correspond. Each pixel column may 5 be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. In FIG. 18b the area available for support circuit placement may be equal to one pixel unit wide by sixty-four pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect 1824 between the substrates in FIG. 18b must fall somewhere within the sixty-four pixel unit area in 10 order to read that column, since the pixel column read bus and the column circuit read bus are superimposed along the path of the sixty-four pixels, such that the interconnect 1824 may be placed anywhere along those sixty-four pixels to connect the read buses.

Moreover, because the interconnect can happen only where the pixel column read bus and the support circuit read bus superimpose, the interconnect range in order to read 15 the corresponding pixel column is 1 pixel wide and 64 pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.

It should be noted that the exemplary aspect ratio of the support circuit area in FIG. 18b is illustrated as 1/64. There are many options to locate or place the interconnect 1824 within that area and the ultimate location may then be chosen by the designer so as to 20 allow the desired spacing from interconnect to interconnect. For example, as illustrated best in FIGS. 18b-18f, it will be appreciated that in an embodiment in which the interconnects or bumps 1824 are in a staggered configuration, there may be one interconnect or bump 1824 per group of pixels 1826.

Additionally, it should be noted that various read bus architectures may be utilized 25 depending on the desired application. As discussed above, larger dedicated support circuits may be employed to process the data read through each interconnect 1824. The staggering of the position of each interconnect/bump 1824 may also provide even greater space for support circuits relative to each area or group of pixels within the pixel array 1810. 30 It should also be noted that many optimum staggering configurations have been found for the same base sensor with different support circuit aspect ratios as illustrated in FIGS. 18b to 18T An optimum configuration can be found by varying the position of the interconnect within the range of the intercept between the pixel column and the support circuit and the pattern of the allocation of the support circuit to each pixel column. It 31 WO 2012/155143 PCT/US2012/037825 should also be noted that all interconnects illustrated in FIGS. 18b to 18f are more than 7 pixels in distance away from each other, in FIG. 18c the area available for support circuit placement may be equal to two pixel units wide by thirty-two pixel units long, which is shown as the heavier vertical lines 5 in the figure. Therefore, the interconnect between the substrates 1852andl854 must fall somewhere in the sixty-four pixel unit area in order to read that column. It should be noted that the aspect ratio of the support circuit area in this example is 2/32. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the 10 interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect. Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and thirty-two pixels long (for this example), which is the intercept 15 between the pixel column and the support circuit to be connected.

In FIG. 18d the area available for support circuit placement may be equal to four pixel units wide by sixteen pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel column. It should be 20 noted that the aspect ratio of the support circuit area in this example is 4/16. Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect. 25 Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and sixteen pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected. 30 In FIG. 18e the area available for support circuit placement may be equal to eight pixel units wide by eight pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect 1824 between the substrates 1852 and 1854 must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example 35 is 8/8. Each pixel column is or may be one pixel wide and sixty-four pixels long and may 32 WO 2012/155143 PCT/US2012/037825 have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect.

Moreover, because the interconnect can be located only where the pixel column 5 read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and eight pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.

In FIG. 18f the area available for support circuit placement may be equal to sixteen 10 pixel units wide by four pixel units long,, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area in order to read the corresponding pixel column. It should be noted that the aspect ratio of the support circuit area in this example is 1.6/4, this example shows the flexibility that these methods and apparatuses disclosed herein can provide. 15 Each pixel column is or may be one pixel wide and sixty-four pixels long and may have one read bus that runs from the top to the bottom of the pixel column. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect.

Moreover, because the interconnect can be located only where the pixel column 20 read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and four pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected.

It should also be noted that the pattern of the association of the support circuit to 25 the pixel column may be different than that of FIGS. 18b through 18f and such association may ultimately provide the optimal distance of the interconnects away from each other.

For example, the interconnects may be optimally placed at least two pixel widths apart, four pixel widths apart, eight pixel widths apart, or more from each other. A designer may optimally determine the distance that the interconnects may be placed apart from one 30 another based on two degrees of freedom: (1) the number of pixels per column, and (2) the circuit aspect ratio and location. In the examples shown in FIGS. 18b-18f, the interconnects 1824 may be located about eight pixels away from each other. However, it will be understood that other designs may be implemented without departing from the spirit or scope of the disclosure. 33 WO 2012/155143 PCT/US2012/037825

For example, as illustrated in FIG. 18b, each of the interconnects 1824 may be located eight pixels in length and one pixel in width away from each other. Because the circuit columns each have an aspect ratio of one pixel in width and sixty-four pixels in length, the interconnects 1824 may then be located eight pixels away from each other in 5 adjacent columns as illustrated in FIG. 18b, until the bottom of the circuit 1800 is reached, in which case the interconnects 1824 are then moved to the top of the next column and continue for the entire width of the pixel array 1810. Conversely, in FIG. 18f, the interconnects 1824 are still located eight pixels in length and one pixel in width away from each other. However, in this example, the circuit column aspect ratio is now four pixels in 10 length and sixteen pixels in width. Thus, for the interconnects 1824 to be at least eight pixels away from each other, one circuit column 1856b must be skipped since the aspect ratio is only four pixels in length, such that the interconnects 1824 maintain optimal spacing. Thus, for example, placing an interconnect 1824 in the upper left comer of the pixel array 1810 in FIG. 18f (on the first pixel of the first column 1828) and then moving IS to the next pixel column 1830 and counting down eight pixels in length, the next interconnect 1824 may then be placed in the third circuit column 1856c, skipping the second circuit column 1856b altogether. This pattern may be used throughout the pixel array. The second, skipped circuit column 1856b is then connected to the pixel array by an interconnect 1824a that is placed in the ninth pixel column and the pattern is repeated for 20 all skipped circuit columns. Thus, as illustrated, optimal interconnect spacing may be achieved and various circuit designs may be accommodated without departing from the scope of the disclosure.

Referring back to FIG. 7, in addition to the first image sensor 710 and the second image sensor 711, which are in electrical communication with a substrate 715 or a 25 plurality of substrates, there is illustrated an embodiment of an imaging sensor having a plurality of pixel arrays that may be configured with staggered interconnects as discussed herein above. Such a configuration may be desirable for three dimensional image capture, wherein the two pixel arrays may be off set during use. In another embodiment, a first pixel array and a second pixel array may be dedicated to receiving a predetermined range 30 of wave lengths of electromagnetic radiation, wherein the first pixel array Is dedicated to a different range of wavelength electromagnetic radiation than the second pixel array. FIG. 19 illustrates a design and testing methodology related to optimizing a pixel array on a first substrate. A step may be to decide on the available tolerancing differences for manufactures for an imaging sensor. A design may then be processed and bump pitch 34 WO 2012/155143 PCT/US2012/037825 may be determined for a certain criteria. A simulated test sensor may then be tested and read and redesigned if desired. FIG. 20 illustrates an embodiment having at least one dedicated support circuit for a given pixel area. A plurality of dedicated support circuits 2060a-2060f may be used in 5 an imaging device 2000 and may be stacked with respect to the pixel array 2010 according to the principles of the disclosure. The pixel array 2010 may comprise a plurality of pixel areas 2050. Each of the plurality of pixel areas, such as 2050a-2050f, may comprise at least one support circuit 2060 dedicated to processing only the data produced by the plurality of pixels 2026 within a given predetennined or defined pixel area 2050 to which 10 the dedicated circuit 2060 is devoted. For example, each pixel area 2050 may have a dedicated analog to digital conversion circuit dedicated to converting the analog data read .from the associated pixels 2026 from within the associated pixel area 2050. This close, and direct association of dedicated circuits can be used to simplify the digital signal processing within the image sensor thereby greatly simplifying timing and serializing processes 15 within the image sensor. Such a feature can be used to control heat production and energy consumption within the image sensor.

In FIG. 21 illustrates a schematically large image sensor showing the scalability of the principles and teaching of the disclosure. Each pixel column is or may be one pixel wide and one-hundred and twenty-eight pixels long. Note that this has been chosen as an 20 example for representing the teaching of the disclosure, but it should be noted that any number of pixels for the column length is possible and may be used without departing from the scope of the disclosure. It should be further noted that the number of pixels for the column length may be an even or odd number and does not have to be a power of 2. As can be seen in the figure, the area available for support circuit placement may be equal to 25 four pixel units' wide by sixteen pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area. Moreover, because the interconnect can be located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may 30 be one pixel wide and sixteen pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected. It should be noted that the aspect ratio of the support circuit area in this example is 4/16. The choice of where to place the interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect. As the figure illustrates, by 35 repeating the methods of this disclosure even the latest imaging sensor technology can be 35 WO 2012/155143 PCT/US2012/037825 used with these methods. It should also be noted that there may be a plurality of interconnects (2516 and 2518) for any give pixel column so as to allow for more flexibility (pixel column parallel processing e.g.) for large array configurations.

In FIG. 22 illustrates a schematically large image sensor showing the scalability of '5 the principles and teaching of the disclosure. Each pixel column is or may be one pixel wide and one-hundred and twenty-eight pixels long. Note that this has been chosen as an example for representing the teaching of the disclosure, but it should be noted that any number of pixels for the column length is possible and may be used without departing from the scope of the disclosure. It should be further noted that the number of pixels for 10 the column length may be an even or odd number and does not have to be a power of 2.

As can be seen in the figure, the area available for support circuit placement may be equal to two pixel units wide by thirty-two-pixel units long, which is shown as the heavier vertical lines in the figure. Therefore, the interconnect between the substrates must fall somewhere in the sixty-four pixel unit area. Moreover, because the interconnect can be 15 located only where the pixel column read bus and the support circuit read bus superimpose, in order to read the corresponding pixel column the interconnect range may be one pixel wide and sixteen pixels long (for this example), which is the intercept between the pixel column and the support circuit to be connected. It should be noted that the aspect ratio of the support circuit area is 2/32. The choice of where to place the 20 interconnect has many options within that area and could be chosen so as to allow the desired spacing from interconnect to interconnect. As the figure illustrates, by repeating the methods of this disclosure even the latest imaging sensor technology can be used with these methods. It should also be noted that there may be a plurality of interconnects (2616 and 2618) for any give pixel column so as to allow for more flexibility (pixel column 25 parallel processing e.g.) for large array configurations. It should be noted that FIGS. 21. and 22 represent the same pixel array with the only difference between the two figures is the aspect ratio of the support circuitry has changed (i.e., 4/16 aspect ratio in FIG. 21 and 2/32 aspect ratio in FIG. 22).

It will be appreciated that the structures and apparatuses disclosed herein are 30 merely exemplary for optimizing an imaging sensor, and it should be appreciated that any structure, apparatus or system for optimizing a pixel array on an image sensor using a three dimensional stacking technology and staggering the interconnects between substrates in the stack, which performs functions the same as, or equivalent to, those disclosed herein are intended to fall within the scope of this disclosure, including those structures, 35 apparatuses or systems for imaging, which are presently known, or which may become 36 WO 2012/155143 PCT/US2012/037825 available in the future. Anything which functions the same as, or equivalently to, a means for optimizing a pixel array on an image sensor using a three dimensional stacking technology and staggering the interconnects between substrates in the stack falls within the scope of this disclosure. 5 Those having ordinary skill in the relevant art will appreciate the advantages provide by the features of the disclosure. For example, it is a potential feature of the disclosure to provide an optimized pixel array on an imaging sensor, which is simple in design and manufacture. Another potential feature of the disclosure is to provide such an imaging sensor with larger pixels relative to overall size. Another potential feature is to 10 provide an optimized pixel array on an image sensor using a three dimensional stacking technology and staggering the interconnects between substrates within the stack.

In the foregoing Detailed Description, various features of the disclosure are either grouped together in a single embodiment for the purpose of streamlining the disclosure or are discussed in different embodiments. This method of disclosure is not to be interpreted 15 as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment and various inventive features disclosed in separate embodiments may be combined to form its own embodiment as claimed more fully below. Thus, the following claims are hereby 20 incorporated into this Detailed Description by this reference, with each claim standing on its own as a separate embodiment of the disclosure.

It is to be understood that the above-described arrangements are only illustrative of the application of the principles of the disclosure. Numerous modifications and alternative arrangements may be devised by those skilled in the art without departing from the spirit 25 and scope of the disclosure and the appended claims are intended to cover such modifications and arrangements. Thus, while the disclosure has been shown in the drawings and described above with particularity and detail, it will be apparent to those of ordinary skill in the art that numerous modifications, including, but not limited to, variations in size, materials, shape, form, function and manner of operation, assembly and 30 use may be made without departing from the principles and concepts set forth herein. 37