Integrated memory controller circuit for fiber optics transceiver

INTEGRATED MEMORY MAPPED CONTROLLER CIRCUIT

FOR FIBER OPTICS TRANSCEIVER

The present invention relates generally to the field of fiber optic transceivers and particularly to circuits used within the transceivers to accomplish control, setup, monitoring, and identification operations.

BACKGROUND OF INVENTION

The two most basic electronic circuits within a fiber optic transceiver are the laser driver circuit, which accepts high speed digital data and electrically drives an LED or laser diode to create equivalent optical pulses, and the receiver circuit which takes relatively small signals from an optical detector and amplifies and limits them to create a uniform amplitude digital electronic output, hi addition to, and sometimes in conjunction with these basic functions, there are a number of other tasks that must be handled by the transceiver circuitry as well as a number of tasks that may optionally be handled by the transceiver circuit to improve its functionality. These tasks include, but are not necessarily limited to, the following:

• Setup functions. These generally relate to the required adjustments made on a part-to-part basis in the factory to allow for variations in component characteristics such as laser diode threshold current.

• Identification. This refers to general purpose memory, typically EEPROM (electrically erasable and programmable read only memory) or other nonvolatile memory. The memory is preferably accessible using a serial communication standard, that is used to store various information identifying the transceiver type, capability, serial number, and compatibility with various standards. While not standard, it would be desirable to further store in this memory additional information, such as sub-component revisions and factory test data.

WO 02/063800 • Eye safety and general fault detection. These functions are used to identify abnormal and potentially unsafe operating parameters and to report these to the user and/or perform laser shutdown, as appropriate.

In addition, it would be desirable in many transceivers for the control circuitry to perform some or all of the following additional functions:

• Temperature compensation functions. For example, compensating for known temperature variations in key laser characteristics such as slope efficiency.

• Monitoring functions. Monitoring various parameters related to the transceiver operating characteristics and environment. Examples of parameters that it would be desirable to monitor include laser bias current, laser output power, received power level, supply voltage and temperature. Ideally, these parameters should be monitored and reported to, or made available to, a host device and thus to the user of the transceiver.

• Power on time. It would be desirable for the transceiver’s control circuitry to 15 keep track of the total number of hours the transceiver has been in the power on state, and to report or make this time value available to a host device.

• Margining. “Margining” is a mechanism that allows the end user to test the transceiver’s performance at a known deviation fiom ideal operating conditions, generally by scaling the control signals used to drive the transceiver s active components.

• Other digital signals. It would be desirable to enable a host device to be able to configure the transceiver so as to make it compatible with various requirements for the polarity and output types of digital inputs and outputs. For instance, digital inputs are used for transmitter disable and rate selection functions while outputs are used to indicate transmitter fault and loss of signal conditions. The configuration values would determine the polarity of one or more of the binary input and output signals. In some transceivers it would be desirable to use the configuration values to specify the scale of one or more of the digital input or output values, for instance by specifying a scaling factor to be used in conjunction with the digital input or output value,

Few if any of these additional functions are implemented in most transceivers, in part because of the cost of doing so. Some of these functions have been

WO 02/063800 implemented using discrete circuitry, for example using a general purpose EEPROM for identification purposes, by inclusion of some functions within the lasei driver or receiver circuitry (for example some degree of temperature compensation in a laser driver circuit) or with the use of a commercial micro-controller integrated circuit.

However, to date there have not been any transceivers that provide a uniform device architecture !that will support all of these functions, as well as additional functions not listed here, in a cost effective manner.

It is the purpose of the present invention to provide a general and flexible integrated circuit that accomplishes all (or any subset) of the above functionality using 10 a straightforward memory mapped architecture and a simple serial communication mechanism.

Fig. 1 shows a schematic representation of the essential features of a typical prior-art fiber optic transceiver. The main circuit 1 contains at a minimum transmit and receiver circuit paths and power 19 and ground connections 18. Thereceiver 15 circuit typically consists of a Receiver Optical Subassembly (ROSA) 2 which contains a mechanical fiber receptacle as well as a photodiode and pre-amplifier (preamp) circuit. The ROSA is in turn connected to a post-amplifier (postamp) integrated circuit 4, the function of which is to generate a fixed output swing digital signal which is connected to outside circuitry via the RX+ and RX- pins 17, The postamp circuit 20 also often provides a digital output signal known as Signal Detect or Loss of Signal indicating tine presence or absence of suitably strong optical input. The Signal Detect output is provided as an output on pin 18. The transmit circuit will typically consist of a Transmitter Optical Subassembly (TOSA), 3 and a laser driver integrated circuit 5. The TOSA contains a mechanical fiber receptacle as well as a laser diode or LED. 25 The laser driver circuit will typically provide AC drive and DC bias current to the laser. The signal inputs for the AC driver are obtained from the TX+ and TX- pins

12. Typically, the laser driver circuitry will require individual factory setup of certain parameters such as the bias current (or output power) level and AC modulation drive to the laser. Typically this is accomplished by adjusting variable resistors or placing 30 factory selected resistors?, 9 (i.e., having factory selected resistance values).

Additionally, temperature compensation of the bias current and modulation is often

WO 02/063800 PCT/US02/03226 required. This function can be integrated in the laser driver integrated circuit or accomplished through the use of external temperature sensitive elements such as thermistors 6, S.

In addition to the most basic functions described above, some transceiver platform standards involve additional functionality. Examples of this are the TX disable 13 and TX fault 14 pins described in the GBIC standard. In the GBIC standard, the TX disable pin allows the transmitter to be shut off by the host device, while the TX fault pin is an indicator to the host device of some fault condition existing in the laser or associated laser driver circuit. In addition to this basic description, the GBIC standard includes a series of timing diagrams describing how these controls function and interact with each other to implement reset operations and other actions. Most of this functionality is aimed at preventing iion-eyesafe emission levels when a fault conditions exists in the laser circuit. These functions may be integrated into the laser driver circuit itself or in an optional additional integrated circuit 11. Finally, the GBIC standard also requires the EEPROM 10 to store standardized serial ID information that can be read out via a serial interface (defined as using the serial interface of the ATMEL AT24C01A family of EEPROM products) consisting of a clock 15 and data 16 line.

As an alternative to mechanical fiber receptacles, some prior art transceivers use fiber optic pigtails which are standard, male fiber optic connectors.

Similar principles clearly apply to fiber optic transmitters or receivers that only implement half of tire full transceiver functions.

SUMMARY OF THE INVENTION

The present invention is preferably implemented as a single-chip integrated circuit, sometimes called a controller, for controlling a transceiver having a laser transmitter and a photodiode receiver. The controller includes memory for storing information related to the transceiver, and analog to digital conversion circuitry for receiving a plurality of analog signals from the laser transmitter and photodiode receiver, converting the received analog signals into digital values, and storing the digital values in predefined locations within the memory. Comparison logic compares

WO 02/063800 one or more of these digital values with limit values, generates flag values based on the comparisons, and stores the flag values in predefined locations within the memory.

Control circuitry in the controller controls the operation of the laser transmitter in accordance with one or more values stored in the memory. A serial interface is provided to enable a host device to read from and write to locations within the memory. A plurality of the control functions and a plurality of the monitoring functions of the controller are exercised by a host computer by accessing corresponding.memory mapped locations within the controller.

In some embodiments the controller further includes a cumulative clock for generating a time value corresponding to cumulative operation time of the transceiver, wherein the generated time value is readable via the serial interface.

In some embodiments the controller further includes a power supply voltage sensor that generates a power level signal corresponding to a power supply voltage level of the transceiver. In these embodiments the analog to digital conversion circuitry is configured to convert the power level signal into a digital power level value and to store the digital power level value in a predefined power level location within the memory. Further, the comparison logic of the controller may optionally include logic for comparing the digital power level value with a power (i.e., voltage) level limit value, generating a flag value based on the comparison of the digital power 20 level signal with the power level limit value, and storing a power level flag value in a predefined power level flag location within the memory: It is noted that the power supply voltage sensor measures the transceiver voltage supply level, which is distinct from the power level of the received optical signal.

Tn some embodiments the controller further includes a temperature sensor that 25 generates a temperature signal corresponding to a temperature of the transceiver. In these embodiments the analog to digital conversion circuitry is configured to convert the temperature signal into a digital temperature value and to store the digital temperature value in a predefined temperature location within the memory. Further, the comparison logic of the controller may optionally include logic for comparing the 30 digital temperature value with a temperature limit value, generating a flag value based on the comparison of the digital temperature signal with the temperature limit value,

WO 02/063800 and storing a temperature flag value in a predefined temperature flag location within the memory.

In some embodiments the controller further includes “margining” circuitry for adjusting one or more control signals generated by the control circuitry in accordance with an adjustment value stored in the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional obj ects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:

Fig. 1 is a block diagram' of a prior art optoelectronic transceiver.

Fig 2 is a block diagram of an optoelectronic transceiver in accordance with the present invention.

Fig. 3 is a block diagram of modules within the controller of the optoelectronic 15 transceiver of Fig. 2.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS A transceiver 100 based on the present invention is shown in Figs. 2 and 3.

The transceiver 100 contains a Receiver Optical Subassembly (ROSA) 102 and

Transmitter Optical Subassembly (TOSA) 103 along with associated post-amplifier 104 and laser driver 105 integrated circuits that communicate the high speed'electrical signals to tlie outside world. In this case, however, all other control and setup functions are implemented with a third single-,chip integrated circuit 110 called the controller IC.

The controller IC 110 handles all low speed communications with the end user. These include the standardized pin functions such as Loss of Signal (LOS) 111, Transmitter Fault Indication (TX FAULT} 14, and the Transmitter Disable Input (TXDIS) 13. The controller IC 110 has a two wire serial interface 121, also called the memory interface, for accessing memory mapped locations in the controller. Memory

Map Tables 1,2,3 and 4, below, are an exemplary memory map for one embodiment of a transceiver controller, as implemented in one embodiment of the present

WO 02/063800 invention. It is noted that Memory Map Tables 1,2,3 and 4, in addition to showing a memory map of values and control features described in this document, also show a number of parameters and control mechanisms that are outside the scope of this document and thus are not part of the present invention.

The interface 121 is coupled to host device interface input/output lines, typically clock (SCL) and data (SDA) lines, 15 and 16. In the preferred embodiment, the serial interface 121 operates in accordance with the two wire serial interface standard that is also used in the GBIC and SFP standards, however other serial interfaces could equally well be used in alternate embodiments. The two wire serial 10 interface 121 is used for all setup and querying of the controller IC 110, and enables access to the optoelectronic transceiver’s control circuitry as a memory mapped device. That is, tables and parameters are set up by writing values to predefined memory locations of one or more nonvolatile memory devices 120,122,128 (e.g., EEPROM devices) in the controller, whereas diagnostic and other output and status 15 values are output by reading predetermined memory locations of the same nonvolatile memory devices 120,121,122. This technique is consistent with currently defined serial ID. functionality of many transceivers where a two wire serial interface is used to read out identification and capability data stored in EEPROM.

It is noted here that some of the memory locations in the memory devices 120, 20 122,128 are dual ported, or even triple ported in some instances. That is, while these memory mapped locations can be read and in some cases written via the serial interface 121, they are also directly accessed by other circuitry in the controller 110. For instance,' certain “margining” values stored in memory 120 are read and used directly by logic 134 to adjust (i.e., scale upwards or downwards) drive level signals 25 being sent to the D/A output devices 123. Similarly, there are flags stored memory 128 that are (A) written by logic circuit 131, and (B) read directly by logic circuit 133. An example of a memory mapped location not in memory devices but that is effectively dual ported is the output or result register of clock 132. In this case the accumulated time value in the register is readable via the serial interface 121, but is 30 written by circuitry in the clock circuit 132.

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In addition to the result register of the clock 132, other memory mapped locations in the controller may be implemented as registers at the input or output of respective sub-circuits of the controller. For instance, the margining values used to control the operation of logic 134 maybe stored in registers in or near logic 134 instead of being stored within memory device 128. In another example, measurement values generated by the ADC 127 may be stored in registers. The memory interface 121 is configured to enable the memory interface to access each of these registers whenever the memory interface receives a command to access the data stored at the corresponding predefined memory mapped location. In such embodiments, “locations within the memory” include memory mapped registers throughout the controller.

In an alternate embodiment, the time value in the result register of the clock 132, or a value corresponding to that time value, is periodically stored in a memory location with the memory 128 (e.g., this may be done once per minute, or one per hour of device operation), hi this alternate embodiment, the time value read by the host device via interface 121 is the last time value stored into the memory 128, as opposed to the current time value in the result register of the clock 132.

As shown in Figs. 2 and 3, the controller IC 110 has connections to the laser driver 105 and receiver components. These connections serve multiple functions. The controller IC has a multiplicity of D/A converters 123. In the preferred embodiment the D/A converters are implemented as current sources, but in other embodiments the D/A converters maybe implemented using voltage sources, and in yet other embodiments the D/A converters may be implemented using digital potentiometers. In the preferred embodiment, the output signals of the D/A converters are used to control key parameters of the laser driver circuit 105. In one embodiment, outputs of the D/A converters 123 are use to directly control the laser bias current as well as control of the level AC modulation to the laser (constant bias operation). In another embodiment, the outputs of the D/A converters 123 of the controller 110 control the level of average output power of the laser driver 105 in addition to the AC modulation level (constant power operation).

In a preferred embodiment, the controller 110 includes mechanisms to compensate for temperature dependent characteristics of the laser. This is

WO 02/063800 implemented in the controller 110 through the use of temperature lookup tables 122 that are used to assign values to the control outputs as a function of the temperature measured by a temperature sensor 125 within the controller IC 110. In alternate embodiments, the controller 110 may use D/A converters with voltage source outputs or may even replace one or more of the D/A converters 123 with digital potentiometers to control the characteristics of the laser driver 105. It should also be noted that while Fig. 2 refers to a system where the laser driver 105 is specifically designed to accept inputs from the controller 110, it is possible to use the controller IC 110 with many other laser driver ICs to control their output characteristics.

IQ |ןן addition to temperature dependent analog output controls, the controller IC may be equipped with a multiplicity of temperature independent (one memory set value) analog outputs. These temperature independent outputs serve numerous functions, but one particularly interesting application is as a fine adjustment to other settings of the laser driver 105 or postamp 104 in order to compensate for process induced variations in the characteristics of those devices. One example of this might be the output swing of the receiver postamp 104. Normally such a parameter would be fixed at design time to a desired value through the use of a set resistor. It often turns out, however, that normal process variations associated with the fabrication of the postamp integrated circuit 104 induce undesirable variations in the resulting output swing with a fixed set resistor. Using the present invention, an analog output of the controller IC 110, produced by an additional D/A converter 123, is used to adjust or compensate the output swing setting at manufacturing setup time on a part-by־part basis.

Tn addition to the connection from the controller to the laser driver 105, Fig. 2 25 shows a number of connections from the laser driver 105 to the controller IC 110, as well as similar connections from the ROSA 106 and Postamp 104 to tlie controller IC 110. These are analog monitoring connections that the controller IC 110 uses to provide diagnostic feedback to the host device via memory mapped locations in the controller IC. The controller IC 110 in the preferred embodiment has a multiplicity of 30 analog inputs. The analog input signals indicate operating conditions of the transceiver and/or receiver circuitry. These analog signals are scanned by a

WO 02/063800 multiplexer 124 and converted using an analog to digital converter (ADC) 127, The

ADC 127 has 12 bit resolution in the preferred embodiment, although ADC’s with other resolution levels may be used in other embodiments. The converted values are stored in predefined memory locations, for instance in the diagnostic value and flag storage device 128 shown in Fig. 3, and are accessible to the host device via memory reads. These values are calibrated to standard units (such as millivolts or microwatts) as part Of a factory calibration procedure.

The digitized quantities stored in memory mapped locations within the controller IC include, but are not limited to, the laser bias cunent, transmitted laser 10 power, and received power (as measured by the photodiode detector in the ROSA 102). In the memory map tables (e.g., Table 1), the measured laser bias current is denoted as parameter B_in, the measured transmitted laser power is denoted as P_in, and the measured received power is denoted as R_1n. The memory map tables indicate the memory locations where, in an exemplary implementation, these measured values are 15 stored, and also show where the corresponding limit values, flag values, and configuration values (e.g., for indicating the polarity of the flags) are stored.

As shown in Fig. 3, the controller 110 includes a voltage supply sensor 126. An analog voltage level signal generated by this sensor is converted to a digital voltage level signal by the ADC 127, and the digital voltage level signal is stored in 20 memory 128. In a preferred embodiment, the A/D input mux 124 and ADC 127 are controlled by a clock signal so as to automatically, periodically convert the monitored signals into digital signals, and to store those digital values in memory 128.

Furthermore, as the digital values are generated, the value comparison logic 131 of the controller compares these values to predefined limit values. The limit 25 values are preferably stored in memory 128 at the factory, but the host device may overwrite the originally programmed limit values with new limit values. Each monitored signal is automatically compared with both a lower limit and upper limit value, resulting in the generation of two limit flag values that are then stored in the diagnostic value and flag storage device 128. For any monitored signals where there 30 is no meaningful upper or lower limit, the corresponding limit value can be set to a value that will never cause the corresponding flag to be set.

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The limit flags are also sometimes call alarm and warning flags. The host device (or end user) can monitor these flags to determine whether conditions exist that are likely to have caused a transceiver link to fail (alarm flags) or whether conditions exist which predict that a failure is likely to occur soon. Examples of such conditions 5 might be a laser bias current which has fallen to zero, which is indicative of an immediate failure of the transmitter output, or a laser bias current in a constant power mode which exceeds its nominal value by more than 50%, which is an indication of a laser end-of-life condition. Thus, the automatically generated limit flags are useful because they provide a simple pass-fail decision on the transceiver functionality based 10 on internally stored limit values.

In a preferred embodiment, fault control and logic circuit 133 logically OR’s the alarm and warning flags, along with the internal LOS (loss of signal) input and Fault Input signals, to produce a binary Transceiver fault (TxFault) signal that is coupled to the host interface, and thus made available to the host device. The host 15 device can be programmed to monitor the TxFault signal, and to respond to an assertion ofthe TxFault signal by automatically reading all the alarm and warning flags in the transceiver, as well as the corresponding monitored signals, so as to determine the cause of the alarm or warning.

The fault control and logic circuit 133 furthermore conveys a loss of signal 20 (LOS) signal received from the receiver circuit (ROSA, Fig. 2) to the host interface.

Another function ofthe fault control and logic circuit 133 is to disable the operation of the transmitter (TOSA, Fig. 2) when needed to ensure eye safety. There . is a standar ds defined interaction between the state of the laser driver and the Tx Disable output, which is implemented by the fault control and logic circuit 133.

When the logic circuit 133 detects a problem that might result in an eye safety hazard, the laser driver is disabled by activating the Tx Disable signal of tlie controller. The host device can reset this condition by sending a command signal on the TxDisableCmd line of the host interface.

Yet another function of the fault control and logic circuit 133 is to determine 30 the polarity of its input and output signals in accordance with a set of configuration flags stored in memory 128. For instance, the Loss of Signal (LOS) output of circuit

WO 02/063800 ' 133 may be either a logic low or logic high signal, as determined by a corresponding configuration flag stored in memory 12S.

Other configuration flags (see Table 4) stored in memory 128 are used to determine the polarity of each of the warning and alarm flags. Yet other configuration 5 values stored in memory 128 are used to determine the scaling applied by the ADC 127 when converting each of the monitored analog signals into digital values.

In an alternate embodiment, another input to the controller 102, at the host interface, is a rate selection signal. In Fig. 3 the rate selection signal is input to logic .133. This host generated signal would typically be a digital signal that specifies the 10 expected data rate of data to be received by the receiver (ROSA 102). For instance, the rate selection signal might have two values, representing high and low data rates (e.g., 2.5 Gb/s and 1.25 Gb/s). The controller responds to the rate selection signal by generating control signals to set the analog receiver circuitry .to a bandwidth corresponding to the value specified by the rate selection signal.

While the combination of all of the above functions is desired in the preferred embodiment of tins transceiver controller, it should be obvious to one skilled in the art that a device which only implements a subset of these functions would also be of great use. Similarly, the present invention is also applicable to transmitters and receivers, and thus is not solely applicable to transceivers. Finally, it should be pointed out that 20 the controller of the present invention is suitable for application of multichannel optical links.

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MEMORY MAP FOR TRANSCEIVER CONTROLLER

TABLE 1

<td> Memory Location (Array 0)</td><td> Name of Location</td><td> Function</td>

<td> OOh - 5Fh</td><td> IEEE Data</td><td> This memory block is used to store required GBIC data</td>

<td> 60h </td><td> Temperature MSB ,</td><td> This byte contains the MSB of the 15-bit 2's complement temperature output from the temperature sensor.</td>

<td> 61h</td><td> Temperature LSB</td><td> This byte contains the LSB of the 15-bit 2's complement temperature output from the temperature sensor. (LSB is 0b). __ ___</td>

<td> 62h - 63h</td><td> V_cc Value</td><td> These bytes contain the MSB (62h) and the LSB (63h) of the measured V_re (15-bit number, with a 0b LSbit)____________</td>

<td> 64h-65h</td><td> Bj״ Value</td><td> These bytes contain the MSB (6411) and the LSB (65h) ofthe measured B_h (laserbias current) (15-bit number, with a 0b LSbit)</td>

<td> 66h - 67h</td><td> Pi, Value</td><td> These bytes contain the MSB (66h) and the LSB (6711) of the measured (transmitted laser power) (15-bit number, with a 0b LSbit)</td>

<td> 68h-69h</td><td> Value</td><td> !These bytes contain the MSB (68h) and the LSB (69h) ofthe measured R^ (received power) (15bit number, with a 0b LSbit)</td>

<td> 6Ah-6Dh</td><td> Reserved</td><td> Reserved</td>

<td> 6Eh</td><td> IO States</td><td> This byte shows the logical value of the I/O pins</td>

<td> 6Fh</td><td> AZD Updated</td><td> Allows the user to verify if an update from the A/D has occurred to the 5 values: temperature, V_cc, B;״, and R״,. The user writes the byte to OOh. Once a conversion is complete for a .give value, its bit will change to‘Γ.________־</td>

<td> 70h-73h .</td><td> Alarm Flags</td><td> These bits reflect the state of the alarms as a conversion updates. High alarm bits are ‘Γ if converted value is greater than corresponding high limit. Low alarm bits are T if converted value is less than corresponding low limit. Otherwise, bits are 0b.</td>

<td> 74h-77h</td><td> Warning Flags</td><td> These bits reflect the state of the warnings as a conversion updates. High warning bits are ‘ Γ if converted value is greater than conesponding high limit. Low warning bits are ‘ 1 ’ if converted value is less than corresponding low limit. Otherwise, bits are 0b.__'</td>

<td> 78h-7Ah</td><td> Reserved</td><td> Reserved___</td>

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<td></td><td> Memory Location (Array 0)</td><td> Name of Location</td><td> Function</td>

<td> 5</td><td> 7Bh - 7Eh</td><td> Password Entry Bytes PWE Byte 3 (7Bh) MSByte PWEByte 2 (7Ch) PWE Byte 1 (7Dh) PWE Byte 0 (7Eh) LSByte</td><td> The four bytes are used for password entry. The entered password will determine the user’s read/write privileges.</td>

<td> 10</td><td> 7Fh</td><td> Array Select</td><td> Writing to this byte determines which of the upper pages of memory is selected for reading and writing. Oxh (Array x Selected) Where x = 1,2,3,4 015</td>

<td> 15</td><td> 80h-FFh</td><td></td><td> Reserved / not currently implemented</td>

<td> Memory Location (Array 1)</td><td> Name of Location</td><td> Function of Location</td>

<td> SOh-FFh</td><td></td><td> Data EEPROM</td>

<td> Memory Location (Array 2)</td><td> Name of Location</td><td> Function of Location</td>

<td> 80h-FFh</td><td></td><td> Data EEPROM _________________</td>

<td></td><td> Memory Location (Array 3)</td><td> Name of Location</td><td> Function of Location</td>

<td> 30</td><td> 80h-81h 88h-89h 90h - 91h 98h-99h A0h־Alh</td><td> Temperature High Alarm V_cc High Alarm Bi, High Alarm P_fa High Alarm Rjj, High Alarm</td><td> The value written to this location serves as the high alarm limit. Data format is the same as the corresponding value (temperature, V_C(,, B_fa, P_fa)RJ.</td>

<td> 35</td><td> 82h-83h 8Ah8־Bh 92h-93h 9Ah -9Bh A2h-A3h</td><td> Temperature Low Alarm V_־c Low Alarm Β,, Low Alarm Pi, Low Alarm Ri״ Low Alarm</td><td> The value written to this location serves as the low alarm limit. Data format is the same as the corresponding value (temperature, V_ce, Β!״ P!,, RJ.</td>

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<td> Memory Location (Array 3)</td><td> Name of Location</td><td> Function of Location</td>

<td> 84h-85h 8Ch-8Dh 94h - 95h 9Ch9־Dh A4h - A5h</td><td> Temp High Warning V_cc High Warning B_m High Warning Pi״ High Warning R״ High Warning</td><td> The value written to this location serves as the high warning limit. Data format is the same as the corresponding value (temperature, V_cc, B^, Pi־״ ^in).</td>

<td> 86h-87h 8Eh8־Fh 96h - 97h 9Eh9־Fh A6h-A7h</td><td> Temperature Low Warning V_cc Low Warning Bi״ Low Warning P_to Low Warning Low Warning</td><td> The value written to this location serves as the low warning limit. Data format is the same as the corresponding value (temperature, V_cc, B_b, Pi־״ R»).</td>

<td> A8h-AFh, C5h BOh - B7h, C6h B8h־BFh, C7h</td><td> D_out control 0-8 F_out control 0-8 L_oul control 0-8</td><td> Individual bit locations are defined, in Table 4.</td>

<td> COh</td><td> Reserved</td><td> Reserved _</td>

<td> Clh</td><td> Prescale</td><td> Selects MCLK divisor for X-delay CLKS.</td>

<td> C2h C3h C4h</td><td> D_out Delay F״״_t Delay L_out Delay</td><td> Selects number of prescale clocks</td>

<td> C8h-C9h CAh-CBh CCh-CDh CEh - CFh</td><td> V_c־ - A/D Scale Β;״ - A/D Scale Pi״ - A/D Scale Ri״ - A/D Scale</td><td> 16 bits of gain adjustment for corresponding A/D conversion values.</td>

<td> DOh</td><td> Chip Address</td><td> Selects chip address when external pin ASEL is low.</td>

<td> Dih</td><td> Margin #2</td><td> Finisar Selective Percentage (FSP) for D/A #2</td>

<td> D2h</td><td> Margin#!</td><td> Finisar Selective Percentage (FSP) for D/A #1</td>

<td> D3h־D6h</td><td> PW1 Byte 3 (D3h) MSB PW1 Byte 2 (D4h) PW1 Byte 1 (D5h) PW1 Byte 0 (D6h) LSB</td><td> The four bytes are used for password 1 entry. The entered password will determine the Finisar customer’s read/write privileges.</td>

<td> D7h</td><td> D/A Control</td><td> This byte determines if the D/A outputs source or sink current, and it allows for the outputs to be scaled. ______</td>

<td> D8h-DFh</td><td> B_b Fast Trip</td><td> ׳These bytes define the fast trip comparison over temperature. ___ ________</td>

<td> EOh־E3h</td><td> Pi״ Fast Trip</td><td> These bytes define the fast trip comparison over temperature._________________________________'</td>

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<td> Memory Location (Array 3)</td><td> Name of Location</td><td> Function of Location</td>

<td> E4h-E7h</td><td> ¾, Fast Trip</td><td> These bytes define the fast trip comparison over temperature.</td>

<td> ESh</td><td> Configuration Override Byte</td><td> Location of the bits is defined in Table 4</td>

<td> E9h</td><td> Reserved</td><td> Reserved</td>

<td> EAh-EBh</td><td> Internal State Bytes</td><td> Location of the bits is defined in Table 4</td>

<td> ECh</td><td> I/O States 1</td><td> Location of the bits is defined in Table 4</td>

<td> EDh-EEh</td><td> D/A Out</td><td> Magnitude of the temperature compensated D/A outputs</td>

<td> EFh</td><td> Temperature Index</td><td> Address pointer to the look-up Arrays</td>

<td> FOh-FFh</td><td> Reserved</td><td> Reserved ________. ____________________</td>

<td> Memory Location (Array 4)</td><td> Name of Location</td><td> Function of Location</td>

<td> OOh-FFh</td><td></td><td> D/A Current vs. Temp #1 (User-Defhied Look-up Array #1)_____________</td>

<td> Memory Location (Array 5)</td><td> Name of Location</td><td> Function of Location</td>

<td> OOh-FFh</td><td></td><td> D/A Current vs. Temp #2 (User-Defined Look-up Array #2) ___________</td>

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TABLE 2 - DETAIL MEMORY DESCRIPTIONS - A/D VALUES AND STATUS BITS

<td> Byte</td><td> Bit</td><td> Name</td><td> Description</td>

<td colspan="4"> Converted analog values. Calibrated 16 bit data.____</td>

<td> 96 (60h)</td><td> All</td><td> Temperature MSB</td><td> Signed 2's complement integer temperature (40 to +125C) Based on internal temperature measurement</td>

<td> 97</td><td> All</td><td> Temperature LSB</td><td> Fractional part of temperature (count/256)</td>

<td> 98</td><td> All</td><td> V_ceMSB</td><td> Internally measured supply voltage in transceiver. Actual voltage is full 16 bit value * lOOuVolt.</td>

<td> 99</td><td> All</td><td> V_CCLSB</td><td> (Yields range of 0 - 6.55V) ________________</td>

<td> 100</td><td> All</td><td> TX Bias MSB</td><td> Measured TX Bias Current in mA Bias current is full 16 bit value *(1/256) mA.</td>

<td> 101</td><td> All</td><td> TX Bias LSB</td><td> (Full range of 0 - 256 mA possible with 4 uA resolution)</td>

<td> 102</td><td> All</td><td> TX Power MSB</td><td> Measured TX output power in mW. Output is full 16 bit value *(1/2048) mW._________________</td>

<td> 103</td><td> All</td><td> TX Power LSB</td><td> Full range of 0 - 32 mW possible with 0.5 pW resolution, or -33 to +15 dBm)___________</td>

<td> 104</td><td> All</td><td> RX Power MSB</td><td> Measured RX input power in mW RX power is foil 16 bit value *(1/16384) mW.</td>

<td> 105</td><td> All</td><td> RX Power LSB</td><td> (Full range of 0 - 4 mW possible with 0.06 pW resolution, or -42 to +6 dBm)__________________</td>

<td> 106</td><td> All</td><td> Reserved MSB</td><td> Reserved for 1^st future definition of digitized analog input</td>

<td> .107</td><td> All</td><td> Reserved LSB</td><td> Reserved for 1^st future definition of digitized analog input</td>

<td> 108</td><td> All</td><td> Reserved MSB</td><td> Reserved for 2^nd future definition of digitized analog input</td>

<td> 109</td><td> All</td><td> Reserved LSB</td><td> Reserved for 2^nd future definition of digitized analog input____{_}________.</td>

<td colspan="4"> General Status Bits __________________________</td>

<td> 110</td><td> .ר</td><td> TX Disable</td><td> Digital state ofthe TX Disable Input Pin</td>

<td> 110</td><td> 6</td><td> Reserved</td><td></td>

<td> 110</td><td> 5</td><td> Reserved</td><td></td>

<td> 110</td><td> 4</td><td> Rate Select</td><td> Digital state ofthe SFP Rate Select Input Pin</td>

<td> 110</td><td> 3</td><td> Reserved</td><td></td>

<td> . 110</td><td> 2</td><td> TX Fault</td><td> Digital state of the TX Fault Output Pin .</td>

<td> 110</td><td> 1</td><td> LOS</td><td> Digital state ofthe LOS Output Pin</td>

<td> 110</td><td> 0</td><td> Power-On-Logic</td><td> Indicates transceiver has achieved power up and data valid _______</td>

<td> 111</td><td> ר</td><td> Temp A/D Valid</td><td> Indicates A/D value in Bytes 96/97 is valid</td>

<td> 111</td><td> 6</td><td> V_cc A/D Valid______</td><td> Indicates A/D value in Bytes 98/99 is valid</td>

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<td> Byte</td><td> Bit</td><td> Name</td><td> Description</td>

<td> 111</td><td> 5</td><td> TX Bias A/D Valid</td><td> Indicates A/D value in Bytes 100/101 is valid</td>

<td> 111</td><td> 4</td><td> TX Power A/D Valid</td><td> Indicates A/D value in Bytes 102/103 is valid</td>

<td> 111</td><td> 3</td><td> RX Power A/D Valid</td><td> Indicates A/D value in Bytes 104/105 is valid</td>

<td> 111</td><td> 2</td><td> Reserved</td><td> Indicates A/D value in Bytes 106/107 is valid</td>

<td> 111</td><td> 1</td><td> Reserved</td><td> Indicates A/D value in Bytes 108/109 is valid</td>

<td> 111</td><td> 0</td><td> Reserved___________</td><td> Reserved</td>

WO 02/1)63800

TABLE 3 - DETAIL MEMORY DESCRIPTIONS - ALARM AND WARNING FLAG BITS

<td> Byte</td><td> Bit</td><td> Name</td><td> Description</td>

<td colspan="4"> Alarm and Warning Flag Bits</td>

<td> 112</td><td> 7</td><td> Temp High Alarm</td><td> Set when internal temperature exceeds high alarm level.</td>

<td> 112</td><td> 6</td><td> Temp Low Alarm</td><td> Set when internal temperature is below low alarm level.</td>

<td> 112</td><td> 5</td><td> V_cc High Alarm</td><td> Set when internal supply voltage exceeds high alarm level.</td>

<td> 112</td><td> 4</td><td> V״ Low Alarm</td><td> Set when internal supply voltage is below low alarm level.</td>

<td> 112</td><td> 3</td><td> TX Bias High Alarm</td><td> Set when.TX Bias current exceeds high alarm level.</td>

<td> 112</td><td> 2</td><td> TX Bias Low Alarm</td><td> Set when TX Bias current is below low alarm level.</td>

<td> 112</td><td> 1</td><td> TX Power High Alarm</td><td> Set when TX output power exceeds high alarm level.</td>

<td> 112</td><td> 0</td><td> TX Power Low Alarm</td><td> Set when TX output power is below low alarm level.</td>

<td> 113</td><td> . ר</td><td> RX Power High Alarm</td><td> Set when Received Power exceeds high alarm level.</td>

<td> 113</td><td> 6</td><td> RX Power Low Alarm</td><td> Set when Received Power is below low alarm level.</td>

<td> 113</td><td> 5-0</td><td> Reserved Alarm</td><td></td>

<td> 114</td><td> All</td><td> Reserved .</td><td></td>

<td> 115</td><td> All</td><td> Reserved</td><td></td>

<td>¹¹⁶</td><td> 7</td><td> Temp High Warning</td><td> Set when internal temperature exceeds high warning level.</td>

<td> 116</td><td> 6</td><td> Temp Low Warning</td><td> Set when internal temperature is below low warning level.</td>

<td> 116</td><td> 5</td><td> V_cc High Warning</td><td> Set when internal supply voltage exceeds high warning level.</td>

<td> 116</td><td> 4</td><td> V״ Low Warning</td><td> Set when internal supply voltage is below low warning level.</td>

<td> 116</td><td> 3</td><td> TX Bias High Warning</td><td> Set when TX Bias cunent exceeds high warning level.</td>

<td> 116</td><td> 2</td><td> TX Bias Low Warning</td><td> Set when TX Bias current is below low warning level.</td>

<td> 116</td><td> 1</td><td> TX Power High Warning</td><td> Set when TX output power exceeds high warning level.</td>

<td> 116</td><td> 0</td><td> TX Power Low Warning</td><td> Set when TX output power is below low warning level.</td>

<td> 117</td><td> 7</td><td> RX Power High Warning</td><td> Set when Received Power exceeds high warning level.</td>

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<td> Byte</td><td> Bit</td><td> Name</td><td> Description</td>

<td> 117</td><td> 6</td><td> RX Power Low Warning</td><td> Set when Received Power is below low warning level.</td>

<td> H7</td><td> 5</td><td> Reserved Warning</td><td></td>

<td> 117</td><td> 4</td><td> Reserved Warning</td><td></td>

<td> 117</td><td> 3</td><td> Reserved Warning</td><td></td>

<td> 117</td><td> 2</td><td> Reserved Warning</td><td></td>

<td> 117</td><td> 1</td><td> Reserved Warning</td><td></td>

<td> 117</td><td> 0</td><td> Reserved Warning</td><td></td>

<td> 118</td><td> All</td><td> Reserved</td><td></td>

<td> 119</td><td> All</td><td> Reserved</td><td></td>

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TABLE 4

<td></td><td> Byte Name</td><td> Bit 7</td><td> Bit 6</td><td> Bit 5</td><td> Bit 4</td><td> Bit 3</td><td> Bit 2</td><td> Bitl</td><td> BitO</td>

<td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td><td></td>

<td> 5</td><td> X-out cntlO</td><td> Talrmhi set</td><td> T alrm 10 set</td><td> V alrm hi set</td><td> V alrm 10 set</td><td> B alrm hi set</td><td> B alrm 10 set</td><td> p alrm hi set</td><td> P alrm 10 set</td>

<td></td><td> X-out cntl 1</td><td> R alrm hi set</td><td> R alrm 10 set</td><td> B ft hi set</td><td> P ft hi set</td><td> R ft hi set</td><td> D-in inv set</td><td> D-in set</td><td> F-in inv set</td>

<td></td><td> X-out cntl 2</td><td> F-in set</td><td> L-in inv set</td><td> L-in set</td><td> Aux inv set</td><td> Aux set</td><td> T alrm hi hib</td><td> T alrm 10 hib</td><td> V alrm hi hib</td>

<td></td><td> X-out cntl3</td><td> V alrm 10 hib</td><td> B alrm hi hib</td><td> B alrm 10 hib</td><td> P alrm hi hib</td><td> P alrm 10 hib</td><td> R alrm hi hib</td><td> R alrm 10 hib</td><td> B ft hi hib</td>

<td></td><td> X-out ent 14</td><td> P ft hi hib</td><td> R ft hi hib</td><td> D-in inv hib ־</td><td> D-in hib</td><td> F-in inv hib</td><td> F-in hib</td><td> L-in inv hib</td><td> L-in hib</td>

<td> 10</td><td> X-out ent 15</td><td> Aux inv hib</td><td> Aux hib</td><td> T alrm hi clr</td><td> T alrm 10 clr</td><td> V alrm hi clr</td><td> V alrm 10 clr</td><td> B alrm hi clr</td><td> B alrm 10 clr</td>

<td></td><td> X-out cntl 6</td><td> P alrm hi clr</td><td> P alrm 10 clr</td><td> R alrm hi clr</td><td> R alrm 10 clr</td><td> B ft hi clr</td><td> P ft hi clr</td><td> R ft hi clr</td><td> D-in inv clr</td>

<td></td><td> X-out ent 17</td><td> D-in clr '</td><td> F-in inv clr</td><td> F-in clr</td><td> L-in inv clr</td><td> L-in clr</td><td> Aux inv clr</td><td> Aux clr</td><td> EE</td>

<td></td><td> X-out cntl 8</td><td> latch select ׳</td><td> invert</td><td> o-ride data</td><td> o-ride select</td><td> S reset data</td><td> HI enable</td><td> LO enable</td><td> Pullup enable</td>

<td></td><td> Prescale</td><td> reserved</td><td> reserved</td><td> Reserved</td><td> reserved</td><td> B³</td><td> B²</td><td> B*</td><td> B°</td>

<td> 15</td><td> X-out delay</td><td> B⁷</td><td> B⁶</td><td> B⁵</td><td> B⁴</td><td> B³</td><td> B²</td><td> B'</td><td> B°</td>

<td></td><td> chip address</td><td> b⁷</td><td> b⁶</td><td> b⁵</td><td> b⁴</td><td> b’</td><td> b²</td><td> b'</td><td> X</td>

<td></td><td> X-ad scale ' MSB</td><td> 2^1s</td><td> 2¹⁴</td><td> 2¹³</td><td> 2¹²</td><td> 2</td><td> * 2¹⁰</td><td> 2’</td><td> 2’</td>

<td> 20</td><td> X-ad scale JLSB</td><td> 2⁷</td><td> 2⁶</td><td> 2⁵</td><td> 2⁴</td><td> 2³</td><td> 2¹</td><td> 2'</td><td> 2“</td>

<td></td><td> D/A cntl</td><td> source/ sink</td><td colspan="3"> D/A #2 range</td><td> source/sink</td><td colspan="2"> D/A#l rang</td><td> 2</td>

<td></td><td></td><td> 1/0</td><td> 2²</td><td> 2'</td><td> 2°</td><td> 1/0</td><td> 2²</td><td> 2'</td><td> 2°</td>

<td></td><td> config/Oride</td><td> manual D/A</td><td> manual index</td><td> manual AD alarm</td><td> EE Bar</td><td> SW-POR</td><td> A/D Enable</td><td> Manual fast alarm</td><td> reserved</td>

<td> 25</td><td> Internal State 1</td><td> D-set</td><td> D-inhibit</td><td> D-delay</td><td> D-clear</td><td> F-set</td><td> F-inhibit</td><td> F-delay</td><td> F-clear</td>

<td></td><td> Internal State 0</td><td> L-set</td><td> L-inhibit</td><td> L-delay</td><td> L־clear</td><td> reserved</td><td> reserved</td><td> reserved</td><td> reserved</td>

<td></td><td> I/O States 1</td><td> reserved</td><td> F-in</td><td> L-in</td><td> reserved</td><td> D-out</td><td> reserved</td><td> .reserved</td><td> reserved</td>

<td></td><td> Margin #1</td><td> 1 Reserved</td><td> Neg_Scale 2</td><td> Neg_Scale “1</td><td> Neg Scale ”0</td><td> Reserved</td><td> Pos_Scale 2</td><td> Pos Scale ”1</td><td> Pos_ScaleO</td>

<td> 30</td><td> Margin #2</td><td> Reserved</td><td> Neg_Scale 2</td><td> Neg Scale 1</td><td> Neg Scale 0</td><td> Reserved</td><td> Pos_Scale 2</td><td> Pos Scale “1</td><td> Pos_ScaleO</td>