Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge

NON-VOLATILE ELECTRICALLY ERASABLE ANDPROGRAMMABLE SEMICONDUCTOR MEMORY CELLUTILIZING ASYMMETRICAL CHARGE □mwn ηρ'ηηι ηιηιύ μνιη η^ιη «χη ψ-η μτοτ njiηηυη'ΟΝ μιοη mo1? "κιηηι

Eitan, Pearl, Latzer & Cohen-ZedekAdvocates, Notaries and Patent Attorneys

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FIELD OF THE INVENTION

The present invention relates generally to semiconductor memory devices andmore particularly to flash electrically erasable programmable read only memory 5 (EEPROM) cells that utilize the phenomenon of hot electron injection to trap charge withina trapping dielectric material within the gate.

BACKGROUND OF THE INVENTION

Memory devices for non-volatile storage of information are currently inwidespread use today, being used in a myriad of applications. A few examples of 10 non-volatile semiconductor memory include read only memory (ROM), programmableread only memory (PROM), erasable programmable read only memory (EPROM),electrically erasable programmable read only memory (EEPROM) and flash EEPROM.

Semiconductor ROM devices, however, suffer from the disadvantage of notbeing electrically programmable memory devices. The programming of a ROM occursis during one of the steps of manufacture using special masks containing the data to bestored. Thus, the entire contents of a ROM must be determined before manufacture. Inaddition, because ROM devices are programmed during manufacture, the time delaybefore the finished product is available could be six weeks or more. The advantage,however, of using ROM for data storage is the low cost per device. However, the 20 penalty is the inability to change the data once the ROM has been manufactured. Ifmistakes in the data programming are found they are typically very costly to correct.Any ROM inventory that exists having incorrect data programming is instantly obsoleteand probably cannot be used. In addition, extensive time delays are incurred because new masks must first be 1

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10 15 20 25 generated from scratch and the entire manufacturing process repeated, at least from theROM programming mask step. Also, the cost savings in the use of ROM memories onlyexist if large quantities of the ROM are produced.

Moving to EPROM semiconductor devices eliminates the necessity of maskprogramming the data but the complexity of the process increases drastically. In addition,the die size is larger due to the addition of programming circuitry and there are moreprocessing and testing steps involved in the manufacture of these types of memory devices.An advantage of EPROMs is that they are electrically programmed, but for erasing,EPROMs require exposure to ultraviolet (UV) light. EPROM dice are placed in packageswith windows transparent to UV light to allow each die to be exposed for erasing, whichmust be performed before the device can be programmed. A major drawback to thesedevices is that they lack the ability to be electrically erased. In many circuit designs it isdesirable to have a non-volatile memory device that can be erased and reprogrammedin-circuit, without the need to remove the device for erasing and reprogramming.

Semiconductor EEPROM devices also involve more complex processing andtesting procedures than ROM, but have the advantage of electrical programming anderasing. Using EEPROM devices in circuitry permits in-circuit erasing andreprogramming of the device, a feat not possible with conventional EPROM memory.Flash EEPROMs are similar to EEPROMs in that memory cells can be programmed (i.e.,written) and erased electrically but with the additional ability of erasing all memory cells atonce, hence the term flash EEPROM. The disadvantage of flash EEPROM is that it is verydifficult and expensive to manufacture and produce.

The widespread use of EEPROM semiconductor memory has prompted muchresearch focusing on constructing better memory cells. Active areas of research havefocused on developing a memory cell that has improved performance characteristics such 2

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10 15 20 25 as shorter programming times, utilizing lower voltages for programming and reading,longer data retention times, shorter erase times and smaller physical dimensions. One sucharea of research involves a memory cell that has an insulated gate. The following prior art reference is related to this area. U.S. Patent No. 4,173,766, issued to Hayes, teaches a metal nitride oxidesemiconductor (MNOS) constructed with an insulated gate having a bottom silicon dioxidelayer and a top nitride layer. A conductive gate electrode, such as polycrystalline silicon ormetal, is placed on top of the nitride layer. A major disadvantage of this device is thedifficulty in using it to construct a flash EEPROM. A consequence of using anoxide-nitride structure as opposed to an oxide-nitride-oxide structure is that duringprogramming the charge gets distributed across the entire nitride layer. The absence of thetop oxide layer lowers the ability to control where the charge is stored in the nitride layer.

Further, in the memory cell disclosed in Hayes, the nitride layer is typically 350Angstroms thick. A thick nitride layer is required in Hayes' device in order to achievesufficient charge retention. Due to the thick nitride layer, very high vertical voltages areneeded for erasing. The relatively thick nitride layer causes the distribution of charge, i.e.,the charge trapping region, to be very wide and a wider charge trapping region makeserasing the cell via the drain extremely difficult if not impossible. Thus, the memory celltaught by Hayes must have a thick nitride layer for charge retention purposes but at theexpense of making it extremely difficult to erase the device via the drain, thus making thedevice impractical for flash EEPROM applications.

To erase the memory cell of Hayes, the electrons previously trapped in thenitride must be neutralized either by moving electrons out of the nitride or by transferringholes into the nitride. Hayes teaches an erase mode for his memory cell whereby theinformation stored on the nitride is erased by grounding the gate and applying a sufficient 3

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10 15 20 potential to the drain to cause avalanche breakdown. Avalanche breakdown involves hothole injection into the nitride in contrast to electron injection. Avalanche breakdown,however, requires relatively high voltages and high currents for the phenomenon to occur.To lower the avalanche breakdown voltage, a heavily doped impurity is implanted into the channel between the source and the drain.

The hot holes are generated and caused to surmount the hole potential barrier ofthe bottom oxide and recombine with the electrons in the nitride. This mechanism,however, is very complex and it is difficult to construct memory devices that work in thismanner. Another disadvantage of using hot hole injection for erase is that since the PNjunction between the drain and the channel is in breakdown, very large currents aregenerated that are difficult to control. Further, the number of program/erase cycles that thememory cell can sustain is limited because the breakdown damages the junction area. Thedamage is caused by the very high local temperatures generated in the vicinity of thejunction when it is in breakdown.

In addition, it is impractical to use the memory device of Hayes in a flash memoryarray architecture. The huge currents generated during erase using avalanche breakdownwould cause significant voltage (i.e., IR), drops along the bit line associated with thememory cell in breakdown.

Another well known technique of erasing is to inject holes from the gate into thenitride layer. This mechanism, however, is very complex and difficult to control due to thehigher mobility of holes versus electrons in the nitride. With elevated temperatures, thehigher mobility of holes causes a large loss of charge retention and consequently lowerthreshold voltage deltas. Deep depletion phenomenon create the need for a companionserial device to control the programming/erase process. 25 4

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10 15 20 U.S. Patent No. 5,168,334, issued to Mitchell et al., teaches a single transistorEEPROM memory cell. Mitchell, however, teaches an oxide-nitride-oxide (ONO)EEPROM memory cell wherein oxide-nitride-oxide layers are formed above the channelarea and between the bit lines for providing isolation between overlying polysilicon wordlines. The nitride layer retains charge to program the memory cell.

Although the memory device of Mitchell includes a top oxide layer, it is not verywell suited for flash EEPROM applications. This is due to the very wide charge trappingregion that must be programmed in order to achieve a sufficient delta in the thresholdvoltage between programming and reading. The Mitchell device is programmed and readin the forward direction. Since reading in the forward direction is less effective thanreading in the reverse direction, the charge trapping region must be wider by default inorder to distinguish between the programmed and unprogrammed states. A wider chargetrapping region, however, makes the memory device very difficult to erase, thus makingthis device inefficient for flash EEPROM applications. A single transistor ONO EEPROM device is disclosed in the technical articleentitled "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," T.Y. Chan,K.K. Young and Chenming Hu, IEEE Electron Device Letters, March 1987. The memorycell is programmed by hot electron injection and the injected charges are stored in theoxide-nitride-oxide (ONO) layer of the device. This article teaches programming andreading in the forward direction. Thus, as in Mitchell, a wider charge trapping region isrequired to achieve a sufficiently large difference in threshold voltages betweenprogramming and reading. This, however, makes it much more difficult to erase the device. 5

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SUMMARY OF THE INVENTION

In accordance with the present invention, a flash electrically erasableprogrammable read only memory (EEPROM) and method of programming, reading anderasing the same are provided. In one embodiment, the flash EEPROM memory cell isconstructed having a charge trapping dielectric layer sandwiched between two silicondioxide layers. The non conducting dielectric layer traps electrical charge and the twolayers of silicon dioxide act as electrical insulators. A conducting gate layer is placed overthe upper silicon dioxide layer. A novel aspect of the memory device is that while it is programmed in theconventional manner, using hot electron programming, it is read in a direction opposite thatof programming. Each cell is programmed conventionally by applying programmingvoltages to the gate and the drain while the source is grounded. Hot electrons areaccelerated sufficiently to be injected into a region of the trapping dielectric layer near thedrain. The device, however, is read in the opposite direction from which it was written,meaning voltages are applied to the gate and the source while the drain is grounded.

Reading in the reverse direction is most effective when relatively low gatevoltages are used. A benefit of utilizing relatively low gate voltages in combination withreading in the reverse direction is that the potential across the portion of the channelbeneath the trapped charge region is significantly reduced. A relatively smallprogramming region or charge trapping region is possible due to the lower channelpotential. This permits much faster programming times because the effect of the chargetrapped in the localized trapping region is amplified. Programming times are reducedwhile the delta in threshold voltage between the programmed versus unprogrammedstates remain the same. Another major benefit is that the erase mechanism of thememory cell is greatly enhanced. 25 6

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The memory cell can be erased by applying suitable erase voltages to the gate and the drainso as to cause electrons to be removed from the charge trapping region of the nitride layer.Electrons move from the nitride through the bottom oxide layer to the drain. Anotherbenefit includes reduced wearout from cycling thus increasing device longevity. An effectof reading in the reverse direction is that a much higher threshold voltage for the sameamount of programming is possible. Thus, to achieve a sufficient delta in the thresholdvoltage between the programmed and unprogrammed states of the memory cell, a muchsmaller region of trapped charge is required when the cell is read in the reverse direction than when the cell is read in the forward direction.

The erase mechanism is enhanced when the charge trapping region is made asnarrow as possible. Programming in the forward direction and reading in the reversedirection permit limiting the width of the charge trapping region to a narrow region nearthe drain. This allows for much more efficient erasing of the memory cell.

Further, utilizing a thinner silicon nitride charge trapping layer than thatdisclosed in the prior art helps to confine the charge trapping region to a laterally narrowerregion near the drain. Further, the thinner top and bottom oxide sandwiching the nitridelayer helps in retention of the trapped charge.

In addition, unlike prior art floating gate flash EEPROM memory cells, thebottom and top oxide thickness can be scaled due to the deep trapping levels that functionto increase the potential barrier for direct tunneling. Since the electron trapping levels areso deep, thinner bottom and top oxides can be used without compromising charge retention.

Another benefit of localized charge trapping is that during erase, the region ofthe nitride away from the drain does not experience deep depletion since the erase occurs 25 near the drain only. The final threshold of the cell after erasing is self limited by the device 7

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10 structure itself. This is in direct contrast to conventional singe transistor floating gate flashmemory cells which are plagued with deep depletion problems. To overcome theseproblems, manufacturers include complex circuitry to control the erase process in order toprevent or recover from deep depletion.

Another approach previously employed in the prior art to solve the deepdepletion problem was to design the floating gate flash memory cell using a split gatedesign forming multiple transistors per cell. The split gate or double transistorconstructions were necessary because the information carrying transistor, i.e., the floating gate transistor, potentially could be over-erased. An over-erase condition caused thethreshold voltage of the cell to go too low. The second transistor, acting as a controltransistor, prevented the floating gate transistor from being over-erased. 8

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BRIEF DESCRIPTION OF THE DRAWINGS

The invention is herein described, by way of example only, with reference to theaccompanying drawings, wherein:

Fig. 1 illustrates a sectional view of a flash EEPROM cell of the prior art5 utilizing Oxide-Nitride-Oxide (ONO) as the gate dielectric;

Fig. 2 illustrates a sectional view of a flash EEPROM cell in accordance with anembodiment of the present invention utilizing ONO as the gate dielectric;

Fig. 3 illustrates a sectional view of a flash EEPROM cell in accordance with anembodiment of the present invention utilizing a silicon rich silicon dioxide with buried 10 poly silicon islands as the gate dielectric;

Fig. 4 is a chart illustrating the threshold voltage as a function of programming time for reading in the forward and reverse directions of a selected memory cell in accordance with this invention;

Fig. 5A illustrates a sectional view of a flash EEPROM cell of the prior art15 showing the area of charge trapping under the gate;

Fig. 5B illustrates the voltage in the channel beneath the gate relative to thetrapped charge when the memory cell is read in the reverse direction;

Fig. 6 is a graph illustrating the difference in threshold voltage in the forwardand reverse directions as a function of drain voltage for a flash EEPROM cell of the 20 present invention that has been programmed.

Fig. 7 is a graph illustrating the difference in drain current in the forward and reverse directions as a function of drain voltage for a flash EEPROM cell of the presentinvention that has been programmed. 9

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Fig. 8 is a graph illustrating the threshold voltage of a flash EEPROM cell of thepresent invention as a function of programming time for reading in the forward and reverse directions.

Fig. 9 is a graph illustrating the leakage current through the region of trapped5 charge as a function of the voltage across the charge trapping region while reading in the reverse direction;

Fig. 10 is a graph illustrating the gate voltage required to sustain a given voltageVx in the channel beneath the edge of the region of trapped charge while reading in the reverse direction; 10 Fig. 11 is a graph illustrating the effect of the gate voltage applied during reading on the difference in drain current between reading in the forward versus the reverse direction;

Fig. 12 is a graph illustrating the effects of the programming time on thedifference in threshold voltage between the forward read and reverse read directions; 15 Fig. 13 is a graph illustrating the effect of programming time and erase time on the threshold voltage for the forward read and reverse read directions.

Fig. 14 is a graph illustrating the effect of drain voltage VD on the thresholdvoltage Vt for two different values of threshold current;

Fig. 15 is a graph illustrating the effect of oxide versus TEOS as the material20 used to form the silicon dioxide on top of the charge trapping layer of the structure of Fig.2 on the programming and erasing of the charge placed on the charge trapping layer when the device is read in the reverse direction;

Fig. 16 is a graph illustrating the erase curves for two different values of drain voltage while the gate is held at ground potential. 10

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Fig. 17 is a graph illustrating the erase curves of threshold voltage Vt versuserase time for two difference values of negative gate voltage;

Fig. 18A illustrates a sectional view of a flash EEPROM cell of the prior artshowing the area of charge trapping under the gate after the cell has been programmed for aperiod of time to allow the cell to be read in the forward direction; and

Fig. 18B illustrates a sectional view of a flash EEPROM cell constructed inaccordance with an embodiment of the present invention showing the area of chargetrapping under the gate after the cell has been programmed for a sufficient time to allow thecell to be read in the reverse direction while achieving the same threshold voltage of thecell illustrated in Figure 18 A. 11

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DETAILED DESCRIPTION OF THE INVENTION

The present invention can best be understood with an understanding of howprior art charge trapping dielectric flash EEPROM memory cells are constructed,programmed and read. Illustrated in Figure 1 is a cross section of a conventional ONO 5 EEPROM memory cell as disclosed in the technical article entitled "A TrueSingle-Transistor Oxide-Nitride-Oxide EEPROM Device," T.Y. Chart, K.K. Young andChenming Hu, IEEE Electron Device Letters, March 1987, incorporated herein byreference. The memory cell, generally referenced 41, comprises a P-type silicon substrate30, two PN junctions between N+ source and drain regions 32, 34 and P type substrate 30, 10 a non conducting nitride layer 38 sandwiched between two oxide layers 36, 40 and apolycrystalline conducting layer 42.

Programming Prior Art Memory Devices

The operation of the prior art memory cell 41 will now be described. To 15 program or write the cell, voltages are applied to the drain 34 and the gate 42 and thesource 32 is grounded. For example, 10 V is applied to the gate and 9 V is applied to thedrain. These voltages generate a vertical and lateral electric field along the length of the channel from the source to the drain. This electric field causes electrons to be drawn off the source and begin accelerating towards the drain. As they move along the length of the 20 channel, they gain energy. If they gain enough energy they are able to jump over the potential barrier of the oxide layer 36 into the silicon nitride layer 38 and become trapped.

The probability of this occurring is a maximum in the region of the channel next to the drain 34 because it is near the drain that the electrons gain the most energy. These accelerated electrons are termed hot electrons and once injected into the nitride layer they 12

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10 15 20 25 become trapped and remain stored there. The trapped electrons cannot spread through thenitride layer because of the low conductivity of the nitride layer and the low lateral electricfield in the nitride. Thus, the trapped charge remains in a localized trapping region in thenitride typically located close to the drain.

In U.S. Patent No. 4,173,766, issued to Hayes, the nitride layer is described astypically being about 350 Angstroms thick (see column 6, lines 59 to 61). Further, thenitride layer in Hayes has no top oxide layer. A top oxide layer would serve as a lowconductivity layer to prevent holes from moving into the nitride from the overlying gateand combining with electrons trapped in the nitride which reduces the charge stored in thenitride. If the memory cell of Hayes used a thinner nitride layer, then electrons trapped inthe nitride layer would be lost to holes entering from the overlying conductive gate. Theconductive gate permits the electrons in the nitride to be removed. Further, once theelectrons are trapped in a given region of the nitride associated with a single cell, theprogramming of adjacent cells can cause an electric field to be generated with respect tothe electrons in the trapped region of the single cell causing further dissipation of theelectrons from the trapped region. During life testing, where the device is subjected toelevated temperatures typically in the range from about 150 degrees Centigrade to 250degrees Centigrade, holes from the gate can enter the nitride and combine with theelectrons to further reduce the amount of charge trapped in the nitride. Although lateralfields exist in the nitride of the Hayes structure as they do in any ONO structure used as gate insulation in an MOS device, the relatively thick nitride layer such as disclosed by

Hayes causes the electrons to move laterally in response to this lateral field and come torest either in traps between the conduction and valence bands or in localized regions ofpositive charge in the nitride layer. Such movement of electrons, commonly known aselectron hopping, can readily occur in a relatively thick nitride layer such as disclosed by 13

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Hayes. Such hopping diffuses and thus reduces the localized intensity of the trapped charge.

As previously described, in order to achieve an effective delta in thresholdvoltage between the unprogrammed and the programmed state of each cell, the charge 5 trapping region of prior art flash EEPROM cells must be made fairly wide. Thus, electronsare trapped in areas far from the drain which directly affects the effectiveness of the erase.In some cases, the device cannot be erased at all because the charge trapping region was programmed too wide.

In memory cells constructed using a conductive floating gate, the charge that 10 gets injected into the gate is distributed equally across the entire gate. The thresholdvoltage of the entire gate increases as more and more charge is injected into the gatebecause the electrons that lodge in the gate screen the gate voltage from the channel.

With reference to Figure 1, in devices with low conductivity or non conductivefloating gates, the injection of hot electrons into the silicon nitride layer causes the gate 15 threshold voltage to increase only in the localized trapping region. This is in contrast to theconductive floating gate memory cells of EPROMs and EEPROMs wherein the gatethreshold voltage of the entire channel rises as programming time increases. In bothconductive floating gate memory cell designs, an increase in the gate threshold voltagecauses the current flowing through the channel to decrease for a given gate voltage. This 20 reduces programming efficiency by lengthening the programming time. However, due tothe localized electron trapping in the non conductive floating gate memory cell design, theprogramming time is reduced less than with the conductive floating gate memory celldesign. The technique of programming flash EEPROM memory cells with eitherconductive or low conductivity or non conductive floating gates is well known in the art 25 and is currently used to program EEPROM and flash EEPROM memory cells. 14

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Reading Prior Art Memory Drives

The method of reading prior art flash EEPROM memory cells will now bedescribed. The conventional technique of reading both prior art conductive floating gate 5 and non conductive localized trapping gate EEPROM or flash EEPROM memory is toapply read voltages to the gate and drain and to ground the source. This is similar to themethod of programming with the difference being that lower level voltages are appliedduring reading than during programming. Since the floating gate is conductive, the trappedcharge is distributed evenly throughout the entire floating conductor. In a programmed 10 device, the threshold is therefore high for the entire channel and the process of readingbecomes symmetrical. It makes no difference whether voltage is applied to the drain andthe source is grounded or vice versa. A similar process is also used to read prior art nonconductive localized gate flash EEPROM devices.

The process of programming typically includes writing followed by reading. 15 This is true for all EPROM and EEPROM memory devices. A short programming pulse isapplied to the device followed by a read. The read is actually used to effectively measurethe gate threshold voltage. By convention, the gate threshold voltage is measured byapplying a voltage to the drain and a separate voltage to the gate, with the voltage on thegate being increased from zero while the channel current flowing from drain to source is 20 measured. The gate voltage that provides 1 μΑ of channel current is termed the thresholdvoltage.

Typically, programming pulses (i.e., write pulses) are followed by read cyclesΓ"—wherein the read is performed in the same direction that the programming pulse isapplied. This is termed symmetrical programming and reading. Programming stops when 25 the gate threshold voltage has reached a certain predetermined point (i.e., the channel 15

P-1326-IL current is reduced to a sufficiently low level). This point is chosen to ensure that a '0' bitcan be distinguished from a '1' bit and that a certain data retention time has been achieved.

The Memory Device of the Present Invention A sectional view of a single bit flash EEPROM cell constructed in accordance with an embodiment of the present invention utilizing ONO as the gate dielectric is shownin Figure 2. The flash EEPROM memory cell, generally referenced 10, comprises a P-typesubstrate 12 having two buried PN junctions, one being between the source 14 andsubstrate 12 and the other being between the drain 16 and the substrate 12. Above thechannel is a layer of silicon dioxide 18, preferably between approximately 60 to 100Angstroms thick, which forms an electric isolation layer over the channel. On top of thesilicon dioxide layer 18 is a charge trapping layer 20 constructed preferably in the range of20 to 100 Angstroms thick and preferably comprised of silicon nitride, S13N4. The hotelectrons are trapped as they are injected into the charge trapping layer. In this fashion, thecharge trapping layer serves as the memory retention layer. Note that the programming,reading and erasing of the memory cell of the present invention is based on the movementof electrons as opposed to movement of holes. The charge trapping dielectric can beconstructed using silicon nitride, silicon dioxide with buried polysilicon islands orimplanted oxide, for example. In the third listed alternative, the oxide can be implantedwith arsenic, for example. The thickness of layer 18 is chosen to be in excess of 50Angstroms to prevent electrons from tunneling through the oxide and leaving chargetrapping layer 20 during the operation of the cell. Thus, the lifetime of the cell of this invention is greatly extended relative to prior art MNOS devices.

Another layer of silicon dioxide 22 is formed over the charge trapping layer, (i.e., silicon nitride layer), and is preferably between approximately 60 to 100 Angstroms 16

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10 15 20 25 thick. The silicon dioxide layer 22 functions to electrically isolate a conductive gate 24formed over the silicon dioxide layer 22. The thickness of gate 24 is approximately 4,000Angstroms. Gate 24 can be constructed from polycrystalline silicon, commonly known as polysilicon.

Charge trapping dielectric materials other than nitride may also be suitable foruse as the asymmetric charge trapping medium. One such material is silicon dioxide withburied polysilicon islands. The silicon dioxide with polysilicon islands is sandwichedbetween two layers of oxide in similar fashion to the construction of the ONO memory cellin Figure 2. A sectional view of a flash EEPROM cell constructed in accordance with apreferred embodiment of the present invention utilizing a silicon rich silicon dioxide layer54 with buried polysilicon islands 55 as the gate dielectric is illustrated in Figure 3. Notethat for simplicity, only a few polysilicon islands are numbered. A P-type substrate 62 hasburied N+ source 58 and N+ drain 60 regions. The silicon dioxide 54 with buriedpolysilicon islands 55 is sandwiched between two layers of silicon dioxide 52, 56.Covering oxide layer 52 is polysilicon gate 50. Gate 50 is typically heavily doped with anN-type impurity such as phosphorus in the 1019 to IO20 atoms/cc range. The operation ofthe memory cell of Figure 3 is similar to that of the memory cell illustrated in Figure 2 withprogramming and reading occurring in opposite directions.

Alternatively, the charge trapping dielectric can be constructed by implanting animpurity, such as arsenic, into a middle layer 54 of silicon dioxide deposited on top of the bottom oxide 56. A key aspect of the present invention lies in the manner in which the flashEEPROM memory cell 10 (Figure 2) is programmed and read. Rather than performingsymmetrical programming and reading, the flash EEPROM memory cell of the presentinvention is programmed and read asymmetrically. This means that programming and 17

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10 reading occur in opposite directions. The arrows labeled PROGRAM and READ in Figure2 point in opposite directions to signify this asymmetry. Thus, programming is performedin what is termed the forward direction and reading is performed in what is termed the opposite or reverse direction.

It is noted that throughout the discussion of the EEPROM memory cell of thepresent invention presented below, the voltage levels discussed in connection therewith areassumed to be independent of the power supply voltage. Thus, the power supply voltagessupplied to the chip embodying the EEPROM memory device may vary while the voltagesapplied to the gate, drain and source thereof will be supplied from regulated voltage sources.

Programming in the Forward Direction

As previously mentioned, the flash EEPROM memory cell 10 of Figure 2 isprogrammed similarly to the prior art flash EEPROM memory cell of Figure 1. Voltages 15 are applied to the gate 24 and drain 16 creating vertical and lateral electrical fields whichaccelerate electrons from the source 14 along the length of the channel. As the electronsmove along the channel some of them gain sufficient energy to jump over the potentialbarrier of the bottom silicon dioxide layer 18 and become trapped in the silicon nitridelayer 20. The electron trapping occurs in a region near the drain indicated by the dashed 20 circle 19 in Figure 2. Electrons are trapped in the portion of nitride layer 20 near but abovethe drain region 16 because the electric fields are the strongest there. Thus, the electronshave a maximum probability of being sufficiently energized to jump the potential barrier ofthe silicon dioxide layer 18 and become trapped in the nitride layer 20 near the drain 16.The threshold voltage of the portion of the channel between the source 14 and drain 16 18

P-1326-IL under the region of trapped charge increases as more electrons are injected into the nitride layer 20.

It is important to note that in order to be able to subsequently erase memorydevice 10 effectively, the programming time period must be limited. As the device 5 continues to be programmed, the width of the charge trapping region increases. Ifprogramming continues past a certain point the charge trapping region becomes too widewhereby erasing is ineffective in removing trapped charge from the nitride layer 20.

However, by reading in the reverse direction, programming times can beshortened. This permits a much narrower charge trapping region. This in turn greatly 10 increases the erase efficiency since fewer electrons need to be removed to erase the device.In addition, the trapped electrons are stored in a narrower region near the drain alsoimproving the effectiveness of the erase.

Reading in the Forward Direction 15 If the flash EEPROM memory cell 10 is read using the conventional technique of reading in the same direction as programming, the time needed to program the devicegreatly increases to achieve the same threshold voltage. Reading in the same direction asprogramming means the device is programmed and read in the same forward direction.During reading, voltages having levels lower than the voltages applied during 20 programming are applied to the gate and drain and the channel current is sensed. If device 10 is programmed (i.e., a logic O') the channel current should be very low and if the device is not programmed (i.e., a logic '1') there should be significant channel current. Preferably, the in the channel current between the '0' and '1' logic states should be maximized in order to better distinguish between the '0' and' Γ logic states. 19

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Illustrated in Figuie 4 is a graph showing the rise in gate threshold voltage as afunction of programming time for reading in the forward direction (curve labeledFORWARD READ) and for reading in the reverse direction (curve labeled REVERSEREAD). Apparent from the graph in Figure 4 is the several orders of magnitude reductionin programming time achieved when reading in the reverse direction versus reading in the forward direction. As is described in more detail below, this dramatic reduction inprogramming time is due to amplification of the effect of the trapped charge injected intothe nitride layer brought about by reading the memory cell in the opposite direction fromwhich it was programmed.

As stated above, the time needed to program the flash EEPROM memory cellgreatly increases when reading occurs in the same direction (i.e., the forward direction) asprogramming. The reason for this will now be explained in more detail with reference toFigures 5A and 5B. Figure 5A illustrates a sectional view of a flash EEPROM cell of theprior art showing the area 66 of charge trapping under the gate 42. Figure 5B illustrates a sectional view of a flash EEPROM cell constructed in accordance with an embodiment of the present invention showing the area 68 of charge trapping under the gate 24. A description of what occurs during programming is presented first followed bywhat occurs during reading. Note that the description that follows also pertains to thememory cell of Figure 3 comprising the silicon dioxide layer 54 having buried polysiliconislands 55 substituting for the nitride layer 20 of Figure 2. During programming, hotelectrons are injected into the nitride layer 20, as described above. Since nitride 20 is anonconductor, the trapped charge remains localized to the region near the drain 34 (Figure5 A) or 16 (Figure 5B). The region of trapped charge is indicated by the cross hatched area 66 in Figure 5A and by the cross hatched area 68 in Figure 5B. Thus, the threshold voltagerises, for example, to approximately 4 V, only in the portion of the channel under the 20

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10 15 20 trapped charge. The threshold voltage of the remainder of the channel under the gateremains at, for example, approximately 1 V. If the device is now read in the conventionalforward direction (i.e., voltages are applied to the gate and drain as indicated by the arrowin Figure 5A), electrons move off the source and begin traveling toward the drain. When alogic ‘0’ is programmed, there can be little or no channel current through the device when itis read. Thus, only if a sufficient portion of the channel is turned off, can the electroncurrent be stopped. If the channel cannot be completely turned off, the electrons will reachthe drain. Whether the electrons reach the drain will be determined by, among other things,the length of the trapping area. If the memory cell is programmed for a sufficiently longperiod, eventually, the channel stops conducting when read in the forward direction. If thetrapped charge region (the programmed area) 66 (Figure 5A) is not long enough, electronscan punch through to the drain 34 in the depletion region under the trapped charge 66.

When the device is read in the forward direction, a voltage is applied to the drainand the gate, for example 2 V and 3 V, respectively, and the source is grounded. Fullinversion occurs in the channel under the area of the nitride 38 that does not have trappedcharge. A vertical electric field exists in the channel that spans the length of the channel upto the region of the channel underneath the trapped charge 66. In the inversion region,electrons travel in a linear fashion up to the edge 35 of the inversion region which isbeneath the left edge 33 of the trapped charge region 66. This is indicated by the lineshown in the channel region in Figure 5A that extends from the source to just beneath theedge 33 of the region of trapped charge 66. Due the fact that the device is in inversion (i.e.,the channel is in a conductive state), the potential in the inversion layer is pinned to groundpotential because the source is grounded. The voltage in the inverted channel near thetrapped charge (i.e., just to the left of the right edge 35 of the channel inversion region) isapproximately zero. Thus, the voltage across the region of trapped charge is close to the 25 21

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10 15 20 full drain potential of 2 V. Due to the drain potential across the channel region beneath thetrapped charge 66 some of the electrons punch through across the trapped region to thedrain, resulting in a channel current.

The diagonal line under the channel in Figures 2 and 5A indicates the reduction in the number of electrons in the channel as a function of channel distance. The channel region under the trapped charge is off (i.e., not inverted) due to the high thresholdvoltage required to invert this region under the trapped charge. However, the channelregion inside the dashed circle 19 in Figure 2 and under the region 66 in Figure 5 A is adepletion region because the device is in saturation (a device will be in saturation whenVDS, the voltage from drain to source, is higher than VDSAT, the saturation voltage).Due to the voltage on the drain 34, a lateral electric field exists in this portion of thechannel under region 66. As a result of this lateral electric field, any electron arriving atthe edge of the depletion region will be swept through and pulled to the drain 34. Asdescribed earlier, this phenomenon is called punch through. Punch through occurs if thelateral electric field is strong enough to draw electrons through to the drain, regardless ofthe threshold level. In order to prevent punch through from occurring during a read, theprior art memory cells require a much longer programming time than does the memorycell of this invention because the prior art memory cells are read in the forwarddirection. As the memory device is programmed for a longer and longer time, more andmore electrons are injected into the nitride, increasing the length of the programmedportion 66 (Figure 5A) of the channel. The memory cell must be programmed for anamount of time that yields a trapped charge region 66 of sufficient length to eliminatethe punch through of electrons. When this occurs, the lateral electric field is too weakfor electrons to punch through to the drain under normal 22

P-1326-IL operating conditions. As an example, for the threshold voltage Vt equaling 3V duringread, Figure 4 shows that a programming time of approximately 3 milliseconds is required.

Reading in the Reverse Direction 5 However, if the flash EEPROM memory cell 10 (Figure 5B) is read in the reverse direction, a very different scenario exists. Reading in the reverse direction meansreading in a direction opposite that of programming. In other words, voltages are appliedto the source 14 and the gate 24 and the drain 16 is grounded. Similar to the prior artmemory device of Figure 5A, the memory device of Figure 5B is programmed in the 10 forward direction by injecting hot electrons into region 68 of the nitride layer 20. Sincenitride 20 is a nonconductor, the trapped charge remains localized to the region 68 near thedrain 16. The region 68 of trapped charge is indicated by the cross hatched area 68 inFigure 5B. Thus, the threshold voltage rises, for example, to approximately 4 V only in theportion of the channel under the trapped charge 68. The threshold voltage of the remainder 15 of the channel remains at, for example, approximately 1 V.

To read the device of Figure 5B in the reverse direction, voltages are applied to the source 14 and the gate 24, for example 2 V and 3 V, respectively, and the drain 16 isgrounded. A major difference between reading in the forward direction and reading in thereverse direction is that when reading in the reverse direction, the gate voltage required to 20 put the channel of the memoiy device into inversion increases significantly. For the sameapplied gate voltage of 3 V, for example, there will be no inversion but rather the channelof the memory device will be in depletion. The reason for this is that the channel regionnext to the drain 16 (which functions as the source in read) is not inverted due to theelectron charge in region 68 of the nitride 20. The channel adjacent the source 14 (which 25 functions as the drain in read) is not inverted because 2 V is applied to the source 14 and 23

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10 15 20 25 the channel, to be inverted, must be inverted relative to 2 V. In the case of reading in thereverse direction, in order to sustain a higher voltage in the channel, a much widerdepletion region must be sustained. A wider depletion region translates to more fixedcharge that must be compensated for before there can be inversion. When reading in thereverse direction in accordance with the present invention, to achieve a voltage drop acrossthe charge trapping region 66 of the prior art memory device shown in Figure 5 A similar tothe voltage drop achieved when reading the same device in the forward direction, a highergate voltage is required, for example, 4 V. This is in contrast to the prior art memorydevice where the source was grounded and a lower gate voltage was required to invert thechannel. In the memory device of the present invention, a much higher gate voltage isrequired to pin the voltage in the channel to a higher voltage, i.e., the 2 V that is applied tothe source terminal rather than ground. In other words, the present invention recognizesand takes advantage of the fact that for the same magnitude potential across the drain andthe source, the voltage across the portion of the channel under the trapped charge region 68(Figure 5B) is significantly reduced when reading occurs in a reverse direction to writing(programming) directly resulting in less punch through and greater impact of theprogramming charge injected in region 68 of the nitride layer 20 (Figure, 5B)~n, thethreshold voltage of the transistor. As an example, for the threshold voltage Vt 3 V duringreverse read, Figure 4 shows that a programming time of approximately 2 microseconds isrequired. This programming time is three orders of magnitude less than the programmingtime required for the same threshold voltage when the cell is read in the forward direction.

In the prior art, memory cells utilizing the ONO structure have had difficultyretaining the localized charge in the nitride layer. This is because such memory cells areprogrammed in a first, forward, direction and then read in the same direction. The readingof the programmed cell in the forward direction requires a significant amount of charge to 24

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10 15 20 be stored on the nitride to provide the desired increase in threshold voltage associated withthe programmed cell. However, in accordance with this invention, by reading in the reversedirection, significantly less charge is required to be stored on the nitride to achieve the sameincrease in threshold voltage in a programmed cell. Figure 4 shows the difference in charge(measured as a function of programming time required to a achieve a given threshold voltageVt) for reading in the reverse direction versus the forward direction. In the prior art, thecharge retention in a localized region of the silicon nitride layer was difficult if notimpossible to achieve because the lateral electric field generated by the charge dispersed thecharge laterally in the nitride layer. Such dispersion particularly occurred during the hightemperature retention bake required for quality control and reliability. The high temperatureretention bake typically requires temperatures between 150 degrees Centigrade to 250degrees Centigrade for at least 12 to 24 hours. The charge in the prior art devices typicallydispersed through the nitride during the high temperature bake causing the performance ofprior art devices using the nitride layer as a charge retention material to be less thansatisfactory. Accordingly, prior art devices that use the nitride layer for charge retention arenot widely used. In addition, charge stored on the nitride layer in prior art memory cells isparticularly prone to lateral diffusion and dispersion through the nitride layer in response tothe retention bake due to the internal fields causing what is known as electron hopping. Thephenomenon of electron hopping is exponentially dependent on the field strength. In thecase of charge in the nitride layer the internally generated electric field strength is directlyrelated to the amount of charge stored on the nitride layer. Because electron hopping isexponentially dependent upon the electric field strength, the additional charge required toobtain a given threshold voltage change or shift when the memory cell is read in the samedirection as it was programmed causes a very significant change in the charge distribution inthe nitride layer. This change in the charge distribution seriously degrades the threshold 25 25

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10 15

voltage from the intended (i.e., design) threshold voltage. Consequently, prior art ONO devices have not been successful.

In accordance with the present invention, by reading the memory cell in the reversedirection from which the memory cell is programmed, the amount of charge required toachieve a given threshold voltage is reduced in some cases by a factor of two or three timesthe amount of charge required to obtain the same threshold voltage shift as when thememory cell is read in the forward direction. Accordingly, the internal electric fieldsgenerated by the charge in the nitride when the memory cell is to be read in the reversedirection are much less than the internal electric fields associated with the charge stored onthe nitride when the memory cell is to be read in the forward direction. Consequentlyelectron hopping is exponentially reduced and the small amount of charge stored in thenitride does not disperse laterally through the nitride due to the internally self generatedelectric fields even during retention bake. Consequently, the memory cell of the presentinvention does not suffer the degradation in performance and reliability of prior art ONOmemory cells which are programmed and read in the same direction.

Sample Flash EEPROM Device Data

Data obtained from flash EEPROM devices constructed in accordance with the present invention will now be presented to help illustrate the principles of operation20 thereof. A graph illustrating the difference in threshold voltage in the forward and reversedirections as a function of drain voltage for a flash EEPROM cell of the present inventionthat has been previously programmed is shown in Figure 6. The memory cell used toobtain the data presented in Figures 6, 7 and 8 was constructed with a bottom oxide layer 18, a top oxide 22 and a nitride layer 20, each 100 Angstroms thick. The drawn width of 26

P-1326-IL the channel measures 0.6 microns and the drawn length of the channel measures 0.65

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microns.

While reading in the forward direction, the threshold voltage is approximatelythe same as the threshold voltage when reading in the reverse direction for low drain 5 voltages. At low drain voltages there is insufficient potential for punch through to occur.However, as the drain voltage increases while reading in the forward direction, the punchthrough region increases resulting in lower threshold voltage. At a high enough drainvoltage, the entire portion of the channel under the trapped charge in region 68 of nitridelayer 20 (Figure 5B) is punched through and the threshold voltage levels off at the original 10 threshold voltage of the channel.

However, while reading in the reverse direction, the Vt versus VD curve appearsto follow the Vt versus Vd curve while reading in the forward direction at low drainvoltages. However, the curves rapidly diverge for higher drain voltages and the thresholdvoltage for reading in the reverse direction levels off at approximately 4 V. At a gate 15 voltage Vq of approximately 4 V and a drain voltage Vd of 1.2 V, the device has reached saturation (Vdsat)· At this gate voltage, any further increase in Vd cannot be transferredthrough the inversion layer thus establishing the maximum potential drop across theportion of the channel beneath the charge trapping region 68. The VT then becomesindependent of further increases in VD. For example, at a drain voltage of 1.6 V, the 20 difference in Vt between reverse and forward read is almost 2 V. A graph illustrating the difference in drain current in the forward and reverse directions as a function of drain voltage for a flash EEPROM cell of the present inventionthat has been programmed is shown in Figure 7. In Figure 7, rather than measure thresholdvoltage, the drain current is measured while keeping the gate voltage constant. In the 25 forward direction, as expected, the drain current Id increases as the drain voltage Vd 27

P-1326-IL 125604/2 increases. The curve labeled FORWARD also resembles the Id curve for reading an unprogrammed cell in the reverse direction.

The drain current while reading in the reverse direction also increases with increasingdrain voltage (measured at the source which functions as the drain when reading in the reversedirection) but the drain current levels off at a much lower current than when reading in the forward direction. The difference between drain current at a Vd of 2 V is on the order of approximately 1000 times. If the logic threshold for this memory cell is set to 10 μΑ, theforward curve can represent a logic '0' and the reverse curve a logic 'Γ. A graph illustrating the threshold voltage Vy of a flash EEPROM cell of the presentinvention as a function of programming time for reading in the forward and reverse directionsis shown in Figure 8. This chart is similar to the chart of Figure 4. Note that the chart ofFigure 8 is derived from a memory device actually constructed. During programming, Vd isheld constant at 5.5 V and Vg is held constant at 10 V. As shown in Figure 8, when the cell isread in the reverse direction, Vy reaches 3 V in slightly under a microsecond of programmingtime. When the cell is read in the forward direction, the same Vy is reached in slightly under amillisecond. Thus, reading in the forward direction, in this case, is approximately 1000 timesless efficient than reading in the reverse direction.

The Voltage Vx in the Channel

The voltage Vx is defined as the voltage in the channel at a distance X from thesource. Using the example presented above, the voltage Vx that exists in the channel of thememory cell of the present invention (Figure 5B, for example) will not be 2V because thedevice is in depletion rather than inversion. On the other hand, the voltage Vx must belarger than 0 because a gate voltage of only 1.5 V is able to sustain approximately 0.4 V inthe channel. The actual voltage in the channel varies across the channel length because of 28

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the lateral electric field set up between the source and the drain. The threshold voltage,however, varies as a function of the voltage in the channel.

With reference to Figure 5B, the channel will be in saturation as long as the gatevoltage νθ is higher than the threshold voltage Vt and the voltage Vx at any point in thechannel is given by

Vx- Vdsat with

Vdsa t=Vg-Vt= Vg- Vt(Vdsa t) and 10 Vt(Vx)-Vto+AVt(Vx)

As is shown in the above equations, the threshold voltage in the channel is equal to the threshold voltage with the source at zero potential Vto plus a delta threshold voltageAVt which is itself a function of the voltage in the channel.

The leakage current through the channel under the region 68 of trapped charge, 15 plotted as a function of the voltage Vtc, across the portion of the channel under the chargetrapping region 68 while reading in the reverse direction, is shown in Figure 9. From thegraph, one can see that the approximate leakage current II through the channel when Vtc is2 V is 10'5 A. In the case of the prior art memory cell read in the forward direction, thevoltage across the portion of the channel under region 68 of trapped charge is 20 approximately 2 V. In contrast, the voltage Vx in the channel of the memory device of thepresent invention at location 23 beneath the edge 21 of the region 68 of trapped charge isnot 2 V but something less, 1 V for example. The leakage current II corresponding to 1 Vacross the trapped charge region is approximately 10' A, a whole two orders of magnitude smaller. 29

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10 15 20

Of importance, the edge of the region of trapped charge formed in the nitridelayer during programming is the portion of the trapped charge that begins to affect the gatevoltage required to invert the channel beneath that point. A graph illustrating the gate voltage required to sustain a given voltage in thechannel, Vx, spanning the distance from the drain to the edge 23 of the channel under theedge 21 of the charge trapping area while reading in the reverse direction is shown inFigure 10. The gate voltage Vq that is required to sustain a particular Vx at the point 23 inthe channel under the edge 21 of the charge trapping area 68 (Figure 5B) is a function ofthe number of acceptors Na in the substrate and the thickness of the oxide Tox and isrepresented by the dashed/dotted line. The solid line represents the threshold voltage in thechannel that exists when the back bias effect on the threshold voltage is zero. In this case,the threshold voltage is constant along the entire channel. However, once there is a voltagein the channel, the threshold voltage is not constant along the channel. As shown in thegraph, the threshold voltage increases nonlinearly as the voltage in the channel increases.The relationship between the incremental increase in threshold voltage as a function ofchannel voltage is well known in the art. A more detailed discussion of this relationshipcan be found in Chapter 2 of The Design and Analysis of VLSI Circuits by L.A. Glasserand D.W. Dobberpuhl, incorporated herein by reference.

It is important to emphasize that the advantages and benefits of reading in thereverse direction are achieved only when combined with the use of relatively low gatevoltages. For a particular drain voltage, e.g., 2 V, applying a high enough Vo such as 5 V,for example, causes the differences in threshold voltages between forward and reversereading to fade. A graph illustrating the effect of the gate voltage Vg applied duringreading on the difference in drain current Id between reading in the forward directionversus reading in the reverse direction is shown in Figure 11. The reverse Vj of the device 25 30

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10 15 20 used to generate the curves in the Figure is 3.5 V. From Figure 11 it can be seen that as Vgis increased while Vd is kept constant, the Id curves for the reverse read begin to resemblethe curves for the forward read. For example, comparing the forward and reverse readcurves when Vg equals 2.5 V shows the read current in the reverse direction being aboutfour orders of magnitude lower. At a gate voltage Vg of 3 V, the difference in read currentbetween the forward and reverse directions drops to a little more than two orders ofmagnitude. At a gate voltage of 5 V, the difference in read current is only approximately15%. These curves clearly show that large differences in Id between the forward andreverse read directions are only obtained when Vq is chosen to be low enough. Thus, thebenefits of reading in the reverse direction are only achieved when suitably low gatevoltages are used for reading. There is an optimum range within which Vq should lie. IfVq is too low, insufficient current is developed in the channel. On the other hand, if Vg ischosen too high, the differences between reading in the reverse and forward directions aregreatly diminished. A graph illustrating the effect of the gate voltage on the difference in thresholdvoltage between the forward and reverse directions is shown in Figure 12. The device usedto generate the curves in Figure 12 was programmed once to a Vj of 3.5 V using a VD of 1.6 V and an Ith of 1 μΑ. The Vt as a function of Vd during reading was subsequently measured. As labeled in Figure 12, the Ith level for the lower two curves is 1 μΑ, and is 40 μΑ for the upper two curves. The effect of raising the Ith, is to force the Vt measurementto be at a higher Vg level even though the amount of charge trapped in the silicon nitridelayer is identical for all measurements. For the lower two curves (Ith of 1 μΑ) the forwardand reverse threshold voltages start to separate from each other at a Vd of approximately50 mV while the Vt for the reverse saturates at approximately 0.6 V. For the upper twocurves (Ith of 40 μΑ) the forward and reverse threshold voltages start to separate from each 25 31

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other at a Vd of approximately 0.35 V while the Vt for the reverse saturates atapproximately 1.35 V. Thus, these curves clearly show that the effect of the trapped chargedepends heavily on the choice of Vg. 5 Erasing Prior Art Memory Devices

As discussed previously in connection with U.S. Patent No. 4,173,766, issued toHayes, a major disadvantage of the Hayes prior art insulated gate device is the difficulty inusing the Hayes device to construct a flash EEPROM. A consequence of using anoxide-nitride structure as opposed to an oxide-nitride-oxide structure is that duringio programming the charge gets distributed across the entire nitride layer. The absence of thetop oxide layer lowers the ability to control where the charge is stored in the nitride layer andallows holes from the gate to neutralize charge in the nitride layer. A thick nitride layer isrequired in order to generate sufficient charge retention in the device. However, therelatively thick nitride layer causes the charge trapping region to be very wide thus makingis erasing the cell difficult if not impossible. Thus there is a tradeoff between charge retentionand sufficiently large threshold voltage deltas on the one hand and the ability to erase the device on the other hand.

Some of the prior art devices that use hot electron programming utilize an erasemechanism whereby the electrons previously trapped in the nitride are neutralized (i.e., 20 erased) by transferring holes into the nitride. The information is erased by grounding thegate and applying a sufficient potential to the drain to cause avalanche breakdown.Avalanche breakdown involves hot hole injection and requires relatively high voltages onthe drain for the phenomenon to occur. The hot holes are generated and caused to jumpover the hole potential barrier of the bottom oxide between the channel and the nitride and 25 recombine with the electrons in the nitride. This mechanism, however, is very complex 32

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and it is difficult to construct memory devices that work in this manner. Another disadvantage of using hot hole injection for erasing is that since the drain/substrate junctionis in breakdown, very large currents are generated that are difficult to control. Further, the number of program/erase cycles that the memory cell can sustain is limited because thebreakdown damages the junction area. The damage is caused by very high localtemperatures generated in the vicinity of the junction when it is in breakdown.

Erasing the Memory Device of the Present Invention

The erase mechanism of the flash EEPROM memory cell 10 (Figure 5B) will

10 now be described in more detail. The mechanism used to erase the flash EEPROM memory cell of the present invention involves the movement of electrons as opposed to themovement of holes. An erase is performed by removing electrons from the charge trappingnitride region 68 either through the gate 24 via the top oxide 22 or through the drain 16 via the bottom oxide 18. 15 One technique is to simultaneously apply a negative potential to the gate 24 and a positive potential to the drain 16 such that electron tunneling occurs from the chargetrapping nitride layer 20 to the drain 16 via the bottom oxide 18. The electron tunneling issubstantially confined to a local area near the drain 16. To facilitate the erasing of thememory cell 10 using this technique, the thickness of the bottom oxide layer 18 is suitably 20 constructed (i.e., has a thickness of about seventy (70) Angstroms) to optimize the removalof electrons from the nitride charge trapping layer 20 into the drain 16. A second well known technique is to simultaneously apply a positive voltagepotential to the gate 24 and zero potential, i.e., ground, to the drain 16 such that electrontunneling occurs from the charge trapping nitride layer 20 through the top oxide 22 to the 25 gate 24. In this case, the thickness of the top oxide 22 is suitably constructed to optimize 33

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10 15 20 the tunneling of electrons from the nitride charge trapping layer 20 into the gate 24 in orderto facilitate the erasing of the memory cell 10. In one embodiment, the top oxide 22 has athickness of 50 Angstroms to 80 Angstroms for a voltage on gate 24 of 10 to 18 volts. A graph illustrating the effect of programming on erase for the forward andreverse directions is shown in Figure 13. The graph presented in Figure 13 is based on dataobtained from a memory cell constructed in accordance with the present invention. Thetop oxide 22, bottom oxide 18 and nitride 20 layers are each 100 Angstroms thick.Programming for forward and reverse utilized a Vd of 5.5 V and VG of 10 V. The forwardand reverse programming curves are identical to those illustrated in the graph of Figure 8.The erase curves for the trapped charge associated with forward read and reverse readutilized a VD of 5.5 V and a VG of-8 V.

As can be seen from Figure 13, the slopes of the forward and reverse erasecurves are different. Reading in the reverse direction requires trapped charge so muchsmaller than does reading in the forward direction that the erase is approximately 10 to 20times more effective. Also apparent from Figure 13 is that the cell does not enter deepdepletion. Even at the 1 second erase mark, the threshold voltage (about 2v) is no lowerthan that of an unprogrammed cell. This is a huge advantage of the memory cell of thepresent invention over prior art memory cells especially floating gate cells where over erasecan cause a failure of the memory array due to deep depletion of the charge on the floating gate.

The erase mechanism in the memory cell is self limiting due to the fact that asthe memory cell is erased, more and more positive charge is stored in the trapping region68 of the nitride layer thereby neutralizing the negative charge stored there while theremainder of the nitride layer 20 remains unaffected. Thus, the threshold voltage of the 25 channel keeps dropping until it levels off at the threshold voltage of an unprogrammed 34

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10 15 20 memory cell which is the threshold voltage of the larger majority of the channel closer tothe source. Over erasing the memory cell of the present invention only affects (i.e., lowers)the threshold voltage of the portion of the channel under the charge trapping region 68which is a relatively narrow region while leaving the threshold voltage of the remainder of the channel at its normal value.

As explained previously, a result of reading in the reverse direction is that anarrower charge trapping region is required due to the higher efficiency of the reverse read.Since erasing is always performed through the drain 16, less charge needs to be moved offthe charge trapping layer 20 and directed through the drain 16. Thus, reading the memory cell 10 in the reverse direction enables much faster erase times. This makes the entire erase process much easier than in the prior art memory device. In the prior art memory device(i.e., forward programming/forward read), the charge trapping region 66 (Figure 5A) wasmuch bigger and wider to achieve the desired change in threshold voltage, thus making theerase process more difficult. To erase the cell 41, a larger amount of charge spread outover a wider trapping region 66 must be directed through the drain 34. The danger withthis lies in that if the charge trapping region 66 becomes too wide, the cell 41 may never beable to be completely erased. The charge trapping region 66 may become too wide if thedevice is overprogrammed which is a real possibility when programming and reading in the forward direction. A graph illustrating the effects associated with over-programming on the abilityto erase in the forward and reverse directions is shown in Figure 14. The graph presentedin Figure 14 was constructed using data obtained from a memory cell 10 constructed inaccordance with the present invention. The top oxide 22 (Figure 5B), bottom oxide 18 andnitride layer 20 are each 100 Angstroms thick for a total ONO thickness of 300 Angstroms.Programming utilized a Vd of 5.0 V and Vq; of 10 V. Erasing utilized a Vd of 5.0 V and a 25 35

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Vg of -8 V. Note that programming and erasing are both in the forward direction. Reading,however, is either in the forward or reverse direction. It is the reverse direction read inconjunction with the careful control of the gate voltage to be within a selected range, that yieldsthe advantages of this invention.

In this case, the memory cell, which has been programmed for 100 milliseconds, doesnot fully erase in a reasonable time (shown in Figure 14 as 100 milliseconds) with Vt beingapproximately 7 V after 100 milliseconds of erase for reading in both the forward and reversedirections. The cell 10 cannot be erased because it has been over programmed, meaning thecharge trapping region was made too wide to effectively erase. After 100 milliseconds ofprogramming, the charge trapping region is very wide. The 13 V (Vd of 5 V and Vg of -8 v)that is applied across the charge trapping region 68 (Figure 5B) to erase the trapped charge iseffective in removing the electrons that are close to the drain 16. However, the electrons thatare trapped further away from drain 16 towards the middle of the channel cannot be effectivelyremoved because the electric field created by the 13 V potential difference between the drainand the gate is much weaker at that point.

As is apparent from Figures 13 and 14, the slopes of the forward and reverse programcurves are different. After approximately one millisecond, the forward program curve exhibitsa higher slope than the reverse program curve. This shows that reading in the reverse directionis more tolerant of over programming than reading in the forward direction in the sense that agiven uncertainty in programming time causes a bigger uncertainty in threshold voltage Vtwhen reading in the forward direction than when reading in the reverse direction. Whenreading in the reverse direction, a Vt of about 4 V is reached after approximately 100microseconds of programming. Even if programming continues up until a millisecond, a factorof 10X, the VT for reading in the reverse direction is only approximately 4.5 V. For reading inthe forward direction, a Vt of 4 V is reached only after approximately 7 milliseconds of 36

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10 15 20 programming. If programming is off by only 3X, the VT increases to approximately 8.3 V. At this high Vt, it is not likely that the device can be erased.

Thus, it is important to stress that reading the memory device in the reverse directiondoes not just enable simpler and faster erasing, but in fact, if the device is to be read in theforward direction and the trapped charge is so adjusted to give the desired threshold voltage Vt,erasing is likely to be not possible at all. This is because much more charge must be trapped onthe dielectric 20 beneath the gate 24 to achieve a usable difference in threshold voltage VTbetween the programmed and the unprogrammed state than when reading in the reversedirection. This makes erasing the memory device at best difficult if not impossible thus makingthe forward programming/forward read impractical for this type of memory device which must be erasable.

The graph of Figure 14 also emphasizes the higher effectiveness during erase of thevoltage on the drain versus the gate. The gate voltage is not as effective due to the distance ofthe gate voltage from the trapped charge which includes the thicknesses of the top oxide 22 andthe nitride layer 20. The drain voltage is more effective since it is more proximate to the region68 of trapped charge. However, the gate voltage is more crucial when the width of the trappedcharge region 68 is narrow. In this case, the gate voltage will be effective in creating an electricfield that covers the entire charge trapping region 68 making the removal of electrons moreefficient. The trapped charge region can only be made sufficiently narrow if the device is readin the reverse direction because only when the device is read in the reverse direction does arelatively small amount of charge stored on the dielectric under the gate yield a sufficientlylarger difference in threshold voltage Vt to allow the programmed state (i.e., charge stored onthe gate) and the unprogrammed state (i.e., no charge stored on the gate) to be differentiated.As discussed previously, if the device is read in the forward direction, the charge trapping 37

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10 15 20 region must be made wide enough to generate a sufficient threshold voltage to differentiate between the programmed and the unprogrammed states. A graph illustrating the programming and erasing curves representing the use of oxideversus TEOS as the dielectric on top of the nitride is shown in Figure 15. The chart presentedin Figure 15 was constructed using data obtained from two memory cells constructed inaccordance with the present invention, one memory cell using TEOS to form the oxide on topof the nitride and the other memory cell using thermal oxidation of the nitride to form the topoxide layer. The top oxide, bottom oxide and nitride layers are 70, 100 and 80 Angstromsthick, respectively. The width/length ratio for each memory cell channel is 0.6/0.65 microns.Programming (which is always done in the forward direction) utilized a Vd of 5.0 V and a Vo,of 10 V. Erasing (which is also always done in the forward direction) utilized a Vd of 5.0 Vand a Vg of -6 V. This chart shows that there is little difference in the programming and erasecharacteristics when either oxide or TEOS is placed on top of the nitride. A graph illustrating erase times for a gate voltage of zero with two different values ofdrain voltage is shown in Figure 16. Both curves were generated by first programming in theforward direction for about 10 microseconds, until the threshold voltage Vj equals about 4 Vand then erasing in the forward direction. For the upper curve, the gate 24 was grounded and6.0 V applied to the drain 16, For the lower curve, the gate 24 was grounded and 6.5 V appliedto the drain. For both curves, the threshold voltage is raised during programming from nearly 1.5 V to approximately 4 V. Erasing then brings the Vt back down to approximately 1.7 V.Note that the time to erase the charge from the dielectric decreases as the drain voltageincreases. The curves show that it takes about 100 seconds with a gate voltage of 6.5 V to erase(i.e., remove) sufficient charge from the dielectric to bring the threshold voltage of the devicedown to about 1.9 V and that it takes about 1000 seconds with a gate voltage of 6.0 V toachieve the same threshold voltage. 25 38

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10 A graph illustrating the erase curve for two different values of negative gate voltage isshown in Figure 17. The graph presented in Figure 17 was constructed using data obtainedfrom a memory cell constructed in accordance with the present invention. The thickness ofeach of the top oxide 22, bottom oxide 18 and nitride 20 layers is 100 Angstroms for a totaldielectric thickness of 300 Angstroms. The channel width/length ratio is 0.6/0.65 microns. For the reverse direction, a constant Vd of 5.5 V and a Vq of -5 V versus a Vq of -7.5 V were utilized. The graph shows that drain and gate voltages on the order of 5 V and -5 Vrespectively, are sufficient to enable an effective erase. This is a big advantage over the priorart where erase voltages of around -10 V on the gate are more typical. The graph also showsthat lowering Vg to -7.5 V is effective to erase the device approximately 20 times faster whilestill retaining a Vg less than 10 V.

Benefits of Reading in the Reverse Direction

Reading the graph in Figure 10, one can see that to achieve a Vx equal to 15 approximately 2 V in the channel (i.e., the same conditions as the prior art memory devicewith 3 V applied to the gate) when reading in the reverse direction, approximately 4 V mustbe applied to the gate. When, for example, 3 V is applied to the gate and the device is readin the reverse direction, only approximately 1.2 V is generated in the channel. This is indirect contrast to the prior art reading in the forward direction wherein the potential across 20 the trapped charge region was almost the full potential applied to the drain (i.e., 2 v). Thissignificant benefit of reading in the reverse direction is that for the same gate voltage a muchlower voltage is present across the portion of the channel under the region of trapped charge.This results in dramatically less leakage current for the same charge trapping 39

P-1326-IL length. Or stated another way, a shorter charge trapping region is needed in the gatedielectric to achieve an equivalent amount of leakage current. A shorter charge trappingregion translates through an exponential function to shorter programming times. Adiscussion of the variation in programming time as a function of various parameters,voltage and temperature is given in a paper entitled "Hot-Electron Injection Into the Oxidein n-Channel MOS Devices," B. Eitan and D. Frohman-Bentchkowsky, IEEETransactions on Electron Devices, March 1981, incorporated herein by reference.

The effect of reading the memory device in the reverse direction is to amplifythe effect of the trapped charge (i.e., the programmed region or the localized trappingregion) on the threshold voltage thereby allowing much less charge to be trapped to achievethe same difference in threshold voltage between the programmed state (i.e., charge storedin the charge trapping region of the gate dielectric) and the unprogrammed state (i.e., nocharge stored in the charge trapping region of the gate dielectric) of the device. For thesame programming time (meaning the same length of trapped charge in the nitride, forexample as shown in Figures 5A and 5B), device 10, when read in the reverse direction,exhibits a leakage current I* approximately two orders of magnitude less than that of aprior art memory cell. As previously discussed, by reading in the reverse direction, a majorbenefit is that the programming time can be reduced because the leakage current issignificantly less and thus less trapped charge is required to achieve the same leakagecurrent as when reading in the forward direction. Thus, the size of the trapping region doesnot have to be as large as with prior art memory cells which translates exponentially intoshorter programming times. A key advantage of reading in the opposite direction from programming is that the effect of the lateral electric field next to the charge trapping region is minimized. In addition, the gate voltage can be reduced to further minimize the potential in the channel. 40

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10 15 20

In fact, the gate voltage can be set to achieve the desired voltage in the channel. This wasdescribed previously with reference to Figure 10. Reducing the gate voltage while readingin the reverse direction minimizes the transfer of high voltage to the trapped charge region.

The area of charge trapping necessary to program memory cell 41 of the prior artis illustrated in Figure 18A and the area of charge trapping necessary to program memorycell 10 of the present invention is illustrated in Figure 18B. The trapping region 68 ofdevice 10 is shown much smaller than trapping region 66 of the prior art device. Asdescribed earlier, reading in the reverse direction permits a smaller (i.e., shorter) charge trapping region.

Programming a smaller, narrower region of trapped charge has numerousbenefits. One major benefit is that programming times are reduced while the delta inthreshold voltage between the programmed versus unprogrammed states remain the same.Thus, short programming times are achieved by taking advantage of the asymmetriccharacteristics of the trapping dielectric flash EEPROM memory cell. Another majorbenefit is that the erase mechanism of the memory cell is greatly enhanced.

Programming in the forward direction and reading in the reverse directionenables limiting the width of the charge trapping region to a narrow region near the drain.This allows for much more rapid and thus more efficient erasing of the memory cell.

Yet another benefit of reading in the reverse direction, as described above, is thata narrow charge trapping region increases the effectiveness of the gate voltage during erasewhen combined with relatively low applied gate voltages. A narrow charge trapping regionis allowed only by reading in the reverse direction while applying low gate voltages during the read.

Further, utilizing a thinner silicon nitride charge trapping layer than disclosed in25 the prior art helps to confine the charge trapping region to a region near the drain that is 41

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10 15 laterally narrower than in the prior art. This improves the retention characteristic of thememory cell. Further, the thinner top and bottom oxide sandwiching the nitride layer helpsretain the vertical electric field.

In addition, when the memory cell is read in the reverse direction, it is moretolerant of over programming. Reading in the forward direction, causes the thresholdvoltage of the memory cell to be very sensitive to inaccuracies in programming time whilereading in the reverse direction reduces this sensitivity of threshold voltage to programmingtime. Over programming while programming to allow reading in the forward direction canpotentially cause the device to become non erasable.

The voltage Vx in the channel is a function of the gate voltage and the impuritylevel in the channel. Vx is the voltage in the channel just beneath the edge of the trappedcharge region above the channel (Figure 5B). A higher gate voltage translates to a highervoltage in the channel. When the device is N channel, the impurity in the channel regionbefore inversion is usually boron. But the voltage Vx is generally independent of the boronimpurity level over a normal range of values in the forward reading mode, but Vx isdependent on the impurity level in the reverse direction, becoming smaller as the impuritylevel goes up. Indeed in the reverse direction the voltage Vx in the channel just beneath theedge of the trapped charge region is given by the following expression

Fv= Fy-fFr+AVr) 20 where Vy is the device threshold voltage for zero substrate bias and AVy is the incremental increase in threshold voltage due to substrate back bias caused by a finite valuefor Vx when the channel is just inverted.

Various thicknesses were tried for the second oxide layer 22 in the ONO structureof Figures 5B and 18B. The following table presents the combinations of thicknesses for 25 the ONO layers that were constructed for three embodiments of the memory cell of thisinvention. Note that all thicknesses are in Angstroms in the table below.

Layer Embodiment #1 Embodiment #2 Embodiment #3 Top Oxide ('O' Layer 22) 150 100 70 Nitride ('Ν' Layer 20) 50 50 50 Bottom Oxide ('0' Layer 18) 70 70 70 Total Thickness 270 220 190 42

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The nitride layer 20 retains the stored charge. By employing the reverse read asopposed to the forward read, the amount of charge required to be retained for a given shiftin threshold voltage is reduced by a factor typically of two or more. By making the nitridelayer 20 thinner and the top oxide layer 22 thicker, the amount of charge required to bestored on the nitride layer 20 for a given threshold voltage shift is also reduced.

It is also noted that as the thickness of the top oxide layer 22 increased, the lateralfields associated with the charge stored on the 50 Angstrom thick nitride layer 20 decreasedslightly. It is also observed that as the thickness of the bottom oxide layer 18 was madethinner, the erase of the charge stored on the nitride layer 20 becomes easier. For a 70Angstrom thick bottom oxide layer 18, the charge stored on the nitride layer 20 is moreeasily erased than if the bottom oxide layer 18 is 100 Angstroms thick.

Thus, the conclusion is that the thinner the nitride layer the better for the purposesof the present invention. Nitride layers as thin as 20 Angstroms are believed possible withthis invention. The thinner nitride layer reduces the lateral field associated with a givencharge stored in a portion of the nitride layer and thus reduces the lateral dispersion of thestored charge as a result of the internally generated electric field associated with the storedcharge.

Optimization Parameters

In terms of optimization, three parameters can be varied to give the quickestprogramming time and the widest margins. The first parameter is the channel length. Alonger channel length, for a given programming time when reading in the reverse direction,increases the distance between the drain and the trapped charge (effectively, the source anddrain designations are flipped). This lowers the level of the lateral electric field even lower.

The second parameter, as described previously, is the gate voltage which can beset to minimize the voltage drop in the channel across the channel region beneath thetrapped charge. This further reduces the lateral electric field in the channel beneath thetrapped charge. Within limits, the voltage in the channel can be 'dialed in' by varyingthe voltage on the gate. This allows control over the voltage drop in the channel beneaththe region of trapped charge. If the gate voltage is made too low then reading a 'Γ, i.e.,the unprogrammed state, becomes problematic. The gate voltage for reading a '1' mustbe still high enough to generate inversion in order to produce sufficient read current for 43

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the sense amplifiers. Thus, a lower limit for the gate voltage is approximately 1 V abovethe threshold voltage. An upper limit on the gate voltage is the voltage at which thevoltage in the channel just beneath the edge of the region of trapped charge is just belowthe voltage potential applied to the source terminal during reading in the reverse 5 direction. A too high gate voltage will cause inversion in the channel and the benefits ofthe present invention are lost. Thus, it is not recommended to apply a gate voltagewhich generates a high voltage in the channel beneath the edge of the charge trappingregion because it defeats the benefits of having a lower potential across the portion ofthe channel beneath the charge trapping region with the accompanying reduction in io leakage current and shortened 44

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10 15 20 programming time. In a preferred embodiment of the present invention, the gate voltageused for reading is approximately 3 V which represents an optimized tradeoff betweenprogramming time and leakage current.

The third optimization method, previously described and which is known in theart, is to vary the boron doping of the channel region under the gate. An increase in thedoping concentration results in a higher threshold voltage Vt and a lower voltage generatedin the channel. This is due to the reduction in the width of the depletion region formed.Thus, a higher doping concentration permits a higher gate voltage to be applied for thesame voltage across the portion of the channel beneath the charge trapping region.

In addition, an increase in the Na doping concentration for the same lengthtrapping region will improve the punch through behavior of the device. By varying thelevel of boron implanted in the channel region, the width of the depletion region under thegate can be varied. An increase in the doping concentration results in a reduction in thewidth of the depletion region for the same applied gate voltage. The reduction in the widthof the depletion region occurs because there is now more fixed charge in the substrate.

Thus, varying the doping concentration can be used to limit the length of the pinchoff ( region under the gate. In addition, the doping concentration can be used to increase ordecrease the initial threshold voltage of the device.

While the invention has been described with respect to a limited number ofembodiments, it will be appreciated that many variations, modifications and otherapplications of the invention may be made. 45

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