Data processing of an audio signal

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Data processing of an audio signal

Koninklijke Philips Electronics N.V. C.112163 WO 98/20483 ΨΌΊΪΊ397,''01203

Data processing of a bitstream signal

The invention relates to a data processing apparatus for data processing an audio signal, to a data processing method, a transmitter comprising the data processing apparatus, a transmitter in the form of a recording apparatus, a record carrier, to second data processing apparatus for reconverting an input signal into a replica of the audio signal, to a 5 receiver comprising the second data processing apparatus, to a receiver in the form of areproducing apparatus and to a transmission signal comprising a data compressed residualbitstream signal. 10 Data processing an audio signal is well known in the art. Reference is made in this respect to EP-A 402,973, document DI in the list of related documents. Thedocument describes a subband coder, in which an audio signal is A/D converted with aspecific sampling frequency, such as 44.1 kHz, and the resulting samples in de form of eg. 24 bits wide words of the audio signal, are supplied to a subband splitter filter. The subband 15 splitter filter splits the wideband digital audio signal into a plurality of relatively narrow bandsubband signals. Using a psycho acoustic model, a masked threshold is derived and blocks ofsamples of the subband signals are subsequently quantised with a specific number of bits persample for each block of the subband signals, in response to said masked threshold, resultingin a significant data compression of the audio signal to be transmitted. The data compression 20 carried out is based on ’throwing away’ those components in the audio signal that areinaudible and is thus a lossy compression method. The data compression described indocument DI is a rather intelligent data compression method and requires a substantialnumber of gates or instructions, when realized in hard or software respectively, so that it isexpensive. Moreover, the subsequent expansion apparatus also requires a substantial number 25 of gates or instructions, when realized in hardware or software respectively .

The invention aims at providing a data processing apparatus forprocessing an audio signal such that it can be data compressed by a lossless coder in a

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WO 98/20488 PCT/IB97/01303 2 relatively simple way. Further, the .invention aims at providing a corresponding data processing apparatus for reconverting the processed bitstream signal into a replica of the audio signal.

The data processing apparatus in accordance with the invention comprises 5 - input means for receiving the audio signal, conversion means for carrying out a conversion on the audio signal so as toobtain a 1-bit bitstream signal, the conversion means comprising sigma-deltamodulator means, prediction means for carrying out a prediction step on a signal so as to obtain a 10 predicted bitstream signal, signal combination means for combining the bitstream signal and the predictedbitstream signal so as to obtain a residual bitstream signal, and output means for supplying the residual bitstream signal.

The invention is based on the following recognition. Bitstream signals take ___ 15 up a considerable amount of capacity. To illustrate this: in a current proposal for a newstandard for an optical audio disk, the disk will contain two channels of bitstream convertedaudio signals, sampled at 64.fs, where fs= 44.1 kHz. This corresponds to a rate four timeshigher than a current CD audio disk. As discussed in an earlier filed but not yet publishedpatent application no. 96202807.2 in the name of applicant, document D7 in the list of 20 related documents that can be found at the end of this description, already low complexitylossless coding algorithms, such as fixed Huffman table coding, are able to reduce thiscapacity to a certain extent. Experiments have revealed that even higher lossless compressionratios can be obtained using more sophisticated, more complex algorithms, such as Lempel-Ziv. 25 Mainly in audio/speech coding, linear prediction is known to be a powerful technique. By removing redundancy from a speech/audio signal prior toquantization, the entropy of signal after quantization can be significantly reduced. The signalsat the input and output of a predictor are either in a floating point or a multi bitrepresentation. 30 In lossless coding of bitstream signals, the complexity of the algorithm, especially at the decoder side is of importance. However, generally, the performance of thelossless coding algorithm is closely related to its complexity.

In accordance with the invention, prediction is used on bitstream signals,ie. signals with only two different representation symbols, either Ό’ or T. This has the WO 98/20488 PCTTS97/01303 3 advantage of an increase of lossless .compression performance, for only a marginal extracomplexity.

Experiments have revealed that already a third order prediction hasconsiderable effect on the statistics of the resulting signal. By means of prediction, as apreprocessing step, prior to data compression, the probability of a Ί’-bit can be broughtdown from 50 % to about 20 %. The effect of this is that the output of the apparatus inaccordance with the invention contains long runs of ’zeroes’, which can be exploited bysimple Huffman coding or run-length coding.

The audio signal can be applied in analog form or in digital form. When A/Dconverting, in accordance with the invention, an analog audio signal with a 1-bit A/Dconverter (also named: bitstream converter or sigma-delta modulator), the audio signal to beA/D converted is sampled with a frequency which is generally a multiplicity of the frequencyof 44.1 kHz or 48 kHz. The output signal of the 1-bit A/D converter is a binary signal,named bitstream signal. When the audio signal is supplied in digital form, sampled at eg. 44.1 kHz, the samples being expressed in eg. 16 bits per sample, this digital audio signal isoversampled with a frequency which is again a multiplicity of this sampling frequency of 44.1 kHz (or 48 kHz), which results in the 1-bit bitstream signal.

Converting an audio signal into a 1-bit bitstream signal has a number ofadvantages. Bitstream conversion is a high quality encoding method, with the possibility of ahigh quality decoding or a low quality decoding with the further advantage of a simplerdecoding circuit. Reference is made in this respect to the publications Ά digital decimatingfilter for analog-to-digital conversion of hi-fi audio signals’, by J.J. van der Kam, documentD2 in the list of related documents, and Ά higher order topology for interpolativemodulators for oversampling A/D converters’, by Kirk C.H. Chao et al, document D3 in thelist of related documents. 1-bit D/A converters are used in CD players, as an example, to reconvertthe bitstream audio signal into an analog audio signal. The audio signal recorded on a CDdisk is however not data compressed, prior to recording on the disk.

It is well known in the art that the resulting bitstream signal of the 1-bitA/D converter is, roughly said, a random signal which has a ’noisy-like’ frequencyspectrum. Such types of signals are hard to data compress.

Surprisingly, however, it was established that applying a prediction step,prior to data compression, eg. using a lossless coder, a significant data reduction could beobtained, in spite of the noisy character of the bitstream signal from the 1-bit A/D converter.

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WO 98/20488 PCT/IDB97/G1303 4

These and other aspects of the invention will be apparent from andelucidated further with reference to the embodiments described in the following figuredescription, in which 5 figure 1 shows an embodiment of the data processing apparatus, figure 2 shows part of an embodiment of a prediction unit for use in the apparatus of figure 1, figure 3 shows an embodiment of the prediction unit and the signalcombination unit incorporated in the data processing apparatus, 10 figure 4 shows the data processing apparatus of figure 1 incorporated in a recording apparatus for recording the residual bitstream signal on a record carrier, figure 5 shows the data processing apparatus incorporated in atransmission apparatus for transmitting the residual bitstream signal via a transmissionmedium, 15 figure 6 shows a further embodiment of the recording apparatus, further provided with an error correction encoder and a channel encoder, figure 7 shows an embodiment of another data processing apparatus forreconverting the residual bitstream signal into a replica of the original audio signal, figure 8 shows an embodiment of the signal combination unit and the20 prediction unit incorporated in the apparatus of figure 7, figure 9 shows the data processing apparatus of figure 7 incorporated in areproducing apparatus for reproducing the residual bitstream signal from a record carrier,and figure 10 shows the data processing apparatus of figure 7 incorporated in25 a receiving apparatus for receiving the residual bitstream signal from a transmission medium, figure 11 shows a further embodiment of the reproducing apparatus,further provided with a channel decoder and an error correction unit, figure 12 shows the derivation of a conversion table for another30 embodiment of the prediction unit in the apparatus of figure 1, figure 13 shows another embodiment of the data processing apparatus,figure 14 shows an embodiment of a data processing apparatus for reconverting the residual bitstream signal obtained by the apparatus of figure 14 into areplica of the original audio signal,

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WO 98/204SS PCT/I397/013G3 5 figure 15 shows .the application of a data compression unit in a recording apparatus, figure 16 shows the application of a data expansion unit in a reproduction apparatus, 5 figure 17a shows the frequency spectrum of the output signal of the 1-bit A/D converter of figure 1, and figure 17b shows the frequency spectrum of the same outputsignal in a smaller frequency range, figure 18 shows a modification of the apparatus of figure 1, figure 19 a data processing apparatus provided with an arithmetic coder, 10 and figure 20 a data processing apparatus provided with an arithmetic decoder.

Figure 1 shows an embodiment of the data processing apparatus in 15 accordance with the invention, comprising an input terminal 1 for receiving the audio signal.In the present example, the audio signal is an analog audio signal. The input terminal 1 iscoupled to an input 2 of a 1-bit A/D converter 4, also called: sigma-delta modulator. Anoutput 6 of the 1-bit A/D converter 4 is coupled to an input 8 of a prediction unit 10 as wellas to a first input 40 of a signal combination unit 42. An output 12 of the prediction unit 10 20 is coupled to a second input 44 of the signal combination unit 42, an output 48 of which iscoupled to an output terminal 14.

The 1-bit A/D converter 4 is adapted to carry out a 1-bit A/D conversionon the audio signal so as to obtain a bitstream signal which is supplied to the output 6. Tothat purpose, the A/D converter 4 receives a sampling frequency equal to N.fs via an input 25 16. fs is a frequency equal to eg. 32 kHz, 44.1 kHz or 48 kHz and N is a large number, such as 64. The audio signal is sampled in the A/D converter 4 with asampling frequency ofeg. 2.8224 MHz (64 x 44.1 kHz). The bitstream signal appearing at the output 6 of the A/Dconverter thus has a bitrate of 2.8224 MHz.

The prediction means 10 are adapted to carry out a prediction step on the 30 bitstream signal applied to its input 8 so as to obtain a predicted bitstream signal at its output 12. The signal combination means 42 is adapted to combine the bitstream signal applied toits input 40 and the predicted bitstream signal applied to its input 44 so as to obtain a residuebitstream signal which is supplied to its output 14.

Figure 17a shows a frequency spectrum of the bitstream signal present at

WO 9S/204SS 6 PCT/3ES97/O13O3 the output 6 of fee A.D converter 4, for an input signal in fee form of a 5 kHz sinusoid,sampled wife a sampling frequency of 2.8224 MHz. The spectrum feus shows frequenciesbetween 0 Hz and 1.4 MHz. Figure 17b shows part of the spectrum shown in figure 17a,namely that part between 0 Hz and 100 kHz, so as to more clearly show the 5 kHz sinusoid 5 comprised in the bitstream signal. Clearly visible is the noise-like character of the bitstreamsignal, especially in fee higher frequency region, which seems to imply that carrying out aprediction step on the said signal, wife a subsequent signal combination of the predictedversion of fee bitstream signal and the bitstream signal so as to obtain said residual signalwill not result in a substantial amount decrease in entropy of the residual signal, such 10 decrease of entropy of the residual signal, compared to fee input signal of the prediction unitbeing the general aim of a prediction unit.

Contrary to this, investigations have made clear feat a significant decreasein entropy of fee residual bitstream signal can be obtained by carrying out a prediction step,in spite of fee noisy-like character of the bitstream signal. 15 The prediction unit 10 can have any form, and could comprise a FIR filter or an IIR filter, where the coefficients of the filter are chosen (or derived) such, feat theoutput signal of fee prediction unit 10 is fee predicted version of fee bitstream signal.

Another embodiment of the prediction unit 10 will be further explained wifereference to figure 2 and 3. Figure 2 shows a part of the prediction unit 10, which comprises 20 a three bit shift register 20 having an input coupled to the input 8 of fee prediction unit 10.Upon fee application of three clock pulses (not shown) to the shift register 20, threesubsequent bits χυχ2,χ3 of the bitstream signal applied to the input 8 are shifted into the shiftregister 20. A detector 22 is present having an input 24 coupled to the input 8 of theprediction unit 10. The detector detects fee bit value of fee next bit x4 directly following the 25 three subsequent bits Xi,x2,x3 “ the bitstream signal. Further, a counter 26 is present whichcounts the number of times that a Ό’ bit follows a specific three bit bit sequence χ2,χ2,χ3and fee number of times feat a Ί’ bit follows that same specific three bit bit sequence. Thisis done for all the eight possible 3-bit bit sequences xj,x2,x3.

Explained in a different way. Assume that the three bit sequence Ί00’ is 30 stored in the shift register 20 and that the detector 24 detects the next bit x4 to be O’. As aresult, fee number N4&gt;0 in the column 28 is increased by one. Upon fee next clock pulseapplied to the shift register 20, the 3-bit word stored in the shift register 20 now equalsΌ00’. Assume feat fee next bit x4 now equals Ί’. As a result, fee number No&gt;1 in thecolumn 30 is increased by one.

WO 9S/204SS 1PCM397/01303 7

This procedure is continued for a relatively large portion of the bitstream signal. When the portion of the bitstream signal has been processed in this way, the columns 28 and 29 are filled with numbers Nj&gt;0,Ν|which indicate the number of occurrences of a Ό’-bit or Ί’-bit respectively as the next bit following the i-th 3-bit sequence given in column 5 32, where i runs from 0 to 7 in the present example.

Next, a predicted binary value x4’ is derived from the numbers in thecolumns 28 and 30 for each of the 3-bit sequences x^xj^ in the column 32, by taking thatbinary value (either Ό’ or Ί’) that resulted in the highest of the count number Ni&gt;0 and Nj jfor the i-th bit sequence in column 32. As an example, if N4 0 equals 78 and N4&gt;1 equals 10 532, the predicted bit x4’ in response to the occurrence of the 3-bit bit sequence Ί00’ is chosen equal to ’Γ. A conversion table can thus be derived comprising the columns .32 and34, so that for each of the eight possible 3-bit sequences stored in the shift register 20, acorresponding predicted bit x4’ can be generated. In the situation where equal count valuesNi0 and Nj j have been derived for a three bit bitsequence i, one can choose one of the two 15 binary values Ό’or Ί ’ at random as the value for the predicted bit.

It should be noted here, that two counters for each 3-bit bit combination are used to count the numbers of ’zeroes’ and ’ones’ following said 3-bit bit combination. Inspite of this, one could use only one counter which is capable of counting up upon theoccurrence of a ’zero’ bit following the 3-bit bit combination and counting down in response 20 to the occurrence of a ’one’ bit following the 3-bit bit combination. If the count value at theend of the test procedure is higher than at the beginning of the test procedure, the predictedbit will be chosen ’zero’. If the count value appears to be lower than the count value at thebeginning of the test procedure, the predicted bit will be chosen ’one’.

If the signal to be processed is substantially time invariant, it may occur 25 that, upon deriving a conversion table from a next portion of the bitstream signal, the samepredicted values x4’ will be obtained. In such case, it suffices to derive the conversion tableonce. For bitstream signals having varying properties, it may be required to each time derivethe conversion table from a subsequent portion of the bitstream signal and to predict thatportion of the bitstream using its own derived conversion table. 30 Figure 3 shows a further elaborated version of the prediction unit 10 together with the signal combination unit 42. The input 8 of the prediction unit 10 is coupledto a first input 40 of a signal combination unit 42. An output 46 of the conversion means26’, which comprises the conversion table derived in the way explained above with referenceto figure 2, is coupled to a second input 44 of the signal combination unit 42, an output 48

W0&gt; 98/204SS ?CT/TB97/M3©3 8 of which is coupled to the output 14 of the data processing apparatus. The signal combinationunit 42 can be in the form of an EXOR, but the combination unit 42 may be of a differentconstruction, such as an EXNOR.

In response to a 3-bit bit sequence X!,X2,X3 stored in the shift register 20, 5 the conversion unit 26’ supplies the bit x4’ at its output 46. This bit x4’ is a prediction of the bit x4 present at the inputs of the shift register 20 and the combination unit 42. Thecombination unit 42 combines the bits x4 and x4’ so as to obtain a residual bit. Upon asubsequent clock signal (not shown) the bit x4 present at the input of the shift register 20 isshifted into the shift register 20, so that a new 3-bit bit sequence is stored in the shift register 10 20. The conversion unit 26’ generates a new prediction bit x4’ in response to this new 3-bit bit sequence stored in the shift register 20. The signal combination unit 42 combines this new prediction bit x4’ with the new bit x4 now present at the input 40 so as to obtain a new 1 residual bit. In this way, a residual bitstream signal is obtained.

Assume that the combination unit 42 is an EXOR, the residual signal has 15 the following property. Assume that both the bits x4 and x4’ are the same, that is, either Ό’or ’Γ. The residual bit supplied by the EXOR is O’. Assume now that the bits x4 and x4’are not equal to each other. As a result, a ’Γ bit is generated as a residual bit by the EXOR42. The occurrence of the T bits in the residual signal are thus a measure for the errorsbetween the predicted bitstream signal applied to the input 44 of the combination unit 42 and 20 the bitstream signal applied to the input 40.

Figure 4 shows an embodiment of a recording apparatus comprising the data processing apparatus shown in figure 1, which may include the prediction unit shown infigure 3. The recording apparatus further comprises a data compression unit 150 for datacompressing the residual bitstream signal into a data compressed residual bitstream signal and 25 a write unit 50 for writing the data compressed residual bitstream signal in a track on therecord carrier 52. In the present example, the record carrier 52 is a magnetic record carrier,so that the write unit 50 comprises at least one magnetic head 54 for writing the residualbitstream signal in the record carrier 52. The record carrier may however be an opticalrecord carrier, such as a CD disk or a DVD disk. 30 Figure 5 shows an embodiment of a transmitter for transmitting an audio signal via a transmission medium TRM, comprising the data processing apparatus as shown in figure 1, which may include the prediction unit shown in figure 3. The transmitter again comprises the data compression unit 150 and further comprises a transmission unit 60 for applying the data compressed residual bitstream signal to the transmission medium TRM.

WO 98/2043S PCTAB97/01303 9

The transmission unit 60 could comprise an antenna 62.

Transmission via a transmission medium, such as a radio frequency linkor a record carrier, generally requires an error correction encoding and a channel encodingcarried out on the data compressed residual signal to be transmitted. Figure 6 shows such 5 signal processing steps carried out on the data compressed residual signal for the recordingarrangement of figure 4. The recording arrangement of figure 6 therefore comprise an errorcorrection encoder 56, well known in the art, and a channel encoder 58, also well known inthe art.

It has been said above that, in some applications, it suffices to use a fixed10 conversion table to process the bitstream signal. Upon reconverting the residual bitstream signal into a replica of the original bitstream signal, also a fixed conversion table suffices. Inan application where, for subsequent portions of the bitstream signal each time acorresponding conversion table needs to be determined, to generate the residual bitstreamsignal, it will be required to use the same conversion tables for the portions in question upon 15 reconverting the residual bitstream signal into the replica of the original bitstream signal. Insuch situation, it may be required to transmit side information representative of theconversion tables used for the various subsequent portions together with the residual signal soas to enable the reconversion upon reception.

As a further example, if it appears that it suffices to use only two 20 conversion tables in the processing apparatus of figure 1, such side information could simplybe a selection signal, selecting one of the two conversion tables. A correspondingreconversion apparatus could comprise the two conversion tables as well, and the selectionsignal could be used to select one of the two conversion tables so as to reconvert the residualbitstream signal into the replica of the original bitstream signal. 25 It should however be noted that, when having derived a conversion table for a portion of the bitstream signal, it is not absolutely necessary to transmit sideinformation corresponding to this conversion table to a reconverter apparatus. Thereconverter apparatus may generate the conversion table by itself. The prediction unit in thereconversion apparatus will have a low prediction accuracy in the beginning, but will ’learn’ 30 itself so as to obtain a prediction conversion table, which will be substantially identical to theconversion table used in the transmitter apparatus.

Figure 7 shows a schematic embodiment of a second data processingapparatus in accordance with the invention, which is capable of reconverting the residualbitstream signal into the replica of the original bitstream signal. The apparatus has an input WO 58/20483 PCT/IB97/G13G3 w terminal 70 for receiving the residual bitstream signal, as supplied by the data processingapparatus of figure 1. The input terminal 70 is coupled to a first input 86 of a signalcombination unit 88, which has an output 76 coupled to an input 72 of a prediction unit 74 aswell as to an input 78 of a 1-bit D/A converter 80. An output 98 of the prediction unit 74 is 5 coupled to a second input 101 of the signal combination unit 88. An output 82 of the D/Aconverter 80 is coupled to an output terminal 84.

The apparatus of figure 7 receives the residual bitstream via its input 70,which is supplied to the input 86 of the signal combination unit 88. The signal combinationunit 88 combines the residue bitstream signal received via its input 86 with a predicted 10 bitstream signal received via its input 101 so as to obtain a reconverted bitstream signal, andto supply the reconverted bitstream signal to its output 76. The prediction unit 74 carries outa prediction step on the reconverted bitstream signal so as to obtain said predicted bitstreamsignal at its output 98. The D/A converter unit 80 carries out a D/A conversion on thereconverted bitstream signal so as to obtain the replica of the original audio signal, which is 15 supplied to the output terminal 84.

The prediction unit 74 can have any form, and could comprise a FIR filter or an HR filter, where the coefficients of the filter are chosen (or derived) such, that the outputsignal of the prediction unit 74 is the predicted version of the bitstream signal.

Another embodiment of the prediction unit 74 will be further explained with 20 reference to figure 8. The input 72 of the prediction unit 74 is coupled to an input 92 of athree bit shift register 94. The three outputs of the three bit positions in the shift register 94are coupled to corresponding inputs of a conversion unit 96. The conversion unit 96comprise the conversion table discussed and explained above with reference to the figures 2and 3. An output 98 of the conversion unit 96 is coupled to a second input 101 of the signal 25 combination unit 88. The signal combination unit 88 can be in the form of an EXOR, but thecombination unit 88 may be of a different construction, such as an EXNOR. It will be clearthat, if the signal combination unit 42 of figure 3 is an EXOR, the signal combination unit 88of figure 8 must be an EXOR as well, in order to regenerate a replica of the originalbitstream signal. 30 In response to a 3-bit bit sequence xpx2,x3 stored in the shift register 94, the conversion unit 96 supplies the bit x4’ at its output 98, in the way explained above withreference to the figures 2 and 3. This bit x4’ is a prediction of the bit x4 that will be suppliedupon the next clock pulse by the combination unit 88 and stored as the new bit x3 in the mostright storage position of the shift register 94. The residual bit present at the input 86 of the

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WO 98/20438 PCT/33B97/01303 11 combination unit 88 is combined with the predicted bit x4’ so as to obtain the replica of theoriginal bit x4 in the original bitstream signal. When the residual bit is ’O’, which meant thata correct prediction was carried out in the apparatus of figure 1 and 3, the combination ofthe residual bit with the predicted bit x4’ results in the bitvalue of the bit X4’ to appear at the 5 output 90 of the combination unit 88. When the residual bit is ’Γ, which meant that anincorrect prediction was carried out in the apparatus of figure 1 and 3, the combination ofthe residual bit with the predicted bit x4’ results in the inverse bitvalue of the bit x4’ toappear at the output 90 of the combination unit 88. In both cases, a correct replica of the bitx4 will appear at the output 76 of the combination unit 88. 10 Upon a subsequent clock signal (not shown) the bit x4 present at the input of the shift register 94 is shifted into the shift register 94, so that a new 3-bit bit sequence isstored in the shift register 94. The conversion unit 96 generates a new prediction bit x4’ inresponse to this new 3-bit bit sequence stored in the shift register 94. The signal combinationunit 88 combines this new prediction bit x4’ with the next residual bit in the residual 15 bitstream signal applied to the input 86 so as to obtain a replica of the next bit x4 in thebitstream signal. In this way, the replica of the bitstream signal is obtained.

Figure 9 shows the data processing apparatus of figure 7 incorporated in areproduction apparatus. The reproducing apparatus further comprises a data expansion unit162 for data expanding the data compressed residual bitstream signal so as to obtain a replica 20 of the original residual bitstream signal and a read unit 100 for reading the data compressedresidual bitstream signal from a track on the record carrier 52. In the present example, therecord carrier 52 is a magnetic record carrier, so that the read unit 100 comprises at leastone magnetic head 102 for reading the data compressed residual bitstream signal from therecord carrier 52. The record carrier may however be an optical record carrier, such as a 25 CD disk or a DVD disk.

Figure 10 shows an embodiment of a receiver for receiving an audiosignal via a transmission medium TRM, comprising the data processing apparatus as shownin figure 7. The receiver further comprises the data expansion unit 162 and a receiving unit105 for receiving the data compressed residual bitstream signal from the transmission 30 medium TRM. The receiving unit 105 could comprise an antenna 107.

As has been explained above, transmission via a transmission medium,such as a radio frequency link or a record carrier, generally requires an error correctionencoding and a channel encoding carried out on the data compressed residual signal to betransmitted, so that a corresponding channel decoding and error correction can be carried out WO 93/20483 12 ?ΟΤ/3Β97/©1303 upon reception. Figure 11 shows the signal processing steps of channel decoding and error correction carried out on the received signal, received by the reading means ICG for the reproducing arrangement of figure 9. The reproducing arrangement of figure 11 therefore comprise a channel decoder 110, well known in the art, and an error correction unit 112, 5 also well known in the art, so as to obtain a replica of the data compressed residual bitstreamsignal.

It has also been said above that, in some applications, it suffices to use afixed conversion table to process the bitstream signal in the apparatus of the figures 1 and 3.Upon reconverting the residual bitstream signal into a replica of the original bitstream signal, 10 also a fixed conversion table suffices, so that no side information needs to be transmitted tothe processing apparatus of the figures 7 and 8. In an application where, for subsequentportions of the bitstream signal each time a corresponding conversion table needs to bedetermined in the apparatus of the figures 1 and 3, to generate the residual bitstream signal,it will be required to use the same conversion tables for the portions in question upon 15 reconverting the residual bitstream signal into the replica of the original bitstream signal inthe apparatus of the figures 7 and 8. In such situation, it will be required to transmit sideinformation representative of the conversion tables used for the various subsequent portionstogether with the residual signal so as to enable the reconversion upon reception. As anexample, this side information thus needs to be recorded on the record carrier 52, such as in 20 the application where the apparatus of the figures 1 and 3 is accommodated in a recordingapparatus and the apparatus of the figures 7 and 8 is incorporated in a reproducing apparatusof the figure 9 or 11, and be reproduced from said record carrier upon reproduction.

If it appears that it suffices to use only two conversion tables in theprocessing apparatus of figure 1, such side information could simply be a selection signal, 25 selecting one of the two conversion tables. A corresponding reconversion apparatus couldcomprise the two conversion tables as well, and the selection signal could be used to selectone of the two conversion tables so as to reconvert the residual bitstream signal into thereplica of the original bitstream signal.

The embodiments described above are based on the prediction of 1 bit 30 (x4’) following a sequence of three subsequent bits (x!,x2,x3) in the bitstream signal. In general, the prediction unit can be capable of predicting from n subsequent bits in thebitstream signal m prediction bits, said m prediction bits being predicted versions of msubsequent bits in the bitstream signal following said n subsequent bits in the bitstreamsignal, where n and m are integers larger than zero.

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WO 98/20488 PCT/IB97/G13G3 13

Figure 12 shows an example how to derive a conversion table which iscapable of predicting one or two prediction bits from a sequence of four consecutive bitsXj,x2,x3,x4 ώ the bitstream signal. Figure 12 shows a part of another prediction unit 10’,which comprises a four bit shift register 20’ having an input coupled to the input § of the 5 prediction unit 10’. Upon the application of four clock pulses (not shown) to the shift register20’, four subsequent bits x1,x2,x3,x4 of the bitstream signal applied to the input 8 are shiftedinto the shift register 20’. A detector 22’ is present having an input 24 coupled to the input 8of the prediction unit 10’. The detector 22’ detects the bit value of the next two bits x5,x6directly following the four subsequent bits X!,x2,X3,x4 in the bitstream signal. Further, a 10 counter 26” is present which counts the number of times that a Ό’ bit follows a specific fourbit bit sequence x1,x2,x3,x4, the number of times that a Ί’ bit follows that same specificfour bit bit sequence, the number of times that a two bit bitsequence Ό0’ follows that samespecific four bit bit sequence xi,x2,x3,x4, the number of times that a two bit bitsequence ΌΓfollows that same specific four bit bit sequence, the number of times that a two bit _ 15 bitsequence Ί0’ follows that same specific four bit bit sequence xj,x2,x3,x4 and the numberof times that a two bit bitsequence ΊΓ follows that same specific four bit bit sequence. Itshould be noted here, that the 2-bit bit combination ’bj,b2’ will be expressed such that thefirst bit bj is the bit x5, where the second bit b2 is the bit x6.

Suppose that the detector 22’ has detected that the two bits xs,x6 equal 20 ’01’. As a result, the counter 26” increases the count value Ni&gt;0 in the column 28’ by one and the count value Ni3 in the column 30’ by one, where i runs from 0 to 15 andcorresponds to the i-th four bit bitsequence given in the column 32’ of the table in figure 12.

Next, upon the application of a number of P clock pulses to the apparatusof figure 12, where P need not necessarily be equal to 2, but may be larger, another 4-bit 25 bitsequence x1,x2,x3,x4 of the bitstream signal is stored in the shift register 20’. The detector22’ detects the bit values of the next two bits x5,x6 in the bitstream signal following the said4-bit bitsequence. Suppose, the next two bits equal ’ll’. As a result, the counter 26”increases the count value Njj in the column 29 by one and the count value Nj ^ in thecolumn 31 by one, where i corresponds to the four bit bitsequence stored in the shift register 30 20’, which is assumed to be the i-th four bit bitsequence given in the column 32’ of the tablein figure 12.

This procedure is repeated a plurality of times, so that for all the sixteenpossible 4-bit bit sequences xj,x2,x3,x4 the count values Ni&gt;0 to Nij5 have been obtained. Thecount values Ni 0 to Nj 5 indicate the number of occurrences of the one bit and two bit WO 98/20483 14 PCT/3B97/01303 bitsequencss following the i-th 4-bit sequence given in column 32’.

Next, either a predicted binary value x5’ or a predicted 2 bit binary sequence x5’x6’ is derived, based upon the count values in the columns 28’, 29, ... to 31, for each of the 4-bit sequences Xj,x2,x3,x4 in the column 32. 5 Suppose that the count value Ni 0 or the count value Νί?1 of the six count values Ni&gt;0 to Ni&gt;5 for the i-th 4 bit bitsequence in column 32’ is substantially larger than allthe others. In such situation, one can decide to choose the Ό’ bit or ’Γ bit, respectively, asthe prediction bit x5’. Suppose that Ni&gt;0 and Ni&gt;2 do not differ very much and are larger thanthe other four count values.In such situation, one could decide to choose the bit combination 10 Ό0’ as the prediction bits for the i-th bitsequence. In this way, the conversion table obtained can thus comprise a column 33 which may comprise either a onebit value as a prediction bit for predicting the bit following a specific 4-bit bit sequence in

I the bitstream signal, or a 2-bit binary word as a 2-bit prediction word for predicting the 2-bitword following another specific 4-bit bit sequence in the bitstream signal. 15 Figure 13 shows schematically another embodiment of the data processing apparatus for data processing an audio signal, which comprises a conversion unit 130 in theform of a conversion table, such as the one explained with reference to figure 12. Thatmeans that the conversion table comprises the columns 32’ and 33 given in figure 12, so thatupon the receipt of a specific 4-bit bit sequence x1}x2,x3,x4, as given in column 32’, a 20 specific prediction bit x5 or two specific prediction bits x5,x6 will be generated at the output131 of the conversion unit 130.

The functioning of the apparatus of figure 13 is as follows. In response toa specific 4-bit bitsequence stored in the shift register 20’ the conversion unit 130 generates,as an example a one bit word, equal to ’Γ. This is the case when a 4-bit sequence Ό000’ is 25 stored in the shift register 20’. The column 33 shows that upon such 4-bit sequence, seecolumn 32’ in the table of figure 12, a ’Γ bit is predicted, see the column 33 in the table offigure 12. The predicted bit x5’ is supplied to the input 44 of the combination unit 42 inwhich the predicted bit x5’ is combined with the real bit x5 in the bitstream present at theinput 40. Next, upon one clock pulse, generated by a central processing unit 132, the 30 information in the shiftregister 20’ is shifted one position to the left, so that the bit x5 is nowstored in the most right storage location of the shift register 20’. Suppose, this bit was indeeda ’Γ bit, as predicted.

Next, the conversion unit converts the 4-bit sequence ’0001’ stored in theshift register 20’ into a 2-bit word ’01’, see the columns 32’ and 33 in the table of figure 12,

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W© 98/20488 15 PCT/TS97/013O3 which 2-bit word is supplied io the output 131. The central processing unit 132 nowgenerates two clock pulses so that the 2-bit prediction word ΌΓ can be combined in thecombination unit 42 with the actual bits «5,^5 in the bitstream signal. The two clock pulsesalso result in a shift by two positions to the left in the shift register 20’ so that the shift 5 register has the values Ό’ and T stored in the positions in the shift register 20’, indicated 'by Xj and x2, and the actual bits x5 and x6 mentioned above are now stored as the new bitsx3 and x4 in the shift register 20’. Thus, upon predicting one bit, the central processing unit132 generates one clock pulse, after which a subsequent prediction step is carried out,whereas, upon predicting a 2-bit word, the central processing unit 132 generates two clock 10 pulses before a subsequent prediction step is carried out.

Suppose that, for subsequent portions of the bitstream signal, a corresponding conversion table is derived first, eg. in the way explained above withreference to figure 12, it is desired to transmit the conversion table together with the residualbitstream signal so as to enable reconversion upon reception of the residual bitstream signal. 15 Figure 13 shows a connection 135 between the prediction unit 26”’ and the central processing unit 132. Via this connection, the conversion table derived in the way describedwith reference to figure 12 can be supplied to the central processing unit 132 andsubsequently supplied to an output 137 for transmission together with the residual bitstreamsignal via the transmission medium 20 Figure 14 shows a corresponding apparatus for reconverting the residual bitstream signal supplied by the apparatus of figure 13. The apparatus of figure 14 shows alarge resemblance with the apparatus of the figures 7 and 8, in the sense that the signalcombination unit 88 and the D/A converter 80 are the same as the a signal combination unitand the D/A converter respectively of figure 7. The input 72 of the prediction unit 74’ is 25 coupled to an input 92 of a four bit shift register 94’. The four outputs of the four bitpositions in the shift register 94’ are coupled to corresponding inputs of a conversion unit96’. The conversion unit 96’ comprise the conversion table discussed and explained abovewith reference to the figure 12. An output 98 of the conversion unit 96’ is coupled to asecond input 101 of the signal combination unit 88. 30 In response to a 4-bit bitsequence xj,x2,x3,x4 stored in the shift register 94’, the conversion unit 96’ supplies either a 1-bit x5’ at its output 98 or a 2-bit wordχ5’,χ6’, in the way explained above with reference to figure 12. This bit x5’ is a predictionof the bit x5, given by the conversion table 96’, that will be supplied upon the next clockpulse by the combination unit 88 and stored as the new bit x4 in the most right storage WO 93/20433 16 PCT/3jB97/013©3 position of the shift register 94’. The residual bit present at the input 86 of the combinationunit 88 is combined with the predicted bit x5’ upon the clock pulse generated by the centralprocessing unit 140, so as to obtain the replica of the original bit x5 in the original bitstreamsignal. When the residual bit is ’O’, which meant that a correct prediction was carried out in 5 the apparatus of figure 13, the combination of the residual bit with the predicted bit x5’results in the right cf the bit x5’ to appear at the output 90 of the combination unit 88 as thebit x5. When the residual bit is Ί’, which meant that an incorrect prediction was carried outin the apparatus of figure 13, the combination of the residual bit with the predicted bit X5’results in the inverse right of the bit x5’ to appear at the output 90 of the combination unit 88 10 as the bit x5. In both cases, a correct replica of the bit x$ will appear at the output 76 of thecombination unit 88.

The 2-bit prediction Χζ’,Χξ is a prediction of the 2-bit worti x5,x6,generated by the conversion table 96’, that will be supplied upon the next two clock pulses ofthe central processing unit 140 by the combination unit 88 and stored as the new 2-bit word_ 15 x3,x4 in the two most right storage positions of the shift register 94’. Two residual bits present at the input 86 of the combination unit 88 are combined with the predicted 2-bit wordx5’,x6’ so as to obtain the replica of the original 2-bit word x5,x6 in the original bitstreamsignal. When the two residual bits are ’0,0’, which meant that a correct prediction wascarried out in the apparatus of figure 13, the combination of the residual bits with the 20 predicted bits x5’,x6’ results in the right of the two bits x5’,x6’ to appear at the output 90 ofthe combination unit 88 as the bits x5,x6. When the residual bits were Ί,Γ, which meantthat an incorrect prediction was carried out in the apparatus of figure 13 on both the bits X5and x6, the combination of the two residual bits with the predicted bits results in the inverse bitvalues of the bits x5’,x6’ to appear at the output 90 of the combination unit 88 as 25 the bits X5,x6. When one of the two residual bits is ’1’ and the other is ’O’, this means thatone of the prediction bits is wrong and should be inverted in order to obtain two correct bitsx5,x6. In all cases, a correct replica of the 2-bit word X5,x6 will appear at the output 76 ofthe combination unit 88.

In the situation where, for subsequent portions of the bitstream signal, a 30 corresponding conversion table is derived first in the apparatus of figure 13, eg. in the wayexplained above with reference to figure 12, it is desired to transmit the conversion tabletogether with the residual bitstream signal so as to enable reconversion upon reception of theresidual bitstream signal in the apparatus of figure 14. Figure 14 therefore shows an inputterminal 142 for receiving the conversion table. The input terminal 142 is coupled to the WO 98/20438 PCT.TB97/01203 17 central processing unit 140, which has a connection 144 with the prediction unit 96’. Via thisconnection, the conversion table can be supplied to the prediction unit 96’.

It has been said earlier that a data compression step is carried out on theresidual bitstream signal prior to transmission. Preferably, a data compression using a 5 lossless coder is carried out. Lossless coders haye the advantage that they can data compressthe audio signal in such a way that, afrer data expansion by a lossless decoder, the originalaudio signal can be reconstructed in a substantially lossless way. That means that there issubstantially no loss of information after compression-expansion. Lossless coders can be inthe form of a variable length coder. Variable length coders are well known in the art. 10 Examples of such variable length coders are Huffman coders, arithmetic coders and Lempel-Ziv coders. Reference is made in this respect to the publications Ά method for theconstruction of minimum-redundancy codes’ by D.A. Huffman, document D4 in the list ofrelated documents, ’An introduction to arithmetic coding’ by G.G. Langdon, document D5 inthe list of related documents, and Ά universal algorithm for sequential data compression’ by 15 J. Ziv et al, document D6 in the list of related documents.

Figure 15 shows an embodiment in which the apparatus of figure 1 is followed by a data compression unit 150, such as a lossless coder. The data compressedresidual bitstream signal is recorded on an optical record carrier 156 by means of an opticalrecording unit 154. 20 Figure 16 shows the corresponding reproduction from the optical record carrier 156. The apparatus shown in figure 16 comprises a data expansion unit 162, such as alossless decoder, that carries out a data expansion step on the data compressed residualbitstream signal. The regenerated residual bitstream signal is supplied to the input 70 of theapparatus of figure 7. 25 A further modification of the embodiment of figure 1 is as follows. In this modification, the prediction unit 10 is coupled between the output of the signal combinationunit 42 and the input 44 of the signal combination unit 42. In this modification, the predictedversion of the bitstream signal is derived by the prediction unit from the residual signal,supplied by the signal combination unit 42. This modification is shown in figure 18, which is 30 in fact identical to the circuit construction of the prediction unit and the signal combinationunit shown in figure 7.

In an equivalent way, a further modification of the embodiment of figure 7 is asfollows. In this modification, the prediction unit 74 is coupled between the input terminal 70and the input 101 of the signal combination unit 88. In this modification, the predicted

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WO 98/20483 ?&lt;σΤΠΒ97/01303 18 version of the bitstream signal is derived by the prediction unit from the residual signal,supplied to the processing apparatus via the terminal 70. This modification is in fact identicalto the circuit construction of the prediction unit and the signal combination unit shown infigure 1. 5 A further improvement of the data processing apparatus can be obtained by a specific embodiment of the prediction unit such as the prediction unit 10 in figure 1. In thisspecific embodiment, the prediction unit 10 is provided with an integrator for integrating theinput signal, which is a representation of the bitstream signal, in the sense that the inputsignal has -1 and +1 representation values to represent the Ό’ and ’1’ bits in the bitstream 10 signal. The integrator simply sums all the representation values, so its instantaneous output isthe cumulative sum of all -1 and +1 values it has received. What the prediction unit in factdoes, is to generate a pseudo audio signal and the predicted bit for the bitstream signal to besupplied to the output 12 is derived from this pseudo audio signal in the following way.

The predictor derives from the last n sample values of the pseudo audio signal 15 generated by the integrator a prediction value for the next sample of the pseudo audio signal.Next the value of the last sample of the pseudo audio signal generated is compared with thepredicted value of the next sample. If, viewed along an amplitude axis, the value of the lastsample of the pseudo audio signal is smaller than the prediction value of the next sample, itis concluded that the next predicted bit in the predicted bitstream signal corresponds to the 20 +1 value (or logical ’Γ) and when the value of the last sample of the pseudo audio signal is larger than the prediction value of the next sample, it is concluded that the next predicted bitin the bitstream signal corresponds to the -1 value (or logical ’O’). The predicted bits aresupplied to the output of the prediction unit 10 as the predicted bitstream signal.

The predicted value of the next sample can be obtained by approximating the 25 last n (which eq equals 40) samples of the pseudo audio signal with a straight line. It will beunderstood that more sophisticated approximation procedures (filter techniques) are equallywell possible to predict the next sample value. In such situation, as said earlier, filtercoefficients for such filters should be derived for the signal on a frame basis and transmittedso as to enable a corresponding decoding on the receiver side. 30 Another data processing apparatus is shown in figure 19. In the data processing apparatus of figure 19, the bitstream signal is supplied to the input 44 of the signalcombination unit 42, and via a prediction filter 10’ and a quantizer Q to the input 40 of thesignal combination unit 42. The apparatus is further provided with a data compression unit150’ which comprises an entropy encoder 154 and a probability determining unit 156. In the

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WO 98/20488 ?CT/E397/O1303 19 present example, the entropy encoder 154 is in the form of an arithmetic coder for encodingthe residual bitstream signal into a data compressed residual bitstream signal in response toprobability values p supplied to its input 192. The probability determining unit 156determines a probability value indicating the probability that a bit in the residual bitstream 5 signal supplied by the combination unit 42 has a predetermined logical value, such as ’Γ.This probability value, denoted p in figure 19, is supplied to the arithmetic coder 154 so asto enable the data compression of the residual bitstream signal in the arithmetic coder 154.The determining unit 156 determines this probability value from the output signal of theprediction filter 10’. This is different from what one would expect when using an arithmetic 10 coder in the data compression unit 150, such as in figure 4 or 15, for compressing theresidual bitstream signal. When using an arithmetic coder in the compression unit 150, theprobability unit 156 would derive the probability value from the residual bitstream signalitself. In the embodiment of figure 19, however, the probability determining unit 156 derivesthe probability value from the output signal generated by the prediction filter 10’. This has 15 an advantage, in that a higher compression ratio can be obtained with the arithmetic coder154. The arithmetic coder 154 can data compress the residual bitstream signal on a framebasis.

The functioning of the apparatus of figure 19 is as follows. The prediction filter10’ realizes a prediction filtering on the bitstream signal so as to obtain a multi bit output 20 signal. The multi bit output signal has a plurality of levels within a range of eg. +3 and -3.A quantizer Q receives the multi bit output signal and generates a bitstream signal therefrom,eg. by allocating a bit of Ί ’ logical value if the multi bit output signal has a positive valueand allocating a bit of Ό’ logical value if the multi bit output signal has a negative value.Further, for each of a plurality of subintervals in the value range of the multi bit output 25 signal, it is determined what the probability is that the corresponding bit in the residualsignal is eg. a Ί* bit. This can be realized by counting the number of;’ones’ and ’zeroes’occurring in the residual bitstream signal during a specific time interval, when the multi bitoutput signal falls in one of such ranges. The probabilities thus obtained for the variousvalues in the multi bit output signal is subsequently supplied as the probability signal p to the 30 arithmetic coder 154. The data compressed residual bitstream signal is supplied by thearithmetic coder 154 to an output line 158, for transmission via a transmission mediumTRM.

Figure 20 shows a corresponding data processing apparatus for decoding thedata compressed residual bitstream signal, received via the transmission medium TRM. The

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WO 93/20433 20 PCT/I397/Q1303 data processing apparatus of figure 20 comprises an entropy decoder 172, which receives thedata compressed residual bitstream signal via an input 174. In the prssent example, theentropy decoder 172 is in the form of an arithmetic decoder that carries out an arithmeticdecoding step on the data compressed bitstream signal under the influence of a probability

5 signal p, supplied to an input 176 so as to generate a replica of original residual bitstreamsignal which is supplied to an output 178. The replica is supplied to an input 86 of the signalcombination unit 88. The signal combination unit 88 further receives a predicted version ofthe bitstream signal via the input 101 and generates the replica of the original bitstreamsignal at its output 76. The output 76 is coupled via a prediction filter 74’and a quantizer Q 10 to the input 101 of the signal combination unit 88. The functioning of the prediction filter 74’and the quantizer Q can be identical to the functioning of the prediction filter 10’ and thequantizer Q in figure 19, that is: the prediction filter 74’ derives its filter coefficients fromthe input signal it receives via its input 72. In another embodiment, the prediction filter 74’receives the filter coefficients from side information received via the transmission medium 15 TRM from the encoder apparatus of figure 19, as will be explained below.

Further, a probability supply unit 180 is present for supplying the probability signal p to the arithmetic decoder 172. The probability signal p can be obtained in differentways. One way is, to derive the probability signal p from the output signal of the predictionfilter 74’, in the same way as the probability determining unit 156 determines then 20 probability signal p from the prediction filter 10’ in figure 19. In such situation, the supplyunit 180 in figure 20 can be identical to the determining unit 156 in figure 19, and the supplyunit 180 has an input coupled to the output of the prediction filter 74’. Another way ofgenerating the probability signal p, is by using side information received via the transmissionmedium TRM, as will be explained hereafter. 25 Side information can be generated by the apparatus of figure 19 for transmission to the apparatus of figure 20. Such side information can include the filtercoefficients for the filter 10’ that are determined on a frame by frame basis, whichcoefficients are transmitted to the filter 74’ for setting the correct filter characteristic of thefilter 74’. Further, the apparatus of figure 19 can generate parameters that describe the 30 conversion of the multi bit output signal of the prediction filter 10’ into the probability signalp. Such parameters are also included in the side information and transmitted to the supplyunit 180, so as to enable the regeneration of the probability signal p in the apparatus offigure 20.

In the above described embodiments of the figures 19 and 20, it is explained WO 98/20488 21

PCT/IS97/Q13GS how the probability signal p can be derived from the multi bit output signal from the prediction filter 10’ and 74’ respectively. It should however be noted that the application of an arithmetic coder is also possible in data processing apparatuses that derive the predicted signal in a different way. Reference is made in this respect to the embodiments shown in 5 figure 1, where the prediction unit 10 is in the form as disclosed in the figures 2 or 12. Nowanother way of deriving the probability signal p is required. It will be clear that, in theembodiments of the prediction unit as shown in figures 2 and 12, the probability signal p canbe derived from the count numbers derived in the detector 22 and 22’ respectively.

The entropy encoder used in the embodiment of figure 19 is adapted to encode 10 the residual bitstream signal using a probability signal in order to obtain the data compressedresidual bitstream signal. One of such entropy encoder is the arithmetic coder describedabove. One other type of such entropy coder is, as an example, the well known finite state ί coder. The entropy decoder used in the embodiment of figure 20 is adapted to decode thedata compressed residual bitstream signal using a probability signal in order to obtain a 15 replica of the residual bitstream signal. One of such entropy decoder is the arithmetic decoder described above. One other type of such entropy decoder is, as an example, the wellknown finite state decoder.

Whilst the invention has been described with reference to preferredembodiments thereof, it is to be understood that these are not limitative examples. Thus, 20 various modifications may become apparent to those skilled in the art, without departingfrom the scope of the invention, as defined by the claims. When the audio signal is suppliedin digital form, such as sampled at 44.1 kHz and the samples being expressed in eg. 16 bits,the A/D converter means are adapted to oversample the digital audio signal with eg. thefrequency of 64 x 44.1 kHz so as to obtain the 1-bit bitstream signal which is supplied to the 25 prediction unit 10.

Further, as regards the conversion tables, such as the one shown and describedin figure 12, the following can be said. In the phase of deriving the conversion table, it mayoccur that, as an example, the count values are such that the bit sequences 0,0,0,0 and0,0,1,0 result in the same prediction bit(s), that the bit sequences 0,0,0,1 and 0,0,1,1 result 30 in the same prediction bit(s), that the bit sequences 0,1,0,0 and 0,1,1,0 result in the sameprediction bit(s), that the bit sequences 1,0,0,0 and 1,0,1,0 result in the same predictionbit(s), the bit sequences 1,1,0,0 and 1,1,1,0 result in the same prediction bit(s), that the bitsequences 1,0,0,1 and 1,0,1,1 result in the same prediction bit(s), that the bit sequences1,1,0,1 and 1,1,1,1 result in the same prediction bit(s), and that the bit sequences 0,1,0,1 PCT/LB97/013C3 WO 38/20483 22 and 0,1,1,1 result in the same prediction bit(s). In this situation, the bit x3 is in fact a don’tcare bit and the prediction bit(s) x4 or x4,x5 can be predicted from the bit combinationx1}x2,x4 alone.

Further, the invention lies in each and every novel feature or combination of 5 features. WO 93/20488 23

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FCT/3GB97/01303

List of related documents (DI) EP-A 402,973 (PHN 13.241) (D2) Ά digital decimating filter for analog-to-digital conversion of hi-fi audio signals’, by J.J. van der Karn in Philips Techn. Rev. 42, no. 6/7, April 1986,pp. 230-8

5 (D3) Ά higher order topology for interpolative modulators for oversampling A/D converters’, by Kirk C.H. Chao et al in IEEE Trans, on Circuits and Systems,Vol 37, no. 3, March 1990, pp. 309-1.8 (D4) Ά method for the construction of minimum-redundancy codes’, by D.A.

Huffman in Proc. of the IRE, Vol. 40(10), September 1952. 10 (D5) ’An introduction to arithmetic coding’ by G.G. Langdon, IBM J. Res. {

Develop., Vol. 28(2), March 1984.

j (D6) Ά universal algorithm for sequential data compression’ by J. Ziv et al, IEEE TRans. on Inform. Theory, Vol. IT-23, 1977. (D7) EP patent application no. 96202807.2, filing date 10-10-96 (PHN 16.029)

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