Low-complexity direct conversion receiver for delay-and-correlate transmitted reference signaling

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A LOW-COMPLEXITY DIRECT CONVERSION RECEIVER FORDELAY-AND-CORRELATE TRANSMITTED REFERENCE SIGNALING

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A LOW-COMPLEXITY DIRECT CONVERSIONRECEIVER FOR DELAY-AND-CORRELATETRANSMITTED REFERENCE SIGNALING

BACKGROUND OF THE INVENTION

Field of the Invention 5 \ This invention relates to spread spectrum communications systems and, more particularly, to a low-complexity transmitted reference spreadspectrum communications receiver.

Description of the Prior Art 10

Spread spectrum communications offer several advantages incommunications applications requiring high reliability. These include lowdensity power spectra and interference rejection. In the case of interferencerejection, the interference may be accidental, that is, simply part of the 15 environment of the communication system. In a specific application, thecommunications environment may include many potential reflectors, givingrise to severe multipath interference. Such multipath interference typicallyinsinuates deep nulls in the form of frequency selective fading. Spreadspectrum communications is an ideal countermeasure to this difficulty. 20 There are several types of spread spectrum systems including direct sequence digital systems, frequency hopping systems, time hoppingsystems, pulsed frequency modulated (or chirp) systems, and varioushybrids. Of these, the direct sequence digital systems and frequency hoppingsystems are perhaps the more widely implemented. In a direct sequence 25 digital system, a pseudorandom code generator is used to modulate afrequency modulated carrier. In a frequency hopping system, a coherentlocal oscillator is made to jump from one frequency to another.

Direct sequence spread spectrum modulation involves a widebandsignal modulated by a narrowband message signal. A conventional 30 implementation is to generate a wideband signal by means of a high speedshift register of n-stages with modulo-two feedback according to a primitive - 2 - polynomial. The high speed digital sequence is then supplied to a balanced modulator whose other input signal is a nanowband carrier. The output signal of the balanced modulator is a wideband signal sometimes referred to as a "wideband carrier".

Spread spectrum communications are often asymmetric in cost andcomplexity. For example, suitable spread spectrum signals may be generatedwith relatively low complexity circuitry. The challenge is then how toaccomplish demodulation of such signals. Usually, it is necessary toconstruct a demodulator which can generate or otherwise process awideband signal in order to recover the narrowband message.

Synchronization is often the most difficult and costly aspect of a spreadspectrum communications system.

In order to simplify the receiver in a spread spectrumcommunications system, it is known to transmit a reference that may beused in place of synchronization and tracking at the receiver; that is, thecoded reference is generated and transmitted with the intended informationsignal. Since the local reference is generated at the transmitter, the receiverneed not have a code sequence or other local reference generator.

The present invention relates to the direct sequence digital type ofspread spectrum communications system using a transmitted reference. Adelay-and-correlate receiver is used to achieve synchronization. Amathematical model of a delay-and-correlate receiver suggests use of analogdelay and multiplier circuits which would account for a significant fraction ofthe receiver cost. A description of the direct sequence digital type of spreadspectrum communications system, as well as other types of spread spectrumcommunications systems, may be found, for example, in Spread SpectrumSystems, 3rd Ed., by Robert C. Dixon, John Wiley & Sons (1994), andSpread Spectrum Communications, Vol. II, by Μ. K. Simon et al.,

Computer Science Press (1985).

SUMMARY OF THE INVENTION

An object of the invention is to provide a method and apparatuswhich will reduce the complexity, and hence the cost, of a delay-and-correlate receiver for a spread spectrum communication system. RD-24,555

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10 15 20 25

The invention eliminates the need for a local reference bytransmitting a reference that the receiver can use to perform despreading. Themethod and apparatus of the invention is in the class of systems known as"transmitted reference" spread spectrum systems. In general, a transmittedreference system sends both a message signal and a reference signal to thereceiver. The message signal contains the information to be communicated,which has been spread through multiplication with a wide band "spreadingwaveform". The reference signal consists of the spreading waveform itself,which the receiver can use to despread the message signal and recover theinformation.

The method and apparatus of the invention are implemented withminimal component digital circuitry, which replaces the analog delay andmultiplier circuits. The method allows direct RF (radio frequency) tobaseband conversion, and thus also eliminates the need for an IF(intermediate frequency) stage. The direct conversion receiver for delay-and-correlate transmitted reference spread spectrum signaling comprises an RFconverter for converting a received direct sequence spread spectrum signal tobaseband. An analog-to-digital converter samples the baseband signal at arate greater than the chipping rate of the direct sequence spread spectrumsignal. A delay stage coupled to the output of the analog-to-digital converterdelays the sampled signal. Multiplier logic receives output signals from theanalog-to-digital converter and the delay stage and generates control outputsignals. A counter responsive to the control output signals increments ordecrements a count or recycles, depending on the decoded control outputsignals.

BRIEF DESCRIPTION OF THE DRAWINGS

The features of the invention believed to be novel are set forth in theappended claims. The invention, however, together with further objects and 30 advantages thereof, may best be understood by reference to the followingdescription taken in conjunction with the accompanying drawing(s) inwhich:

Figure 1 is a block diagram of a transmitter typically employed withthe invention; ,,RD-24,555

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Figure 2 is a block diagram of the receiver according to the invention;Figure 3 is a block diagram of the receiver illustrated in Figure 2, showing in more detail the simple analog-to-digital converter;

Figure 4 illustrates the comparator output signals for a sample input 5 waveform;

Figure 5 is a logic diagram of a circuit which generates one part ofthe input signal to the counter; and

Figure 6 is a logic diagram of a circuit which generates another partof the input signal to the counter. 10

DETAILED DESCRIPTION OF A PREFERREDEMBODIMENT OF THE INVENTION

Figure 1 illustrates a transmitter which is typically employed with theinvention. Data are applied to one input of an Exclusive OR (XOR) gate 11, 15 and a pseudorandom code generated by a sequence generator 12 is applied toa second input of XOR gate 11. The output signal of XOR gate 11 issupplied to an n-stage shift register 13 which provides the signal with aknown delay. In an adder 14, the delayed signal from shift register 13 isadded to the code produced by sequence generator 12, and the summed 20 signal is supplied to an amplifier and filter 15. The output signal produced byamplifier and filter 15 is mixed with an RF signal from a local oscillator (notshown) in a mixer 16 to generate the transmitted signal.

The receiver according to the invention is shown in Figure 2. Thereceived signal from antenna 20 is supplied to an RF amplifier and filter 21. 25 After amplification and passband filtering, the received signal is directlyconverted to baseband by a mixer 22. The baseband signal is supplied to again control 23, the output signal of which is sampled at a rate greater thanthe chipping rate by an analog-to-digital converter (ADC) 24. A simpleADC may be used as there are only three different transmitted levels. 30 Because there generally is some offset between the transmitter local oscillator and the receiver local oscillator (not shown) providing an RF signalto mixer 22, the baseband signal is likely to be sine wave modulated. Theoscillator offset is designed to be much less than the chipping rate, however,so that the sign change that occurs at the zero crossing of the sine wave ,RD-24,555 -5-

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affects only a small percentage of the samples to a delay-and-correlate devicecomprised of a delay path 25 and a multiplier circuit 26. Delay path 25 isimplemented by a shift register made up of series of flip-flops triggered by alocal receiver clock (not shown), providing a total delay very close to that of 5 shift register 13 of the transmitter shown in Figure 1. The output signals ofADC 24 and delay line 25 are supplied to multiplier circuit 26. True signalmultiplication is approximated by a simple combinational circuit. The outputsignal of multiplier circuit 26 is supplied to a counter 27 which increments,decrements, or remains unchanged, according to the output signal of the 10 multiplier circuit. At the end of each message symbol, the most significantbit of the counter determines whether a "0" or a " 1" was sent. Counter 27 isthen cleared to 00...0 for the next message symbol.

As the transmitted baseband signal utilizes only three different levels,the circuit depicted in Figure 3 illustrates a particularly simple ADC 24 15 implementation. Two comparators 31 and 32 perform the analog-to-digitalconversion, and the delay path 25 requires only two parallel delay lines 33and 34, implemented by a series of flip-flops. The output signals ofcomparators 31 and 32 are designated C/t) and C2(t), respectively, eachsignal being a function of time t, and the output signals of delay lines or shift 20 registers 33 and 34 are designated Cj(t-d) and C2(t-d), respectively, drepresenting the net delay of the shift registers. Figure 4 shows thewaveforms and high and low thresholds Cj and C2, respectively.Multiplication logic 26 generates output signals Xq and Xj which controlcounter 27 to increment, decrement or recycle (i.e., do nothing). A truth table 25 for the multiplier logic 35 is shown below:

Multiplication Logic Truth Table

Cj(t-d) C2(t-d) C,(t-d) C2(t-d) C,(t-d) C2(t-d) c,(t-d) C2(t-d) 0 0 0 1 1 0 1 1 Recycle Not Possible c,(t) c?(t) 0 0 1 1 0 X X X I 0 0 1 0 X 0 X X X 0 X 1 0 X X X X X X X X 1 1 1 0 0 X X X 1 1

In the above truth table the output signal X may be termed "don't care" since , RD-24,555

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-6- it can have any one of three states; increment, decrement or recycle (i.e., donothing). These three states are represented according to the following table:

*0 . *1 Increment 1 1 Decrement 1 0 Recycle 0 X

The output state is recycle whenever Χθ=0. These input signals are provided5 to counter 27 which decodes the commands.

The truth table for the Χθ generation logic is shown below: C,(d) c2(d) C,(d) c2(d) c,(d) C2(d) c,(d) C7(d) Cl C2 0 0 0 1 1 0 1 1 0 0 1 X X 0 0 1 X X X X 1 0 X X X X 1 1 0 X X 1

Figure 5 is the logic diagram of the circuit implementing the truth10 table for Χθ. As can be seen, a minimal number of gates are required for this implementation; specifically, two AND gates 51 and 52 and one NORgate 53. AND gate 51 receives the input signals Cp C2, Cj(d), and C2(d) togenerate the logical output signals Ci«C2*Ci(d)»C2(d). NOR gate 53receives the same input signals to generate the logical output signals 15 C, · C2 «C, (&lt;i)*C2(c/). These two output signals are combined in AND gate52 to generate Χθ.

The truth table for the Xt generation logic is shown below: 2£l c^d) c?(d) C,(d) c2(d) c,(d) c2(d) C,(d) c9(d) C1 c2 0 0 0 1 1 0 1 1 0 0 1 0 X 1 0 1 0 0 X 0 1 0 X X X X 1 1 1 0 X 1

Figure 6 is the logic diagram of the circuit implementing the truth 20 RD-24,555

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-7- table for Xj. As can be seen, a minimal number of gates are required for thisimplementation; specifically, two Exclusive NOR gates 61 and 62 and oneAND gate 63. Exclusive NOR gate 61 receives input signals Cj and C2 andgenerates the output signals C1O2 + Cy· C2, and Exclusive NOR gate 62 5 receives the input signals Cj(d) and C2(d) and generates the output signalsCi(d)*C2(d) + C,(i/)»C2(i/). These two output signals are supplied to ANDgate 63 which generates Xj as the output signal.

While only certain preferred features of the invention have beenillustrated and described, many modifications and changes will occur to 10 those skilled in the art. It is, therefore, to be understood that the appendedclaims are intended to cover all such modifications and changes as fall withinthe true spirit of the invention.