Asynchronised multiple switch system

This invention relates to an ATDM switching system comprising a serial to parallel converter (100) arranged to receive incoming packets of data (which include their own routing information) from several input ports (107) in serial format and deliver them, in parallel format, to a Random Access Memory (RAM) (101, 102) in such a way that the packets form queues within the memory, one for each output port. Packets are then transferred in parallel format, one from each queue in turn, to a parallel to serial converter (105) which delivers them to their respective output ports (109) in serial format. The arrangement is such that when the memory becomes full the system can accommodate incoming packets by overwriting data in the longest queue, a technique that can significantly reduce the total number of packets lost during long term operation.