Multilayer structure and its fabrication process

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Technical field and prior art

The present invention relates to a method of manufacturing multilayer composite structures facilitating the integration of electronic, optoelectronic and / or power components / functionalities.

The production of structures allowing the integration on a same platform of MOS type electronic components (for example CMOS circuits) and of III-V type electronic, optoelectronic and / or power components (for example transistors or optical sources / detectors) is based on the ability to combine on the same substrate:

high-quality crystalline layers of monocrystalline silicon allowing the production of electronic components of the MOS type, and materials of the ΠΙ-V type (GaAs, InP as well as their alloys) for the production of electronic, optoelectronic and / or power components. type III-V.

Many techniques have been tested by teams of researchers to find a satisfactory manufacturing methodology for these layers.

Direct epitaxial growth of III-V materials (for example GaAs, InP, alloys, ...) on silicon by CVD (for Chemical Vapor Deposition, chemical vapor deposition) or MBE (for Molecular Beam Epitaxy, epitaxy by molecular jet) have been studied during the last decades without however obtaining convincing results in terms of crystalline quality (emerging dislocation problems, antiphase domains, point defects, etc.).

According to another known technique, it is possible to physically transfer a thin monocrystalline layer of InP, GaAs material on a silicon substrate without significantly altering the intrinsic crystalline quality of these layers, as described in particular in the Jalaguier document; Transfer of 3 in GaAs film on Silicon substrate, ELECTRONICS

LETTERS, 19th February 1998 Vol. 34 No. 4 pp. 408-409). This layer transfer is carried out using the well-known Smart Cut ™ technology, an example of which is described in particular in document US Pat. No. 5,374,564 or in the article by AJ Auberton-Hervé et al. titled Why can Smart-Cut Change the future of microelectronics?, Int. Journal of High Speed ​​Electronics and Systems, Vol. 10, Nol, 2000, p.131-146.

In addition, it has been demonstrated that it is possible to combine growth techniques with those of transfer of layers to integrate silicon and III-V materials on the same mechanical platform.

According to a first embodiment, one way to obtain GaAs on a silicon wafer with a diameter of 200 mm, without having a GaAs donor substrate, consists in growing GaAs on a germanium substrate ( Ge) monocrystalline. The growth of GaAs on germanium makes it possible to obtain a very good quality of thin films given the very low mismatch in lattice parameter between these two materials. Nevertheless, taking into account the price and the mechanical fragility of these massive substrates, it is more advantageous to carry out a transfer of a thin film of germanium on silicon (such as GaAs and InP) then to carry out the crystal growth of GaAs. The GaAs thus obtained is of equivalent quality to that epitaxied on a solid GaAs substrate.

The GeOI structure (germanium on silicon with an intermediate layer of silica) has been demonstrated in large diameter, i.e. up to 200 mm in diameter. It is to date the most direct methodology for combining silicon and GaAs.

However, for the application targeted in the present invention, namely integration of microelectronic, optoelectronic and / or power functions on silicon and ΠΙ-V materials, this structure does not have the best advantages. In fact, with an epitaxied Ge / GaAs transferred structure, it is difficult to produce CMOS components on the silicon support substrate because it is first necessary to locally discover the silicon in order to manufacture the circuit there. In addition to the thermal budget problem specific to manufacturing, there is a topology which makes the electrical connection between the circuit and the optical component difficult, if not impossible.

According to a second embodiment of this technique, structures with an active layer of silicon for the CMOS components at the surface and an optically active layer below the layer of silicon have thus been developed to overcome these drawbacks.

Documents US Pat. No. 6,645,829 and US Pat. No. 6,677,655 thus describe the manufacture of structures comprising buried active optical layers such as:

- [Si substrate / oxide (SiO2) / Ge layer / Si layer] or else

- [Si substrate / oxide (SiO2) / Si layer / Ge layer / oxide (SiO₂) / Si layer],

However, in this type of structures, the optically active layer is always in direct contact with a layer of silicon of more or less good quality depending on the manufacturing methods (epitaxial or bonding) used for the production of this silicon layer.

Furthermore, document US 2004/0252931 proposes forming multilayer structures by bonding a multilayer monolithic electronic device comprising an electrically active layer and an optically active layer, on another layer, the electrical and optical layers possibly being SOI layers. transferred onto a support substrate.

Summary of the invention

To overcome the aforementioned drawbacks, the present invention provides a solution which makes it possible to produce a multilayer structure homogeneously integrating III-V type materials with active layers of silicon, while simplifying the number of steps necessary in order to '' improve manufacturing yields.

To this end, the invention relates to a method of manufacturing a multilayer structure comprising at least the following steps:

a) epitaxial growth of a growth layer on a silicon substrate,

b) formation of at least one stud in the growth layer,

c) deposition of an oxide layer on the silicon substrate,

d) transfer of a silicon layer to the oxide layer,

e) formation of a cavity in the silicon and oxide layers above each pad,

f) growth of a III-V type material from each stud of the growth layer uncovered in the cavity.

Thanks to the method of the invention, a structure is obtained comprising directly on the surface both an active layer of silicon for MOS type components and one or more islands of III-V type materials for electronic, optoelectronic and / or electronic components. or power. This structure is also produced more simply than with the prior methods, in particular due to the fact that the method of the invention involves only one transfer of the layer in the entire manufacturing cycle.

According to one aspect of the invention, in step b), each pad is produced by chemical etching of the growth layer through a first opening mask applied to said growth layer. The number and shape of the studs can be varied. In the case of forming a plurality of studs, these are preferably spaced uniformly from one another.

According to another aspect of the invention, in step e), the cavity is produced by chemical etching of the active silicon layer and of the oxide layer through a second opening mask applied to said layer. active silicon, said mask being aligned on each pad of the growth layer.

In step d), the transfer of the active silicon layer can be achieved by bonding an SOI structure to the oxide layer, the base substrate of the SOI structure being removed after bonding.

The silicon substrate is preferably but not exclusively a disoriented silicon substrate.

The growth layer can be a germanium layer and the III-V type material can be a material chosen from at least gallium arsenide (GaAs), AIGaAs, and InGaAs.

Furthermore, the growth layer can also be an aluminum nitride (AIN) layer. In this case, the III-V type material can be a material chosen from at least GaN, AIGaN, InGaN and ZnGaN.

The method may further comprise, after step b) and before step c), at least one heat treatment step so as to allow migration and annihilation of the dislocations towards the edges of each pad.

The present invention also relates to a multilayer structure comprising:

a silicon substrate, at least one pad of a growth layer of a III-V type material, an oxide layer on the silicon substrate, an active silicon layer on the oxide layer, the layer oxide and the active silicon layer comprising a cavity above each pad of the growth layer, said cavity being filled with a III-V type material.

Brief description of the figures

The characteristics and advantages of the present invention will emerge better from the following description, given by way of indication and without limitation, with reference to the appended drawings in which:

FIGS. IA to 1K are schematic sectional views showing the manufacture of a multilayer structure in accordance with an embodiment of the invention, FIG. 2 is a flowchart of the steps implemented in FIGS. IA to 1K.

Detailed description of embodiments of the invention

The present invention applies generally to the production of multilayer structures, preferably in the form of plates (wafers), allowing easy integration of electronic components (for example FET, MOSFET or HBT transistors), optoelectronic (for example sources. / light detectors) and / or power (for example Very High Mobility transistor (HEMT)) based on III-V type materials at the level of a microelectronic circuit based on silicon technology. This type of circuit can include all the components usually encountered in silicon technology, such as those making it possible to perform logic and / or analog functions, memory functions, etc.

To this end, the multilayer structure of the present invention comprises a surface layer of active silicon and one or more islands of ΠΙ-V material emerging at the level of this layer of silicon.

A method of manufacturing a multilayer structure in accordance with an embodiment of the invention is now described with reference to FIGS. 1A to 1K and 2,

The first step consists in forming, by epitaxial growth, a germanium layer 2 on a silicon substrate 1 (step S1, FIG. IA). The germanium layer 2 corresponds to a growth layer, that is to say a nucleation or growth germ layer, from which a III-V material will subsequently be formed by resumption of selective epitaxial growth. Epitaxial growth is a well known technique and will therefore not be described in more detail.

The germanium layer 2 thus formed has a thickness of between 100 nanometers and 10 microns approximately and has a dislocation density of between 1.10⁶/ cm² and 1.10⁸/ cm² about.

The silicon substrate 1 can be formed of an oriented silicon substrate (crystalline axis and the normal of the surface (100) aligned) or disoriented (presence of an angle, also called miscut or offcut, between crystalline axis and the normal of the surface (100)). The substrate 1 is preferably but not necessarily a disoriented silicon substrate because it makes it possible to obtain an epitaxial growth layer with very few defects.

The second step consists in forming one or more germanium spots from the germanium layer 2. In the example described here, a mask 10 is applied to the germanium layer 2, for example by lithography (step S2, FIG. IB ), then a chemical etching is carried out on the parts of the germanium layer 2 exposed through the openings of the mask 10 (step S3, FIG. 1C). Once the etching is complete and the mask removed, a germanium pad 20 remains on the silicon substrate 1 as shown in FIG. 1C.

In the example described here, a single germanium stud was formed. However, in accordance with the present invention, several studs can be formed from the growth layer. Likewise, each stud is not limited to a particular shape. The studs can have any type of shape (square, round, annular, etc.) as required. The formation of one or more pads can also be obtained by other etching techniques such as plasma or ion etching for example.

When several pads are formed, they are preferably uniformly spaced from each other on the silicon substrate 1. The silicon substrate 1 with the germanium pad 20 can also undergo thermal cycling making it possible to virtually eliminate all the dislocations at the level of the pad 20 by migration and annihilation of the dislocations towards the edges of the pad (step S4). Such thermal cycling is in particular described in the document Luan et al., High-quality Ge epilayers on Si with low threadîng-dîslocation densities, APL 75 n 19 Nov 1999, pp 2909-2911). This cycling is carried out at temperatures of the order of 800 to 1000 ° C. over a period ranging from a few tens of minutes to a few hours. Several thermal cycles are sometimes necessary.

A thick bonding oxide layer 3 is then deposited on the silicon substrate 1 and on the germanium pad 20 (step S5, FIG. ID). The bonding oxide layer is, for example, a layer of SiO₂ with a thickness of a few hundred nanometers if the germanium 2 layer is not patterned (that is to say no formation of spots). Otherwise, the SiO layer₂ has a thickness of about three times the height of the germanium stud (s) formed. The surface of the bonding oxide layer 3 is planarized (step S6), for example by chemical mechanical polishing (CMP).

An SOI structure 4 is then bonded to the surface of the bonding oxide layer 3 (step S7, FIG. 1E). The SOI structure 4 comprises, as well known per se, a silicon substrate 43, a buried oxide layer (S1O2) 42 and an active silicon layer 41, that is to say a layer of high-grade monocrystalline silicon. crystalline quality allowing the production of MOS type electronic components. In a known manner, such an SOI (silicon on insulator) structure can be produced using Smart Cut ™ technology which comprises the following steps:

- implantation of gaseous species, (H, He, ... alone or in combination) in a first substrate of oxidized silicon to form an embrittlement zone therein delimiting a donor silicon wafer,

bonding, for example by molecular adhesion, of the first silicon substrate on a second silicon substrate corresponding to the support substrate prepared as described above,

- detachment by splitting (thermally and / or mechanically) of the donor silicon wafer in the area weakened by implantation, and possibly

- finishing by chemical etching, polishing / planarization, and / or heat treatment.

This gives an SOI structure (identical to structure 4) comprising a silicon support substrate with a buried oxide layer (identical to silicon substrate 43 with the oxide layer (SiO₂) buried 42) and a silicon film obtained by the transfer of the donor silicon wafer (corresponding to the active silicon layer 41).

The SOI structure 4 is bonded to the bonding oxide layer 3 by means of a strong low-temperature bonding which can be obtained, for example, with bonding by molecular adhesion, via plasma activation (oxygen, nitrogen, etc. ). Annealing in a temperature range of between 600 ° C and 1100 ° C approximately can be applied to strengthen the bonding interface between the bonding oxide layer 3 and the SOI structure 4 (step S8), but also to recover the initial properties of silicon.

The silicon substrate 43 is then removed by grinding (wafer grinding), by polishing (CMP) and by chemical etching (step S9, FIG. 1F). The buried oxide layer is also removed (step S10, FIG. IG), for example by dry chemical etching (for example plasma etching) or wet or else by selective etching with TMAH (tetramethylammonium hydroxide).

As represented in FIG. IG, a bilayer structure of SOI type is thus obtained on a silicon substrate containing a germanium pad 20.

The next two steps consist in forming a cavity making it possible to open the structure above the germanium pad 20. As in step S3, an opening mask 11 is applied to the active silicon layer 41 (step SU, FIG. 1H), for example by lithography, then a chemical etching of the parts of the active silicon layer 41 exposed through the opening of the mask 11 (step S12, FIG. II) is carried out. An alignment of the aperture mask 11 is necessary to open the layer 41 above the germanium pad 20. The mask 11 corresponds to the duplicate of the mask 10 used during step S3. Once the etching is complete and the mask has been removed, the active silicon layer 41 has a cavity 12 which extends above the germanium pad 20 as shown in FIG. IL is then removed, by dry chemical etching (for example plasma etching ) or wet, the part of the oxide layer 3 located between the germanium pad 20 and the cavity 12 so as to extend the latter up to the pad 20 (step S13, FIG. IJ).

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Once the germanium pad has been discovered, a resumption of selective epitaxial growth of gallium arsenide (GaAs) is carried out (step S14, FIG. 1K). This resumption of growth makes it possible to fill the cavity 12 with a pad or island of GaAs 5 constituted here of gallium arsenide (GaAs) emerging at the level of the surface of the active layer of silicon 41.

GaAs is not the only III-V type material that can be formed on a germanium layer or pad by resumption of epitaxy. For example, AIGaAs or InGaAs can also be formed from a germanium growth layer.

Furthermore, the material of the growth layer is not limited only to germanium. The growth layer can also be an aluminum nitride (AIN) layer formed on a silicon substrate (110) or (100) and from which it is possible to form III-V type materials such as silicon. GaN, and / or AIGaN, and / or InGaN, and / or ZnGaN.

The manufacturing process of the present invention makes it possible to homogeneously integrate III-V type materials and silicon on the same mechanical support, regardless of the size of the wafers or wafers to be produced, such as for example wafers. 200 mm or 300 mm in diameter.

Many advantageous applications are possible with the multilayer structure of the present invention. In particular, the island or islands of III-V materials formed can be used to produce optoelectronic components of the source or detector type which can be used as connection means. The electronic chips manufactured from such a structure can then be connected to external devices by optical links (for example connection to optical fibers or waveguides) and take advantage of bandwidths and higher rates than with electrical connections and connections.

According to another advantageous application, the structure of the invention can be used to place within a silicon circuit a set of transistors based on ΠΙ-V material having intrinsic performance (switching speed, on current, etc.). ) superior to MOS type transistors.